CN115602533A - Mask forming method and semiconductor device processing method - Google Patents
Mask forming method and semiconductor device processing method Download PDFInfo
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- CN115602533A CN115602533A CN202211345849.3A CN202211345849A CN115602533A CN 115602533 A CN115602533 A CN 115602533A CN 202211345849 A CN202211345849 A CN 202211345849A CN 115602533 A CN115602533 A CN 115602533A
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- 238000000034 method Methods 0.000 title claims abstract description 102
- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 238000003672 processing method Methods 0.000 title claims abstract description 8
- 238000005530 etching Methods 0.000 claims abstract description 112
- 239000000758 substrate Substances 0.000 claims abstract description 77
- 229920001400 block copolymer Polymers 0.000 claims abstract description 51
- 239000007789 gas Substances 0.000 claims abstract description 43
- 229920003229 poly(methyl methacrylate) Polymers 0.000 claims abstract description 40
- 239000004926 polymethyl methacrylate Substances 0.000 claims abstract description 40
- 239000004793 Polystyrene Substances 0.000 claims abstract description 39
- 229920002223 polystyrene Polymers 0.000 claims abstract description 38
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 21
- 239000001301 oxygen Substances 0.000 claims abstract description 21
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 21
- NINIDFKCEFEMDL-UHFFFAOYSA-N Sulfur Chemical compound [S] NINIDFKCEFEMDL-UHFFFAOYSA-N 0.000 claims abstract description 15
- 229910052717 sulfur Inorganic materials 0.000 claims abstract description 13
- 239000011593 sulfur Substances 0.000 claims abstract description 13
- 238000012545 processing Methods 0.000 claims abstract description 9
- 230000008569 process Effects 0.000 claims description 58
- 229920002120 photoresistant polymer Polymers 0.000 claims description 38
- 239000006117 anti-reflective coating Substances 0.000 claims description 34
- 230000004888 barrier function Effects 0.000 claims description 25
- RAHZWNYVWXNFOC-UHFFFAOYSA-N Sulphur dioxide Chemical compound O=S=O RAHZWNYVWXNFOC-UHFFFAOYSA-N 0.000 claims description 16
- 239000011248 coating agent Substances 0.000 claims description 13
- 238000000576 coating method Methods 0.000 claims description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
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- 229910052799 carbon Inorganic materials 0.000 claims description 6
- 239000001307 helium Substances 0.000 claims description 6
- 229910052734 helium Inorganic materials 0.000 claims description 6
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 claims description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 2
- 230000005284 excitation Effects 0.000 claims description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 2
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 2
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 2
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- 239000010410 layer Substances 0.000 description 110
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- 230000002209 hydrophobic effect Effects 0.000 description 1
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- 239000000178 monomer Substances 0.000 description 1
- 239000002086 nanomaterial Substances 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
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- 229920005553 polystyrene-acrylate Polymers 0.000 description 1
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- XTQHKBHJIVJGKJ-UHFFFAOYSA-N sulfur monoxide Chemical class S=O XTQHKBHJIVJGKJ-UHFFFAOYSA-N 0.000 description 1
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- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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- Drying Of Semiconductors (AREA)
Abstract
The application discloses a mask forming method and a semiconductor device processing method, which comprises the following steps: forming a mask layer with a patterned groove on a substrate; forming a block copolymer within the trench, wherein the block copolymer comprises a polystyrene block formed on a sidewall of the trench, and a polymethylmethacrylate block located between adjacent polystyrene blocks; and introducing etching gas, and etching the block copolymer after ionization until the polymethyl methacrylate block is removed, wherein the etching gas comprises sulfur and oxygen. The mask forming method can provide a pattern transfer function for the wafer with high-precision processing, and further form an etching pattern with smaller critical dimension on the wafer.
Description
Technical Field
The present disclosure relates to the field of wafer processing technologies, and in particular, to a mask forming method and a semiconductor device processing method.
Background
The photolithography process is an important technology in the wafer processing process, and a preset pattern can be formed on the wafer by using the photolithography process. At present, a photoresist layer is usually disposed on a silicon substrate and is assisted by other corresponding hard mask structures, and the photoresist layer is etched layer by using a technical principle that etching rates of different film layers are different, so that a pattern formed by exposing the photoresist is finally transferred onto the silicon substrate.
Under the condition that the process size of the wafer is relatively large, the precision of the photoetching technical scheme can meet the requirement of process precision by combining the immersion photoetching process and the double (multiple) pattern exposure technology. However, with the continuous reduction of the process, the scaling and transferring of the pattern in the current photolithography technology have reached the limit due to the influence of the defects of the photoresist forming material itself in the 16nm, 14nm, or even 10nm process, and thus, a method for processing a wafer with high precision process is needed to form an etching pattern with smaller critical dimension on the wafer.
Disclosure of Invention
The application discloses a mask forming method and a semiconductor device processing method, which are used for providing a pattern transfer effect for a wafer with a high-precision processing procedure and further forming an etching pattern with a smaller critical dimension on the wafer.
In order to solve the above problems, the following technical solutions are adopted in the present application:
in a first aspect, the present application discloses a mask forming method, which includes:
forming a mask layer with a patterned groove on a substrate;
forming a block copolymer within the trench, wherein the block copolymer comprises a polystyrene block formed on a sidewall of the trench, and a polymethylmethacrylate block located between adjacent polystyrene blocks;
and introducing etching gas, and etching the segmented copolymer after ionization until the polymethyl methacrylate block is removed, wherein the etching gas comprises sulfur and oxygen.
In a second aspect, the present application discloses a method for forming a semiconductor device, wherein a mask is formed by the above mask forming method for processing.
The technical scheme adopted by the application can achieve the following beneficial effects:
the embodiment of the application discloses a mask forming method, which can form a mask layer with a required structure on a substrate, and then transfer a groove structure formed on the mask layer to the substrate through pattern transfer modes such as etching and the like to form a semiconductor device with the required structure. When the mask forming method disclosed by the embodiment of the application is executed, a mask layer is formed on a substrate, a patterning groove is formed on the mask layer, the width and other dimensions of the patterning groove are relatively large, and the mask layer can be formed on the substrate by adopting a conventional photoetching technology; then, a block copolymer can be formed in the trench, and a polystyrene block in the block copolymer is formed on the side wall of the trench, so that a polymethyl methacrylate block in the block copolymer is formed between adjacent polystyrene blocks, obviously, the space occupied by the polymethyl methacrylate block in the block copolymer formed in the patterned trench on the mask layer is obviously smaller than the space occupied by the patterned trench on the mask layer; and then, by ionizing the etching gas containing the sulfur element and the oxygen element, the polystyrene block and the polymethyl methacrylate block in the block copolymer can be etched together until the polymethyl methacrylate block is removed, and because the plasma sulfur ionized by the etching gas can not react with the polystyrene block, the two blocks have a high selection ratio, so that in the process of etching the block copolymer, when the polymethyl methacrylate block is basically and completely etched and removed, the polystyrene block with a relatively large thickness can still be reserved, the polystyrene block can be used as a mask in the subsequent etching process, the width size of a patterning groove on the mask layer is further reduced, the purpose of pattern scaling is realized, and further, in a process of 16nm or even smaller, a pattern transfer function is provided for semiconductor devices such as wafers and the like, so that etching patterns with smaller key sizes are formed on the semiconductor devices.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the application and not to limit the application. In the drawings:
FIG. 1 is a flow chart of a method of forming a mask disclosed in an embodiment of the present application;
fig. 2 is a schematic view of a part of a process of forming a mask by using the mask forming method disclosed in the embodiment of the present application.
Description of the reference numerals:
100-substrate,
210-polystyrene block, 220-polymethyl methacrylate block,
310-barrier layer, 320-dielectric layer,
410-first anti-reflective coating, 420-second anti-reflective coating.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the technical solutions of the present application will be described in detail and completely with reference to the following specific embodiments of the present application and the accompanying drawings. It should be apparent that the described embodiments are only some of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Technical solutions disclosed in the embodiments of the present application are described in detail below with reference to the accompanying drawings.
As shown in fig. 1 and fig. 2, an embodiment of the present application discloses a mask forming method, by which a mask can be formed to provide a masking effect for a semiconductor device such as a wafer, and then a patterned trench can be formed in a corresponding region on the semiconductor device by etching or the like. In addition, the mask forming method disclosed in the embodiments of the present application can be applied to the process of manufacturing a semiconductor device with a relatively large process size (e.g., greater than 16 nm), and can also be applied to the process of manufacturing a semiconductor device with a relatively small process size (e.g., equal to or less than 16 nm).
In detail, the mask forming method disclosed in the embodiment of the present application includes:
s1, forming a mask layer with a patterned trench on the substrate 100, specifically, the substrate 100 may be a silicon substrate 100, and parameters such as a diameter and a size of the substrate may be determined according to actual requirements, which is not limited herein. The mask layer may specifically be a hard structure, which may include carbon element and/or silicon element, and the mask layer may be formed on the upper surface of the substrate 100 by deposition, and the dimensions of the mask layer, such as thickness, may be determined according to parameters, such as a selection ratio between the mask layer and the substrate 100, and a depth of a trench to be formed on the substrate 100. Then, a corresponding patterned trench can be formed on the mask layer by etching and the like, so as to prepare for etching work of a trench required to be formed on the semiconductor device. It should be noted that the size of the patterned trench formed on the mask layer, such as the width, is larger than the width of the trench to be formed on the semiconductor device, that is, the mask forming method disclosed in the embodiments of the present application has the capability of scaling the pattern.
After the step S1 is completed, the method for forming a mask disclosed in the embodiment of the present application further includes:
and S2, forming a block copolymer in the groove, specifically forming the block copolymer in the groove by adopting a directional self-assembly mode so as to obtain a pattern with high density and relatively small size (specifically sub-10 nm). In the mask forming method disclosed in the embodiment of the present application, the block copolymer includes a polystyrene block 210 and a polymethylmethacrylate block 220, and in the process of forming the block copolymer, the polystyrene block 210 is formed on the sidewall of the trench, and the polymethylmethacrylate block 220 is formed between adjacent polystyrene blocks 210, so that in the subsequent etching process, the purpose of further scaling the trench formed in advance on the mask layer by using the block copolymer can be achieved by removing the polymethylmethacrylate block 220.
The block copolymer is generally formed by connecting two monomer polymer chains with different chemical properties through covalent bonds, the connecting block has incompatibility chemically and is easy to self-assemble, and micro-phase separation can be carried out under the conditions of thermal annealing, solvent annealing, surface tension driving, hydrogen bond driving, hydrophilic/hydrophobic driving, electric field driving, magnetic field driving and the like, so that dense arrays with different ordered nanostructures are formed spontaneously. And, one block in the periodic structure is removed by an image transfer method (e.g., dry etching), so that the other block can be left as a mask when etching the substrate 100.
As described above, in the embodiment of the present application, the block copolymer formed in the trench includes the polystyrene block 210 and the polymethylmethacrylate block 220, which are chemically different. In the process of forming the block polymer, the planar shape and the size formed by a certain block (specifically, the polymethyl methacrylate block 220) to be removed are made to be the same as those of the trench to be formed on the substrate 100, that is, a corresponding etching gas is selected to remove a corresponding one of the two blocks and leave the other block as a mask when the substrate 100 is etched, so that the purpose of pattern transfer is achieved.
After forming the block copolymer in the trench, the mask forming method disclosed in the embodiment of the present application further includes:
s3, introducing etching gas, ionizing the etching gas to enable the etching gas to form plasma, and etching the specific type of block corresponding to the structure of the groove required to be formed on the substrate 100 in the block copolymer by using the plasma formed by the etching gas.
In more detail, when the two blocks in the block copolymer are made of the above-mentioned materials, the etching gas can include sulfur and oxygen to utilize the characteristic that the polystyrene does not contain oxygen and cannot be consumed by the sulfur in plasma state, while the polymethyl methacrylate block 220 can be consumed by the sulfur in plasma state and the oxygen in plasma state at the same time, so that the polymethyl methacrylate block 220 has a higher selectivity to the polystyrene block 210, which makes the etching rate of the polymethyl methacrylate block 220 much greater than that of the polystyrene block 210 during the etching process, and thus the polystyrene block 210 with a relatively large thickness can still be remained when the polymethyl methacrylate block 220 in the block copolymer is substantially completely removed. More specifically, in the above step S3, in the etching of the block copolymer using the ionized etching gas, the etching process may be stopped under conditions such that the polymethylmethacrylate block 220 in the block copolymer is substantially completely removed, thereby forming a "new trench" of relatively smaller size, the sidewall of which is substantially surrounded by the polystyrene block 210, within the trench in which the block copolymer is formed.
For polystyrene and polymethyl methacrylate, the reaction process between the polystyrene and the polymethyl methacrylate and the plasma state sulfur element and oxygen element generated by etching gas specifically comprises the following steps:
(C 8 H 8 ) n (s)+O·→CO x (g)+H 2 O(g)
(C 5 H 8 O 2 ) n (s)+S·+O·→CO x (g)+H 2 O(g)+SO x (g)
the etching process is performed in the process chamber, and during the etching process, the carbon and sulfur oxides formed after the polystyrene block 210 and the polymethyl methacrylate block 220 are etched can be exhausted out of the process chamber along with the exhausting process, and accordingly, the water vapor generated by the reaction can also be exhausted along with the exhausting process.
The embodiment of the application discloses a mask forming method, by which a mask layer with a required structure can be formed on a substrate 100, and then, a trench structure formed on the mask layer can be transferred onto the substrate 100 by pattern transfer modes such as etching and the like, so as to form a semiconductor device with the required structure. When the mask forming method disclosed in the embodiment of the present application is performed, a mask layer is formed on a substrate 100, and a patterned trench is formed on the mask layer, where the patterned trench has a relatively large size, such as width, and the mask layer can be formed on the substrate 100 by using a conventional photolithography technique; then, a block copolymer can be formed in the trench, and the polystyrene block 210 in the block copolymer is formed on the sidewall of the trench, so that the polymethyl methacrylate block 220 in the block copolymer is formed between the adjacent polystyrene blocks 210, obviously, the space occupied by the polymethyl methacrylate block 220 in the block copolymer formed in the patterned trench on the mask layer is obviously smaller than the space occupied by the patterned trench on the mask layer; and then, by ionizing the etching gas containing the sulfur element and the oxygen element, the polystyrene block 210 and the polymethyl methacrylate block 220 in the block copolymer can be etched together until the polymethyl methacrylate block 220 is removed, and because the plasma sulfur ionized by the etching gas can not react with the polystyrene block 210, the two blocks have a high selection ratio, so that in the process of etching the block copolymer, when the polymethyl methacrylate block 220 is basically and completely etched and removed, the polystyrene block 210 with a relatively large thickness can still be reserved, the polystyrene block 210 can be used as a mask in the subsequent etching process, the width size of a patterned groove on the mask layer is further reduced, the purpose of pattern scaling is realized, and further, in a process of 16nm or even smaller, a pattern transfer function is provided for a semiconductor device such as a wafer, and the like, so as to form an etched pattern with a smaller critical size on the semiconductor device.
As described above, the etching gas includes elemental sulfur and elemental oxygen, and optionally, the etching gas includes a gas containing elemental oxygen alone and a gas containing elemental sulfur alone. In order to avoid introducing other elements as much as possible and to interfere with the etching process, in a specific embodiment of the present application, the etching gas includes sulfur dioxide, and in this case, the plasma generated by ionizing the etching gas only includes oxygen plasma and sulfur plasma, which can improve the etching precision.
In the process of etching the block copolymer formed in the patterned trench of the mask layer, the flow range of sulfur dioxide can be controlled between 60 sccm and 150sccm, in this case, the etching rate of the polymethyl methacrylate block 220 in the block copolymer is relatively high, and the ionization and reaction completeness of the sulfur dioxide is relatively high, so that the high etching efficiency and the low etching cost are both considered.
Furthermore, in the process of etching the block copolymer, the etching temperature in the process chamber can be controlled to be between 30 and 60 ℃, the range of the process pressure intensity in the process chamber can be controlled to be between 8 and 20mtorr, and the range of the excitation power is controlled to be between 500 and 800W, so that the ionization degree of etching gas is improved, and the etching efficiency of the block copolymer is improved; moreover, the bias power can be controlled within a range of 40-70W, so that the degree of longitudinal (i.e. depth direction) etching can be increased to a certain extent, and the etching process can be ensured to be continuously carried out to a deep position as far as possible. With the above parameter ranges of the process recipe, the etching efficiency of the polymethylmethacrylate block 220 in the block copolymer is relatively high.
In addition, in the etching process, the etching time can be in the range of 60 to 80 seconds, and in this case, after the polymethylmethacrylate block 220 in the block polymer is completely etched and removed, the polystyrene block 210 with the remaining thickness can be basically ensured to be used as a mask of the substrate 100 with the conventional thickness, so that the patterned trench (formed by polystyrene clamp) on the mask layer can be transferred to the substrate 100, and a trench with the required depth is formed on the substrate 100. Of course, if the thickness of the substrate 100 is relatively irregular or the depth of the trench to be formed in the substrate 100 is not a regular dimension, the etching time can be selected accordingly according to the actual situation.
As described above, only the etching gas may be introduced during the etching of the block copolymer. In another embodiment of the present application, optionally, in the process of etching the block copolymer, an auxiliary gas is further introduced, where the auxiliary gas specifically includes oxygen and helium, and the helium can increase the total amount of gas in the process chamber, so that the distribution of the etching gas in the process chamber is more uniform, and further, the etching uniformity of different regions on the block copolymer is improved. The oxygen gas may ionize the oxygen plasma such that the oxygen ionized oxygen plasma can participate in the etching of the polystyrene blocks 210 and the polymethylmethacrylate blocks 220. In the case where the ratio of oxygen plasma to sulfur plasma is greater than 2:1, the etch rate can be increased to some extent. Of course, neither the helium nor the oxygen flow rates during the introduction of the auxiliary gas should be excessive. Specifically, the flow rate of oxygen can be in the range of 5-10 sccm, which can provide a positive effect on the etching rate; and the flow range of the helium gas is between 10 and 50sccm, so that the distribution uniformity of the etching gas in the process chamber is improved under the condition that the process pressure and the flow of the etching gas are not influenced as much as possible.
In addition, under the influence of actual requirements and the like, the density of trenches required to be formed in different regions of the semiconductor device may be different, and by forming the mask by using the mask forming method disclosed in any of the above embodiments, it may be ensured that the etching rates of the patterned trenches having different densities (formed by the polystyrene block 210 in a clamping manner) in the mask layer formed on the substrate 100 are substantially the same.
In detail, when the block copolymer is etched by the mask forming method using the above process recipe, it is tested that the etching rates of the polymethylmethacrylate block 220 and the polystyrene block 210 are respectively the same for the region of the mask layer where relatively dense trenches are to be formed
And
the selectivity ratio is 3.34, and the etch rates of the polymethylmethacrylate block 220 and the polystyrene block 210 are respectively the same for the regions of the mask layer where relatively sparse trenches are to be formed
And
the selectivity is 3.22, and obviously, the selectivities of the polymethyl methacrylate and the polystyrene in the two types of regions are equivalent, so that when the mask is formed by using the mask forming method disclosed in the above embodiment of the present application, the etching rates of the regions with different trench densities on the mask can be basically ensured to be equivalent.
In the above embodiments, the mask layer may be formed using a hard material including silicon element and/or carbon element, and the mask layer may be directly formed on the substrate 100. In another embodiment of the present application, the step S1 may include:
s11, forming a barrier layer 310 on the substrate 100, wherein the barrier layer 310 is made of tetraethyl silicate silicon oxide, and further, the barrier layer 310 is used for blocking an etching process. Specifically, in the case where the barrier layer 310 made of the above material is provided, the etching gas including sulfur dioxide is prevented from etching the barrier layer, thereby preventing the etching gas including sulfur dioxide from having an etching effect on the substrate 100. That is, after the polymethyl methacrylate block 220 in the front-stage copolymer is completely etched and removed, the etching process of the block copolymer cannot be stopped at the corresponding etching time due to factors such as errors in the etching rate, and the plasma formed by ionization of the etching gas is prevented from generating an etching effect on the substrate 100, so that the odd-even effect is prevented, and the subsequent etching precision is prevented from being adversely affected. Specifically, the barrier layer 310 may be formed on the substrate 100 by deposition, and parameters such as the thickness of the barrier layer 310 may be determined according to parameters such as the thickness of the block copolymer and the substrate 100, which is not limited herein.
Based on the step S11, the step S1 further includes:
s12, forming a mask layer with a patterned trench on a side of the barrier layer 310 away from the substrate 100, that is, in this embodiment, the barrier layer 310 is sandwiched between the mask layer and the substrate 100.
Under the condition of adopting the technical scheme, the block copolymer can be etched by using the etching gas containing sulfur dioxide until the polymethyl methacrylate block 220 in the block copolymer is completely removed, then the barrier layer 310 can be continuously etched by replacing other types of etching gas, and the polystyrene block 210 and the like are etched in the etching process of the barrier layer 310, so that the pattern is transferred between the mask layer and the barrier layer 310, and then the barrier layer 310 is used as the mask to continuously etch, so that the pattern can be transferred to the substrate 100.
Further, considering that the similarity between the chemical properties of the barrier layer 310 and the substrate 100 is relatively high, and the selectivity between the two is relatively low during etching, which results in a relatively great difficulty in transferring the pattern on the barrier layer 310 onto the substrate 100, the step S11 further includes:
forming a dielectric layer 320 on the substrate 100, wherein the material of the dielectric layer 320 is nitrogen-doped silicon carbide; and
a barrier layer 310 is formed on the side of dielectric layer 320 facing away from substrate 100.
Under the condition of adopting the technical scheme, the dielectric layer 320 is clamped between the substrate 100 and the barrier layer 310, so that the image transfer work is assisted by the dielectric layer 320, the difficulty of the image transfer work, namely the etching process is reduced, and the etching precision can be improved.
Specifically, the dielectric layer 320 may also be formed on the substrate 100 by deposition, and the parameters such as the thickness of the dielectric layer 320 may be determined comprehensively according to the depth of the trench to be formed on the substrate 100 and the parameters such as the thickness of the dielectric layer 320, which are not limited herein. More specifically, the barrier layer 310 and the dielectric layer 320 can be deposited by a plasma enhanced chemical vapor deposition method, so that the thickness and the composition uniformity of the barrier layer 310 and the dielectric layer 320 are relatively good, and the etching precision is further improved.
As mentioned above, the mask layer may comprise a carbon-containing and/or silicon-containing hard mask layer, and in one embodiment of the present application, optionally, the mask layer comprises the first anti-reflective coating 410, and the first anti-reflective coating 410 comprises a carbon element, based on which the step S1 comprises:
s21, sequentially forming a first anti-reflective coating 410 and a photoresist layer on the substrate 100, specifically, the first anti-reflective coating 410 may be formed on the upper surface of the substrate 100 by deposition, and the photoresist layer may be formed on the surface of the first anti-reflective coating 410 away from the substrate 100 by spin coating, and the like. Alternatively, the first anti-reflective coating 410 may be a Spin-On-Carbon hard mask (SOC) whose main component is a high C content polymer. The method has the following functions: flattening the rugged substrate or filling the grooves or through holes formed in the substrate, wherein the rugged substrate has a certain function of eliminating substrate reflection; in the photolithography process of the advanced process, the thickness of the photoresist is small, and the requirement of etching stop cannot be met only by covering the photoresist.
After step S21, step S1 further includes:
s22, exposing the photoresist layer to form a first intermediate piece, wherein the first intermediate piece includes a patterned photoresist layer, that is, the photoresist layer can be processed into the patterned photoresist layer through exposure and development, so as to facilitate the first anti-reflective coating 410 to be formed into a patterned mask layer;
then, the step S1 further includes:
s23, etching the first intermediate until the pattern of the photoresist layer extends to the bottom of the first anti-reflective coating 410, so as to form a mask layer having a patterned trench on the substrate 100. Specifically, the thicknesses of the photoresist layer and the first anti-reflective coating layer 410 to be formed may be correspondingly determined according to parameters such as the depth of the trench to be formed on the substrate 100, and then, the patterned photoresist layer may be removed by photolithography, and the pattern on the photoresist layer may be transferred onto the first anti-reflective coating layer 410.
Considering that the selection ratio between the first anti-reflective coating 410 and the photoresist layer is relatively high, optionally, the mask layer further includes a second anti-reflective coating 420, and the second anti-reflective coating 420 is sandwiched between the substrate 100 and the first anti-reflective coating 410. Alternatively, the second anti-reflective coating 420 can be a Si-containing anti-reflective coating (Si-ARC), the primary material of which is an organosiloxane (organosiloxane), which can serve to reduce reflection and standing wave problems.
Correspondingly, based on the mask layer with the above structure, the step S21 includes:
a first anti-reflection coating 410, a second anti-reflection coating 420, and a photoresist layer are sequentially formed on the substrate 100. Specifically, the first anti-reflective coating 410 may be formed on the upper surface of the substrate by deposition, and then the second anti-reflective coating 420 may be formed on the surface of the first anti-reflective coating 410 facing away from the substrate 100 by deposition, and then a photoresist layer may be formed on the side surface of the second anti-reflective coating 420 facing away from the first anti-reflective coating 410 by spin coating or the like.
Correspondingly, the step S23 includes:
and etching the first intermediate piece until the photoresist layer is removed to form a second intermediate piece. Specifically, when the photoresist layer in the first intermediate member is etched away, the pattern on the photoresist layer may be transferred along with the etching process, and the pattern is affected by the specific material of the second anti-reflective coating layer 420, and when the photoresist layer is etched away, the pattern on the photoresist layer may still extend on the second anti-reflective coating layer 420, that is, the second anti-reflective coating layer 420 is not etched through, or it may also occur that the second anti-reflective coating layer 420 is etched through when the photoresist layer is removed, so that the pattern on the photoresist layer has already extended onto the first anti-reflective coating layer 410, which is not limited herein.
After the photoresist layer is etched and removed, step S23 in the etching process further includes:
the second intermediate is etched until the pattern of the photoresist layer extends to the bottom of the first anti-reflective coating layer 410 to form a mask layer having a patterned trench on the substrate 100. Of course, in order to ensure the normal operation of the subsequent etching process, in the case that the pattern of the photoresist layer extends to the bottom of the first anti-reflective coating 410, the second anti-reflective coating 420 still has to be remained, i.e., the mask layer is ensured to include the first anti-reflective coating 410 and the second anti-reflective coating 420, so that the two are used as a mask in the process of etching the block copolymer.
Based on the mask forming method disclosed in any of the above embodiments, the embodiments of the present application further disclose a semiconductor device processing method, and the semiconductor device processing method forms a mask by using the mask forming method disclosed in any of the above embodiments to perform processing. That is, in the process of processing a semiconductor device, a mask may be formed on the substrate 100 for forming the semiconductor device by using the mask forming method disclosed in any of the above embodiments, and then, the substrate 100 and the mask are etched by using a corresponding etching gas, so that the patterned trench formed by the polymethyl methacrylate on the mask and having a smaller size may be transferred onto the substrate 100, so as to finally form the semiconductor device.
In the embodiments of the present application, the differences between the embodiments are described in emphasis, and different optimization features between the embodiments can be combined to form a better embodiment as long as the differences are not inconsistent, and further description is omitted here in view of brevity of the text.
The above description is only an example of the present application and is not intended to limit the present application. Various modifications and changes may occur to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.
Claims (10)
1. A mask forming method, comprising:
forming a mask layer with a patterned groove on a substrate;
forming a block copolymer within the trench, wherein the block copolymer comprises a polystyrene block formed on a sidewall of the trench, and a polymethylmethacrylate block located between adjacent polystyrene blocks;
and introducing etching gas, and etching the block copolymer after ionization until the polymethyl methacrylate block is removed, wherein the etching gas comprises sulfur and oxygen.
2. The mask forming method according to claim 1, wherein the etching gas comprises sulfur dioxide, and a flow rate of the sulfur dioxide ranges from 60 to 150 seem during the etching of the block copolymer.
3. The mask forming method according to claim 2, wherein during the etching of the block copolymer, the etching temperature is in the range of 30 to 60 ℃, the process pressure is in the range of 8 to 20mtorr, the excitation power is in the range of 500 to 800W, the bias power is in the range of 40 to 70W, and the etching time is in the range of 60 to 80s.
4. The mask forming method according to claim 2, wherein an auxiliary gas is further introduced during the etching of the block copolymer, the auxiliary gas including oxygen and helium, the flow rate of the oxygen being in a range of 5 to 10sccm, and the flow rate of the helium being in a range of 10 to 50sccm.
5. The mask forming method according to claim 1,
the forming of the mask layer with the patterned trench on the substrate includes:
forming a barrier layer on a substrate, wherein the barrier layer is made of tetraethyl silicate silicon oxide;
and forming a mask layer with a patterned groove on one side of the barrier layer, which is far away from the substrate.
6. The mask forming method according to claim 5,
the forming a barrier layer on a substrate includes:
forming a dielectric layer on a substrate, wherein the dielectric layer is made of nitrogen-doped silicon carbide;
and forming a barrier layer on one side of the dielectric layer, which is far away from the substrate.
7. The method as claimed in claim 6, wherein the barrier layer and the dielectric layer are deposited by PECVD.
8. The mask forming method according to claim 1, wherein the mask layer includes a first anti-reflective coating including an element of carbon;
the forming of the mask layer with the patterned trench on the substrate includes:
sequentially forming the first anti-reflection coating and a photoresist layer on the substrate;
exposing the photoresist layer to form a first intermediate piece, wherein the first intermediate piece comprises a patterned photoresist layer;
and etching the first intermediate piece until the pattern of the photoresist layer extends to the bottom of the first anti-reflection coating so as to form a mask layer with a patterned groove on the substrate.
9. The mask forming method according to claim 8, wherein the mask layer further comprises a second antireflection coating, the second antireflection coating being laminated on a side of the first antireflection coating facing away from the substrate, the second antireflection coating comprising silicon element;
the sequentially forming the first anti-reflection coating and the photoresist layer on the substrate comprises:
sequentially forming a first anti-reflection coating, a second anti-reflection coating and a photoresist layer on the substrate;
the etching the first intermediate piece until the pattern of the photoresist layer extends to the bottom of the first anti-reflection coating comprises the following steps:
etching the first intermediate piece until the photoresist layer is removed to form a second intermediate piece;
and etching the second intermediate piece until the pattern of the photoresist layer extends to the bottom of the first anti-reflection coating so as to form a mask layer with a patterned groove on the substrate.
10. A semiconductor device processing method characterized in that processing is performed by forming a mask by the mask forming method claimed in any one of claims 1 to 9.
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| CN202211345849.3A CN115602533A (en) | 2022-10-31 | 2022-10-31 | Mask forming method and semiconductor device processing method |
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| CN202211345849.3A CN115602533A (en) | 2022-10-31 | 2022-10-31 | Mask forming method and semiconductor device processing method |
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