CN115602083A

CN115602083A - Display panel, detection method thereof and display device

Info

Publication number: CN115602083A
Application number: CN202211326084.9A
Authority: CN
Inventors: 李玥; 程琳; 周星耀; 张蒙蒙; 杨帅
Original assignee: Xiamen Tianma Microelectronics Co Ltd
Current assignee: Xiamen Tianma Microelectronics Co Ltd
Priority date: 2019-12-24
Filing date: 2019-12-24
Publication date: 2023-01-13
Also published as: CN110910803B; CN110910803A

Abstract

In a short-circuit bar structure in the display panel, a first circuit unit and a second circuit unit share a first transmission signal line so as to respectively transmit signals to the first circuit unit and the second circuit unit through the first transmission signal line. And arranging the first transmission signal line between the first circuit unit and the second circuit unit so that only one transmission signal line of the plurality of transmission signal lines, namely the first transmission signal line, is arranged between the first circuit unit and the second circuit unit. Therefore, the difference between the resistance between the first circuit unit and the fan-out line and the difference between the resistance between the second circuit unit and the fan-out line is reduced, so that the difference of the voltages input into the same-color sub-pixels in different rows is reduced, the problem of vertical stripes of a pure-color picture is solved, and the display effect of the pure-color picture is improved.

Description

Display panel, detection method thereof and display device

The application is a divisional application, the application number of the original application is 201911348638.3, the date of the original application is 2019, 12 and 24, and the whole content of the original application is incorporated into the application by reference.

Technical Field

The present invention relates to the field of display technologies, and in particular, to a display panel, a detection method thereof, and a display device.

Background

With the continuous development of display technologies, the application range of display panels is wider and wider, and people have higher and higher requirements on the display panels. In particular, the display quality of the display panel is always one of the important indicators for the quality of the display panel for consumers and panel manufacturers. Therefore, how to detect the display panel is an urgent technical problem to be solved by those skilled in the art.

Disclosure of Invention

The embodiment of the invention provides a display panel, a detection method thereof and a display device, which are used for improving the display effect.

An embodiment of the present invention provides a display panel, including: a substrate having a display region and a non-display region; the non-display area includes: a fan-out region and a bonding region;

the fan-out region includes: a plurality of fan-out lines; the fan-out area is arranged between the display area and the binding area;

the binding region includes: a shorting bar structure and a plurality of input terminals; wherein one of the input terminals is electrically connected with one fanout line;

the shorting bar structure includes: a plurality of transmission signal lines extending in a first direction, a plurality of output lines extending in a second direction, and a first circuit unit, a second circuit unit, and a third circuit unit arranged in the second direction; the first circuit unit, the second circuit unit and the third circuit unit are respectively electrically connected with different output lines; one of the output lines is electrically connected to one of the input terminals;

the plurality of transmission signal lines include: a first transmission signal line; the first circuit unit and the second circuit unit share a first transmission signal line, and the first transmission signal line is arranged between the first circuit unit and the second circuit unit.

The embodiment of the invention also provides a display device which comprises the display panel.

The embodiment of the invention also provides a detection method of the display panel, which comprises the following steps:

when the display panel displays a pure color picture, lightening the sub-pixels of the corresponding colors;

loading a bright-state signal to the first transmission signal line, loading a dark-state signal to the second transmission signal line and the third transmission signal line respectively, loading corresponding control signals to the first control signal line to the fifth control signal line respectively, and lighting the first color sub-pixel or the third color sub-pixel;

and loading dark-state signals to the first transmission signal line and the second transmission signal line, loading bright-state signals to the third transmission signal line, and respectively loading corresponding control signals to the first control signal line to the fifth control signal line to light a second color sub-pixel.

The invention has the following beneficial effects:

in the display panel, the detection method thereof and the display device provided by the embodiment of the invention, the shorting bar structure in the display panel is provided with the first circuit unit, the second circuit unit and the third circuit unit which are sequentially arranged along the second direction, and the first circuit unit and the second circuit unit share one first transmission signal line, so that signals can be respectively transmitted to the first circuit unit and the second circuit unit through the first transmission signal line. And by arranging the first transmission signal line between the first circuit unit and the second circuit unit, only one transmission signal line of the plurality of transmission signal lines, that is, the first transmission signal line, can be arranged between the first circuit unit and the second circuit unit. Therefore, the difference between the resistance between the first circuit unit and the fan-out line and the resistance between the second circuit unit and the fan-out line is reduced, the difference between the RC loading between the first circuit unit and the fan-out line and the RC loading between the second circuit unit and the fan-out line is reduced, the difference of voltages input into the same-color sub-pixels in different rows is reduced, the problem of vertical stripes of a pure-color picture can be improved, and the display effect of the pure-color picture is improved.

Drawings

Fig. 1 is a schematic structural diagram of a display panel in the related art;

FIG. 2 is a schematic diagram of a display panel according to the related art;

FIG. 3 is a signal timing diagram corresponding to the display panel shown in FIG. 2;

FIG. 4 is a schematic view of a layout structure corresponding to the display panel shown in FIG. 2;

FIG. 5 is a schematic structural diagram of a display panel according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of a specific structure of a display panel according to an embodiment of the present invention;

FIG. 7 is a schematic diagram of another exemplary embodiment of a display panel;

FIG. 8 is a schematic structural diagram of another display panel according to an embodiment of the present invention;

FIG. 9 is a schematic view of a layout structure corresponding to the display panel shown in FIG. 8;

FIG. 10 is a schematic structural diagram of another display panel according to an embodiment of the present invention;

FIG. 11 is a flowchart illustrating a method for inspecting a display panel according to an embodiment of the present invention;

FIG. 12 is a timing diagram of a display panel according to an embodiment of the present invention;

FIG. 13 is a flowchart illustrating a method for inspecting a display panel according to another embodiment of the present invention;

FIG. 14 is a timing diagram of still another signal corresponding to the display panel in the embodiment of the present invention;

fig. 15 is a schematic structural diagram of a display device in an embodiment of the invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the drawings of the embodiments of the present invention. It is to be understood that the embodiments described are only a few embodiments of the present invention, and not all embodiments. And the embodiments and features of the embodiments may be combined with each other without conflict. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the invention without inventive step, are within the scope of protection of the invention.

Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. The use of "first," "second," and similar terms in the present application do not denote any order, quantity, or importance, but rather the terms are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item preceding the word comprises the element or item listed after the word and its equivalent, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

It should be noted that the sizes and shapes of the figures in the drawings are not to be considered true scale, but are merely intended to schematically illustrate the present invention. And like reference numerals refer to like or similar elements or elements having like or similar functions throughout.

After the display panel is manufactured, a Visual Test (VT) is generally performed, and in the VT Test, a data signal is generally input to the display panel through a shorting bar structure, so that a pure color picture is displayed. Generally, the shorting bar structure may be disposed in a fan-out region of the display panel. However, the traces in the fan-out area are very densely distributed, so that the shorting bar structure can cause signal interference to the traces in the fan-out line. In order to improve the interference of the shorting bar structure on the wiring in the fan-out area, the shorting bar structure may be disposed in the bonding area of the display panel.

As shown in fig. 1 and fig. 2, the display panel may include a display area A1, a fan-out area A2, and a bonding area A3; the display area A1 may have a plurality of data lines 10, a plurality of gate lines GA, a plurality of red subpixels R, a plurality of green subpixels G, and a plurality of blue subpixels B. The fan-out area A2 may have a plurality of fan-out lines 20. The bonding area A3 has a plurality of input terminals 30 and a shorting bar structure 40. One data line 10 is electrically connected to one fanout line 20, one fanout line 20 is electrically connected to one input terminal 30, and the shorting bar structure 40 is electrically connected to each input terminal 30. That is, the shorting bar structure 40 is electrically connected to the data line 10 through the input terminal 30 and the fanout line 20.

As shown in fig. 2, the shorting bar structure 40 may include: control lines CW1, CW2, and CW3, transmission lines CR-1, CR-2, CB-1, CB-2, CG, a plurality of transistors M01, a plurality of transistors M02, a plurality of transistors M03, a plurality of transistors M04, and a plurality of transistors M05. One transistor M01 and one transistor M02 are electrically connected to one data line 10, one transistor M03 is electrically connected to one data line 10, and one transistor M04 and one transistor M05 are electrically connected to one data line 10.

The gates of all transistors M01 and M04 are connected to the control line CW1, the gates of all transistors M02 and M05 are connected to the control line CW2, and the gates of all transistors M03 are connected to the control line CW3.

A first pole of each transistor M01 is electrically connected to the transmission line CR-1, and a second pole of each transistor M01 is electrically connected to the corresponding data line 10.

A first pole of each transistor M02 is electrically connected to the transmission line CB-1, and a second pole of each transistor M02 is electrically connected to the corresponding data line 10.

A first pole of each transistor M03 is electrically connected to the transmission line CG, and a second pole of each transistor M03 is electrically connected to the corresponding data line 10.

A first pole of each transistor M04 is electrically connected to the transmission line CB-2, and a second pole of each transistor M04 is electrically connected to the corresponding data line 10.

A first pole of each transistor M05 is electrically connected to the transmission line CR-2, and a second pole of each transistor M05 is electrically connected to the corresponding data line 10.

The transistors M01 to M05 may be N-type transistors.

Fig. 3 shows a timing diagram of signals corresponding to the shorting bar structure 40 in the display panel shown in fig. 2. Here, CW1 in fig. 3 represents a signal transmitted on the control line CW1, CW2 represents a signal transmitted on the control line CW2, and a high-level signal of a fixed voltage is transmitted on the control line CW3. GA1 represents signals transmitted on the gate line GA to which the sub-pixels in the first row are electrically connected, and GA2 represents signals transmitted on the gate line GA to which the sub-pixels in the second row are electrically connected.

The example of inputting a data signal to the display panel using the shorting bar structure 40 to cause the display panel to display a red screen will be described.

In the period t01, when the signal ga1 is a high level signal, a Thin Film Transistor (TFT) in the first row of sub-pixels is turned on. When the signal ga2 is a low level signal, the tft in the second row of sub-pixels is turned off. Since the signal cw2 is a low level signal, all the transistors M02 and all the transistors M05 are turned off. A dark signal (e.g., 6V) is applied to the transmission line CG, and a high level signal of a fixed voltage is transmitted on the control line CW3, so that all the transistors M03 are turned on to supply the dark signal to the data line to which the green sub-pixels are electrically connected, so that the green sub-pixels in the first row input the dark signal, and the green sub-pixels do not emit light. Since the signal cw1 is a high level signal, all the transistors M01 and all the transistors M04 are turned on. And loading a dark state signal to the transmission line CB-2, and providing the dark state signal to the corresponding data line through the turned-on transistor M04, so that the blue sub-pixel in the first row inputs the dark state signal, and the blue sub-pixel does not emit light. A bright-state signal (for example, a bright-state signal of 3V) is applied to the transmission line CR-1, and the bright-state signal is supplied to the corresponding data line through the turned-on transistor M01, so that the bright-state signal is input to the red sub-pixel in the first row, and the red sub-pixel emits light to display red.

In the period t02, when the signal ga1 is a low level signal, the thin film transistors in the first row of sub-pixels are turned off. When the signal ga2 is a high level signal, the thin film transistor in the sub-pixel in the second row is turned on. Since the signal cw1 is a low level signal, all the transistors M01 and all the transistors M04 are turned off. A dark signal is applied to the transmission line CG, and a high level signal of a fixed voltage is transmitted on the control line CW3, so that all the transistors M03 are turned on to supply the dark signal to the data line to which the green sub-pixels are electrically connected, so that the green sub-pixels in the second row input the dark signal, and the green sub-pixels do not emit light. Since the signal cw2 is a high-level signal, all the transistors M02 and all the transistors M05 are turned on. A bright-state signal (for example, a bright-state signal of 3V) is applied to the transmission line CR-2, and the bright-state signal is provided to the corresponding data line through the turned-on transistor M04, so that the bright-state signal is input to the red sub-pixel in the second row, and the red sub-pixel emits light to display red. And loading a dark state signal to the transmission line CB-1, and providing the dark state signal to the corresponding data line through the turned-on transistor M02, so that the blue sub-pixel in the second row inputs the dark state signal, and the blue sub-pixel does not emit light.

In a similar way, the rest processes are analogized so that the red sub-pixels in the display panel all emit light, and the green sub-pixels and the blue sub-pixels do not emit light, so that the display panel can display pure-color red pictures. It should be noted that the working process of displaying the green image and the blue image on the display panel may be analogized, and details are not described herein.

Fig. 2 is a schematic diagram of a Layout (Layout) of the shorting bar structure, as shown in fig. 4. Referring to fig. 1 and 4, in a direction F2 along the fan-out area A2 toward the bonding area A3, the transmission line CR-2, the control line CW2-1, the control line CW1-1, the transmission line CB-2, the control line CW3, the transmission line CG, the transmission line CB-1, the control line CW2-2, the control line CW1-2, and the transmission line CR-1 are sequentially arranged. Wherein control line CW2-1 and control line CW2-2 are electrically interconnected to form control line CW2, and control line CW1-1 and control line CW1-2 are electrically interconnected to form control line CW1.

And, all transistors M05 are located between the transmission line CR-2 and the control line CW1-1, all transistors M04 are located between the transmission line CB-2 and the control line CW2-1, all transistors M03 are located between the transmission line CB-2 and the transmission line CG, all transistors M02 are located between the transmission line CB-1 and the control line CW1-2, and all transistors M01 are located between the transmission line CR-1 and the control line CW 2-2.

As can be seen from fig. 4, a transmission line CR-2 is provided between the transistor M05 and the fan-out line 20, and a transmission line is provided between the transistor M01 and the fan-out line 20: CR-2, CB-2, CG and CB-1, four transmission lines in total, that is, a transmission line is arranged between the transistor M05 and the transistor M01: CB-2, CG and CB-1, three transmission lines in total. In practical applications, in order to facilitate signal transmission and reduce the resistance of the transmission line, the transmission line is generally set to be wider, so that compared with the distance between the transistor M05 and the fan-out line 20, the distance between the transistor M01 and the fan-out line 20 is longer, and the resistance between the transistor M01 and the fan-out line 20 is larger than the resistance between the transistor M05 and the fan-out line 20, so that a load (RC Loading) between the transistor M01 and the fan-out line 20 is larger than the load between the transistor M05 and the fan-out line 20, and thus the voltage input into the red sub-pixel in the stage t01 may be smaller than the voltage input into the red sub-pixel in the stage t02, which will cause the light emitting luminance of the red sub-pixels in different columns to be different, and further cause a problem of vertical stripes in a red picture.

It should be noted that, when the display panel displays a blue image, the above problem of displaying a red image also occurs, and the principle is the same, which is not described herein again.

Since the display panel displays a pure color image through the shorting bar structure, the shorting bar structure is generally applied to detecting the quality of the display panel in the VT test stage. If a vertical stripe appears when the display panel displays a pure color picture through the short-circuit bar structure during the VT test, the display panel is classified into a class of defective products. However, if there is no other defect in the display panel, but the vertical stripes appear in the pure color picture due to the structure of the short bar shown in fig. 4, the resource waste and the cost increase will result.

Accordingly, the embodiment of the invention provides a display panel, which can solve the problem that vertical stripes appear in a pure-color picture due to a short-circuit bar structure.

As shown in fig. 5 to 9, the display panel provided in the embodiment of the present invention may include: a substrate base having a display area AA and a non-display area BB; the non-display area BB includes: a fan-out area B1 and a binding area B2;

the fan-out area B1 includes: a plurality of fanout lines 120; the fan-out area B1 is arranged between the display area AA and the binding area B2;

the binding region B2 includes: a shorting bar structure 140 and a plurality of input terminals 130; wherein, one input terminal 130 is electrically connected with one fanout line 120;

the shorting bar structure 140 includes: a plurality of transmission signal lines extending in the first direction F1, a plurality of output lines 150 extending in the second direction F2, and first, second, and third circuit units 140-1, 140-2, and 140-3 arranged in the second direction F2; the first circuit unit 140-1, the second circuit unit 140-2 and the third circuit unit 140-3 are electrically connected to different output lines 150, respectively; one output line 150 is electrically connected to one input terminal 130;

the plurality of transmission signal lines include: a first transmission signal line S1; the first circuit unit 140-1 and the second circuit unit 140-2 share a first transmission signal line S1, and the first transmission signal line S1 is disposed between the first circuit unit 140-1 and the second circuit unit 140-2.

In the display panel provided by the embodiment of the invention, the short-circuit bar structure in the display panel is provided with the first circuit unit, the second circuit unit and the third circuit unit which are sequentially arranged along the second direction, and the first circuit unit and the second circuit unit share one first transmission signal line, so that signals can be respectively transmitted to the first circuit unit and the second circuit unit through the first transmission signal line. And by arranging the first transmission signal line between the first circuit unit and the second circuit unit, only one transmission signal line of the plurality of transmission signal lines, that is, the first transmission signal line, can be arranged between the first circuit unit and the second circuit unit. Therefore, the difference between the resistance between the first circuit unit and the fan-out line and the difference between the resistance between the second circuit unit and the fan-out line is reduced, and the difference between the RC loading between the first circuit unit and the fan-out line and the RC loading between the second circuit unit and the fan-out line is reduced, so that the difference of voltages input into different rows of sub-pixels with the same color is reduced, the problem of vertical stripes of a pure color picture can be improved, and the display effect of the pure color picture is improved.

In specific implementation, in the embodiment of the present invention, as shown in fig. 5 to fig. 8, the display area AA may further include a plurality of sub-pixels arranged in an array and a plurality of display driving signal lines extending along the second direction F2; one column of sub-pixels is electrically connected to one display driving signal line, and one fanout line 120 is electrically connected to at least one display driving signal line. Illustratively, the display driving signal lines may include data lines 110 for transmitting data signals; one data line 110 is electrically connected to a column of sub-pixels. One data line 110 is electrically connected to one input terminal 130. The shorting bar structure 140 is electrically connected to the plurality of input terminals 130, one input terminal 130 is electrically connected to one fanout line 120, and one fanout line 120 is electrically connected to one data line 110. That is, the shorting bar structures 140 are electrically connected to the data lines 110, respectively.

Illustratively, the sub-pixel may include a light emitting device and a pixel driving circuit driving the light emitting device to emit light. Wherein, the light emitting device may include: 18. at least one of Organic Light Emitting Diodes (OLED) and Quantum Dot Light Emitting Diodes (QLED). Moreover, the general pixel driving circuit may include a plurality of transistors such as a driving transistor and a switching transistor, and a storage capacitor, and the specific structure and the operation principle thereof may be the same as those in the related art, which is not described herein again.

Illustratively, the plurality of sub-pixels may include a first color sub-pixel, a second color sub-pixel, and a third color sub-pixel. The first color, the second color, and the third color may be selected from red, green, and blue, and are not limited herein. For example, the first color may be set to red, the second color may be set to green, and the third color may be set to blue, so that the display panel may display a red pure color picture, a green pure color picture, and a blue pure color picture. In addition, when displaying a color image, the display panel may display an image by mixing red, green and blue colors.

In specific implementation, as shown in fig. 6 to 8, in the embodiment of the present invention, the 3n-2 th column of sub-pixels and the 3n th column of sub-pixels respectively include first color sub-pixels and third color sub-pixels that are alternately arranged, and the arrangement order of the first color sub-pixels and the third color sub-pixels in the 3n-2 th column of sub-pixels and the 3n th column of sub-pixels is opposite; and, the 3n-1 th column of subpixels includes second color subpixels arranged in sequence. Wherein n is an integer. It should be noted that, the display panels with different resolutions have different requirements on the number of sub-pixels, and therefore, the specific value of n may be designed according to the actual application environment, and is not limited herein.

For example, in practical implementation, in the embodiment of the present invention, as shown in fig. 6 to 8, in the 3n-2 th column of sub-pixels, the odd-numbered rows may be set as the first color sub-pixels, and the even-numbered rows may be set as the third color sub-pixels. In the 3 n-th column of sub-pixels, the odd rows are the third color sub-pixels, and the even rows are the first color sub-pixels. The following description will take the first color sub-pixel as the red sub-pixel R, the second color sub-pixel as the green sub-pixel G, and the third color sub-pixel as the blue sub-pixel B. Exemplarily, as shown in fig. 6 to 8, in a direction indicated by an arrow in the first direction F1, taking n =1 and n =2 as an example, there are a1 st column sub-pixel, a2 nd column sub-pixel, a3 rd column sub-pixel, a 4 th column sub-pixel, a 5 th column sub-pixel, and a 6 th column sub-pixel. The arrangement modes of the sub-pixels in the 1 st column sub-pixel and the 4 th column sub-pixel are the same, the arrangement modes of the sub-pixels in the 2 nd column sub-pixel and the 5 th column sub-pixel are the same, and the arrangement modes of the sub-pixels in the 3 rd column sub-pixel and the 6 th column sub-pixel are the same. In the 1 st column of sub-pixels, the odd row of sub-pixels are red sub-pixels R, and the even row of sub-pixels are blue sub-pixels B. Each sub-pixel in the 2 nd column of sub-pixels is a green sub-pixel G. In the 3 rd column of sub-pixels, the sub-pixels in the odd rows are the blue sub-pixels B, and the sub-pixels in the even rows are the red sub-pixels R. Of course, in practical applications, the arrangement of the sub-pixels of each color may be designed and determined according to practical application environments, and is not limited herein.

In practical implementation, as shown in fig. 6 to 8, in the embodiment of the present invention, the first circuit unit 140-1 is close to the display area AA, the third circuit unit 140-3 is located on a side of the first circuit unit 140-1 away from the display area AA, and the second circuit unit 140-2 is located between the first circuit unit 140-1 and the second circuit unit 140-2. This allows the first circuit unit 140-1, the second circuit unit 140-2, and the third circuit unit 140-3 to be sequentially arranged in the direction indicated by the arrow of the first direction F1. In addition, the third circuit unit may correspond to a row of subpixels of the same color, so that a switching signal does not need to be input to the third transmission signal line, and the third circuit unit may be disposed at the lowermost portion of the display panel because the switching signal does not need to be input thereto, thereby avoiding a space, and reasonably disposing the first circuit unit and the second circuit unit in the avoided space.

In specific implementation, in the embodiment of the present invention, as shown in fig. 6 to 9, the plurality of transmission signal lines may further include: a second transmission signal line S2 and a third transmission signal line S3. The second transmission signal line S2 includes: a first sub transmission signal line S2-1 and a second sub transmission signal line S2-2; the first sub-transmission signal line S2-1 is electrically connected with the first circuit unit 140-1, and the second sub-transmission signal line S2-2 is electrically connected with the second circuit unit 140-2; the first sub-transmission signal line S2-1 is located on a side of the first circuit unit 140-1 away from the first transmission signal line S1, and the second sub-transmission signal line S2-2 is located between the second circuit unit 140-2 and the third circuit unit 140-3. This also enables transmission of a data signal to the first circuit unit 140-1 through the first sub transmission signal line S2-1 and also enables transmission of a data signal to the second circuit unit 140-2 through the second sub transmission signal line S2-2. Moreover, by positioning the first sub-transmission signal line S2-1 on the side of the first circuit unit 140-1 away from the first transmission signal line S1 and positioning the second sub-transmission signal line S2-2 between the second circuit unit 140-2 and the third circuit unit 140-3, only one first transmission signal line S1 can be disposed between the first circuit unit 140-1 and the second circuit unit 140-2, and the remaining transmission signal lines are no longer disposed.

In practical implementation, in the embodiment of the present invention, as shown in fig. 6 to 9, the third transmission signal line S3 may be electrically connected to the third circuit unit 140-3. This may transmit the data signal to the third circuit unit 140-3 through the third transmission signal line S3.

For example, in practical implementation, in the embodiment of the present invention, as shown in fig. 6 to 9, the third transmission signal line S3 may be located on a side of the third circuit unit 140-3 away from the second circuit unit 140-2. This makes it possible to keep the third circuit unit 140-3 away from the edge of the substrate base, thereby preventing damage to the third circuit unit 140-3 when the substrate base is cut. In addition, the third transmission signal line S3 may also be used as an electrode for shielding static electricity, so that static electricity around the display panel may be prevented from causing electrostatic interference with the third circuit unit 140-3.

For example, in practical implementation, in the embodiment of the present invention, the third transmission signal line S3 may be located between the third circuit unit 140-3 and the second sub-transmission signal line S2-2. Therefore, the third transmission signal wire S3 and the second sub-transmission signal wire S2-2 can be designed to be closer, so that the wiring design is facilitated, and the process preparation difficulty is reduced.

Illustratively, in implementation, in the embodiment of the present invention, as shown in fig. 6 to 8, the first circuit unit 140-1 may be made to include: a plurality of first sub-circuit units 141, a first control signal line SW1, and a second control signal line SW2; one first sub-circuit unit 141 corresponds to one column of sub-pixels in the 3 nth column of sub-pixels, and the output line 150 corresponding to the first sub-circuit unit 141 is electrically connected to the display driving signal line of the corresponding column of sub-pixels. Exemplarily, the 3 rd column of sub-pixels corresponds to one first sub-circuit unit 141, and the output line 150 corresponding to the first sub-circuit unit 141 is electrically connected to the data line 110 corresponding to the 3 rd column of sub-pixels. The 6 th column of sub-pixels corresponds to a first sub-circuit unit 141, and the output line 150 corresponding to the first sub-circuit unit 141 is electrically connected to the data line 110 corresponding to the 6 th column of sub-pixels.

Illustratively, in implementation, in an embodiment of the present invention, as shown in fig. 6 to 9, the first sub-circuit unit 141 may include: a first transistor M1 and a second transistor M2;

the gates of all the first transistors M1 are electrically connected with the first control signal line SW1, the sources of all the first transistors M1 are electrically connected with the first transmission signal line S1, the gates of all the second transistors M2 are electrically connected with the second control signal line SW2, and the sources of all the second transistors M2 are electrically connected with the first sub-transmission signal line S2-1; in the same first sub-circuit unit 141, the drains of the first transistor M1 and the second transistor M2 are electrically connected to the corresponding output line 150.

The drain of the first transistor M1 and the drain of the second transistor M2 are electrically connected to the input terminal 130 via the corresponding output line 150, so that the drain of the first transistor M1 and the drain of the second transistor M2 are electrically connected to the corresponding data line 110 via the corresponding output line 150, the input terminal 130, and the fanout line 120 in this order.

For example, in practical implementation, the first transistor M1 may be in a conducting state under the control of the on signal on the first control signal line SW1, so that the signal on the first transmission signal line S1 may be provided to the corresponding data line 110. The first transistor M1 may be in an off state under the control of an off signal on the first control signal line SW 1. Further, the first transistor M1 may be an N-type transistor, or the first transistor M1 may also be a P-type transistor. Of course, in practical applications, the specific type of the first transistor M1 may be determined according to practical application environments, and is not limited herein.

For example, in practical implementation, the second transistor M2 may be in a conducting state under the control of an on signal on the second control signal line SW2, so that a signal on the first sub-transmission signal line S2-1 may be provided to the corresponding data line 110. The second transistor M2 may be in an off state under the control of an off signal on the second control signal line SW 2. Further, the second transistor M2 may be an N-type transistor, or the second transistor M2 may also be a P-type transistor. Of course, in practical applications, the specific type of the second transistor M2 may be determined according to practical application environments, and is not limited herein.

Illustratively, in implementation, in an embodiment of the present invention, as shown in fig. 6 to 8, the second circuit unit 140-2 may include: a plurality of second sub-circuit units 142, a third control signal line SW3, and a fourth control signal line SW4; one second sub-circuit unit 142 corresponds to one column of sub-pixels in the 3n-2 th column of sub-pixels, and the output line 150 corresponding to the second sub-circuit unit 142 is electrically connected to the display driving signal line of the corresponding column of sub-pixels. Illustratively, the sub-pixel of the 1 st column corresponds to one second sub-circuit unit 142, and the second sub-circuit unit 142 is electrically connected to the data line 110 corresponding to the sub-pixel of the 1 st column.

Illustratively, in practical implementation, in the embodiment of the present invention, as shown in fig. 6 to 8, the second sub-circuit unit 142 includes: a third transistor M3 and a fourth transistor M4;

the gates of all the third transistors M3 are electrically connected to the third control signal line SW3, the sources of all the third transistors M3 are electrically connected to the first transmission signal line S1, the gates of all the fourth transistors M4 are electrically connected to the fourth control signal line SW4, and the sources of all the fourth transistors M4 are electrically connected to the second sub-transmission signal line S2-2; in the same second sub-circuit unit 142, the drain of the third transistor M3 is electrically connected to the drain of the fourth transistor M4 and the corresponding output line 150.

The drain of the third transistor M3 and the drain of the fourth transistor M4 are electrically connected to the input terminal 130 via the corresponding output line 150, so that the drain of the third transistor M3 and the drain of the fourth transistor M4 are electrically connected to the corresponding data line 110 via the corresponding output line 150, the input terminal 130, and the fanout line 120 in this order.

For example, in practical implementation, the third transistor M3 may be in a conducting state under the control of an on signal on the third control signal line SW3, so that a signal on the first transmission signal line S1 may be provided to the corresponding data line 110. The third transistor M3 may be in an off state under the control of an off signal on the third control signal line SW 3. Further, the third transistor M3 may be an N-type transistor, or the third transistor M3 may also be a P-type transistor. Of course, in practical applications, the specific type of the third transistor M3 may be determined according to the practical application environment, and is not limited herein.

For example, in practical implementation, the fourth transistor M4 may be in a conducting state under the control of the on signal on the fourth control signal line SW4, so that the signal on the second sub-transmission signal line S2-2 may be provided to the corresponding data line 110. The fourth transistor M4 may be in an off state under the control of an off signal on the fourth control signal line SW 4. Further, the fourth transistor M4 may be an N-type transistor, or the fourth transistor M4 may also be a P-type transistor. Of course, in practical applications, the specific type of the fourth transistor M4 may be determined according to the practical application environment, and is not limited herein.

Illustratively, in implementation, in an embodiment of the present invention, as shown in fig. 6 to 8, the third circuit unit 140-3 may include: a plurality of fifth transistors M5 and a fifth control signal line SW5; the gates of all the fifth transistors M5 are electrically connected to the fifth control signal line SW5, the sources of all the fifth transistors M5 are electrically connected to the third transmission signal line S3, and the fifth transistors M5 are electrically connected to the output lines 150 corresponding to one another.

Illustratively, in practical implementation, in the embodiment of the present invention, as shown in fig. 6 to 8, one fifth transistor M5 corresponds to one column of sub-pixels in the 3n-1 th column of sub-pixels, and the output line 150 corresponding to the fifth transistor M5 is electrically connected to the display driving signal line of the corresponding column of sub-pixels. Exemplarily, the 2 nd column of sub-pixels corresponds to one fifth transistor M5, and the fifth transistor M5 is electrically connected to the data line 110 corresponding to the 2 nd column of sub-pixels.

The drain of the fifth transistor M5 is electrically connected to the input terminal 130 through the corresponding output line 150, so that the drain of the fifth transistor M5 can be electrically connected to the corresponding data line 110 through the corresponding output line 150, the input terminal 130, and the fanout line 120 in sequence.

For example, in practical implementation, the fifth transistor M5 may be in a conducting state under the control of an on signal on the fifth control signal line SW5, so that the signal on the third transmission signal line S3 may be provided to the corresponding data line 110. The fifth transistor M5 may be in an off state under the control of an off signal on the fifth control signal line SW 5. Further, the fifth transistor M5 may be an N-type transistor, or the fifth transistor M5 may also be a P-type transistor. Of course, in practical applications, the specific type of the fifth transistor M5 may be determined according to practical application environments, and is not limited herein.

In the embodiment of the present invention, the Transistor may be a Thin Film Transistor (TFT) or a Metal Oxide semiconductor field effect Transistor (MOS), and is not limited herein. In specific implementation, the source and the drain of each transistor may be interchanged according to the type of the transistor and the signal of the gate, and no specific distinction is made here.

For example, in implementation, as shown in fig. 8 and 9, the first control signal line SW1 and the fourth control signal line SW4 may be electrically connected. In this way, only one input port may be provided in the display panel, i.e., corresponding data signals may be input to the first control signal line SW1 and the fourth control signal line SW4 during the VT test. Therefore, the wiring space and the wiring design difficulty can be reduced. Furthermore, this also improves the uniformity of the signals applied to the first control signal line SW1 and the fourth control signal line SW4, so as to improve the control uniformity of the first transistor M1 and the fourth transistor M4.

For example, in specific implementation, as shown in fig. 8 and 9, the second control signal line SW2 and the third control signal line SW3 may be electrically connected. Thus, only one input port may be provided in the display panel, that is, corresponding data signals may be input to the second control signal line SW2 and the third control signal line SW3 in the VT test. Therefore, the occupied space of wiring and the difficulty of wiring design can be reduced. Also, this may also improve the uniformity of the signals applied to the second control signal line SW2 and the third control signal line SW3 to improve the control uniformity of the second transistor M2 and the third transistor M3.

For example, in a specific implementation, as shown in fig. 10, the output line 150 electrically connected to the second circuit unit 140-2 is connected in parallel with a resistor R0, and the resistor R0 of the output line 150 electrically connected to the second circuit unit 140-2 is the same as the resistor R0 of the output line 150 electrically connected to the first circuit unit 140-1. By connecting the resistance R0 in parallel to the output line 150 electrically connected to the second circuit unit 140-2, the total resistance R0 of the output line 150 electrically connected to the second circuit unit 140-2 can be reduced, and the total resistance R0 of the output line 150 electrically connected to the second circuit unit 140-2 can be approximated to the total resistance R0 of the output line 150 electrically connected to the first circuit unit 140-1. In addition, by designing the resistance R0 value of the resistor R0 connected in parallel to the output line 150 electrically connected to the second circuit unit 140-2, the total resistance R0 of the output line 150 electrically connected to the second circuit unit 140-2 can be substantially the same as the total resistance R0 of the output line 150 electrically connected to the first circuit unit 140-1, so that the voltages inputted to the same color sub-pixels in different rows can be substantially the same, the luminance of the pure color image can be substantially the same, and the problem of the vertical stripes of the pure color image can be improved.

In an actual process, the same or different features may not be completely the same due to limitations of process conditions or other factors, and therefore, the same relationship between the features may be satisfied only by approximately satisfying the above conditions, and all of the features fall within the scope of the present invention. For example, the above-described identity may be the same as allowed within an error allowable range.

Illustratively, the output line 150 electrically connected to the second circuit unit 140-2 in parallel with the resistor R0 may be implemented as follows: the width of the output line 150 to which the second circuit unit 140-2 is electrically connected is increased so that the total resistance of the output line 150 to which the second circuit unit 140-2 is electrically connected is decreased. Alternatively, the output line 150 electrically connected to the second circuit unit 140-2 and connected in parallel with the resistor R0 may be implemented as follows: a conductive layer is provided on the other film layer and is connected in parallel with the output line 150 to which the second circuit unit 140-2 is electrically connected, so that the total resistance of the output line 150 to which the second circuit unit 140-2 is electrically connected is reduced. Of course, in practical applications, the design may be determined according to practical application environments, and is not limited herein.

For example, the first transmission signal line, the second transmission signal line and the third transmission signal line may be disposed in the same material layer as the data line. Therefore, the first transmission signal line, the second transmission signal line, the third transmission signal line and the data line can be formed by adopting the same composition process, so that the working difficulty can be reduced, and the resistivity of the first transmission signal line, the second transmission signal line and the third transmission signal line can be reduced because the material of the common data line is a metal material.

Illustratively, the first to fifth transistors may be fabricated at the same time as the transistors in the display region. This may improve the process uniformity of these transistors and may also reduce the process preparation difficulty.

Based on the same inventive concept, an embodiment of the present invention further provides a method for detecting the display panel, which includes the following steps:

when the display panel displays a pure color picture, lightening the sub-pixels of the corresponding color;

loading a bright-state signal to the first transmission signal line S1, loading a dark-state signal to the second transmission signal line S2 and the third transmission signal line S3, respectively, loading corresponding control signals to the first control signal line SW1 to the fifth control signal line SW5, respectively, and lighting the first color sub-pixel or the third color sub-pixel;

the first transmission signal line S1 and the second transmission signal line S2 are loaded with a dark signal, the third transmission signal line S3 is loaded with a bright signal, and the first control signal line SW1 to the fifth control signal line SW5 are loaded with corresponding control signals, respectively, to illuminate the second color sub-pixel.

In the detection method provided by the embodiment of the present invention, the dark-state signal is loaded on the first transmission signal line and the second transmission signal line, the bright-state signal is loaded on the third transmission signal line, and the corresponding control signals are respectively loaded on the first control signal line to the fifth control signal line, so as to light the second color sub-pixel, thereby displaying the second color pure-color picture. And the first color sub-pixel or the third color sub-pixel is lightened to display the first color pure color picture or the third color pure color picture by loading a bright state signal to the first transmission signal line, loading a dark state signal to the second transmission signal line and the third transmission signal line respectively, and loading corresponding control signals to the first control signal line to the fifth control signal line respectively. Because the first transmission signal line is arranged between the first circuit unit and the second circuit unit, RC Loading between an output line electrically connected with the first circuit unit and an output line electrically connected with the second circuit unit can be reduced, and the problem that vertical stripes appear on a first color pure color picture or a third color pure color picture can be solved.

Illustratively, in practical implementation, in the embodiment of the present invention, lighting the first color sub-pixel may include the following steps, as shown in fig. 11:

s11, in a first stage, loading a bright state signal to a first transmission signal line S1, loading a dark state signal to a second transmission signal line S2 and a third transmission signal line S3 respectively, loading an opening signal to a second control signal line SW2 and a third control signal line SW3, loading a stopping signal to a first control signal line SW1 and a fourth control signal line SW4, and loading an opening signal to a fifth control signal line SW5 to enable a second circuit unit 140-2 to output a bright state signal, and outputting a dark state signal by the first circuit unit 140-1 and the third circuit unit 140-3;

and S12, in the second stage, a bright state signal is loaded on the first transmission signal line S1, a dark state signal is loaded on the second transmission signal line S2 and the third transmission signal line S3 respectively, an opening signal is loaded on the first control signal line SW1 and the fourth control signal line SW4, a stopping signal is loaded on the second control signal line SW2 and the third control signal line SW3, and an opening signal is loaded on the fifth control signal line SW5, so that the first circuit unit 140-1 outputs a bright state signal, and the second circuit unit 140-2 and the third circuit unit 140-3 output a dark state signal.

For example, taking the first color sub-pixel as the red sub-pixel R, the red sub-pixel R may be turned on when the display panel displays a red pure color picture. Next, a display panel shown in fig. 10 is taken as an example, and a detection process of the display panel provided by the embodiment of the invention is described with reference to a signal timing chart shown in fig. 12.

Wherein SW1 represents signals loaded on the first control signal line SW1 and the fourth control signal line SW4, SW2 represents signals loaded on the second control signal line SW2 and the third control signal line SW3, GA1 represents signals transmitted on the gate line GA electrically connected to the first row of sub-pixels, and GA2 represents signals transmitted on the gate line GA electrically connected to the second row of sub-pixels. The fifth control signal line SW5 is always applied with an on signal (e.g., a low level signal) of a fixed voltage.

At stage t11, the process of step S11 described above is implemented. The method specifically comprises the following steps: when the signal ga1 is a low level signal, the thin film transistors in the first row of sub-pixels are turned on. When the signal ga2 is a high level signal, the thin film transistor in the second row of sub-pixels is turned off. Since the signal sw1 is a high level signal (i.e., off signal), all the first transistors M1 and all the fourth transistors M4 are turned off. A dark signal (e.g., 6V) is applied to the third transmission signal line S3, and a low-level signal (i.e., an on signal) with a fixed voltage is transmitted on the fifth control signal line SW5, so that all the fifth transistors M5 are turned on to provide the dark signal to the data line 110 electrically connected to the green sub-pixel G, so that the green sub-pixel G in the first row inputs the dark signal, and the green sub-pixel G does not emit light. Since the signal sw2 is a low level signal (i.e., an on signal), all the second transistors M2 and all the third transistors M3 are turned on. A dark signal (e.g., 6V) is applied to the first sub-transmission signal line S2-1 and the second sub-transmission signal line S2-2, and the turned-on second transistor M2 provides the dark signal to the corresponding data line 110, so that the blue sub-pixel B in the first row inputs the dark signal, and the blue sub-pixel B does not emit light. A bright signal (e.g., 3V) is applied to the first transmission signal line S1, and the turned-on third transistor M3 provides the bright signal to the corresponding data line 110, so that the bright signal is input to the red sub-pixel R in the first row, and the red sub-pixel R emits light to display red.

In stage t12, the process of step S12 described above is implemented. The method comprises the following specific steps: when the signal ga1 is a high level signal, the thin film transistor in the first row of sub-pixels is turned off. When the signal ga2 is a low level signal, the tft in the second row of sub-pixels is turned on. Since the signal sw2 is a high level signal (i.e., a turn-off signal), all the second transistors M2 and all the third transistors M3 are turned off. A dark signal (e.g., 6V) is applied to the third transmission signal line S3, and a low-level signal (i.e., an on signal) with a fixed voltage is transmitted on the fifth control signal line SW5, so that all the fifth transistors M5 are turned on to provide the dark signal to the data line 110 electrically connected to the green sub-pixel G, so that the green sub-pixel G in the first row inputs the dark signal, and the green sub-pixel G does not emit light. Since the signal sw1 is a low level signal (i.e., an on signal), all the first transistors M1 and all the fourth transistors M4 are turned on. A dark-state signal (e.g., 6V) is applied to the first sub-transmission signal line S2-1 and the second sub-transmission signal line S2-2, and the dark-state signal is provided to the corresponding data line 110 through the turned-on fourth transistor M4, so that the blue sub-pixel B in the second row inputs the dark-state signal, and the blue sub-pixel B does not emit light. A bright-state signal (e.g., 3V) is applied to the first transmission signal line S1, and the bright-state signal is provided to the corresponding data line 110 through the turned-on first transistor M1, so that the bright-state signal is input to the red sub-pixel R in the second row, and the red sub-pixel R emits light to display red.

The rest of the processes are analogized in turn, so that the display panel displays a red pure-color picture, and the specific process is not described herein.

In the embodiment of the present invention, only one transmission signal line of the plurality of transmission signal lines, i.e., the first transmission signal line S1, is disposed between the first circuit unit 140-1 and the second circuit unit 140-2. Further, by connecting the resistance R0 in parallel to the output line 150 to which the second circuit unit 140-2 is electrically connected, the resistance R0 of the output line 150 to which the second circuit unit 140-2 is electrically connected can be made substantially the same as the resistance R0 of the output line 150 to which the first circuit unit 140-1 is electrically connected. Therefore, when the display panel displays the red pure-color picture through the short-circuit bar structure 140, the problem of vertical stripes is improved, and the display effect of the red pure-color picture is improved.

In addition, in the embodiment of the invention, one transmission signal line, namely the first transmission signal line, is arranged for inputting the bright-state signal to the red sub-pixel, so that the difference of light emission of the red sub-pixels in different columns can be further reduced, and the display effect of the red pure-color picture can be further improved.

Illustratively, in practical implementation, in the embodiment of the present invention, lighting the third color sub-pixel may include the following steps, as shown in fig. 13:

s21, in a first stage, loading a bright signal to the first transmission signal line S1, loading a dark signal to the second transmission signal line S2 and the third transmission signal line S3, respectively, loading an on signal to the first control signal line SW1 and the fourth control signal line SW4, loading a stop signal to the second control signal line SW2 and the third control signal line SW3, and loading an on signal to the fifth control signal line SW5, so that the first circuit unit 140-1 outputs a bright signal, and the second circuit unit 140-2 and the third circuit unit 140-3 output a dark signal;

s22, in the second stage, a bright state signal is loaded to the first transmission signal line S1, a dark state signal is loaded to the second transmission signal line S2 and the third transmission signal line S3, an on signal is loaded to the second control signal line SW2 and the third control signal line SW3, an off signal is loaded to the first control signal line SW1 and the fourth control signal line SW4, and an on signal is loaded to the fifth control signal line SW5, so that the second circuit unit 140-2 outputs a bright state signal, and the first circuit unit 140-1 and the third circuit unit 140-3 output dark state signals.

Illustratively, taking the third color sub-pixel as the blue sub-pixel B as an example, the blue sub-pixel B may be lighted when the display panel displays a blue pure color picture. Next, a detection process of the display panel according to the embodiment of the present invention is described with reference to the signal timing chart shown in fig. 14 by taking the display panel shown in fig. 10 as an example.

At stage t21, the process of step S21 described above is implemented. The method specifically comprises the following steps: when the signal ga1 is a low level signal, the thin film transistors in the first row of sub-pixels are turned on. When the signal ga2 is a high level signal, the thin film transistor in the second row of sub-pixels is turned off. Since the signal sw2 is a high level signal (i.e., a turn-off signal), all the second transistors M2 and all the third transistors M3 are turned off. A dark signal (e.g., 6V) is applied to the third transmission signal line S3, and a low-level signal (i.e., an on signal) with a fixed voltage is transmitted on the fifth control signal line SW5, so that all the fifth transistors M5 are turned on to provide the dark signal to the data line 110 electrically connected to the green sub-pixel G, so that the green sub-pixel G in the first row inputs the dark signal, and the green sub-pixel G does not emit light. Since the signal sw1 is a low level signal (i.e., an on signal), all the first transistors M1 and all the fourth transistors M4 are turned on. A dark signal (e.g., 6V) is applied to the first sub-transmission signal line S2-1 and the second sub-transmission signal line S2-2, and the dark signal is provided to the corresponding data line 110 through the turned-on fourth transistor M4, so that the red sub-pixel R in the first row inputs the dark signal, and the red sub-pixel R does not emit light. A bright-state signal (e.g., 3V) is applied to the first transmission signal line S1, and the bright-state signal is provided to the corresponding data line 110 through the turned-on first transistor M1, so that the bright-state signal is input to the blue sub-pixel B in the first row, and the blue sub-pixel B emits light to display blue.

At stage t22, the process of step S22 described above is implemented. The method specifically comprises the following steps: when the signal ga1 is a high level signal, the thin film transistor in the first row of sub-pixels is turned off. When the signal ga2 is a low level signal, the tft in the second row of sub-pixels is turned on. Since the signal sw1 is a high level signal (i.e., off signal), all the first transistors M1 and all the fourth transistors M4 are turned off. A dark signal (e.g., 6V) is applied to the third transmission signal line S3, and a low-level signal (i.e., an on signal) with a fixed voltage is transmitted on the fifth control signal line SW5, so that all the fifth transistors M5 are turned on to provide the dark signal to the data line 110 electrically connected to the green sub-pixel G, so that the green sub-pixel G in the first row inputs the dark signal, and the green sub-pixel G does not emit light. Since the signal sw2 is a low level signal (i.e., an on signal), all the second transistors M2 and all the third transistors M3 are turned on. A dark-state signal (e.g., 6V) is applied to the first sub-transmission signal line S2-1 and the second sub-transmission signal line S2-2, and the turned-on second transistor M2 provides the dark-state signal to the corresponding data line 110, so that the red sub-pixel R in the second row inputs the dark-state signal, and the red sub-pixel R does not emit light. A bright signal (e.g., 3V) is applied to the first transmission signal line S1, and the turned-on third transistor M3 provides the bright signal to the corresponding data line 110, so that the bright signal is input to the blue sub-pixel B in the second row, and the blue sub-pixel B emits light to display blue.

The rest of the processes are analogized in turn, so that the display panel displays a blue pure-color picture, and the specific process is not described herein.

In the embodiment of the present invention, only one transmission signal line of the plurality of transmission signal lines, i.e., the first transmission signal line S1, is disposed between the first circuit unit 140-1 and the second circuit unit 140-2. Further, by connecting the resistance R0 in parallel to the output line 150 to which the second circuit unit 140-2 is electrically connected, the resistance R0 of the output line 150 to which the second circuit unit 140-2 is electrically connected can be made substantially the same as the resistance R0 of the output line 150 to which the first circuit unit 140-1 is electrically connected. Therefore, when the display panel displays the blue pure-color picture through the short-circuit bar structure 140, the problem of vertical stripes is solved, and the display effect of the blue pure-color picture is improved.

Also, the light emitting device in the blue sub-pixel has a lower light emitting efficiency than the light emitting devices in the red and green sub-pixels, and thus requires a larger current when it is aged. Therefore, in the embodiment of the present invention, one transmission signal line, i.e., the first transmission signal line, is provided for inputting the bright-state signal to the blue sub-pixels, so that the difference of light emission of the blue sub-pixels in different columns can be further reduced, and the display effect of the blue pure-color picture can be further improved.

In a specific implementation, in the embodiment of the present invention, lighting the second color sub-pixel may include: the first transmission signal line S1 and the second transmission signal line S2 are loaded with a dark signal, the third transmission signal line S3 is loaded with a bright signal, and the first control signal line SW1 to the fifth control signal line SW5 are loaded with an on signal, so that the first circuit unit 140-1 and the second circuit unit 140-2 output a dark signal, and the third circuit unit 140-3 outputs a bright signal.

For example, taking the second color sub-pixel as the green sub-pixel G, the green sub-pixel G may be turned on when the display panel displays a green pure color picture. Next, a process of detecting the display panel according to the embodiment of the present invention will be described by taking the display panel shown in fig. 10 as an example.

Specifically, the first to fifth control signal lines SW1 to SW5 are always loaded with low level signals (i.e., turn-on signals), so that all of the first to fifth transistors M1 to M5 are turned on. In addition, when a dark signal (for example, 6V) is applied to each of the first transmission signal line S1, the first sub-transmission signal line S2-1, and the second sub-transmission signal line S2-2, the dark signal may be input to the red sub-pixel R and the blue sub-pixel B, and the red sub-pixel R and the blue sub-pixel B may not emit light. When a bright signal (e.g., 3V) is outputted to the third circuit unit 140-3, the bright signal can be inputted to the green sub-pixel G, so that the green sub-pixel G emits light to display green.

It should be noted that, since the regions where the fifth transistors M5 are located are all located between the second sub-transmission signal line S2-2 and the third transmission signal line S3, RC loading of the output lines 150 electrically connected to the fifth transistors M5 can be substantially the same, so that when a green solid color picture is displayed, a vertical stripe problem can be avoided.

Based on the same inventive concept, the embodiment of the invention further provides a display device, which comprises the display panel provided by the embodiment of the invention. The principle of the display device for solving the problems is similar to that of the display panel, so the implementation of the display device can be referred to the implementation of the display panel, and repeated descriptions are omitted here.

In specific implementation, in the embodiment of the present invention, the display device may be: a full screen handset as shown in figure 15. Of course, the display device may also be: any product or component with a display function, such as a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like. Other essential components of the display device are understood by those skilled in the art, and are not described herein or should not be construed as limiting the invention.

In the display panel, the detection method thereof and the display device provided by the embodiment of the invention, the shorting bar structure in the display panel is provided with the first circuit unit, the second circuit unit and the third circuit unit which are sequentially arranged along the second direction, and the first circuit unit and the second circuit unit share one first transmission signal line, so that signals can be respectively transmitted to the first circuit unit and the second circuit unit through the first transmission signal line. And by arranging the first transmission signal line between the first circuit unit and the second circuit unit, only one transmission signal line of the plurality of transmission signal lines, that is, the first transmission signal line, can be arranged between the first circuit unit and the second circuit unit. Therefore, the difference between the resistance between the first circuit unit and the fan-out line and the difference between the resistance between the second circuit unit and the fan-out line is reduced, and the difference between the RC loading between the first circuit unit and the fan-out line and the RC loading between the second circuit unit and the fan-out line is reduced, so that the difference of voltages input into different rows of sub-pixels with the same color is reduced, the problem of vertical stripes of a pure color picture can be improved, and the display effect of the pure color picture is improved.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims

1. A display panel, comprising: a substrate base plate having a display region and a non-display region; the non-display area includes: a fan-out region and a binding region; the fan-out region includes: a plurality of fan-out lines; the fan-out area is arranged between the display area and the binding area;

the shorting bar structure includes: a plurality of transmission signal lines extending in a first direction, a plurality of output lines extending in a second direction, and a first circuit unit, a second circuit unit, and a third circuit unit arranged in the second direction; the first circuit unit, the second circuit unit and the third circuit unit are respectively and electrically connected with different output lines;

the plurality of transmission signal lines include: a first transmission signal line; the first circuit unit and the second circuit unit share a first transmission signal line, and the first transmission signal line is arranged between the first circuit unit and the second circuit unit;

a second transmission signal line and a third transmission signal line;

the second transmission signal line includes: a first sub transmission signal line and a second sub transmission signal line; the first sub transmission signal line is electrically connected with the first circuit unit, and the second sub transmission signal line is electrically connected with the second circuit unit; the first sub transmission signal line is positioned on one side of the first circuit unit, which is far away from the first transmission signal line, and the second sub transmission signal line is positioned on one side of the second circuit unit, which is far away from the first transmission signal line;

the third transmission signal line is electrically connected to the third circuit unit.

2. The display panel of claim 1,

the plurality of sub-pixels comprise a first color sub-pixel, a second color sub-pixel and a third color sub-pixel;

the display area comprises a plurality of pixel columns, wherein the 3n-2 th column of sub-pixels and the 3n th column of sub-pixels respectively comprise first color sub-pixels and third color sub-pixels which are alternately arranged, and the arrangement sequence of the first color sub-pixels and the third color sub-pixels in the 3n-2 th column of sub-pixels and the 3n th column of sub-pixels is opposite; the 3n-1 th column of sub-pixels comprises second color sub-pixels which are sequentially arranged, wherein n is a positive integer;

a fanout line corresponding to the 3 nth column of sub-pixels is connected to the first circuit unit; a fan-out line corresponding to the 3n-2 th column of sub-pixels is linked to the second circuit unit; and the fanout line corresponding to the sub-pixel of the 3 nth column is connected to the third circuit unit.

3. The display panel of claim 1,

the first circuit unit is directly adjacent to the second circuit unit, and a transistor is not arranged between the first circuit unit and the second circuit unit.

4. The display panel according to claim 2, wherein the third transmission signal line is located on a side of the third circuit unit facing away from the second circuit unit.

5. The display panel according to claim 2, wherein the third transmission signal line is located between the third circuit unit and the second sub transmission signal line.

6. The display panel according to any one of claims 2 to 5, wherein the first circuit unit includes: a plurality of first sub-circuit units, a first control signal line and a second control signal line; wherein the first sub-circuit unit includes: a first transistor and a second transistor;

the gates of all the first transistors are electrically connected with the first control signal line, the sources of all the first transistors are electrically connected with the first transmission signal line, the gates of all the second transistors are electrically connected with the second control signal line, and the sources of all the second transistors are electrically connected with the first sub-transmission signal line; in the same first sub-circuit unit, the drain electrode of the first transistor and the drain electrode of the second transistor are electrically connected with corresponding output lines;

the second circuit unit includes: a plurality of second sub-circuit units, a third control signal line, and a fourth control signal line; wherein the second sub-circuit unit includes: a third transistor and a fourth transistor;

the gates of all the third transistors are electrically connected with the third control signal line, the sources of all the third transistors are electrically connected with the first transmission signal line, the gates of all the fourth transistors are electrically connected with the fourth control signal line, and the sources of all the fourth transistors are electrically connected with the second sub-transmission signal line; in the same second sub-circuit unit, the drain of the third transistor and the drain of the fourth transistor are electrically connected to corresponding output lines;

the third circuit unit includes: a plurality of fifth transistors and fifth control signal lines; the gates of all the fifth transistors are electrically connected with the fifth control signal line, the sources of all the fifth transistors are electrically connected with the third transmission signal line, and the fifth transistors are respectively electrically connected with output lines in one-to-one correspondence.

7. The display panel of claim 6, wherein the display area comprises: a plurality of sub-pixels and a plurality of display driving signal lines extending along the second direction; one column of sub-pixels is electrically connected with one display driving signal line, and one fan-out line is electrically connected with at least one display driving signal line;

the first circuit unit is close to the display area, the third circuit unit is located on one side, away from the display area, of the first circuit unit, and the second circuit unit is located between the first circuit unit and the second circuit unit.

8. The display panel of claim 7,

one first sub-circuit unit corresponds to one column of sub-pixels in the 3 nth column of sub-pixels, and an output line corresponding to the first sub-circuit unit is electrically connected with display driving signal lines of the corresponding column of sub-pixels;

one second sub-circuit unit corresponds to one column of sub-pixels in the 3n-2 th column of sub-pixels, and an output line corresponding to the second sub-circuit unit is electrically connected with a display driving signal line of the corresponding column of sub-pixels;

one fifth transistor corresponds to one column of sub-pixels in the 3n-1 th column of sub-pixels, and an output line corresponding to the fifth transistor is electrically connected with a display driving signal line of the corresponding column of sub-pixels.

9. The display panel of claim 8, wherein the first color sub-pixel is a red sub-pixel, the second color sub-pixel is a green sub-pixel, and the third color sub-pixel is a blue sub-pixel.

10. The display panel according to claim 6, wherein the first control signal line and the fourth control signal line are electrically connected, and wherein the second control signal line and the third control signal line are electrically connected.

11. The display panel according to any one of claims 1 to 5, wherein a resistance is connected in parallel to an output line to which the second circuit unit is electrically connected, and a resistance of the output line to which the second circuit unit is electrically connected is the same as a resistance of the output line to which the first circuit unit is electrically connected.

12. A display device characterized by comprising the display panel according to any one of claims 1 to 11.

13. A method for inspecting a display panel according to any one of claims 1 to 11, comprising:

when the display panel displays a pure-color picture, lightening the sub-pixels of the corresponding colors;

14. The method as claimed in claim 13, wherein in the 3n-2 column of sub-pixels, the odd line is a first color sub-pixel, and the even line is a third color sub-pixel;

the lighting the first color sub-pixel comprises:

a first stage of loading the bright state signal to the first transmission signal line, loading the dark state signal to the second transmission signal line and the third transmission signal line, respectively, loading the start signal to the second control signal line and the third control signal line, loading the stop signal to the first control signal line and the fourth control signal line, and loading the start signal to the fifth control signal line, so that the second circuit unit outputs the bright state signal, and the first circuit unit and the third circuit unit output the dark state signal;

and a second stage of loading a bright state signal to the first transmission signal line, loading a dark state signal to the second transmission signal line and the third transmission signal line respectively, loading an opening signal to the first control signal line and the fourth control signal line, loading a stopping signal to the second control signal line and the third control signal line, and loading the opening signal to the fifth control signal line, so that the first circuit unit outputs the bright state signal, and the second circuit unit and the third circuit unit output the dark state signal.

15. The detecting method according to claim 13, wherein in the 3n-2 column of sub-pixels, the odd line is a first color sub-pixel, and the even line is a third color sub-pixel;

the illuminating the third color sub-pixel comprises:

a first stage of loading a bright-state signal to the first transmission signal line, loading a dark-state signal to the second transmission signal line and the third transmission signal line, respectively, loading an on signal to the first control signal line and the fourth control signal line, loading a stop signal to the second control signal line and the third control signal line, and loading an on signal to the fifth control signal line, so that the first circuit unit outputs the bright-state signal, and the second circuit unit and the third circuit unit output the dark-state signal;

and a second stage of loading the bright state signal on the first transmission signal line, loading a dark state signal on the second transmission signal line and the third transmission signal line respectively, loading an opening signal on the second control signal line and the third control signal line, loading a stopping signal on the first control signal line and the fourth control signal line, and loading the opening signal on the fifth control signal line, so that the bright state signal is output by the second circuit unit, and the dark state signal is output by the first circuit unit and the third circuit unit.

16. The detection method of any one of claims 13-15, wherein illuminating the second color sub-pixel comprises:

loading dark state signals to the first transmission signal line and the second transmission signal line, loading bright state signals to the third transmission signal line, and loading the start signals to the first control signal line to the fifth control signal line, so that the first circuit unit and the second circuit unit output the dark state signals, and the third circuit unit outputs the bright state signals.