CN115600549B - Accurate detection method for determining integrated circuit layout design defects based on grid subdivision - Google Patents
Accurate detection method for determining integrated circuit layout design defects based on grid subdivision Download PDFInfo
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Abstract
The invention discloses an accurate detection method for determining design defects of an integrated circuit layout based on grid subdivision, which comprises the steps of firstly filling in network numbers of circuit nodes in an integrated circuit schematic diagram, and calibrating corresponding positions of the circuit nodes in the layout; then converting wiring, a bonding pad caused by a via hole and an isolation gasket in the layout into a layout polygon, performing Boolean operation with the originally defined copper-clad polygon to form a unified layout polygon, and generating a triangle mesh subdivision with constraint based on the unified layout polygon and the edges of the unified layout polygon; and finally traversing the triangle mesh subdivision with the constraint and filling the network numbers, acquiring the network numbers of all the position points according to the triangles of the circuit nodes, which correspond to the position points in the layout, and corresponding the network numbers of the position points to the network numbers of the circuit nodes in the integrated circuit schematic diagram, and judging the design defects according to the corresponding results, thereby realizing the accurate detection of the design defects of the integrated circuit layout.
Description
Technical Field
The invention belongs to the technical field of integrated circuit layout detection, and particularly relates to an accurate detection method for determining integrated circuit layout design defects based on grid subdivision.
Background
With the development of communication technology, research and development of very large scale integrated circuits have been gradually developed. In order to improve the performance of electronic devices, reduce the volume and cost, transistors and other components and circuitry are integrated on a small semiconductor substrate. In order to realize more functions, very large scale integrated circuits have several to hundreds of layers of structures, each of which is extremely complex, integrating tens of millions or even hundreds of millions of transistors, with multi-scale structures ranging from centimeter-scale of overall dimensions to nanometer-scale of the smallest component.
The layout of the ultra-large scale integrated circuit consists of structures such as copper-clad polygons, wires, through holes, bonding pads, isolation gaskets and the like, and the connection relation of the structures is derived from a schematic diagram forming the layout of the integrated circuit, so that the connection topological diagram corresponding to the connection relation is consistent with the topological structure of the circuit schematic diagram. However, the actual design of the integrated circuit layout may change the topological relation of the integrated circuit layout due to unreasonable size of the pads, the isolation pads and wiring connection, for example, the problem of disconnection caused by overlarge radius of the isolation pads or the problem of short circuit caused by overlarge radius of the pads, and the problem of actual wrong connection of the via holes caused by negligence of engineers, etc.; for example, an oversized anti-pad radius as shown in fig. 2-3 results in a disconnection problem, an oversized pad and spacer radius in fig. 2 results in a disconnection, and fig. 3 ensures connectivity for the correct radius; too large a pad radius in fig. 4-5 results in a short circuit problem, too large a pad radius in fig. 4 results in a short circuit, while fig. 5 guarantees a connection relationship for the correct pad radius, and fig. 6-7 show a virtually wrong connection problem of the via due to the engineer's negligence: the lack of a spacer in the middle layer of fig. 6 results in a short circuit, while fig. 7 is a correct addition of a spacer.
Disclosure of Invention
Aiming at the defects of the prior art, the application provides an accurate detection method for determining integrated circuit layout design defects based on grid subdivision, which comprises the following steps:
acquiring an integrated circuit schematic diagram and a corresponding integrated circuit layout;
filling in network numbers of circuit nodes in the integrated circuit schematic diagram;
determining the corresponding position of a circuit node in the integrated circuit schematic diagram in the integrated circuit layout according to the integrated circuit schematic diagram and the position Guan Jibiao of the integrated circuit layout, and taking the position as the circuit node of the integrated circuit layout;
converting wiring, a bonding pad caused by a via hole and an isolation gasket in the integrated circuit layout into a layout polygon, and performing polygon Boolean operation with the originally defined copper-clad polygon to form a unified layout polygon;
generating triangle mesh subdivision with constraint according to the layout polygon and circuit nodes in the integrated circuit layout;
traversing the triangle mesh with the constraint and filling in network numbers;
acquiring a network number of a corresponding position point in the integrated circuit layout according to a triangle associated with the position point of a circuit node in the integrated circuit schematic diagram;
comparing and judging the network numbers of the circuit nodes in the integrated circuit layout with the network numbers of the circuit nodes in the integrated circuit schematic diagram, and determining whether the integrated circuit layout has design defects according to the judging result.
In some embodiments, the filling out the network number of the circuit node in the integrated circuit schematic includes:
step 1-1: numbering all circuit nodes in the integrated circuit schematic diagram to form a set { i } of all circuit nodes in the integrated circuit schematic diagram, wherein i=1, 2, …, N and N are the number of the circuit nodes;
step 1-2: filling circuit nodes into all circuit branches in the integrated circuit schematic diagram to form an association matrix;
step 1-3: setting an initialization parameter, namely, the current processing circuit node k=1; current network number net=1; circuit node processing set { Process i The value of the element is 0, i represents the ith circuit node, i=1, 2, …, N is the number of circuit nodes, and the front line set is V front ={k}；
Step 1-4: if the front line set is an empty set, setting net=net+1, and turning to the step 1-5; if the front line set is not the empty set, the step 1-7 is carried out;
step 1-5: setting k=k+1, if the current processing node is greater than the number of circuit nodes, ending the step of filling in the network numbers of the circuit nodes in the integrated circuit schematic diagram, otherwise, turning to the steps 1-6;
step 1-6: if Process k =0, adding the current processing circuit node to the front-line set and proceeding to steps 1-7 if Process k If the value is equal to 1, the step 1-5 is carried out;
step 1-7: the last circuit node v in the front line set is fetched, and removed from the front line set, and then a determination is made:
if Process v =0, set Net v =Net，Net v Setting a Process for the network number of the circuit node v v =1, searching all column numbers with a v-th row value of 1 in the correlation matrix, adding a circuit node with a Process value of 0 corresponding to the column number into the front line set, and turning to the steps 1-4 until the step of filling in the network number of the circuit node in the integrated circuit schematic diagram is finished; if Process v =1, then go directly to steps 1-4.
In some embodiments, the determining a corresponding position of the circuit node in the integrated circuit schematic in the integrated circuit layout according to the integrated circuit schematic and the position Guan Jibiao of the integrated circuit layout, and taking the position as the circuit node of the integrated circuit layout includes:
generating a network table file according to the integrated circuit schematic diagram, wherein the network table file comprises component types, circuit node names corresponding to component pins, package PCB device information corresponding to the circuit node names and all network information;
filling in the network number of the circuit node in the integrated circuit schematic diagram according to the name of the circuit node corresponding to the component pin and the network information corresponding to the component;
and marking the corresponding positions of the circuit nodes in the integrated circuit schematic diagram in the integrated circuit layout according to the same circuit node names corresponding to the component pins in the integrated circuit layout.
In some embodiments, the steps of converting the trace, the pad caused by the via hole and the isolation pad in the integrated circuit layout into a layout polygon and performing a polygon boolean operation with the originally defined copper-clad polygon to form a unified layout polygon include:
step 2-1: converting the wiring defining the starting point, the ending point and the width into a rectangle;
step 2-2: converting the isolation pad caused by the via hole into a hollowed polygon;
step 2-3: converting the bonding pad caused by the via hole into a copper-clad polygon;
step 2-4: converting the hollowed-out circle defined in the copper-clad polygon into a hollowed-out regular polygon in the copper-clad polygon;
step 2-5: performing Boolean 'union' operation on the rectangle and the originally defined copper-clad polygon to form a first new copper-clad polygon;
step 2-6: performing Boolean 'difference' operation on the first new copper-clad polygon, the hollowed polygon and the hollowed regular polygon to form a second new copper-clad polygon;
step 2-7: and (3) carrying out Boolean 'union' operation on the second new copper-clad polygon and the copper-clad polygon formed in the step (2-3) to form a unified layout polygon.
The originally defined copper-clad polygon is a polygon which is defined as a layout polygon in a layout design file and polygon vertexes are arranged anticlockwise.
In some embodiments, the converting the trace defining the start point, the end point, and the width into a rectangle includes:
and taking the length of the wiring line between the starting point and the ending point as the center, and respectively expanding a half of preset width to two sides of the width to form the rectangle.
In some embodiments, the generating a constrained triangle mesh subdivision from the layout polygons and circuit nodes in the integrated circuit layout includes:
step 3-1: forming Delaunay triangle grids according to all vertexes of the layout polygon and position coordinate points in the integrated circuit layout corresponding to circuit nodes of the integrated circuit layout;
step 3-2: collecting all sides of polygons which do not belong to the common sides of the two triangles in the Delaunay triangle grid, and sorting according to side length to form a setLost；
Step 3-3: from the collectionLostRemoving the longest side from the collectionLostRemoving the components;
step 3-4: starting from one vertex of the side with the longest side, searching triangles which contain the vertex and are positioned on two sides of the side with the longest side, exchanging the public sides of the triangles and the neighboring triangles if the side intersected with the side with the longest side is searched and is not the side of the other polygon, obtaining two new triangles, canceling the exchanging of the intersected side if the side intersected with the side with the longest side is searched and directly adding one vertex and a grid node at the intersection point of the two sides, and inserting the grid node into the Delaunay triangle grid, wherein the grid node divides the two neighboring triangles into four triangles, and the vertex divides the two intersected sides into four sides sharing the vertex; wherein the neighbor triangle is a triangle with a common side with the searched triangle;
step 3-5: repeating the steps 3-4 until the side with the longest side length is the common side of the two neighbor triangles;
step 3-6: judging the setLostWhether it is an empty set, if not, re-from said setLostRemoving the longest side from the collectionLostAnd (3) continuing to execute the step (3-4) after the step is removed, and if yes, directly forming the triangular mesh subdivision with constraint.
In some embodiments, before traversing the constrained triangle mesh and filling in the network numbers, further comprising:
recording each corresponding position point of the circuit node in the marked integrated circuit schematic diagram in the integrated circuit layout, and recording triangles associated with each position point; the triangle associated with the position point comprises a vertex of the triangle and the position point, and one position point is associated with a plurality of triangles.
In some embodiments, traversing the constrained triangle mesh and performing network numbering comprises:
step 4-1: numbering each copper-clad polygon in sequence, and initially setting the numbers of all triangles in the constrained triangle mesh subdivision as unnumbered, and setting the current q=1 th copper-clad polygon to be processed;
step 4-2: setting a current peripheral grid cell as a setFrontThe set ofFrontIs empty from the firstqAny edge of each copper-clad polygoneStarting from the left triangle associated with this edge is foundtTriangle is arrangedtIs the number of the q-th copper-clad polygon, and then the triangle is formedtAdding to a collectionFrontIn (a) and (b); wherein, the firstqAny edge of each copper-clad polygoneIs the left triangle of (1) including the edgeeAnd triangle sideeDirection and the first of (2)qCopper-clad multipleEdge of a polygoneIs the same triangle;
step 4-3: from the collectionFrontTaking out a triangletAnd from the collectionFrontIf the triangle is removedtAny one or more of the three neighbor triangles of (a) are unnumbered and the common edge is not an edge of any copper-clad polygon, then the triangle is treatedtTo join the set of one or more neighbor triangles of (a)FrontAnd add new to the collectionFrontIs numbered as (1)qNumbering the copper-clad polygons; wherein the common side is the triangletAdjacent triangles are adjacent to the triangletIs a common edge of (2);
step 4-4: judging the setFrontIf the set is the empty set, if the set is not the empty set, the step is shifted to step 4-3, and if the set is the empty set, the set is firstly setq=q+1, then go to step 4-2 until the setFrontIs empty;
step 4-5: judging whether all the copper-clad polygons are processed, and if so, ending the superposition of the copper-clad polygons; if not, returning to continue to process the untreated copper-clad polygon until all copper-clad polygons are processed.
In some embodiments, the obtaining, according to the triangle associated with the corresponding position point of the circuit node in the integrated circuit schematic diagram, the network number of the position point includes:
and finding out any associated triangle for the triangle associated with the corresponding position point of the circuit node in each integrated circuit schematic diagram, wherein the number of the triangle is used as the number of the position point, and the number of the position point is the network number of the position point.
In some embodiments, comparing the network number of the circuit node in the integrated circuit layout with the network number of the circuit node in the integrated circuit schematic diagram, and determining whether the integrated circuit layout has a design defect according to the determination result includes:
according to the position relationship between the circuit nodes in the integrated circuit schematic diagram and the integrated circuit layout defined by a user, establishing a mapping relationship between the network numbers of the position points and the network numbers of the circuit nodes in the integrated circuit schematic diagram, if the mapping relationship is one-to-one mapping, determining that the integrated circuit layout has no design defect, if the mapping relationship is not one-to-one mapping, determining that the integrated circuit layout has the design defect, and if the position of the circuit node which is not corresponding to the mapping relationship is the position of the design defect.
The invention has the beneficial effects that:
firstly, filling in network numbers of circuit nodes in an integrated circuit schematic diagram, and calibrating corresponding positions of the circuit nodes in the integrated circuit schematic diagram in a layout; then, converting the wiring, bonding pads, isolation gaskets and other structures in the layout into layout polygons and performing Boolean operation to form uniform layout polygons, and generating triangle mesh subdivision with constraint based on the uniform layout polygons and edges thereof; and finally traversing the triangle mesh subdivision with the constraint and filling the network numbers, acquiring the network numbers of all the position points according to the triangles of the circuit nodes, which correspond to all the position points in the layout, and corresponding the network numbers of all the position points to the network numbers of the circuit nodes in the integrated circuit schematic diagram, wherein if the network numbers of all the position points completely correspond to the network numbers of the circuit nodes in the integrated circuit schematic diagram, the detected integrated circuit layout design is determined to have no defect, otherwise, the design is defective, the problems of open circuit caused by overlarge radius of the isolation gasket, short circuit caused by overlarge radius of the pad, actual error connection of the via hole caused by negligence of an engineer and the like are detected, so that the accurate detection of the integrated circuit layout design defect is realized.
Drawings
Fig. 1 is a general flow chart of the present invention.
Fig. 2 is a schematic diagram of a bond pad and spacer radius that is too large to cause a circuit break.
Fig. 3 is a schematic diagram of proper pad and spacer radius guaranteed connectivity.
Fig. 4 is a schematic diagram of a short circuit caused by an excessive pad radius.
Fig. 5 is a schematic diagram of a correct pad radius guaranteed connection relationship.
Fig. 6 is a schematic diagram of a short circuit caused by the lack of a spacer in the middle layer.
Fig. 7 is a schematic diagram of a correct addition of spacer spacers.
FIG. 8 is a schematic diagram of a copper clad layer, a bonding pad and an isolation pad of any one layer layout.
Fig. 9 is a schematic diagram of conversion of copper clad layers, pads and spacer pads into layout polygons.
FIG. 10 is a restored polygon edge
Schematic of the process.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
The application provides an accurate detection method for determining integrated circuit layout design defects based on grid subdivision, which comprises the following steps of S100-S800 as shown in FIG. 1:
s100: acquiring an integrated circuit schematic diagram and a corresponding integrated circuit layout;
s200: filling in network numbers of circuit nodes in the integrated circuit schematic diagram;
the method comprises the following specific steps:
step 1-1: numbering all circuit nodes in the integrated circuit schematic diagram to form a set { i } of all circuit nodes in the integrated circuit schematic diagram, wherein i=1, 2, …, N and N are the number of the circuit nodes;
step 1-2: filling circuit nodes into all circuit branches in the integrated circuit schematic diagram to form an association matrix;
wherein, the circuit branch is set aslThe association matrix is A, and the size of the association matrix is N rows and N columns. The specific method comprises the following steps: firstly, initializing all elements of an association matrix to be 0, and setting circuit branches to bel j J=1, 2, …, M is the number of all circuit branches of the integrated circuit schematic diagram, and if two nodes M and n connected by the circuit branch are found, the element a of the correlation matrix a is modified mn = A nm =1, wherein a mn The elements of m rows and n columns of the incidence matrix A;
step 1-3: setting an initialization parameter, namely, the current processing circuit node k=1; current network number net=1; circuit node processing set { Process i The value of the element is 0, i represents the ith circuit node, i=1, 2, …, N is the number of circuit nodes, and the front line set is V front ={k}；
Step 1-4: if the front line set is an empty set, setting net=net+ 1, and turning to the step 1-5; if the front line set is not the empty set, the step 1-7 is carried out;
step 1-5: setting k=k+1, if the current processing node is greater than the number of circuit nodes, ending the step of filling in the network numbers of the circuit nodes in the integrated circuit schematic diagram, otherwise, turning to the steps 1-6;
step 1-6: if Process k =0, adding the current processing circuit node to the front-line set and proceeding to steps 1-7 if Process k If the value is equal to 1, the step 1-5 is carried out;
step 1-7: the last circuit node v in the front line set is fetched, and removed from the front line set, and then a determination is made:
if Process v =0, set Net v =Net，Net v Setting a Process for the network number of the circuit node v v =1, searching all column numbers with a v-th row value of 1 in the correlation matrix, adding a circuit node with a Process value of 0 corresponding to the column number into the front line set, and turning to the steps 1-4 until the step of filling in the network number of the circuit node in the integrated circuit schematic diagram is finished; if Process v =1, then go directly to steps 1-4.
S300: determining the corresponding position of a circuit node in the integrated circuit schematic diagram in the integrated circuit layout according to the integrated circuit schematic diagram and the position Guan Jibiao of the integrated circuit layout, and taking the position as the circuit node of the integrated circuit layout;
wherein, there is also a net-table file between the integrated circuit schematic and the integrated circuit layout, and the net-table file is generated by the circuit schematic design software based on the integrated circuit schematic. The information recorded by the network table file contains information of each used component in the schematic diagram, including component types (resistance, inductance, capacitance, transformer, potentiometer, switch and the like) and device types (diode, triode, field effect transistor, power supply and the like), circuit node names corresponding to component pins, package PCB device information corresponding to the component pins and all network information.
According to the names of the circuit nodes corresponding to the pins of the components and the network information corresponding to the components, the network numbers of the circuit nodes in the integrated circuit schematic diagram can be filled in;
meanwhile, the names of the circuit nodes corresponding to the component pins are also marked in the integrated circuit design layout, and the positions of the circuit nodes in the integrated circuit schematic diagram corresponding to the layout can be marked according to the same circuit node names corresponding to the component pins.
S400: converting wiring, a bonding pad caused by a via hole and an isolation gasket in the integrated circuit layout into a layout polygon, and performing polygon Boolean operation with the originally defined copper-clad polygon to form a unified layout polygon;
the method for forming the unified layout polygons comprises the following specific steps of:
step 2-1: converting the wiring defining the starting point, the ending point and the width into a rectangle;
the method for converting the rectangular shape comprises the following steps: taking the length of the wiring line between the starting point and the ending point as the center, and respectively expanding one half of preset width to two sides of the width to form the rectangle; the preset width is the set wiring width.
Step 2-2: converting the isolation pad caused by the via hole into a hollowed polygon;
wherein the hollowed-out polygon is defined by a shape defined by a spacer:
if the defined shape is a circle, the defined shape can be converted into a hollowed positive n-sided shape, n=6, 8, 12, 18 and the like can be taken according to the precision requirement, and the larger the n value is, the higher the required precision is, but the larger the calculation amount is brought at the same time;
if the defined shape is an ellipse, discrete points can be taken on the ellipse in a mode of equal radian under polar coordinates, the number of the discrete points can be taken according to the precision requirement, and the larger the number of the discrete points is, the higher the required precision is;
if the defined shape is a polygon, directly taking the defined polygon;
step 2-3: converting the bonding pad caused by the via hole into a copper-clad polygon;
wherein the copper-clad polygon is defined by a shape defined by the pad:
if the defined shape is a circle, the defined shape can be converted into a positive n-sided shape according to the precision requirement, n=6, 8, 12, 18 and the like can be taken according to the precision requirement, and the larger the n value is, the higher the required precision is, but the larger the calculation amount is brought at the same time;
if the defined shape is an ellipse, discrete points can be taken on the ellipse in a mode of equal radian under polar coordinates, the number of the discrete points can be taken according to the precision requirement, and the larger the number of the discrete points is, the higher the required precision is;
if the defined shape is a polygon, directly taking the defined polygon;
as shown in FIG. 8, FIG. 8 is a schematic diagram of a copper-clad layer, a bonding pad and an isolation pad of any one layout. If the network where the via and the pad brought by the via are not the same network as the network where the copper-clad layer is, a spacer needs to be added between the copper-clad layer and the pad.
Further, as shown in fig. 9, fig. 9 is a schematic diagram of converting the copper clad layer, the bonding pad and the isolation pad into a layout polygon. The spacer and the bonding pad are directly approximated by a regular octagon, and the distance between the vertex of the regular polygon and the center of the regular polygon is taken as a circle radius, so that the size of the regular polygon is defined. For copper-clad polygons, the polygons are defined as (1, 2,3, 4) and numbered in a counterclockwise arrangement, and for hollowed-out polygons defined by the isolation gaskets, the polygons are defined as (5,6,7,8,9,10,11,12) and numbered in a clockwise arrangement; the filled polygons defined by pads within the hollowed polygons are defined as (13,14,15,16,17,18,19,20) and numbered counterclockwise.
Step 2-4: converting the hollowed-out circle defined in the copper-clad polygon into a hollowed-out regular polygon in the copper-clad polygon;
step 2-5: performing Boolean 'union' operation on the rectangle and the originally defined copper-clad polygon to form a first new copper-clad polygon;
the copper-clad polygon comprises a rectangle converted by wiring and an originally defined copper-clad polygon;
step 2-6: performing Boolean 'difference' operation on the first new copper-clad polygon, the hollowed polygon and the hollowed regular polygon to form a second new copper-clad polygon;
step 2-7: performing Boolean 'union' operation on the second new copper-clad polygon and the copper-clad polygon formed in the step 2-3 to form a unified layout polygon, wherein the unified layout polygon is the final copper-clad polygon;
the originally defined copper-clad polygon is a polygon which is defined as a layout polygon in a layout design file and polygon vertexes are arranged anticlockwise.
S500: generating triangle mesh subdivision with constraint according to the layout polygon and circuit nodes in the integrated circuit layout;
as shown in fig. 10:
step 3-1: forming Delaunay triangle grids according to all vertexes of the layout polygon and position coordinate points in the integrated circuit layout corresponding to circuit nodes of the integrated circuit layout;
step 3-2: collecting all of the Delaunay triangle meshEdges of polygons not belonging to a common edge of two triangles are ordered according to side length to form a setLost；
Step 3-3: from the collectionLostThe side (side) with the longest side length is taken out
) At the same time->
From the collectionLostRemoving the components;
step 3-4: from the edge
Is a vertex of (a)AStarting, searching for the vertexAAnd the vertexC、DIs positioned at the side->
Triangle delta on both sidesACD，ΔACDIs->
And (2) with the side->
Intersection, exchanging the triangle deltaACDTriangle delta with its neighborsDCETo obtain triangle deltaACEAnd deltaEDAThe method comprises the steps of carrying out a first treatment on the surface of the Wherein the neighbor triangle is a triangle with a common side with the searched triangle;
step 3-5: repeating said steps 3-4 until said edge
Is the common edge of two neighbor triangles; />
Step 3-6: judging the setLostWhether it is an empty set, if not, re-from said setLostRemoving the longest side from the collectionLostAfter removing, continuing to execute the step 3-4, if yes, directly formingForming a triangle mesh with constraint.
S600: traversing the triangle mesh with the constraint and filling in network numbers;
further, before traversing the triangle mesh with constraint and filling in the network number, the method further comprises:
recording each corresponding position point of the circuit node in the marked integrated circuit schematic diagram in the integrated circuit layout, and recording triangles associated with each position point; the triangle associated with the position point comprises a vertex of the triangle and the position point, and one position point is associated with a plurality of triangles.
The specific steps of traversing the triangle mesh with the constraint and filling in the network number include:
step 4-1: numbering each copper-clad polygon in sequence, and initially setting the numbers of all triangles in the constrained triangle mesh subdivision as unnumbered, and setting the current q=1 th copper-clad polygon to be processed;
step 4-2: setting a current peripheral grid cell as a setFrontThe set ofFrontIs empty from the firstqAny edge of each copper-clad polygoneStarting from the left triangle associated with this edge is foundtTriangle is arrangedtIs the number of the q-th copper-clad polygon, and then the triangle is formedtAdding to a collectionFrontIn (a) and (b); wherein, the firstqAny edge of each copper-clad polygoneIs the left triangle of (1) including the edgeeAnd triangle sideeDirection and the first of (2)qCopper-clad polygonal edgeeIs the same triangle;
step 4-3: from the collectionFrontTaking out a triangletAnd from the collectionFrontIf the triangle is removedtAny one or more of the three neighbor triangles of (a) are unnumbered and the common edge is not an edge of any copper-clad polygon, then the triangle is treatedtTo join the set of one or more neighbor triangles of (a)FrontAnd add new to the collectionFrontTriangle of (2)Is numbered as the firstqNumbering the copper-clad polygons; wherein the common side is the triangletAdjacent triangles are adjacent to the triangletIs a common edge of (2);
step 4-4: judging the setFrontIf the set is the empty set, if the set is not the empty set, the step is shifted to step 4-3, and if the set is the empty set, the set is firstly setq=q+1, then go to step 4-2 until the setFrontIs empty;
step 4-5: judging whether all the copper-clad polygons are processed, and if so, ending the superposition of the copper-clad polygons; if not, returning to continue to process the untreated copper-clad polygon until all copper-clad polygons are processed.
S700: acquiring a network number of a corresponding position point in the integrated circuit layout according to a triangle associated with the position point of a circuit node in the integrated circuit schematic diagram;
the method specifically comprises the following steps: and finding out any associated triangle for the triangle associated with the corresponding position point of the circuit node in each integrated circuit schematic diagram, wherein the number of the triangle is used as the number of the position point, and the number of the position point is the network number of the position point.
S800: comparing and judging the network numbers of the circuit nodes in the integrated circuit layout with the network numbers of the circuit nodes in the integrated circuit schematic diagram, and determining whether the integrated circuit layout has design defects according to the judging result.
According to the position relationship between the circuit nodes in the integrated circuit schematic diagram and the integrated circuit layout defined by a user, a mapping relationship between the network numbers of the position points and the network numbers of the circuit nodes in the integrated circuit schematic diagram is established, if the mapping relationship is one-to-one mapping, the integrated circuit layout is determined to have no design defect, if the mapping relationship is not one-to-one mapping, the integrated circuit layout is determined to have the design defect, and the position of the circuit node which is not corresponding to the mapping relationship is the position of the design defect.
For example: assuming that the number of circuit nodes of a certain integrated circuit is 10, 2 networks are formed, the network numbers of which are shown in the following table, and the network numbers of the position points corresponding to the circuit nodes in the integrated circuit schematic diagram, which are obtained according to the steps S200-S700, are shown in the table 1 for the layout designed according to the integrated circuit schematic diagram:
| circuit node sequence number | Network numbering of circuit nodes | Corresponding location point network numbering |
| 1 | 1 | 2 |
| 2 | 1 | 2 |
| 3 | 2 | 1 |
| 4 | 2 | 1 |
| 5 | 2 | 1 |
| 6 | 2 | 1 |
| 7 | 2 | 1 |
| 8 | 1 | 3 |
| 9 | 2 | 1 |
| 10 | 2 | 1 |
TABLE 1
As can be seen from table 1, the detected integrated circuit layout design is defective in that the circuit node network number 1 maps corresponding location point network numbers 2 and 3 simultaneously, not one-to-one.
The foregoing is merely a preferred embodiment of the present invention, and it should be noted that modifications and improvements made by those skilled in the art without departing from the present technical solution shall be considered as falling within the scope of the claims.
Claims (10)
1. The accurate detection method for determining the design defects of the integrated circuit layout based on the mesh subdivision is characterized by comprising the following steps of:
acquiring an integrated circuit schematic diagram and a corresponding integrated circuit layout;
filling in network numbers of circuit nodes in the integrated circuit schematic diagram;
determining the corresponding position of a circuit node in the integrated circuit schematic diagram in the integrated circuit layout according to the integrated circuit schematic diagram and the position Guan Jibiao of the integrated circuit layout, and taking the position as the circuit node of the integrated circuit layout;
converting wiring, a bonding pad caused by a via hole and an isolation gasket in the integrated circuit layout into a layout polygon, and performing polygon Boolean operation with the originally defined copper-clad polygon to form a unified layout polygon;
generating triangle mesh subdivision with constraint according to the layout polygon and circuit nodes in the integrated circuit layout;
traversing the triangle mesh with the constraint and filling in network numbers;
acquiring a network number of a corresponding position point in the integrated circuit layout according to a triangle associated with the position point of a circuit node in the integrated circuit schematic diagram;
comparing and judging the network numbers of the circuit nodes in the integrated circuit layout with the network numbers of the circuit nodes in the integrated circuit schematic diagram, and determining whether the integrated circuit layout has design defects according to the judging result.
2. The method according to claim 1, characterized in that: the filling out of network numbers of circuit nodes in the integrated circuit schematic diagram comprises the following steps:
step 1-1: numbering all circuit nodes in the integrated circuit schematic diagram to form a set { i } of all circuit nodes in the integrated circuit schematic diagram, wherein i=1, 2, …, N and N are the number of the circuit nodes;
step 1-2: filling circuit nodes into all circuit branches in the integrated circuit schematic diagram to form an association matrix;
step 1-3: setting an initialization parameter, namely, the current processing circuit node k=1; current network number net=1; circuit node processing set { Process i The value of the element is 0, i represents the ith circuit node, i=1, 2, …, N is the number of circuit nodes, and the front line set is V front ={k}；
Step 1-4: if the front line set is an empty set, setting net=net+1, and turning to the step 1-5; if the front line set is not the empty set, the step 1-7 is carried out;
step 1-5: setting k=k+1, if the current processing node is greater than the number of circuit nodes, ending the step of filling in the network numbers of the circuit nodes in the integrated circuit schematic diagram, otherwise, turning to the steps 1-6;
step 1-6: if Process k =0, adding the current processing circuit node to the front-line set and proceeding to steps 1-7 if Process k If the value is equal to 1, the step 1-5 is carried out;
step 1-7: the last circuit node v in the front line set is fetched, and removed from the front line set, and then a determination is made:
if Process v =0, set Net v =Net，Net v Setting a Process for the network number of the circuit node v v =1, searching all column numbers with a v-th row value of 1 in the correlation matrix, adding a circuit node with a Process value of 0 corresponding to the column number into the front line set, and turning to the steps 1-4 until the step of filling in the network number of the circuit node in the integrated circuit schematic diagram is finished; if Process v =1, then go directly to steps 1-4.
3. The method according to claim 2, characterized in that: the determining, according to the integrated circuit schematic diagram and the position Guan Jibiao of the integrated circuit layout, a position of a circuit node in the integrated circuit schematic diagram corresponding to the integrated circuit layout, and taking the position as the circuit node of the integrated circuit layout includes:
generating a network table file according to the integrated circuit schematic diagram, wherein the network table file comprises component types, circuit node names corresponding to component pins, package PCB device information corresponding to the circuit node names and all network information;
filling in the network number of the circuit node in the integrated circuit schematic diagram according to the name of the circuit node corresponding to the component pin and the network information corresponding to the component;
and marking the corresponding positions of the circuit nodes in the integrated circuit schematic diagram in the integrated circuit layout according to the same circuit node names corresponding to the component pins in the integrated circuit layout.
4. A method according to claim 3, characterized in that: the specific steps of converting the wiring, the bonding pad caused by the via hole and the isolation pad in the integrated circuit layout into layout polygons and performing polygon Boolean operation with the originally defined copper-clad polygons to form uniform layout polygons are as follows:
step 2-1: converting the wiring defining the starting point, the ending point and the width into a rectangle;
step 2-2: converting the isolation pad caused by the via hole into a hollowed polygon;
step 2-3: converting the bonding pad caused by the via hole into a copper-clad polygon;
step 2-4: converting the hollowed-out circle defined in the copper-clad polygon into a hollowed-out regular polygon in the copper-clad polygon;
step 2-5: performing Boolean 'union' operation on the rectangle and the originally defined copper-clad polygon to form a first new copper-clad polygon;
step 2-6: performing Boolean 'difference' operation on the first new copper-clad polygon, the hollowed polygon and the hollowed regular polygon to form a second new copper-clad polygon;
step 2-7: performing Boolean 'union' operation on the second new copper-clad polygon and the copper-clad polygon formed in the step 2-3 to form a unified layout polygon;
the originally defined copper-clad polygon is a polygon which is defined as a layout polygon in a layout design file and polygon vertexes are arranged anticlockwise.
5. The method according to claim 4, wherein: the converting the trace defining the starting point, the ending point and the width into a rectangle comprises:
and taking the length of the wiring line between the starting point and the ending point as the center, and respectively expanding a half of preset width to two sides of the width to form the rectangle.
6. The method according to claim 5, wherein: generating triangle mesh with constraint according to the layout polygon and circuit nodes in the integrated circuit layout, including:
step 3-1: forming Delaunay triangle grids according to all vertexes of the layout polygon and position coordinate points in the integrated circuit layout corresponding to circuit nodes of the integrated circuit layout;
step 3-2: collecting all sides of polygons which do not belong to the common sides of the two triangles in the Delaunay triangle grid, and sorting according to side length to form a setLost；
Step 3-3: from the collectionLostRemoving the longest side from the collectionLostRemoving the components;
step 3-4: starting from one vertex of the side with the longest side, searching triangles which contain the vertex and are positioned on two sides of the side with the longest side, exchanging the public sides of the triangles and the neighboring triangles if the side intersected with the side with the longest side is searched and is not the side of the other polygon, obtaining two new triangles, and canceling the exchanging of the intersected side if the side intersected with the side with the longest side is searched and directly adding one vertex and a grid node at the intersection point of the two sides, and inserting the grid node into the Delaunay triangle grid, wherein the grid node divides two neighboring triangles into four triangles, and the two intersected sides are divided into four sides sharing the vertex by the vertex; the neighbor triangle is a triangle with a common side with the searched triangle;
step 3-5: repeating the steps 3-4 until the side with the longest side length is the common side of the two neighbor triangles;
step 3-6: judging the setLostWhether it is an empty set, if not, re-from said setLostRemoving the longest side from the collectionLostIs removed fromAnd then continuing to execute the step 3-4, if yes, directly forming the triangular mesh subdivision with constraint.
7. The method according to claim 6, wherein: before traversing the triangle mesh with the constraint and filling in the network number, the method further comprises the following steps:
recording each corresponding position point of the circuit node in the marked integrated circuit schematic diagram in the integrated circuit layout, and recording triangles associated with each position point; the triangle associated with the position point comprises a vertex of the triangle and the position point, and one position point is associated with a plurality of triangles.
8. The method according to claim 7, wherein: traversing the triangle mesh with the constraint and filling in the network number, wherein the method comprises the following steps:
step 4-1: numbering each copper-clad polygon in sequence, and initially setting the numbers of all triangles in the constrained triangle mesh subdivision as unnumbered, and setting the current q=1 th copper-clad polygon to be processed;
step 4-2: setting a current peripheral grid cell as a setFrontThe set ofFrontIs empty from the firstqAny edge of each copper-clad polygoneStarting from the left triangle associated with this edge is foundtTriangle is arrangedtIs the number of the q-th copper-clad polygon, and then the triangle is formedtAdding to a collectionFrontIn (a) and (b); wherein, the firstqAny edge of each copper-clad polygoneIs the left triangle of (1) including the edgeeAnd triangle sideeDirection and the first of (2)qCopper-clad polygonal edgeeIs the same triangle;
step 4-3: from the collectionFrontTaking out a triangletAnd from the collectionFrontIf the triangle is removedtAny one or more of the three neighbor triangles of (a) are unnumbered and the common edge is not an edge of any copper-clad polygon, then the triangle is treatedtIs one of (2)Or multiple neighbor triangles joining the setFrontAnd add new to the collectionFrontIs numbered as (1)qNumbering the copper-clad polygons; wherein the common side is the triangletAdjacent triangles are adjacent to the triangletIs a common edge of (2);
step 4-4: judging the setFrontIf the set is the empty set, if the set is not the empty set, the step is shifted to step 4-3, and if the set is the empty set, the set is firstly setq=q+1, then go to step 4-2 until the setFrontIs empty;
step 4-5: judging whether all the copper-clad polygons are processed, and if so, ending the superposition of the copper-clad polygons; if not, returning to continue to process the untreated copper-clad polygon until all copper-clad polygons are processed.
9. The method according to claim 8, wherein: the obtaining the network number of the position point according to the triangle associated with the position point corresponding to the circuit node in the integrated circuit schematic diagram, including:
and finding out any associated triangle for the triangle associated with the corresponding position point of the circuit node in each integrated circuit schematic diagram, wherein the number of the triangle is used as the number of the position point, and the number of the position point is the network number of the position point.
10. The method according to claim 9, wherein: comparing and judging the network number of the circuit node in the integrated circuit layout with the network number of the circuit node in the integrated circuit schematic diagram, and determining whether the integrated circuit layout has a design defect according to a judging result, wherein the method comprises the following steps:
according to the position relationship between the circuit nodes in the integrated circuit schematic diagram and the integrated circuit layout defined by a user, establishing a mapping relationship between the network numbers of the position points and the network numbers of the circuit nodes in the integrated circuit schematic diagram, if the mapping relationship is one-to-one mapping, determining that the integrated circuit layout has no design defect, if the mapping relationship is not one-to-one mapping, determining that the integrated circuit layout has the design defect, and if the position of the circuit node which is not corresponding to the mapping relationship is the position of the design defect.
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| CN117034857B (en) * | 2023-10-10 | 2024-01-12 | 北京智芯仿真科技有限公司 | Method and device for identifying integrated circuit layout network by polygon large-area overlapping |
| CN117272914B (en) * | 2023-10-31 | 2024-03-12 | 北京智芯仿真科技有限公司 | Method and device for quickly determining copper-clad shape to form topological structure based on quadtree |
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| CN111767688B (en) * | 2020-09-03 | 2020-12-01 | 北京智芯仿真科技有限公司 | Integrated circuit layout polygon unstructured grid self-adaptive subdivision method and system |
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