CN115600549A - Precise detection method for determining layout design defects of integrated circuit based on mesh subdivision - Google Patents
Precise detection method for determining layout design defects of integrated circuit based on mesh subdivision Download PDFInfo
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Abstract
The invention discloses a precise detection method for determining the design defects of an integrated circuit layout based on mesh generation, which comprises the steps of filling in the network number of circuit nodes in an integrated circuit schematic diagram, and calibrating the corresponding positions of the circuit nodes in the layout; then, converting routing lines, pads and isolation gaskets in the layout, which are caused by the via holes, into layout polygons and performing Boolean operation on the layout polygons and the originally defined copper-clad polygons to form uniform layout polygons, and generating a constrained triangular mesh subdivision based on the uniform layout polygons and the edges of the uniform layout polygons; and finally, traversing the constrained triangular mesh subdivision, filling network numbers, acquiring the network numbers of the position points according to the triangles to which the position points corresponding to the circuit nodes in the layout belong, corresponding the network numbers of the position points to the network numbers of the circuit nodes in the integrated circuit schematic diagram, and judging the design defects according to the corresponding results, thereby realizing the accurate detection of the design defects of the integrated circuit layout.
Description
Technical Field
The invention belongs to the technical field of integrated circuit layout detection, and particularly relates to an accurate detection method for determining design defects of an integrated circuit layout based on mesh subdivision.
Background
With the development of communication technology, research and development of very large scale integrated circuits have been gradually developed. In order to improve the performance of electronic equipment, reduce the size and cost, transistors, other components and circuits are integrated on a small semiconductor substrate. In order to realize more functions, the ultra-large scale integrated circuit has a structure from several layers to hundreds of layers, each layer of structure is extremely complex, transistors of tens of millions or even hundreds of millions are integrated, and the ultra-large scale integrated circuit has a multi-scale structure from a centimeter level of the whole size to a nanometer level of the most tiny component.
The layout of the very large scale integrated circuit is composed of structures such as copper-clad polygons, routing lines, via holes, bonding pads, isolation gaskets and the like, and the connection relationship of the structures is derived from a schematic diagram forming the layout of the integrated circuit, so that the connection topological diagram corresponding to the connection relationship is consistent with the topological structure of the circuit schematic diagram. However, in an actually designed integrated circuit layout, the topological relation of the integrated circuit layout may be changed due to unreasonable sizes of the pads and the spacers and unreasonable wiring connections, for example, the problem of open circuit caused by an excessively large radius of the spacers, or the problem of short circuit caused by an excessively large radius of the pads, and the problem of actual erroneous connection of the vias caused by negligence of engineers may occur; for example, an excessive radius of the anti-pad as shown in fig. 2-3 causes open circuit problems, an excessive radius of the pad and spacer in fig. 2 causes open circuit, and fig. 3 ensures connectivity for the correct radius; fig. 4-5 show the shorting problem caused by an excessive pad radius, fig. 4 shows the shorting caused by an excessive pad radius, fig. 5 shows the connection relationship for the correct pad radius, and fig. 6-7 show the via connection error caused by engineer negligence: the lack of spacer pads in the middle layer of fig. 6 results in a short circuit, while fig. 7 shows the correct addition of spacer pads.
Disclosure of Invention
In view of the deficiencies of the prior art, the present application provides a method for accurately detecting layout design defects of an integrated circuit based on mesh generation, comprising the steps of:
acquiring an integrated circuit schematic diagram and a corresponding integrated circuit layout;
filling network numbers of circuit nodes in the schematic diagram of the integrated circuit;
calibrating the corresponding position of the circuit node in the integrated circuit schematic diagram in the integrated circuit layout according to the position relation between the integrated circuit schematic diagram and the integrated circuit layout, and taking the position as the circuit node of the integrated circuit layout;
converting the routing lines, the bonding pads and the isolation gaskets in the integrated circuit layout into layout polygons and performing polygon Boolean operation with the originally defined copper-clad polygons to form uniform layout polygons;
generating a triangular mesh subdivision with constraints according to the layout polygon and the circuit nodes in the integrated circuit layout;
traversing the constrained triangular mesh generation and filling in network numbers;
acquiring the network number of a position point according to a triangle associated with the position point corresponding to the circuit node in the integrated circuit schematic diagram in the integrated circuit layout;
and comparing and judging the network number of the circuit node in the integrated circuit layout with the network number of the circuit node in the integrated circuit schematic diagram, and determining whether the integrated circuit layout has a design defect according to a judgment result.
In some embodiments, said populating a network number of a circuit node in an integrated circuit schematic includes:
step 1-1: numbering all circuit nodes in the integrated circuit schematic diagram to form a set { i }, i =1,2, … of all circuit nodes in the integrated circuit schematic diagram, wherein N is the number of the circuit nodes;
step 1-2: filling circuit nodes in all circuit branches in the integrated circuit schematic diagram to form an incidence matrix;
step 1-3: setting initialization parameters, namely current processing circuit node k =1; the current network number Net =1; circuit node processing set Process i A value of 0,i for the element denotes the i-th circuit node, i =1,2, …, N is the number of circuit nodes, the set of front lines is V front ={k}；
Step 1-4: if the front line set is an empty set, setting Net = Net +1, and turning to the step 1-5; if the front line set is not an empty set, turning to the step 1-7;
step 1-5: setting k = k +1, if the number of the current processing nodes is larger than the number of the circuit nodes, finishing the step of filling the network numbers of the circuit nodes in the integrated circuit schematic diagram, and otherwise, turning to the step 1-6;
step 1-6: if Process k If not, adding the current processing circuit node to the front line set and transferring to the step 1-7, if the Process is finished k If not, turning to the step 1-5;
step 1-7: taking out the last circuit node v in the front line set, removing the last circuit node from the front line set, and then judging:
if the Process is processed v =0, set Net v =Net，Net v Setting a Process for the network number of the circuit node v v =1, searching all column numbers with a v-th row value of 1 in the incidence matrix, adding the circuit node with a Process value of 0 corresponding to the column number into the front line set, and turning to step 1-4 until the step of filling the network number of the circuit node in the schematic diagram of the integrated circuit is finished; if the Process is v And =1, directly carrying out the step 1-4.
In some embodiments, the calibrating, according to the position relationship between the integrated circuit schematic diagram and the integrated circuit layout, the corresponding position of the circuit node in the integrated circuit schematic diagram in the integrated circuit layout, and using the position as the circuit node in the integrated circuit layout, includes:
generating a network table file according to the integrated circuit schematic diagram, wherein the network table file comprises component types, circuit node names corresponding to component pins, package PCB (printed circuit board) device information corresponding to the circuit node names and all network information;
filling the network number of the circuit node in the schematic diagram of the integrated circuit according to the circuit node name corresponding to the pin of the component and the network information corresponding to the component;
and marking the corresponding positions of the circuit nodes in the integrated circuit schematic diagram in the integrated circuit layout according to the same circuit node names corresponding to the component pins in the integrated circuit layout.
In some embodiments, the step of converting the routing lines, the pads caused by the via holes, and the spacers in the integrated circuit layout into layout polygons and performing a polygon boolean operation with the originally defined copper-clad polygons to form unified layout polygons includes:
step 2-1: converting the routing defining the starting point, the end point and the width into a rectangle;
step 2-2: converting the spacer caused by the via hole into a hollowed polygon;
step 2-3: converting the bonding pad caused by the via hole into a copper-clad polygon;
step 2-4: converting the hollowed circle defined in the copper-clad polygon into a hollowed regular polygon in the copper-clad polygon;
step 2-5: performing Boolean 'union' operation on the rectangle and the originally defined copper-clad polygon to form a first new copper-clad polygon;
step 2-6: performing Boolean 'difference' operation on the first new copper-clad polygon, the hollowed polygon and the hollowed regular polygon to form a second new copper-clad polygon;
step 2-7: and performing Boolean 'combination' operation on the second new copper-clad polygon and the copper-clad polygon formed in the step 2-3 to form a uniform layout polygon.
The originally defined copper-clad polygon is a polygon which is defined as a layout polygon in a layout design file, and the vertexes of the polygon are arranged in a counterclockwise mode.
In some embodiments, converting the trace defining the start point, the end point, and the width into a rectangle includes:
and respectively expanding half of preset width to two sides of the width by taking the length of the routing line between the starting point and the end point as a center to form the rectangle.
In some embodiments, the generating a constrained triangle mesh subdivision according to the layout polygon and the circuit node in the integrated circuit layout includes:
step 3-1: forming a Delaunay triangular grid according to all vertexes of the layout polygon and position coordinate points in the integrated circuit layout corresponding to the circuit nodes of the integrated circuit layout;
step 3-2: collecting the Delaunay triangle meshAll the edges of the polygon which do not belong to the common edge of the two triangles are sorted according to the side length to form a setLost；
Step 3-3: from the collectionLostTaking out the side with the longest side, and simultaneously taking the side with the longest side out of the setLostRemoving;
step 3-4: starting from one vertex of the side with the longest side length, searching triangles which comprise the vertex and are positioned at two sides of the side with the longest side length, if the side intersected with the side with the longest side length is not the side of another polygon, exchanging the common sides of the triangle and the adjacent triangle to obtain two new triangles, if the side intersected with the side with the longest side length is searched to be the side of another polygon, canceling the exchange of the intersected sides, directly adding a vertex and a grid node at the intersection point of the two sides, inserting the grid node into the Delaunay triangle grid, dividing the two adjacent triangles into four triangles by the grid node, and dividing the two intersected sides into four sides sharing the vertex by the vertex; wherein the neighbor triangle is a triangle having a common side with the searched triangle;
step 3-5: repeating the steps 3-4 until the side with the longest side length is the common side of the two adjacent triangles;
step 3-6: determining the setLostIf it is not, then re-selecting said setLostTaking out the side with the longest side length, and taking the side with the longest side length out of the setLostAnd (5) continuing to execute the step (3-4) after the step (5) is removed, and if so, directly forming the triangle mesh subdivision with the constraint.
In some embodiments, before traversing the constrained triangle mesh partitioning and filling in the network number, the method further comprises:
recording each corresponding position point of a circuit node in a calibrated integrated circuit schematic diagram in the integrated circuit layout, and recording a triangle associated with each position point; the triangle associated with the position point comprises a vertex of the triangle and the position point, and one position point is associated with a plurality of triangles.
In some embodiments, traversing the constrained triangular mesh partitioning and filling in a network number comprises:
step 4-1: numbering each copper-clad polygon in sequence, initially setting the numbers of all triangles in the constrained triangular mesh subdivision to be unnumbered, and setting the number of each triangle to be a q =1 copper-clad polygon to be processed currently;
step 4-2: setting a current peripheral grid cell to a setFrontThe set ofFrontIs empty, from the secondqAny side of each copper-clad polygoneStarting from, find the left triangle with this edge associationtIs provided with a triangletIs the number of the qth copper-clad polygon, and then the triangle is numberedtJoin to collectionsFrontPerforming the following steps; wherein, the firstqEach copper-clad polygon arbitrary edgeeIs a left triangle including the sideeAnd the triangle sideeIn the direction ofqEach covered with copper polygonal edgeeTriangles with the same direction;
step 4-3: from the collectionFrontTake out a triangletAnd from the collectionFrontIf the triangle is removedtThe number of any one or more of the three neighboring triangles is unnumbered, and the common edge is not the edge of any copper-clad polygon, then the triangle is puttOne or more neighbor triangles of (a) join the setFrontAnd adding a new one to said collectionFrontThe triangle of (1) is numberedqNumbering the copper-clad polygons; wherein the common side is the triangletAdjacent triangles and said triangletA common edge of (a);
step 4-4: determining the setFrontWhether the set is an empty set or not, if not, the step is shifted to a step 4-3, if the set is an empty set, the setting is firstly carried outq=q+1, and then go to step 4-2 until said setFrontIs empty;
and 4-5: judging whether all the copper-clad polygons are processed or not, and finishing the superposition of the copper-clad polygons if the processing is finished; and if not, returning to continuously process the unprocessed copper-clad polygons until all the copper-clad polygons are processed.
In some embodiments, the obtaining the network number of the position point according to the triangle associated with the corresponding position point of the circuit node in the schematic diagram of the integrated circuit in the integrated circuit layout includes:
finding out any one associated triangle for the triangle associated with the corresponding position point of the circuit node in each integrated circuit schematic diagram in the integrated circuit layout, and taking the number of the triangle as the number of the position point, wherein the number of the position point is the network number of the position point.
In some embodiments, the comparing and determining the network number of the circuit node in the integrated circuit layout with the network number of the circuit node in the schematic diagram of the integrated circuit, and determining whether the integrated circuit layout has a design defect according to the determination result includes:
according to the position relation between the circuit node in the integrated circuit schematic diagram and the integrated circuit schematic diagram defined by a user, establishing a mapping relation between the network number of the position point and the network number of the circuit node in the integrated circuit schematic diagram, if the mapping relation is one-to-one mapping, determining that no design defect exists in the integrated circuit schematic diagram, and if the mapping relation is not one-to-one mapping, determining that the design defect exists in the integrated circuit schematic diagram, wherein the position of the circuit node which does not correspond to the mapping relation is the position of the design defect.
The invention has the beneficial effects that:
firstly, filling network numbers of circuit nodes in an integrated circuit schematic diagram, and calibrating corresponding positions of the circuit nodes in the integrated circuit schematic diagram in a layout; then, converting structures such as routing lines, bonding pads and isolation gaskets caused by via holes in the layout into layout polygons and performing Boolean operation to form uniform layout polygons, and generating a triangular mesh subdivision with constraints based on the uniform layout polygons and the edges thereof; and finally, traversing the constrained triangular mesh subdivision, filling network numbers, acquiring the network numbers of the position points according to the triangles to which the position points corresponding to the circuit nodes in the layout belong, and corresponding the network numbers of the position points to the network numbers of the circuit nodes in the integrated circuit schematic diagram, wherein if the network numbers of the position points completely correspond to the network numbers of the circuit nodes in the integrated circuit schematic diagram, the detected integrated circuit layout design is determined to have no defects, otherwise, the design is defective, and accordingly, the problems of open circuit caused by overlarge radius of an isolation gasket, short circuit caused by overlarge radius of a bonding pad, through hole actual wrong connection caused by negligence of an engineer and the like are detected, so that the accurate detection of the design defects of the integrated circuit layout is realized.
Drawings
FIG. 1 is a general flow diagram of the present invention.
Fig. 2 is a schematic diagram of an open circuit caused by an excessive radius of the pad and the spacer.
Fig. 3 is a schematic diagram of the correct pad and spacer radius assurance communication.
Fig. 4 is a schematic diagram of a short circuit caused by an excessively large radius of a pad.
Fig. 5 is a schematic diagram of a correct pad radius assurance connection.
Fig. 6 is a schematic diagram of a short circuit caused by the absence of a spacer in the middle layer.
FIG. 7 is a schematic view of a proper spacer.
Fig. 8 is a schematic diagram of a copper-clad layer, a bonding pad and a spacer in any layer layout.
Fig. 9 is a schematic diagram of the conversion of the copper clad layer, the bonding pad and the spacer into layout polygons.
FIG. 10 is a diagram of restoring a polygon edge
Schematic illustration of the process.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
The application provides an accurate detection method for determining layout design defects of an integrated circuit based on mesh generation, which comprises the steps of S100-S800 as shown in figure 1:
s100: acquiring an integrated circuit schematic diagram and a corresponding integrated circuit layout;
s200: filling network numbers of circuit nodes in the schematic diagram of the integrated circuit;
the method comprises the following specific steps:
step 1-1: numbering all circuit nodes in the integrated circuit schematic diagram to form a set { i }, i =1,2, … of all circuit nodes in the integrated circuit schematic diagram, wherein N is the number of the circuit nodes;
step 1-2: filling circuit nodes in all circuit branches in the integrated circuit schematic diagram to form an incidence matrix;
wherein, the circuit branch is set aslThe incidence matrix is A, and the size of the incidence matrix is N rows and N columns. The specific method comprises the following steps: first, all elements of the incidence matrix are initialized to be 0, and the circuit branches arel j J =1,2, …, M are the number of all circuit branches of the schematic diagram of the integrated circuit, and if two nodes M and n connected to the circuit branch are found, the element a of the incidence matrix a is modified mn = A nm =1, wherein A mn Is the element of m rows and n columns of the incidence matrix A;
step 1-3: setting initialization parameters, namely current processing circuit node k =1; the current network number Net =1; circuit node processing set Process i A value of 0,i for the element denotes the ith circuit node, i =1,2, …, N being the number of circuit nodes, the front line set being V front ={k}；
Step 1-4: if the front line set is an empty set, setting Net = Net +1, and turning to the step 1-5; if the front line set is not an empty set, turning to the step 1-7;
step 1-5: setting k = k +1, if the number of the current processing nodes is larger than the number of the circuit nodes, finishing the step of filling the network numbers of the circuit nodes in the integrated circuit schematic diagram, and otherwise, turning to the step 1-6;
step 1-6: if the Process is processed k If not, adding the current processing circuit node to the front line set and transferring to the step 1-7, if the Process is finished k If not, turning to the step 1-5;
step 1-7: taking out the last circuit node v in the front line set, removing the last circuit node from the front line set, and then judging:
if the Process is processed v =0, set Net v =Net，Net v Setting a Process for the network number of the circuit node v v =1, searching all column numbers with a v-th row value of 1 in the incidence matrix, adding the circuit node with a Process value of 0 corresponding to the column number into the front line set, and turning to step 1-4 until the step of filling the network number of the circuit node in the schematic diagram of the integrated circuit is finished; if the Process is processed v And if the value is not less than 1, directly transferring to the step 1-4.
S300: calibrating the corresponding position of the circuit node in the integrated circuit schematic diagram in the integrated circuit layout according to the position relation between the integrated circuit schematic diagram and the integrated circuit layout, and taking the position as the circuit node of the integrated circuit layout;
wherein, a network table file is also arranged between the integrated circuit schematic diagram and the integrated circuit layout, and the network table file is generated by the circuit schematic diagram design software based on the integrated circuit schematic diagram. The information recorded by the network table file contains information of each used component in the schematic diagram, including component types (resistance, inductance, capacitance, transformer, potentiometer, switch, etc.) and device types (diode, triode, field effect transistor, power supply, etc.), circuit node names corresponding to pins of the component, information of the corresponding packaged PCB device, and all network information.
According to the circuit node name corresponding to the pin of the component and the network information corresponding to the component, the network number of the circuit node in the integrated circuit schematic diagram can be filled;
meanwhile, the circuit node names corresponding to the component pins are also marked in the integrated circuit design layout, and the corresponding positions of the circuit nodes in the integrated circuit schematic diagram in the layout can be marked according to the same circuit node names corresponding to the component pins.
S400: converting the routing lines, the bonding pads and the isolation gaskets in the integrated circuit layout into layout polygons and performing polygon Boolean operation with the originally defined copper-clad polygons to form uniform layout polygons;
the specific steps for forming the uniform layout polygon are as follows:
step 2-1: converting the routing defining the starting point, the end point and the width into a rectangle;
the method for converting the image into the rectangle is as follows: with the length of the routing line between the starting point and the end point as the center, respectively extending a half of preset width to two sides of the width to form the rectangle; the preset width is the set routing width.
Step 2-2: converting the spacer caused by the via hole into a hollowed-out polygon;
wherein the hollowed polygon is determined by the shape defined by the spacer:
if the defined shape is a circle, the circle can be converted into a hollowed regular n-polygon, n =6, 8, 12, 18 and the like can be taken according to the precision requirement, and the larger the value of n, the higher the precision requirement is, but the larger the calculation amount is brought;
if the defined shape is an ellipse, discrete points can be taken on the ellipse in a mode of equal radian under polar coordinates, the number of the discrete points can be taken according to the precision requirement, and the larger the number of the discrete points is, the higher the precision requirement is represented;
if the defined shape is a polygon, directly taking the defined polygon;
step 2-3: converting the bonding pad caused by the via hole into a copper-clad polygon;
wherein the copper-clad polygon is determined by the shape defined by the pad:
if the defined shape is a circle, the defined shape can be converted into a regular n-polygon according to the precision requirement, and n =6, 8, 12, 18 and the like can be taken according to the precision requirement, wherein the larger the value of n, the higher the required precision is, but the larger the calculation amount is brought;
if the defined shape is an ellipse, discrete points can be taken on the ellipse in a mode of equal radian under polar coordinates, the number of the discrete points can be taken according to the precision requirement, and the larger the number of the discrete points is, the higher the precision requirement is represented;
if the defined shape is a polygon, directly taking the defined polygon;
as shown in fig. 8, fig. 8 is a schematic diagram of a copper-clad layer, a pad and a spacer in any layout. If the network of the via holes and the pads brought by the via holes is not the same network as the network of the copper clad layers, an isolation gasket needs to be added between the copper clad layers and the pads.
Further, as shown in fig. 9, fig. 9 is a schematic diagram of the copper clad layer, the bonding pad and the spacer being converted into layout polygons. The size of the regular polygon is defined by directly approximating the spacer and the pad by a regular octagon, and taking the distance between the vertex of the regular polygon and the center as the radius of the circle. For the copper-clad polygon, the polygon is defined as (1,2,3,4) and numbered in anticlockwise arrangement, and for the hollowed-out polygon defined by the isolation gasket, the polygon is defined as (5,6,7,8,9,10,11,12) and numbered in clockwise arrangement; for the filling polygon defined by the pads in the hollow polygon, the polygon is defined as (13,14,15,16,17,18,19,20) and the number is arranged in a counterclockwise direction.
Step 2-4: converting the hollowed circle defined in the copper-clad polygon into a hollowed regular polygon in the copper-clad polygon;
step 2-5: performing Boolean 'combination' operation on the rectangle and the originally defined copper-clad polygon to form a first new copper-clad polygon;
the device comprises a rectangle converted by routing and an originally defined copper-clad polygon;
step 2-6: performing Boolean 'difference' operation on the first new copper-clad polygon, the hollowed-out polygon and the hollowed-out regular polygon to form a second new copper-clad polygon;
step 2-7: performing Boolean 'combination' operation on the second new copper-clad polygon and the copper-clad polygon formed in the step 2-3 to form a uniform layout polygon, wherein the uniform layout polygon is the final copper-clad polygon;
the originally defined copper-clad polygon is a polygon defined as a layout polygon in a layout design file, and the vertexes of the polygon are arranged in a counterclockwise mode.
S500: generating a triangular mesh subdivision with constraints according to the layout polygon and the circuit nodes in the integrated circuit layout;
as shown in fig. 10:
step 3-1: forming a Delaunay triangular grid according to all vertexes of the layout polygon and position coordinate points in the integrated circuit layout corresponding to the circuit nodes of the integrated circuit layout;
step 3-2: collecting all the edges of the polygons which do not belong to the common edge of the two triangles in the Delaunay triangular mesh, and sorting the edges according to the edge length to form a setLost；
Step 3-3: from the collectionLostTaking out the side with the longest side (side)
) At the same time, the edge is moved
From the collectionLostRemoving;
step 3-4: from the edge
One vertex ofAStarting from, searching for including said vertexAAnd the vertexC、DIs located at the edge
Triangle delta of two sidesACD，ΔACDIs not limited by
And edge
Intersect, exchange said triangle deltaACDWith its neighbour triangleΔDCEGet the triangle deltaACEAnd deltaEDA(ii) a Wherein the neighbor triangle is a triangle having a common side with the searched triangle;
step 3-5: repeating said steps 3-4 until said edge
Is a common edge of two neighboring triangles;
step 3-6: determining the setLostIf it is not, then re-selecting said setLostTaking out the side with the longest side length, and taking the side with the longest side length out of the setLostAnd (5) continuing to execute the step (3-4) after removing the intermediate mesh, if so, directly forming the triangular mesh subdivision with the constraint.
S600: traversing the constrained triangular mesh generation and filling in the network number;
further, before traversing the constrained triangular mesh subdivision and filling the network number, the method further comprises the following steps:
recording each position point corresponding to a circuit node in a calibrated integrated circuit schematic diagram in the integrated circuit layout, and recording a triangle associated with each position point; the triangle associated with the position point comprises a vertex of the triangle and the position point, and one position point is associated with a plurality of triangles.
The specific steps of traversing the constrained triangular mesh subdivision and filling the network number comprise:
step 4-1: numbering each copper-clad polygon in sequence, initially setting the numbers of all triangles in the constrained triangular mesh subdivision to be unnumbered, and setting the number of each triangle to be a q =1 copper-clad polygon to be processed currently;
step 4-2: setting a current peripheral grid cell to a setFrontThe set ofFrontIs empty, from the secondqAny side of each copper-clad polygoneStarting from, find the left triangle with this edge associationtSet up a triangletIs the number of the qth copper-clad polygon, and then the triangle is numberedtJoin to a collectionFrontPerforming the following steps; wherein, the first and the second end of the pipe are connected with each other,first, theqEach copper-clad polygon arbitrary edgeeIs a left triangle including the sideeAnd the triangle sideeIn the direction ofqEach covered with copper polygonal edgeeTriangles with the same direction;
step 4-3: from the collectionFrontTake out a triangletAnd from the collectionFrontIf the triangle is removedtThe number of any one or more of the three neighboring triangles is unnumbered, and the common edge is not the edge of any copper-clad polygon, then the triangle is puttOne or more neighbor triangles of (2) join the setFrontAnd adding a new one to said collectionFrontThe triangle of (1) is numberedqNumbering the copper-clad polygons; wherein the common side is the triangletAdjacent triangles and said triangletA common edge of (a);
step 4-4: determining the setFrontWhether the set is an empty set or not, if not, the step is switched to the step 4-3, and if the set is an empty set, the setting is firstly carried outq=q+1, and then go to step 4-2 until said setFrontIs empty;
and 4-5: judging whether all the copper-clad polygons are processed or not, and finishing the superposition of the copper-clad polygons if the processing is finished; and if not, returning to continuously process the unprocessed copper-clad polygons until all the copper-clad polygons are processed.
S700: acquiring the network number of the position point according to the triangle associated with the corresponding position point of the circuit node in the integrated circuit schematic diagram in the integrated circuit layout;
the method specifically comprises the following steps: finding out any one associated triangle for the triangle associated with the corresponding position point of the circuit node in each integrated circuit schematic diagram in the integrated circuit layout, and taking the serial number of the triangle as the serial number of the position point, wherein the serial number of the position point is the network serial number of the position point.
S800: and comparing and judging the network number of the circuit node in the integrated circuit layout with the network number of the circuit node in the integrated circuit schematic diagram, and determining whether the integrated circuit layout has a design defect according to the judgment result.
The method comprises the steps of establishing a mapping relation between a network number of a position point and a network number of a circuit node in an integrated circuit schematic diagram according to a position relation between the circuit node in the integrated circuit schematic diagram and the integrated circuit schematic diagram defined by a user, determining that no design defect exists in the integrated circuit schematic diagram if the mapping relation is one-to-one mapping, determining that the design defect exists in the integrated circuit schematic diagram if the mapping relation is not one-to-one mapping, and determining that the position where the circuit node which does not correspond to the mapping relation is the position where the design defect exists.
For example: assuming that 10 circuit nodes of an integrated circuit form 2 networks, the network numbers of which are shown in the following table, and for a layout designed according to the integrated circuit schematic diagram, the network numbers of the position points corresponding to the circuit nodes in the integrated circuit schematic diagram obtained in steps S200-S700 are shown in table 1:
| circuit node sequence number | Circuit node network numbering | Corresponding location |
| 1 | 1 | 2 |
| 2 | 1 | 2 |
| 3 | 2 | 1 |
| 4 | 2 | 1 |
| 5 | 2 | 1 |
| 6 | 2 | 1 |
| 7 | 2 | 1 |
| 8 | 1 | 3 |
| 9 | 2 | 1 |
| 10 | 2 | 1 |
TABLE 1
As can be seen from table 1, the detected integrated circuit layout design has defects because the circuit node net number 1 maps the corresponding position point net numbers 2 and 3 at the same time, not one-to-one mapping.
The above is only a preferred embodiment of the present invention, and it should be noted that several modifications and improvements made by those skilled in the art without departing from the technical solution should also be considered as falling within the scope of the claims.
Claims (10)
1. The precise detection method for determining the layout design defect of the integrated circuit based on mesh generation is characterized by comprising the following steps:
acquiring an integrated circuit schematic diagram and a corresponding integrated circuit layout;
filling network numbers of circuit nodes in the schematic diagram of the integrated circuit;
calibrating the corresponding position of the circuit node in the integrated circuit schematic diagram in the integrated circuit layout according to the position relation between the integrated circuit schematic diagram and the integrated circuit layout, and taking the position as the circuit node of the integrated circuit layout;
converting the routing lines, the bonding pads and the isolation gaskets in the integrated circuit layout into layout polygons and performing polygon Boolean operation with the originally defined copper-clad polygons to form uniform layout polygons;
generating a triangular mesh subdivision with constraints according to the layout polygon and the circuit nodes in the integrated circuit layout;
traversing the constrained triangular mesh generation and filling in the network number;
acquiring the network number of a position point according to a triangle associated with the position point corresponding to the circuit node in the integrated circuit schematic diagram in the integrated circuit layout;
and comparing and judging the network number of the circuit node in the integrated circuit layout with the network number of the circuit node in the integrated circuit schematic diagram, and determining whether the integrated circuit layout has a design defect according to the judgment result.
2. The method of claim 1, wherein: the filling of the network number of the circuit node in the schematic diagram of the integrated circuit comprises the following steps:
step 1-1: numbering all circuit nodes in the integrated circuit schematic diagram to form a set { i }, i =1,2, … of all circuit nodes in the integrated circuit schematic diagram, wherein N is the number of the circuit nodes;
step 1-2: filling circuit nodes in all circuit branches in the integrated circuit schematic diagram to form an incidence matrix;
step 1-3: setting initialization parameters, namely current processing circuit node k =1; the current network number Net =1; circuit node processing set Process i A value of 0,i for the element denotes the ith circuit node, i =1,2, …, N being the number of circuit nodes, the front line set being V front ={k}；
Step 1-4: if the front line set is an empty set, setting Net = Net +1, and turning to the step 1-5; if the front line set is not an empty set, turning to the step 1-7;
step 1-5: setting k = k +1, if the number of the current processing nodes is larger than the number of the circuit nodes, finishing the step of filling the network numbers of the circuit nodes in the integrated circuit schematic diagram, and otherwise, turning to the step 1-6;
step 1-6: if the Process is processed k If not, adding the current processing circuit node to the front line set and transferring to the step 1-7, if the Process is finished k If not, turning to the step 1-5;
step 1-7: taking out the last circuit node v in the front line set, removing the last circuit node from the front line set, and then judging:
if the Process is processed v =0, set Net v =Net，Net v Setting a Process for the network number of the circuit node v v =1, searching all column numbers with a v-th row value of 1 in the incidence matrix, adding the circuit node with a Process value of 0 corresponding to the column number into the front line set, and turning to step 1-4 until the step of filling the network number of the circuit node in the schematic diagram of the integrated circuit is finished; if the Process is v And if the value is not less than 1, directly transferring to the step 1-4.
3. The method of claim 2, wherein: the calibrating the corresponding position of the circuit node in the integrated circuit schematic diagram in the integrated circuit layout according to the position relationship between the integrated circuit schematic diagram and the integrated circuit layout, and taking the position as the circuit node of the integrated circuit layout, includes:
generating a network table file according to the integrated circuit schematic diagram, wherein the network table file comprises component types, circuit node names corresponding to component pins, package PCB (printed circuit board) device information corresponding to the circuit node names and all network information;
filling network numbers of circuit nodes in the schematic diagram of the integrated circuit according to the circuit node names corresponding to the pins of the components and the network information corresponding to the components;
and marking the corresponding positions of the circuit nodes in the integrated circuit schematic diagram in the integrated circuit layout according to the same circuit node names corresponding to the component pins in the integrated circuit layout.
4. The method of claim 3, wherein: the method comprises the following steps of converting routing lines, bonding pads and isolation gaskets in the integrated circuit layout into layout polygons and carrying out polygon Boolean operation with the originally defined copper-clad polygons to form unified layout polygons, wherein the concrete steps of forming the unified layout polygons comprise:
step 2-1: converting the routing defining the starting point, the end point and the width into a rectangle;
step 2-2: converting the spacer caused by the via hole into a hollowed-out polygon;
step 2-3: converting the bonding pad caused by the via hole into a copper-clad polygon;
step 2-4: converting the hollowed circle defined in the copper-clad polygon into a hollowed regular polygon in the copper-clad polygon;
step 2-5: performing Boolean 'union' operation on the rectangle and the originally defined copper-clad polygon to form a first new copper-clad polygon;
step 2-6: performing Boolean 'difference' operation on the first new copper-clad polygon, the hollowed-out polygon and the hollowed-out regular polygon to form a second new copper-clad polygon;
step 2-7: performing Boolean 'combination' operation on the second new copper-clad polygon and the copper-clad polygon formed in the step 2-3 to form a uniform layout polygon;
the originally defined copper-clad polygon is a polygon defined as a layout polygon in a layout design file, and the vertexes of the polygon are arranged in a counterclockwise mode.
5. The method of claim 4, wherein: converting the trace defining the starting point, the ending point and the width into a rectangle, includes:
and respectively expanding half of preset width to two sides of the width by taking the length of the routing line between the starting point and the ending point as a center to form the rectangle.
6. The method of claim 5, wherein: generating a triangular mesh subdivision with constraints according to the layout polygon and the circuit nodes in the integrated circuit layout, comprising:
step 3-1: forming a Delaunay triangular grid according to all vertexes of the layout polygon and position coordinate points in the integrated circuit layout corresponding to the circuit nodes of the integrated circuit layout;
step 3-2: collecting all the edges of the polygons which do not belong to the common edge of the two triangles in the Delaunay triangular mesh, and sorting the edges according to the edge length to form a setLost；
Step 3-3: from the collectionLostTaking out the side with the longest side, and simultaneously taking the side with the longest side out of the setLostRemoving;
step 3-4: starting from one vertex of the side with the longest side length, searching triangles which comprise the vertex and are positioned at two sides of the side with the longest side length, if the side which is intersected with the side with the longest side length is not the side of another polygon, exchanging the common side of the triangle and the adjacent triangle to obtain two new triangles, if the side which is intersected with the side with the longest side length is searched to be the side of another polygon, canceling the exchange of the intersected side, directly adding a vertex and a grid node at the intersection point of the two sides, inserting the grid node into the adjacent Delaunay triangle grid, dividing the two triangles into four triangles by the grid node, and dividing the two intersected sides into four sides which share the vertex by the vertex; wherein, the neighbor triangle is a triangle having a common side with the searched triangle;
step 3-5: repeating the steps 3-4 until the side with the longest side length is the common side of the two adjacent triangles;
step 3-6: determining the setLostIf not, repeating said collectionLostTaking out the side with the longest side length, and taking the side with the longest side length out of the setLostAnd (5) continuing to execute the step (3-4) after removing the intermediate mesh, if so, directly forming the triangular mesh subdivision with the constraint.
7. The method of claim 6, wherein: before traversing the constrained triangular mesh subdivision and filling the network number, the method also comprises the following steps:
recording each corresponding position point of the circuit node in the calibrated integrated circuit schematic diagram in the integrated circuit layout, recording the triangle associated with each position point; the triangle associated with the position point comprises a vertex of the triangle and the position point, and one position point is associated with a plurality of triangles.
8. The method of claim 7, wherein: traversing the constrained triangular mesh subdivision and filling network numbers, comprising the following steps:
step 4-1: numbering each copper-clad polygon in sequence, initially setting the numbers of all triangles in the constrained triangle mesh subdivision to be unnumbered, and setting the number of the copper-clad polygon to be q =1 to be processed currently;
step 4-2: setting a current peripheral grid cell to a setFrontSaid setFrontIs empty, from the secondqAny side of each copper-clad polygoneStarting from, find the left triangle with this edge associationtIs provided with a triangletIs the q-th copper-clad polygonNumbering of the shapes, and then numbering the trianglestJoin to collectionsFrontThe preparation method comprises the following steps of (1) performing; wherein, the firstqEach copper-clad polygon arbitrary edgeeIs a left triangle including the sideeAnd the triangle sideeIn the direction ofqEach covered with copper polygonal edgeeTriangles with the same direction;
step 4-3: from the collectionFrontTake out a triangletAnd from the collectionFrontIf the triangle is removedtThe number of any one or more of the three neighboring triangles is unnumbered, and the common edge is not the edge of any copper-clad polygon, then the triangle is puttOne or more neighbor triangles of (a) join the setFrontAnd adding a new one to said collectionFrontThe triangle of (1) is numberedqNumbering the copper-clad polygons; wherein the common side is the triangletAdjacent triangles and said triangletA common edge of (a);
step 4-4: determining the setFrontWhether the set is an empty set or not, if not, the step is shifted to a step 4-3, if the set is an empty set, the setting is firstly carried outq=q+1, and then go to step 4-2 until said setFrontIs empty;
and 4-5: judging whether all the copper-clad polygons are processed or not, and finishing the superposition of the copper-clad polygons if the processing is finished; and if not, returning to continuously process the unprocessed copper-clad polygons until all the copper-clad polygons are processed.
9. The method of claim 8, wherein: the obtaining the network number of the position point according to the triangle associated with the position point corresponding to the circuit node in the integrated circuit schematic diagram in the integrated circuit layout includes:
finding out any one associated triangle for the triangle associated with the corresponding position point of the circuit node in each integrated circuit schematic diagram in the integrated circuit layout, and taking the number of the triangle as the number of the position point, wherein the number of the position point is the network number of the position point.
10. The method of claim 9, wherein: comparing and judging the network number of the circuit node in the integrated circuit layout with the network number of the circuit node in the integrated circuit schematic diagram, and determining whether the integrated circuit layout has a design defect according to a judgment result, comprising the following steps:
according to the position relation between the circuit node in the integrated circuit schematic diagram and the integrated circuit schematic diagram defined by a user, establishing a mapping relation between the network number of the position point and the network number of the circuit node in the integrated circuit schematic diagram, if the mapping relation is one-to-one mapping, determining that no design defect exists in the integrated circuit schematic diagram, and if the mapping relation is not one-to-one mapping, determining that the design defect exists in the integrated circuit schematic diagram, wherein the position of the circuit node which does not correspond to the mapping relation is the position of the design defect.
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116522855A (en) * | 2023-07-05 | 2023-08-01 | 北京智芯仿真科技有限公司 | Power supply method and system for optimizing integrated circuit multi-power supply and multi-load |
| CN117034857A (en) * | 2023-10-10 | 2023-11-10 | 北京智芯仿真科技有限公司 | Method and device for identifying integrated circuit layout network by polygon large-area overlapping |
| CN117034858A (en) * | 2023-10-10 | 2023-11-10 | 北京智芯仿真科技有限公司 | Method and device for rapidly meshing large-area overlapped integrated circuit layout |
| CN117151020A (en) * | 2023-10-31 | 2023-12-01 | 北京智芯仿真科技有限公司 | Method and device for rapidly judging intersecting state of copper-clad shapes based on quadtree |
| CN117272914A (en) * | 2023-10-31 | 2023-12-22 | 北京智芯仿真科技有限公司 | Method and device for quickly determining copper-clad shape to form topological structure based on quadtree |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5450331A (en) * | 1992-01-24 | 1995-09-12 | Vlsi Technology, Inc. | Method for verifying circuit layout design |
| CN101002204A (en) * | 2004-08-04 | 2007-07-18 | 英赛特半导体有限公司 | Method and apparatus for locating short circuit faults in anintegrated circuit layout |
| CN111767688A (en) * | 2020-09-03 | 2020-10-13 | 北京智芯仿真科技有限公司 | Integrated circuit layout polygon unstructured grid self-adaptive subdivision method and system |
| CN114117998A (en) * | 2022-01-28 | 2022-03-01 | 北京智芯仿真科技有限公司 | Self-adaptive determination method and device for integrated circuit layout bonding pad and isolation gasket |
-
2022
- 2022-11-30 CN CN202211513940.1A patent/CN115600549B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5450331A (en) * | 1992-01-24 | 1995-09-12 | Vlsi Technology, Inc. | Method for verifying circuit layout design |
| CN101002204A (en) * | 2004-08-04 | 2007-07-18 | 英赛特半导体有限公司 | Method and apparatus for locating short circuit faults in anintegrated circuit layout |
| CN111767688A (en) * | 2020-09-03 | 2020-10-13 | 北京智芯仿真科技有限公司 | Integrated circuit layout polygon unstructured grid self-adaptive subdivision method and system |
| CN114117998A (en) * | 2022-01-28 | 2022-03-01 | 北京智芯仿真科技有限公司 | Self-adaptive determination method and device for integrated circuit layout bonding pad and isolation gasket |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116522855A (en) * | 2023-07-05 | 2023-08-01 | 北京智芯仿真科技有限公司 | Power supply method and system for optimizing integrated circuit multi-power supply and multi-load |
| CN116522855B (en) * | 2023-07-05 | 2023-09-05 | 北京智芯仿真科技有限公司 | Power supply method and system for optimizing integrated circuit multi-power supply and multi-load |
| CN117034857A (en) * | 2023-10-10 | 2023-11-10 | 北京智芯仿真科技有限公司 | Method and device for identifying integrated circuit layout network by polygon large-area overlapping |
| CN117034858A (en) * | 2023-10-10 | 2023-11-10 | 北京智芯仿真科技有限公司 | Method and device for rapidly meshing large-area overlapped integrated circuit layout |
| CN117034858B (en) * | 2023-10-10 | 2023-12-29 | 北京智芯仿真科技有限公司 | Method and device for rapidly meshing large-area overlapped integrated circuit layout |
| CN117034857B (en) * | 2023-10-10 | 2024-01-12 | 北京智芯仿真科技有限公司 | Method and device for identifying integrated circuit layout network by polygon large-area overlapping |
| CN117151020A (en) * | 2023-10-31 | 2023-12-01 | 北京智芯仿真科技有限公司 | Method and device for rapidly judging intersecting state of copper-clad shapes based on quadtree |
| CN117272914A (en) * | 2023-10-31 | 2023-12-22 | 北京智芯仿真科技有限公司 | Method and device for quickly determining copper-clad shape to form topological structure based on quadtree |
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