CN115599194A - Design system and method for enabling Embedded Flash to quickly enter low power consumption - Google Patents

Design system and method for enabling Embedded Flash to quickly enter low power consumption Download PDF

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Publication number
CN115599194A
CN115599194A CN202211597144.0A CN202211597144A CN115599194A CN 115599194 A CN115599194 A CN 115599194A CN 202211597144 A CN202211597144 A CN 202211597144A CN 115599194 A CN115599194 A CN 115599194A
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China
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embedded flash
signal
low
mcu
power consumption
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CN202211597144.0A
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CN115599194B (en
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王立华
潘明方
熊海峰
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Shanghai Taisi Microelectronics Co ltd
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Shanghai Taisi Microelectronics Co ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/325—Power saving in peripheral device
    • G06F1/3268—Power saving in hard disk drive
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3293—Power saving characterised by the action undertaken by switching to a less power-consuming processor, e.g. sub-CPU
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The invention discloses a design system and a method for quickly entering Embedded Flash into low power consumption, wherein the system comprises: a low-power-consumption sleep flag signal sleeping, an Embedded Flash controller, an OR gate, an AND gate, a register and an Embedded Flash device which are provided by the MCU; the sleeping is coupled to the input end of the OR gate, the output end of the OR gate is coupled to one input end of the AND gate, and the other input end of the AND gate loads a reset signal hrstn; the output end of the AND gate is coupled to the register, and the low-power-consumption mode can be quickly entered without setting a power management unit under the premise of not influencing the performance of the read instruction.

Description

Design system and method for enabling Embedded Flash to quickly enter low power consumption
Technical Field
The invention relates to the technical field of memory chips, in particular to a design system and a design method for enabling Embedded Flash to quickly enter low power consumption.
Background
The Embedded Flash is used as a storage unit of codes and data and widely applied to various low-power consumption MCUs. When the Embedded Flash works normally, namely when the signal CE selected by the Embedded Flash is effective, the power consumption is in mA level, and when the MCU enters a low power consumption mode, namely when the selected signal CE is ineffective, the power consumption is in uA level, so that when the MCU enters the low power consumption mode, whether the Embedded Flash can quickly enter the low power consumption mode is particularly important for the power consumption of the whole system.
In the prior art, when the MCU needs to enter a low power consumption mode, a request is sent to a power management unit of a system, and then the power management unit controls the Embedded Flash to enter the low power consumption mode.
Under normal working conditions, if the CE is set to be invalid after reading and writing each time and new reading operation comes in, a period of initialization time after the CE is set to be valid is needed, the time of Embedded flashes of different manufacturers is slightly different, the maximum time is more than 15us, and if the delay exists in each reading instruction, even if the delay of some manufacturers is ns, the reading performance is influenced for an MCU system with a system clock more than dozens of MHz.
The prior art can not meet the requirements of people at the present stage, and the improvement of the prior art is urgently needed based on the current situation.
Disclosure of Invention
The invention aims to provide a design system and a design method for enabling Embedded Flash to quickly enter low power consumption, so as to solve the problems in the background technology.
On one hand, the invention provides a design system for enabling Embedded Flash to rapidly enter low power consumption in the following technical scheme, which comprises a low power consumption sleep mark signal sleeping provided by an MCU, an Embedded Flash controller, an OR gate, an AND gate, a register and an Embedded Flash device;
preferably, the Embedded Flash controller is provided with an Embedded Flash interface time sequence control unit;
preferably, the sleeping is coupled to an input end of the or gate, an output end of the or gate is coupled to one input end of the and gate, and the other input end of the and gate loads a reset signal hrstn common to the MCU and the Embedded Flash controller.
Preferably, the output end of the and gate is coupled to the register, one input end of the register loads the ce control signal n _ ce provided by the Embedded Flash interface timing control unit, and the other input end of the register loads the clock source signal hclk shared by the MCU and the Embedded Flash controller.
Preferably, the output end of the register loads the Embedded Flash device by outputting the selected signal eflash _ ce.
On the other hand, the invention provides another technical scheme as follows, and the design method for the Embedded Flash to quickly enter low power consumption comprises the following specific steps:
step S1; negating a low-power-consumption sleep flag signal sleeping in the MCU system, performing AND logic operation on the low-power-consumption sleep flag signal sleeping and a reset signal hrstn of an Embedded Flash controller, and using an output signal hrstn _ mux of the AND logic operation as a reset signal of a register;
step S2; after the MCU system enters a low power consumption mode, setting a sleeping signal from an invalid state to an effective state, and resetting a signal eflash _ ce selected by an Embedded Flash device to be invalid;
and step S3: when the MCU system exits the low power consumption mode, the sleeping signal is set to be in an invalid state from an effective state, and the eflash _ ce signal is immediately released to be effective;
and step S4: and when the eflash _ ce signal is effective, the MCU system recovers the normal operation of the Embedded Flash.
Preferably, when the MCU system enters a low power consumption mode and the eflash _ ce is set to be invalid, the Embedded Flash enters a uA-level low power consumption mode.
Preferably, after the MCU system exits the low power consumption mode, the reset of the control logic of the eflash _ ce is released immediately, and the eflash _ ce is set to be valid, at this time, the CPU in the MCU stops sending the read/write command request to the Embedded Flash controller.
Preferably, after the MCU system exits the low power consumption mode and the eflash _ ce completes the first delay greater than 10us, the MCU system enters normal operation.
The invention has the following beneficial effects:
(1) The invention uses simple logic to realize that the Embedded Flash enters the low power consumption mode quickly without affecting the performance of the read instruction;
(2) The design complexity of the invention is far lower than that of the traditional method, and the error probability of the design is greatly reduced.
Drawings
FIG. 1 is a schematic diagram of the overall circuit structure of the system of the present invention;
FIG. 2 is a schematic flow diagram of the process of the present invention;
FIG. 3 is a timing diagram of signals before and after the present invention enters low power consumption.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the invention without making any creative effort, shall fall within the protection scope of the invention.
Referring to fig. 1, in one aspect, the present invention provides a design system for enabling Embedded Flash to quickly enter low power consumption in the following technical solution, including a low power consumption sleep flag signal sleeping provided by an MCU, an Embedded Flash controller (including an Embedded Flash interface timing control unit), an or gate, an and gate, a register, and an Embedded Flash device.
The low-power-consumption sleep flag signal sleeping is generated by a CPU in an MCU (microprogrammed control unit), the sleeping is coupled to the input end of an OR gate, the output end of the OR gate is coupled to one input end of the AND gate, the other input end of the AND gate is loaded with a reset signal hrstn (comprising MCU _ hrstn and Embedded Flash _ hrstn) shared by the MCU and an Embedded Flash controller, the output end of the AND gate outputs a signal hrstn _ mux to the reset end of a register, the data input end of the register is loaded with a ce control signal n _ ce provided by an Embedded Flash interface timing control unit, the clock input end of the register is loaded with a clock source signal hclk (comprising MCU _ hclk and Embedded Flash _ hclk) shared by the MCU and the Embedded Flash controller, and the output end of the register is loaded to the Embedded Flash device by outputting a selected signal eflash _ fclk;
in the embodiment, after the MCU system is normally powered on, the Embedded Flash controller sets the signal eflash _ ce selected by the Embedded Flash device output by the register to be valid through the Embedded Flash interface timing control unit, a delay larger than 10us occurs after the eflash _ ce is set to be valid by the first read operation, and each subsequent read operation does not require the delay.
In the embodiment, when the MCU system enters a low power consumption mode, a low power consumption sleep flag signal sleeping on a CPU interface is set to be effective, and at the moment, the CPU in the MCU does not send a read-write instruction request to an Embedded Flash controller; because the clock of the Embedded Flash controller and the MCU are the same clock source, the eflash _ ce is set to be invalid by resetting the control logic of the eflash _ ce within the sleep effective time of the signal, and therefore the Embedded Flash can immediately enter the uA-level low-power-consumption mode.
In an embodiment, after the MCU system is awakened from the low power consumption sleep state, the low power consumption sleep flag signal sleeping is set to be invalid immediately, the reset of the eflash _ ce control logic is released immediately, and meanwhile, eflash _ ce is set to be valid, so that the MCU system can start to work normally after the first delay greater than 10us is completed.
Referring to fig. 2, in another aspect, the present invention provides another technical solution, which is a design method for enabling Embedded Flash to quickly enter low power consumption, and the specific steps include:
step S1: negating a low-power-consumption sleep flag signal sleeping in the MCU system, performing AND logic operation on the low-power-consumption sleep flag signal sleeping and a reset signal hrstn of an Embedded Flash controller, and using a signal hrstn _ mux output by the AND logic operation as a reset signal of a register;
step S2: when the MCU system enters a low power consumption mode, setting a sleeping signal from an invalid state to an effective state, and immediately resetting a signal eflash _ ce selected by an Embedded Flash device to be invalid;
and step S3: when the MCU system is awakened to exit the low power consumption mode, the sleeping signal is set to be in an invalid state from an effective state, and the eflash _ ce signal is immediately released to be effective;
and step S4: and when the eflash _ ce signal is valid, the MCU system restarts to restore normal operation to the Embedded Flash.
Referring to fig. 3, the present invention further provides another optional embodiment, in the embodiment, before the MCU system is released from reset, that is, when the signal hrstn is level 0, the signal eflash _ ce is reset by the MCU system, and the output is invalid level value 0, after the signal hrstn is released from reset and the MCU system is running, the signal eflash _ ce is level value of the signal n _ ce, and after the MCU enters the low power mode, the signal sleeping is changed to level 1 to be valid, and at this time, the signal eflash _ ce is reset to level 0 to be invalid.
The method takes the low-power-consumption sleep mark of the CPU as a reset source, and can set all the Embedded Flash interface signals to be invalid when the MCU system enters a low-power-consumption mode by utilizing the reset source.
Although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that various changes in the embodiments and/or modifications of the invention can be made, and equivalents and modifications of some of the features described in the embodiments and/or modifications can be made without departing from the spirit and scope of the invention.

Claims (10)

1. A design system for quickly entering low power consumption by Embedded Flash is characterized in that: a power management unit is not arranged, and the low-power mode is quickly entered on the premise of not influencing the performance of the read instruction;
the system comprises: a low-power-consumption sleep flag signal sleeping, an Embedded Flash controller, an OR gate, an AND gate, a register and an Embedded Flash device which are provided by the MCU;
the Embedded Flash controller is provided with an Embedded Flash interface time sequence control unit;
the sleeping is coupled to the input end of the OR gate, the output end of the OR gate is coupled to one input end of the AND gate, and the other input end of the AND gate loads a reset signal hrstn;
an output end of the AND gate outputs a signal hrstn _ mux to be loaded to a reset end of the register, a data input end of the register loads a ce control signal n _ ce provided by the Embedded Flash interface time sequence control unit, a clock input end of the register loads a clock source signal hclk, and an output end of the register loads a signal eflash _ ce selected by the Embedded Flash device to the Embedded Flash device through outputting.
2. The Embedded Flash fast-access low-power design system of claim 1, characterized in that: the Embedded Flash controller sets the signal eflash _ ce selected by the Embedded Flash device output by the register to be effective or ineffective through the Embedded Flash interface time sequence control unit.
3. The Embedded Flash fast-entry low-power design system of claim 1, characterized in that: the reset signal hrstn is a common reset signal of the MCU and the Embedded Flash controller.
4. The Embedded Flash fast-entry low-power design system of claim 1, characterized in that: the clock source signal hclk is a common clock source signal of the MCU and the Embedded Flash controller.
5. A design method for fast entering low power consumption of Embedded Flash is characterized by comprising the following steps:
step S1: negating a low-power-consumption sleep flag signal sleeping in the MCU system, performing AND logic operation on the low-power-consumption sleep flag signal sleeping and a reset signal hrstn of an Embedded Flash controller, and using an output signal hrstn _ mux of the AND logic operation as a reset signal of a register;
step S2: after the MCU system enters a low power consumption mode, setting the sleeping signal from an invalid state to an effective state, and resetting a signal eflash _ ce selected by an Embedded Flash device to be invalid;
and step S3: when the MCU system exits from the low power consumption mode, setting the sleeping signal from an active state to an inactive state, and releasing the eflash _ ce as active;
and step S4: and when the eflash _ ce is valid, the MCU system recovers the normal operation of the Embedded Flash.
6. The Embedded Flash fast-access low-power-consumption design method according to claim 5, characterized in that: before the MCU system does not enter the low power consumption mode and after the MCU system exits the low power consumption mode, the eflash _ ce keeps an effective state.
7. The Embedded Flash fast-access low-power-consumption design method according to claim 5, characterized in that: before the MCU system does not enter a low power consumption mode, when the MCU executes the first read operation, setting the eflash _ ce to be effective and then having a delay larger than 10 us.
8. The Embedded Flash fast-access low-power-consumption design method of claim 5, characterized in that: when the MCU system enters a low power consumption mode and after the eflash _ ce is set to be invalid, the Embedded Flash enters a uA-level low power consumption mode.
9. The Embedded Flash fast-access low-power-consumption design method according to claim 5, characterized in that: when the MCU system exits from the low power consumption mode, the reset of the control logic of the eflash _ ce is immediately released, meanwhile, the eflash _ ce is set to be effective, and at the moment, the CPU in the MCU stops sending a read-write instruction request to the Embedded Flash controller.
10. The Embedded Flash fast-access low-power-consumption design method according to claim 5, characterized in that: and after the MCU system exits the low power consumption mode and the first delay of more than 10us is finished by the eflash _ ce, the MCU system enters normal work.
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090089562A1 (en) * 2007-09-27 2009-04-02 Ethan Schuchman Methods and apparatuses for reducing power consumption of processor switch operations
WO2013180401A2 (en) * 2012-05-28 2013-12-05 Song Seung-Hwan Non-volatile memory comprising pure-logic transistor
CN103631360A (en) * 2013-11-15 2014-03-12 北京兆易创新科技股份有限公司 Chip allowing sleep mode and method
CN106802870A (en) * 2016-12-29 2017-06-06 杭州朔天科技有限公司 A kind of efficient embedded system chip Nor Flash controllers and control method

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090089562A1 (en) * 2007-09-27 2009-04-02 Ethan Schuchman Methods and apparatuses for reducing power consumption of processor switch operations
WO2013180401A2 (en) * 2012-05-28 2013-12-05 Song Seung-Hwan Non-volatile memory comprising pure-logic transistor
CN103631360A (en) * 2013-11-15 2014-03-12 北京兆易创新科技股份有限公司 Chip allowing sleep mode and method
CN106802870A (en) * 2016-12-29 2017-06-06 杭州朔天科技有限公司 A kind of efficient embedded system chip Nor Flash controllers and control method

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