CN111459560A

CN111459560A - RISC-V architecture based multi-core processor wake-up system

Info

Publication number: CN111459560A
Application number: CN202010237790.0A
Authority: CN
Inventors: 胡振波; 周在新
Original assignee: Shin Lai Zhirong Semiconductor Technology Shanghai Co ltd
Current assignee: Shin Lai Zhirong Semiconductor Technology Shanghai Co ltd
Priority date: 2020-03-30
Filing date: 2020-03-30
Publication date: 2020-07-28

Abstract

The invention discloses a multi-core processor awakening system based on a RISC-V architecture, which comprises: and the txevt register can send an event pulse signal to the outside of the processor core to wake up other processor cores which are sleeping by reading and writing the txevt register. The method is simple and easy to operate, and can be used for mutual awakening among cores of the multi-core processor to achieve the purpose of saving power consumption.

Description

RISC-V architecture based multi-core processor wake-up system

Technical Field

The invention relates to the technical field of low-power-consumption kernel interrupt processing and low-power-consumption, in particular to a multi-core processor awakening system based on a RISC-V (reduced instruction-computer-graphics) architecture.

Background

The multi-core processor integrates two or more complete processor cores into one processor, and the processor can support a plurality of processors on a system bus, and all bus controllers and command signals are provided by the bus controllers. At present, multi-core technology has become the most interesting topic and research direction. The multi-core architecture opens up a new direction for the fields of performance improvement, energy-saving calculation and the like. The multi-core process will bring about a great revolution affecting aspects of the whole computer industry, including various fields of computer systems such as architecture research, embedded system design and solution design, compiling technology, operating system core algorithm, application software design and the like.

However, the multi-core processor may also encounter various problems, for example, when two cores access a shared resource at the same time, contention may be generated, and the solution is to stop one core to enter a sleep mode, and perform access by the other core first, and wake up the second core to perform access by the second core after the access by the first core is completed.

Disclosure of Invention

In order to solve the technical problem, the invention relates to a multi-core processor wake-up system based on a RISC-V architecture, which is additionally provided with a processor low-power consumption register named as a txevt register, and the processor based on the RISC-V instruction architecture can send an event signal pulse to the outside of the processor by writing the register through a CSR. While other core processors can go to sleep by writing wfe _ en register execution wfe, which can achieve the event-only wake-up.

In order to achieve the purpose, the technical scheme of the invention is as follows:

the multi-core processor awakening system based on the RISC-V architecture comprises: and the txevt register can send an event pulse signal to the outside of the processor core to wake up other processor cores which are sleeping by reading and writing the txevt register.

Preferably, the txevt register is a custom CSR register, and the read-write permission is readable and writable in a user mode.

Preferably, the txevt register comprises two fields, wherein a reserved bit is arranged between an X L EN-1 bit and a 1 st bit, and a 0 th bit is an EVT field.

Preferably, when writing a 1 to the EVT domain, the EVT domain is automatically cleared in the next cycle after a single cycle of the pulse signal is generated; when writing a 0 to the EVT domain, there will not be any change.

Based on the technical scheme, the invention has the beneficial effects that:

(1) the invention adds a mechanism for sending the event pulse signal to the outside of the processor core, can send a single-cycle pulse signal only by writing the txevt register, and is simple and easy to operate;

(2) the method and the device can be used for mutual awakening among cores of the multi-core processor.

Drawings

FIG. 1 is a diagram of the txevt register storage information format of the present invention;

FIG. 2 is a flowchart illustrating a process of accessing a shared resource by multiple cores according to an embodiment of the present invention;

fig. 3 is a schematic circuit diagram of an implementation of the txevt register sending the event pulse signal according to an embodiment of the present invention.

Detailed Description

The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

Example one

The invention relates to a multi-core processor wake-up system based on a RISC-V architecture, which is additionally provided with a low-power-consumption register design of a processor, wherein the register is named as a txevt register, and an event pulse signal is generated by writing 1 into the register. The pulse signal lasts for one cycle, and after 1 is written out, the register is automatically cleared to wait for the next 1-writing operation in the next cycle to generate a new event pulse.

The txevt register is a self-defined CSR register, and the read-write permission is readable and writable in a user mode.

The information format of the txevt register is shown in fig. 1, the register has two domains, a reserved bit is arranged between the X L EN-1 bit and the 1 st bit, and the 0 th bit is an EVT domain.

When writing 1 to this bit field, the EVT field will generate a single-cycle pulse signal as an event signal, and then the bit field will be automatically cleared in the next cycle. When writing a 0 to this bit field, there will not be any change.

The single-period event pulse signal means that the signal has a low level to a high level, the high level is maintained for one period, and the signal is automatically pulled down to the low level after one period.

As shown in fig. 2, when multiple cores access a shared resource, a user needs to stop one of the processor cores 1 and enter a sleep state, at this time, the wfi instruction behavior is switched to the wfe instruction behavior, the sleep state waits for the wake-up of the external event signal, after the access of the other processor core 2 is completed, the CSR instruction is written into the register 1 to txevt, at this time, an event pulse signal is generated to wake-up the processor core 1, and the processor core 1 continues to access the shared resource.

Further, the txevt register is implemented in a circuit as shown in fig. 3, where the signals include wbck _ csr _ dat signal, tx _ evt _ wr _ ena signal, tx _ evt _ nxt signal, clk signal, tx _ evt _ r [0] signal, and tx _ evt signal, where:

the wbck _ CSR _ dat signal represents the data written back to the CSR register, when the user accesses the txevt register, the value of wbck _ CSR _ dat is the value written into the txevt register;

the tx _ evt _ wr _ ena signal indicates that an operation to write the txevt register currently occurs;

the tx _ evt _ nxt signal is an input of the D flip-flop and represents the value of the D flip-flop which is currently ready to store the signal;

the clk signal, representing a clock signal;

the tx _ evt _ r signal represents an output signal of the D flip-flop;

the tx _ evt _ r [0] signal, representing bit 0 of the D flip-flop output signal;

the tx _ evt signal represents an event pulse signal.

As shown in fig. 3, when initiating the operation of writing the txevt register, the signal tx _ evt _ wr _ ena is pulled high, at which time the selector will select wbck _ csr _ dat as the input of the D flip-flop, now assuming that a 1-write operation is currently initiated, then wbck _ csr _ dat is now 1, and since the SET enable of the D flip-flop is connected to the tx _ evt _ wr _ ena signal, the D flip-flop will write 1, and after one clock cycle the Q-terminal of the D flip-flop gets data 1, so the value of the tx _ evt _ R signal is 1, then the value of the tx _ evt _ R [0] bit is also 1, since the C L R enable of the D flip-flop is directly connected to tx _ evt _ R [0], then the D flip-flop will be cleared at the next clock rising edge, so that at the next clock cycle tx _ evt _ R [0] is SET to zero, and the signal tx _ evt _ R [0] is shifted to the outer core to obtain an event.

The above description is only a preferred embodiment of the wake-up system of the multi-core processor based on RISC-V architecture disclosed in the present invention, and not intended to limit the scope of the present invention, and all equivalent structures or equivalent flow transformations made by the present specification, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.

Claims

1. RISC-V architecture based multi-core processor wake-up system, comprising: and the txevt register can send an event pulse signal to the outside of the processor core to wake up other processor cores which are sleeping by reading and writing the txevt register.

2. The RISC-V architecture based multi-core processor wake-up system of claim 1, wherein the txevt register is a custom CSR register with read and write permissions readable and writable in user mode.

3. A RISC-V architecture based multi-core processor wake-up system as claimed in claim 1 or 2, characterized in that the txevt register comprises two fields, where between the X L EN-1 bit and the 1 st bit is a reserved bit and the 0 th bit is an EVT field.

4. A RISC-V architecture based multi-core processor wake-up system as claimed in claim 3, wherein when writing a 1 to the EVT domain, a one cycle pulse signal is generated and then the EVT domain is automatically cleared in the next cycle; when writing a 0 to the EVT domain, there will not be any change.