CN115598960A - Clock adjusting device, laser radar and terminal equipment - Google Patents

Clock adjusting device, laser radar and terminal equipment Download PDF

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Publication number
CN115598960A
CN115598960A CN202110766477.0A CN202110766477A CN115598960A CN 115598960 A CN115598960 A CN 115598960A CN 202110766477 A CN202110766477 A CN 202110766477A CN 115598960 A CN115598960 A CN 115598960A
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phase
clock
signal
sampling
unit
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吴小可
曹国亮
魏渠渠
石现领
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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    • G—PHYSICS
    • G04—HOROLOGY
    • G04R—RADIO-CONTROLLED TIME-PIECES
    • G04R20/00—Setting the time according to the time information carried or implied by the radio signal
    • G04R20/02—Setting the time according to the time information carried or implied by the radio signal the radio signal being sent by a satellite, e.g. GPS
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S17/00—Systems using the reflection or reradiation of electromagnetic waves other than radio waves, e.g. lidar systems
    • G01S17/02—Systems using the reflection of electromagnetic waves other than radio waves
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
    • G01S7/48—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S17/00
    • G01S7/481—Constructional features, e.g. arrangements of optical elements

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Remote Sensing (AREA)
  • General Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Optical Radar Systems And Details Thereof (AREA)

Abstract

A clock adjusting device, a laser radar and a terminal device are used for improving the accuracy of sampling a signal to be detected in the technical field of electronics. The clock adjusting device comprises a clock generating unit, a phase adjusting unit and a phase control unit, wherein the clock generating unit generates a first clock signal, the phase adjusting unit obtains N second clock signals according to the first clock signal, the N second clock signals correspond to N phases, N is a positive integer greater than or equal to 2, and the phase control unit sends a first phase adjusting instruction to the phase adjusting unit according to a preset rule and a sampling result of the N second clock signals on a signal to be measured so as to instruct the phase adjusting unit to obtain a third clock signal with the phase as a target phase according to the first clock signal. By pre-sampling the signal to be detected by using the N phases, the method is beneficial to formally sampling the signal to be detected by using a target phase with a better sampling result in the N phases, and the sampling accuracy of the signal to be detected is effectively improved.

Description

Clock adjusting device, laser radar and terminal equipment
Technical Field
The application relates to the technical field of electronics, in particular to the field of digital circuits, and provides a clock adjusting device, a laser radar and a terminal device.
Background
With the development of electronic technology, the application of asynchronous circuits in digital circuit systems is more and more extensive. Asynchronous circuits refer to circuits in which there are at least two clock domains, with electronic devices located in the same clock domain using the same clock signal and electronic devices located in different clock domains using different clock signals. In an asynchronous circuit, a signal generated by one clock domain belongs to an asynchronous signal for another clock domain, and a driving clock of the asynchronous signal is not aligned with a driving clock of the other clock domain. Therefore, how to make the clock domain receiving the asynchronous signal accurately sample the asynchronous signal sent by other clock domains is crucial to accurately complete the control operation related to the asynchronous signal.
However, in the prior art, the clock domain in the asynchronous circuit usually uses a clock signal with a fixed period for sampling, i.e. the asynchronous signal is sampled once every other fixed time interval. However, when an asynchronous signal sent from a certain clock domain occurs within a time interval between two adjacent sampling, the clock domain receiving the asynchronous signal cannot accurately sample the asynchronous signal, and thus the level of the input asynchronous signal cannot be accurately transmitted to the output, which is not favorable for the stability of the asynchronous circuit.
Disclosure of Invention
The application provides a clock adjusting device, a laser radar and a terminal device, which are used for improving the accuracy of sampling signals to be detected (such as asynchronous signals).
In a first aspect, the present application provides a clock adjustment apparatus, comprising: a clock generating unit for generating a first clock signal; the phase adjusting unit is used for adjusting the phase of the first clock signal from the clock generating unit to obtain N second clock signals, the N second clock signals correspond to N phases, and N is a positive integer greater than or equal to 2; the phase control unit is used for obtaining N second clock signals from the phase adjusting unit, sampling results of the signals to be detected according to a preset rule and the N second clock signals, and sending a first phase adjusting instruction to the phase adjusting unit, wherein the first phase adjusting instruction is used for indicating a target phase; and the phase adjusting unit is also used for adjusting the phase of the first clock signal from the clock generating unit according to the first phase adjusting instruction to obtain a third clock signal, and the phase of the third clock signal is a target phase. In the above design, the clock signal corresponding to each phase is used to pre-sample the signal to be tested before formally sampling the signal to be tested, which is helpful for obtaining a target phase with a better sampling result in each phase, and the target phase with a better sampling result is used, so that the sampling accuracy and the sampling stability of formally sampling the signal to be tested can be improved.
In one possible design, the signal to be tested may be an asynchronous signal, for example, an asynchronous signal sent by another clock domain to the clock domain where the clock adjustment device is located. Therefore, the design can enable the clock domain for receiving the asynchronous signals to have the capacity of flexibly adjusting the clock phase, and the adjusted clock phase can be always matched with the received asynchronous signals, so that the sampling accuracy of the trans-clock domain transmission asynchronous signals is effectively improved, and the stability of an asynchronous circuit is improved.
In one possible design, the signal to be tested may be preset or configured, and may be actively sent to the phase control unit after the power is turned on, so that the phase control unit can actively perform phase calibration on the clock signal sampling the signal to be tested after the power is turned on.
In a possible design, after the phase adjustment unit obtains the third clock signal, the phase control unit may further re-determine the target phase, for example, after the phase adjustment unit starts up to calibrate the clock signal of the sampling signal to be detected, the phase control unit performs secondary calibration of the target phase according to the actually received signal to be detected, so that the clock signal clock of the sampling signal to be detected can be always kept matched with the signal to be detected, and the accuracy and stability of sampling are effectively improved.
In one possible design, the phase control unit may include a flip-flop and a sampling control unit, a first input of the flip-flop is configured to receive a signal to be measured, a second input of the flip-flop is connected to an output of the phase adjustment unit, an output of the flip-flop is connected to an input of the sampling control unit, and an output of the sampling control unit is connected to an input of the phase adjustment unit. The trigger can sample the signal to be detected by using each second clock signal output by the phase adjusting unit to obtain an output signal corresponding to each second clock signal, and the sampling control unit can send a first phase adjusting instruction to the phase adjusting unit according to a preset rule and the output signals corresponding to the N second clock signals. In this design, the flip-flop can only sample when clock border, does not sample when non-clock border, consequently, samples the signal to be measured through using the flip-flop, not only helps reducing the emergence probability of circuit burr, can also reduce the sampling consumption.
In a possible design, in the case that the flip-flop includes a D flip-flop, the output of the flip-flop may include the output Q and/or the output of the D flip-flop
Figure BDA0003151854370000021
For example comprising the output Q but not comprising the output
Figure BDA0003151854370000022
Or comprising an output
Figure BDA0003151854370000023
But does not include the output terminal Q, or includes both the output terminal Q and the output terminal Q
Figure BDA0003151854370000024
Therefore, the clock control unit can sample the signal to be tested by using the D trigger at the clock rising edge of the second clock signal to obtain a stable output signal.
In one possible design, the predetermined rule may be related to a sampling result that is correctly sampled, in which case, the sampling control unit may include a sampling unit and an evaluation control unit, an input end of the sampling unit is connected to an output end of the trigger, an output end of the sampling unit is connected to an input end of the evaluation control unit, and an output end of the evaluation control unit is connected to an input end of the phase adjusting unit. The sampling unit can acquire M output signals obtained by sampling the signal to be detected by the trigger for M times under each second clock signal, and the evaluation control unit can send a first phase adjustment instruction to the phase adjustment unit according to the reference signal and the M output signals corresponding to each second clock signal from the sampling unit based on a preset rule. Where M is a positive integer greater than or equal to 2 and the reference signal is used to indicate that the output signal is correctly sampled. Therefore, the sampling operation is executed by using the sampling unit, the evaluation control unit is used for executing the evaluation operation and the phase adjustment operation, the sampling operation and the evaluation and phase adjustment operation after sampling can be decoupled, and the influence of the execution of the evaluation operation and the phase adjustment operation on the sampling operation is reduced while the working pressure of each unit is reduced.
In one possible design, the evaluation control unit may further send an enable signal to the sampling unit, where the enable signal is used to instruct the sampling unit to collect the output signal of the trigger within the valid period of the indication message. The effective time period of the indication message can be used for indicating a period of time for the sampling unit to receive the enabling signal, so that the evaluation control unit can send the enabling signal to the sampling unit once before the signal to be tested comes each time, and the sampling unit can enable the sampling capability of the sampling unit after receiving one enabling signal every time, namely, the sampling operation of the output signal of the trigger is started within a period of time. The specific sampling duration may be preset or configured in the sampling unit, or when the enable signal has the capability of carrying information, the evaluation control unit may also be carried in the enable signal to notify the sampling unit, which is not limited specifically. Through the design, the operation of sampling the output signal by the sampling unit can be uniformly monitored and controlled by the evaluation control unit, and the flexibility of the evaluation control unit on the management of the whole clock regulation process is improved.
In one possible design, the N second clock signals may be obtained by N-1 phase adjustments, where in any one phase adjustment: the evaluation control unit may send a second phase adjustment instruction to the phase adjustment unit after determining that the sampling unit obtains M output signals corresponding to the current second clock signal, and the phase adjustment unit may perform phase adjustment on the first clock signal from the clock generation unit according to the second phase adjustment instruction to obtain a next second clock signal, where a phase of the next second clock signal is an unadjusted one of the N phases. Through the design, the operation of obtaining the N second clock signals by the phase adjusting unit can be uniformly monitored and controlled by the evaluation control unit, and the flexibility of the evaluation control unit on the management of the whole clock adjusting process is further improved.
In one possible design, any two adjacent phases in the N phases may have the same phase interval according to the sequence of the phases from large to small or from small to large, where the phase interval may be a fixed value preset or configured, or may be a variable value that supports user modification according to an actual scene. In this way, by setting the N second clock signals with the same phase interval, a sampling result with a relatively uniform phase distribution is obtained, thereby simplifying the complexity of determining the target phase.
In a possible design, the preset rule is used to indicate that the target phase is obtained according to a phase interval formed by consecutive adjacent phases with sampling index values not less than an index threshold, wherein the sampling index value of any phase is positively correlated with the number of output signals, which are the same as the reference signal, in the M output signals corresponding to the phase, and the adjacent phase is an adjacent phase in the N phases in the order from large to small or from small to large. In this way, since the phase interval is constructed by using the phase satisfying the requirement of the sampling index, the phase interval can be regarded as an interval in which the sampling index is relatively stable, and the target phase is selected in the interval, so that even if the phase slightly shifts due to environmental changes, a certain sampling effect can be ensured as long as the phase interval is not exceeded.
In one possible design, the target phase may be one of the following: a center phase of each phase included in the phase interval; the phase position corresponding to the gravity center point of the phase position area is obtained according to each phase position contained in the phase position interval and at least two corresponding phase positions positioned at two sides of the phase position interval; the central phases of two corresponding phases at two sides of the phase interval. Two corresponding phases at two sides of the phase interval have the same or the closest sampling index value. By means of the design, when the sampling environment becomes worse (for example, the temperature rises), the phase interval gradually erodes inwards from the edge phase to the most central phase, the sampling success rate of the eroded phase is reduced, and the central phase or the gravity center phase of the phase interval belongs to the most stable phase point in the phase interval. In this way, by setting the center phase or the center-of-gravity phase of the phase section as the target phase, the third clock signal obtained based on the target phase can have the optimum environment-coping capability, and the third clock signal does not need to be adjusted even if the environment slightly changes, thereby contributing to improvement of stability in sampling the signal to be measured using the third clock signal.
In one possible design, when there are multiple phase intervals, the target phase may be determined according to a phase interval, of the multiple phase intervals, in which the included phase range is the largest. Therefore, the phase interval with the largest phase range belongs to the phase area with the best stability, the target phase is selected based on the phase area with the best stability, even if the target phase slightly shifts in actual operation, the target phase only shifts to the phase adjacent to the left side or the right side, and the phase adjacent to the left side or the right side of the phase interval with the largest phase range can also have a better sampling success rate, namely, the phase after the shift can also ensure that the sampling accuracy is better.
In one possible embodiment, the phase range of the phase interval of the N phases is not less than the phase range of one clock cycle of the first clock signal. Therefore, the N phases cover two clock cycles of the first clock signal, so that the sampling result can simultaneously contain the sampling results in two repeated clock cycles, the accidental problem of determining the target phase by adopting one clock cycle can be avoided, the critical phase between the two clock cycles can be considered, and the target phase can be selected more accurately.
In one possible design, the phase adjustment unit may be a phase locked loop, or include N delay chains, and any two of the N delay chains include a different number of delay units.
In one possible design, the third clock signal may be used for one or more of the following operations: the programmable logic circuit for the laser radar samples a target echo signal sent by a receiving module of the laser radar; the method comprises the following steps that a programmable logic circuit for the laser radar samples a driving control command sent by a central processing unit of the laser radar; a scanning mechanism for the laser radar samples scanning control signals sent by a programmable logic circuit of the laser radar; the transmitting module for the laser radar samples a transmitting control signal sent by a programmable logic circuit of the laser radar; the central processing unit for the lidar samples detection results and the like sent by the programmable logic circuit of the lidar.
In one possible design, the signal under test may include one or more of the following: a receiving module of the laser radar sends a target echo signal; a driving control command sent by a central processing unit of the laser radar; scanning control signals sent by a programmable logic circuit of the laser radar; a transmitting control signal sent by a programmable logic circuit of the laser radar; the detection results sent by the programmable logic circuit of the laser radar, and the like.
In a second aspect, the present application provides a lidar comprising first and second circuits in different clock domains, the second circuit comprising a clock adjustment apparatus as designed in any of the first aspects above. The first circuit is used for sending a signal to be tested to the second circuit, and the second circuit is used for sampling the signal to be tested by using a third clock signal obtained after the adjustment of the clock adjusting device.
In one possible design, where the lidar includes a central processing unit, programmable logic, a transmit module, a receive module, and a scanning mechanism located in different clock domains, the first circuit, the second circuit, and the signal under test may be one or more of the following combinations: the combination is one, the first circuit is a programmable logic circuit, the second circuit is a transmitting module, and the signal to be detected comprises a transmitting control signal; the second combination, the first circuit is a receiving module, the second circuit is a programmable logic circuit, and the signal to be detected comprises a target echo signal of the laser radar; in a third combination, the first circuit is a central processing unit, the second circuit is a programmable logic circuit, and the signal to be tested comprises a driving control command; fourthly, the first circuit is a programmable logic circuit, the second circuit is a scanning mechanism, and the signal to be detected comprises a scanning control command; and fifthly, the first circuit is a programmable logic circuit, the second circuit is a central processing unit, the signal to be detected comprises a detection result, and the detection result is obtained according to the transmitted laser signal and the target echo signal.
In a third aspect, the present application provides a terminal device, including the lidar of the second aspect.
Illustratively, some examples of terminal devices include, but are not limited to: smart home devices (such as televisions, floor sweeping robots, smart table lamps, sound systems, smart lighting systems, appliance control systems, home background music, home theater systems, intercom systems, video surveillance systems, and the like), smart transportation devices (such as automobiles, ships, unmanned aerial vehicles, trains, trucks, and the like), smart manufacturing devices (such as robots, industrial devices, smart logistics, smart factories, and the like), smart terminals (mobile phones, computers, tablet computers, palmtops, desktops, earphones, sounds, wearable devices, vehicle-mounted devices, virtual reality devices, augmented reality devices, and the like).
For the beneficial effects of the second and third aspects, please refer to the technical effects that can be achieved by the corresponding design in the first aspect, and the detailed description is omitted here.
Drawings
Fig. 1 schematically illustrates an application scenario of a lidar provided in an embodiment of the present application;
fig. 2 schematically illustrates an architecture diagram of a lidar-based driving system provided in an embodiment of the present application;
fig. 3 is a circuit diagram illustrating a possible asynchronous signal sampling circuit provided by an embodiment of the present application;
fig. 4 is a schematic diagram illustrating a sampling result provided by an embodiment of the present application;
fig. 5 is a schematic structural diagram schematically illustrating a clock adjustment apparatus provided in an embodiment of the present application;
fig. 6 schematically illustrates a structure of a phase adjustment unit provided in an embodiment of the present application;
fig. 7 is a schematic structural diagram schematically illustrating another phase adjustment unit provided in an embodiment of the present application;
fig. 8 is a schematic diagram illustrating an association relationship between a phase and a sampling success rate provided by an embodiment of the present application.
Detailed Description
The clock adjusting device disclosed by the application can be applied to terminal equipment with signal processing capability, and is particularly suitable for terminal equipment with asynchronous signal processing capability. In some embodiments of the present application, the clock adjusting apparatus may be a terminal device or a separate unit, and when the clock adjusting apparatus is a separate unit, the unit may be embedded in one or more clock domains of the terminal device and may control the terminal device to adjust clock signals of one or more internal clock domains to improve the accuracy of sampling asynchronous signals transmitted by other clock domains by one or more clock domains. In other embodiments of the present application, the clock adjusting apparatus may also be a unit packaged inside the terminal device, and is used to implement a clock phase adjusting function for a clock domain in the terminal device. The terminal device may be an intelligent device with signal processing capability, including but not limited to: smart home devices such as televisions, floor sweeping robots, smart table lamps, sound systems, smart lighting systems, appliance control systems, home background music, home theater systems, intercom systems, video surveillance, and the like; intelligent transportation devices such as automobiles, boats, drones, trains, vans, trucks, and the like; intelligent manufacturing equipment such as robots, industrial equipment, intelligent logistics, intelligent factories, and the like. Alternatively, the terminal device may be a computer device with signal processing capabilities, e.g. a stationA computer, a personal computer, a server, etc. It should also be understood that the terminal device may also be a portable electronic device with signal processing capabilities, such as a cell phone, a tablet, a palm top computer, a headset, a stereo, a wearable device (such as a smart watch), an in-vehicle device, a virtual reality device, an augmented reality device, etc. Examples of portable electronic devices include, but are not limited to, a dock
Figure BDA0003151854370000051
Figure BDA0003151854370000052
Or other operating system. The portable electronic device may also be a device such as a Laptop computer (Laptop) with a touch sensitive surface (e.g., a touch panel), etc.
The technical solutions in the embodiments of the present application will be described in detail below with reference to specific drawings.
In a specific application scenario, the clock adjusting apparatus may be applied to a Laser Radar (LR). Fig. 1 schematically illustrates an application scenario of a lidar provided in an embodiment of the present application, in which lidar 100 is mounted on a vehicle, and is therefore also referred to as a vehicle-mounted lidar. Besides the vehicle-mounted laser radar, the laser radar also comprises a ship-mounted laser radar installed on a ship, an airborne laser radar installed on a machine and the like. In one possible example, as shown in fig. 1, lidar 100 may be specifically mounted at a head position of a vehicle and includes a mechanical rotation member and a transmitting mirror fixedly connected to the mechanical rotation member. In the driving process of the vehicle, the transmitting mirror can emit a laser signal, the mechanical rotating part can change the transmitting angle of the laser signal emitted by the transmitting mirror through rotation, the laser radar 100 can also receive a target echo signal corresponding to the laser signal emitted by the transmitting mirror, and then the environmental information of each position around the vehicle is obtained through detection based on the target echo signal, and the environmental information can be used for completing the driving function of the vehicle, including but not limited to automatic driving or auxiliary driving. In addition, the lidar may further include other possible optical components or electronic components, and the application is not particularly limited. It should be noted that, although the mechanical rotating part of laser radar 100 is cylindrical in appearance and the reflector is rectangular in appearance as illustrated in fig. 1, the mechanical rotating part and the reflector in an actual scene may also be in other shapes, for example, the mechanical rotating part may also be annular or polygonal, the reflector may also be circular or annular, etc., and the present application does not specifically limit this. In addition, fig. 1 is only an example of an application scenario of a mechanical type of lidar, and in other application scenarios, the lidar may be of other types, such as a liquid lidar, which is not specifically limited in this application.
As a further example, fig. 2 shows a schematic diagram of an architecture of a laser radar-based driving system provided in an embodiment of the present application, and as shown in fig. 2, the architecture may further include one or more of an upper computer 200, a Global Positioning System (GPS) 300, or an Inertial Navigation System (INS) 400, such as the upper computer 200, the GPS300, and the INS400, in addition to the laser radar 100. The upper computer 200 is a computer capable of directly sending a control command, and may be a vehicle-mounted central control computer in the field of car networking. The vehicle central control unit is also typically connected to a display screen, which can be used to display an environmental image of the vehicle surroundings, such as an environmental image constructed by lidar 100 in conjunction with GPS300, INS400, and other sensors. When the display screen is a touch screen, the display screen can also receive driving instructions or other instructions input by a user through touch operation. The GPS300 is a satellite system composed of a plurality of satellites covering the world, and can acquire an absolute position of a vehicle on the earth, such as longitude, latitude, altitude, and the like of the position of the vehicle, at any time, so as to guide the vehicle to arrive at a destination on time along a driving route. The INS400 is called inertial navigation for short, and is an autonomous navigation system that does not depend on external information and radiates energy to the outside, and measures acceleration of a vehicle in an inertial reference system by an inertial sensor such as a gyroscope based on newton's law of mechanics, integrates the measured acceleration over time, and converts the integration into a navigation coordinate system to obtain information such as speed, yaw angle, and position of the vehicle in the navigation coordinate system. The INS400 may be applied to various environments including air, ground, or underwater, and may obtain a better position accuracy.
With continued reference to fig. 2, in one possible implementation, laser radar 100 may include a Central Processing Unit (CPU) 110, a programmable logic circuit 120, a scanning mechanism 130, a transmitting module 140, and a receiving module 150. The programmable logic circuit 120 is mainly used for processing tasks with high real-time requirements, such as performing communication interaction with the scanning mechanism 130, the transmitting module 140 and the receiving module 150. The CPU110 is mainly used for processing tasks other than the tasks processed by the programmable logic circuit 120, including tasks with low real-time requirements and more complex tasks. The scanning mechanism 130 may be carried in the mechanical rotation component of fig. 1 for changing the rotation direction of the mechanical rotation component to change the environmental scanning angle, and the emission module 140 may be carried in the emission mirror of fig. 1 for emitting the laser signal through the emission mirror. The transmitting module 140 and the receiving module 150 may be coaxial or anisometric, and may be a transmitting module to a receiving module, or a transmitting module to multiple receiving modules, or multiple transmitting modules to one receiving module, or multiple transmitting modules to multiple receiving modules, which is not limited specifically. In addition, the components in laser radar 100, CPU110 and upper computer 200, programmable logic circuit 120 and GPS300, and programmable logic circuit 120 and INS400 may be connected by a Controller Area Network (CAN) bus to implement message communication therebetween.
In a possible driving scenario, the upper computer 200 may receive a driving instruction of a user and send the driving instruction to the CPU110, the CPU110 generates a corresponding driving control instruction according to the driving instruction and sends the driving control instruction to the programmable logic circuit 120, the programmable logic circuit 120 determines a scanning mode of a surrounding environment according to the driving control instruction, generates a scanning control signal according to the scanning mode, and sends the scanning control signal to the scanning mechanism 130, where the scanning control signal is used to instruct the scanning mechanism 130 to control an internal angle sensor to scan according to the instructed scanning mode. Wherein, the scanning mode includes but is not limited to: scan angle, scan dimension (one-dimensional scan, two-dimensional scan, three-dimensional scan, etc.) or scan period, etc. In addition, the programmable logic circuit 120 may also determine a transmission mode of the laser signal according to the driving control command, generate a transmission control signal according to the transmission mode, and send the transmission control signal to the transmission module 140, where the transmission mode includes, but is not limited to: emission period, or emission intensity, etc. Further, the transmitting module 140 transmits a laser signal according to the transmitting mode indicated by the transmitting control signal, the laser signal is reflected by the target object after being scanned to the target object in the environment by the scanning mechanism 130, and the reflected target echo signal can be further received by the receiving module 150 and transmitted to the programmable logic circuit 120 by the receiving module 150. The programmable logic circuit 120 may further obtain a detection result (for example, including a time difference between receiving and transmitting, a signal strength difference between receiving and transmitting, and the like) by comparing the received target echo signal and the transmitted laser signal, and then may send the detection result to the CPU110, and the CPU110 obtains relevant information of the target object, such as distance, direction, height, speed, posture, even shape, and the like, according to the detection result. In addition, when two-dimensional or three-dimensional scanning is adopted, the CPU110 can also construct point cloud data according to detection results, calibrate the point cloud data by utilizing environmental information sensed by a vehicle-mounted camera or other sensors, construct a driving image according to the calibrated point cloud data, and send the driving image to the upper computer 200 so as to be displayed to a driver through the upper computer 200, so that the driving experience of the driver is effectively improved. It should be noted that in other driving scenarios, the programmable logic circuit 120 may also directly send the received target echo signal to the CPU110, and the CPU110 performs an operation of comparing the target echo signal with the laser signal, so as to reduce the working pressure of the programmable logic circuit 120.
As a further example, and with continued reference to FIG. 2, there may be at least two components of lidar 100 that are located in different clock domains, e.g., CPU110 is located in clock domain 1, programmable logic circuit 120 is located in clock domain 2, and scanning mechanism 130 is located in clock domain3, the transmitting module 140 is located in clock domain 4, and the receiving module 150 is located in clock domain 5. In other scenarios, the transmitting module 140 and the receiving module 150 may be located in the same clock domain. In this case, during the driving process, the driving control command sent from the CPU110 to the programmable logic circuit 120, the scan control signal sent from the programmable logic circuit 120 to the scanning mechanism 130, the emission control signal sent from the programmable logic circuit 120 to the emission module 140, the target echo signal sent from the reception module 150 to the programmable logic circuit 120, the detection result sent from the programmable logic circuit 120 to the CPU110, and the like are signals transmitted across clock domains, which are simply referred to as asynchronous signals. However, since the detection principle of lidar 100 requires measurement of the time difference between the received target echo signal and the transmitted laser signal, the speed of light reaches 3 × 10 8 m/s, and therefore the time measurement accuracy of lidar 100 needs to be at least on the order of ns or even ps. Based on such a high time precision measurement requirement, the driving function can be timely and accurately realized only if the clock domain receiving the asynchronous signal can also analyze and judge the asynchronous signal crossing the clock domain with high time precision.
However, taking the programmable logic circuit 120 in the clock domain 2 as an example to send a transmission control signal (belonging to an asynchronous signal) to the transmission module 140 in the clock domain 4, fig. 3 exemplarily shows a possible asynchronous signal sampling circuit diagram provided in the embodiment of the present application, as shown in fig. 3, in this example, the transmission module 140 includes a D flip-flop (which may also be other types of flip-flops, such as an RS flip-flop, a JK flip-flop, or a T flip-flop, and is not limited in particular), and the D flip-flop includes two input terminals, one of which is referred to as a clock input terminal (i.e., a port including a triangular mark in fig. 3) for receiving the clock signal CLK generated by the clock domain 4 itself, and the other is referred to as a data input terminal for receiving the transmission control signal sent by the programmable logic circuit 120 in the clock domain 2, and the D flip-flop can use the clock signal CLK received by the clock input terminal to sample the transmission control signal received by the data input terminal. In some embodiments, with continued reference to FIG. 3, D-touchThe generator may also comprise two outputs, namely an output Q and an output
Figure BDA0003151854370000071
Output terminal Q and output terminal
Figure BDA0003151854370000072
The output signal sampled by the D flip-flop can be output, and the output signal can be further input into a subsequent circuit of the emission module 140 to drive a laser tube in the subsequent circuit to emit a laser signal. Wherein, the output terminal Q and the output terminal
Figure BDA0003151854370000073
Is opposite, e.g. when the output Q outputs a level 1, the output Q outputs a level signal
Figure BDA0003151854370000074
Output level 0, or when output Q outputs level 0, output
Figure BDA0003151854370000075
The output level is 1. In other embodiments, the D flip-flop may also include the output Q but not the output
Figure BDA0003151854370000076
Alternatively, the D flip-flop may also comprise an output
Figure BDA0003151854370000077
But does not include the output Q, or, although the D flip-flop includes both the output Q and the output
Figure BDA0003151854370000078
But output terminal Q and output terminal
Figure BDA0003151854370000079
There may be only one output terminal active and the other output terminal inactive.
Suppose output Q and output Q in D flip-flop
Figure BDA00031518543700000710
All are operated, table 1 exemplarily shows an input-output relationship table of a D flip-flop, and as shown in table 1, when the clock signal CLK is at the rising edge of the clock, if the emission control signal is level 0, the output terminal Q will output level 0, and the output terminal Q will output level 0
Figure BDA00031518543700000711
A level 1 will be output. On the contrary, when the clock signal CLK is at the rising edge of the clock, if the emission control signal is level 1, the output terminal Q will output level 1, and the output terminal Q will output level 1
Figure BDA00031518543700000712
A level 0 is output. When the clock signal CLK is at a non-clock rising edge (including a clock falling edge, a 0 level, a 1 level, or any level between the 0 level and the 1 level), the output terminal Q and the output terminal Q are at any level of the emission control signal
Figure BDA00031518543700000713
The level outputted in the previous period is maintained.
Table 1: input-output relation table of D flip-flop
Figure BDA0003151854370000081
Further illustratively, the clock signal CLK is based on an initial clock signal CLK in clock domain 2 0 Derived, e.g. as an initial clock signal CLK 0 Or to the initial clock signal CLK 0 A clock signal after phase adjustment, regardless of the change of the phase of the clock signal CLK, the clock period of the clock signal CLK and the initial clock signal CLK 0 Always keeps the same clock period, or, said, the clock frequency of the clock signal CLK is the same as the initial clock signal CLK 0 The clock frequency of the clock signal CLK and the initial clock signal CLK are kept consistent 0 Is same frequency and same phase or different frequencyClock signals of the phases. Based on this, fig. 4 illustrates a schematic diagram of sampling results of the transmission control signals by the clock signals with different phases provided by the embodiment of the present application, in this example, the initial clock signal CLK 0 Is a pulse signal that varies periodically with a frequency of 125 MHz. Wherein:
FIG. 4A shows that the initial clock signal CLK is directly applied 0 The sampling result applied to the clock input terminal of the D flip-flop to obtain the emission control signal is shown schematically in (A) of FIG. 4, when the D flip-flop detects the clock signal CLK during the variation period of the emission control signal 0 When the rising edge of the clock comes, the level of the emission control signal is level 1, so that the D flip-flop outputs level 1 at the output end Q after sampling the emission control signal. Then, when the D flip-flop detects the clock signal CLK 0 When the rising edge of the clock comes again, the level of the emission control signal is level 0, and thus, after the D trigger samples the emission control signal, level 0 is output at the output end Q. From this, the clock signal CLK used in FIG. 4 (A) 0 The transmit control signal can be sampled 100% accurately.
FIG. 4 (B) shows the initial signal CLK 0 Phase delay D of 0 Then, the phase-shifted clock signal CLK = CLK 0 +D 0 As shown in (B) of fig. 4, the sampling result of the emission control signal applied to the clock input terminal of the D flip-flop is that, during the variation period of the emission control signal, the D flip-flop does not detect the clock rising edge of the clock signal CLK, resulting in that the output terminal Q of the D flip-flop outputs a level 0. From this, the clock signal CLK used in FIG. 4 (B) 0 +D 0 The transmit control signal cannot be sampled.
FIG. 4 (C) shows the initial signal CLK 0 Phase delay D of 1 Then, the phase-shifted clock signal CLK = CLK 0 +D 1 The sampling result of the emission control signal applied to the clock input terminal of the D flip-flop is schematically shown, as shown in (C) of fig. 4, during the variation period of the emission control signal, when the D flip-flop detects that the clock rising edge of the clock signal CLK comes, the emission control signal is emittedThe level of the control signal is a level between level 0 and level 1, in which case, after the D flip-flop samples the transmission control signal, level 0 may be output at the output Q (corresponding to the sampling result, see the single-node line illustrated in (C) in fig. 4), and level 1 may be output at the output Q (corresponding to the sampling result, see the double-node line illustrated in (C) in fig. 4). That is, the probability that the D flip-flop outputs both level 0 and level 1 is 50%. From this, the clock signal CLK used in FIG. 4 (C) 0 +D 1 The accuracy of the successful sampling to the transmission of the control signal is 50%.
Shown in FIG. 4 (D) is the initial signal CLK 0 Phase delay D of 2 Then, the phase-shifted clock signal CLK = CLK 0 +D 2 As shown in (D) of fig. 4, when the D flip-flop detects that a clock rising edge of the clock signal CLK arrives during a change period of the emission control signal, the level of the emission control signal is level 1, and thus, after the D flip-flop samples the emission control signal, level 1 is output at the output terminal Q. From this, the clock signal CLK used in FIG. 4 (D) 0 +D 2 The transmit control signal can also be sampled 100% accurately.
As can be seen from the sampling process illustrated in fig. 4 (a) to 4 (D), the transition edge of the asynchronous signal (which refers to the time when the level of the asynchronous signal starts to transition, for example, the time when the emission control signal transitions from level 0 to non-level 0, or the time when the emission control signal transitions from non-level 0 to level 0) is not an ideal steep edge, but has a slope. When the time interval between the clock rising edge of the clock signal CLK of the D flip-flop and the transition edge of the asynchronous signal is smaller than a certain value, the time interval is not enough for the D flip-flop to establish time or maintain time requirements, which causes the D flip-flop to make a probabilistic error in the level determination of the asynchronous signal. Moreover, when the time interval between the clock rising edge of the clock signal CLK and the transition edge of the asynchronous signal is smaller, the probability of the occurrence of an error in the level determination is larger, which is called a metastable state phenomenon of transmitting the asynchronous signal across the clock domain. When the D flip-flop is in a metastable state, the D flip-flop cannot predict a correct output level, nor when the D flip-flop can stabilize at a correct output level, so that the D flip-flop can only output one or more levels randomly or according to a certain rule, for example, stably output an intermediate level between level 0 and level 1, or oscillate output (i.e., the output level is frequently switched between level 0 and level 1), and such an unnecessary output level propagates in a cascade manner along each circuit on a signal path, so that subsequent processing of the circuit becomes problematic, and the stability of the whole circuit system is affected.
In view of this, the present application provides a clock adjusting apparatus, which can adjust a phase of a clock signal used for sampling a signal to be tested in a clock domain to a target phase with a better sampling result, so as to improve accuracy of sampling the signal to be tested in the clock domain. The signal to be measured may be an asynchronous signal or a synchronous signal. When the signal is an asynchronous signal and is applied to laser radar, one or more of the following signals can be specifically included: driving control commands, scanning control signals, emission control signals, target echo signals, detection results, and the like, and are not particularly limited.
It should be noted that the clock adjusting apparatus in the present application may be applied to the above-mentioned laser radar, and may also be applied to other apparatuses, devices, or chips besides the above-mentioned laser radar, for example, to other intelligent terminals with signal processing functions besides the above-mentioned laser radar, or to components provided in other intelligent terminals, including but not limited to other sensors such as a controller, a chip, or a camera, and other components. Alternatively, the clock adjusting device in the present application may be applied to the driving system, and may also be applied to other imaging systems besides the driving system, such as a building three-dimensional modeling system, a terrain mapping system, or a rendezvous and docking system. Moreover, with the evolution of the system architecture and the appearance of new scenes, the clock adjusting device provided by the present application is also applicable to similar technical problems, and the present application does not specifically limit the same.
The specific structure of the clock adjusting apparatus in the present application will be described below with reference to specific embodiments, and it is apparent that the described embodiments are only a part of the embodiments of the present application, and not all embodiments.
It should be noted that the terms "system" and "network" in the embodiments of the present application may be used interchangeably. "at least one" means one or more, "a plurality" means two or more. "and/or" describes the association relationship of the associated objects, meaning that there may be three relationships, e.g., a and/or B, which may mean: a alone, A and B together, and B alone, wherein A and B may be singular or plural. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship. "at least one of the following" or similar expressions refer to any combination of these items, including any combination of the singular or plural items. For example, at least one (one) of a, b, or c, may represent: a, b, c, a-b, a-c, b-c, or a-b-c, wherein a, b, c may be single or multiple.
And "connected" in the embodiments of the present application may be understood as an electrical connection, and the connection of two electrical components may be a direct or indirect connection between the two electrical components. For example, a and B may be connected directly, or a and B may be connected indirectly through one or more other electrical elements, for example, a and B may be connected, or a and C may be connected directly, or C and B may be connected directly, and a and B are connected through C. In some scenarios, "connected" may also be understood as coupled, such as an electromagnetic coupling between two inductors. In short, the connection between A and B can enable the transmission of electric energy between A and B.
In addition, the port name in the embodiment of the present application is only an exemplary expression, and in other examples, other port names may also be provided, for example, an input terminal, an output terminal, or a control terminal may also be collectively referred to as a communication terminal, which is not limited in this application. In addition, in the embodiment of the present application, one port corresponds to another port, which may mean that the two ports are the same port, or that the two ports are different ports but are communicated through a line, which is not limited in the present application.
And, unless specifically stated otherwise, the embodiments of the present application refer to the ordinal numbers "first", "second", etc., for distinguishing between a plurality of objects, and do not limit the priority or importance of the plurality of objects. For example, the first phase adjustment instruction is an instruction sent to the phase adjustment unit to determine the target phase, and the second phase adjustment instruction is an instruction sent to use the target phase after the target phase is determined, and these two phase adjustment instructions are only used to distinguish different phase adjustment instructions sent in different time periods and different requirements, and do not indicate different priorities or importance levels of these two phase adjustment instructions.
Fig. 5 schematically illustrates a structural diagram of a clock adjustment apparatus provided in an embodiment of the present application, and as shown in fig. 5, the clock adjustment apparatus 500 includes a clock generation unit 510, a phase adjustment unit 520, and a phase control unit 530. Wherein, the output terminal of the clock generating unit 510 is connected to the first input terminal (a) of the phase adjusting unit 520 1 ) Output terminal (a) of phase adjusting unit 520 3 ) Connected to a first input terminal (b) of the phase control unit 530 1 ) Second input terminal (b) of phase control unit 530 2 ) For receiving a signal S to be measured (e.g. an asynchronous signal sent by another clock domain), an output (b) of the phase control unit 530 3 ) A second input terminal (a) connected to the phase adjusting unit 520 2 ). In an implementation, the clock generation unit 510 is used for generating a first clock signal (CLK) 0 ) The first clock signal CLK 0 After the first clock signal CLK is outputted to the phase adjusting unit 520 through the output terminal of the clock generating unit 510, the phase adjusting unit 520 receives the first clock signal CLK 0 Performing phase adjustment to obtain N second clock signals (CLK) 1 、CLK 2 、……、CLK N ) And N second clock signals CLK 1 ～CLK N Corresponding to the N phases, N is a positive integer greater than or equal to 2. Further, N second clock signals CLK 1 ～CLK N Through the output terminal a of the phase adjusting unit 520 3 The output is sent to the phase control unit 530, and the phase control unit 530 uses the N second clock signalsTo the input end b 2 The input signal S to be detected is sampled to obtain sampling results of the N second clock signals on the signal S to be detected, and then a first phase adjustment instruction is sent to the phase adjustment unit 520 according to the sampling results and a preset rule, where the first phase adjustment instruction is used for indicating a target phase. The phase adjustment unit 520 receives the first phase adjustment indication, and then adjusts the first clock signal CLK from the clock generation unit 510 according to the first phase adjustment indication 0 And adjusting the phase to obtain a third clock signal, wherein the phase of the third clock signal is a target phase, and the third clock signal is subsequently used for sampling the signal S to be detected.
In a possible implementation manner, as shown in fig. 3, taking the transmitting module 140 in which the clock adjusting apparatus 500 is disposed in the clock domain 4 as an example, the following may be preset or configured in the laser radar 100: after the programmable logic circuit 120 in the clock domain 2 is powered on, the transmission control signal (signal to be tested) is actively sent to the transmission module 140 in the clock domain 4, which will have service interaction in the future, according to a preset or configured period, after the transmission module 140 in the clock domain 4 is powered on, N second clock signals with different phases can be obtained according to an initial clock signal (i.e., a first clock signal) of the clock domain 4, and the transmission control signal sent by the programmable logic circuit 120 in the clock domain 2 is sampled by using the N second clock signals, so as to obtain sampling results corresponding to the N second clock signals, then, according to a preset rule and the sampling results corresponding to the N second clock signals, a target second clock signal is obtained from the N second clock signals, and further, the phase of the initial clock signal generated by the clock domain 4 is adjusted based on the target phase corresponding to the target second clock signal, so as to obtain a third clock signal with the target phase, and then the third clock signal is used to sample a real transmission control signal sent by the programmable logic circuit 120 in the clock domain 2 in a real scanning process. The emission control signal sent by the emission module 140 after the start-up may be preset or configured in the emission module 140, and may also be set according to the real emission control signal that will appear in the real scanning process, so that the target phase determined based on the emission control signal used after the start-up may also be applicable to the real emission control signal.
It should be noted that the clock adjusting apparatus 500 is particularly suitable for the case of having a fixed signal to be measured, such as the case of calibration of a laser radar. In the calibration situation, the programmable logic circuit 120 in the lidar 100 may repeatedly send a certain fixed known transmission control signal to the transmission module 140 to drive the transmission module 140 to send a laser signal to a fixed target object according to the fixed known transmission control signal, and the programmable logic circuit 120 may further receive a target echo signal acquired by the reception module 150 for the transmission control signal, and then report the target echo signal to the CPU110, so that the CPU110 completes calibration of each device in the lidar 100 with reference to the target echo signal. In this scenario, since the emission control signal is fixedly known and the target object is fixedly known, the target echo signal is also fixedly known. Based on this, in implementation, the fixed known transmission control signal may be set or configured in the transmission module 140 in advance, so that the transmission module 140 uses the transmission control signal to complete the phase adjustment function for the clock domain 4 after the power-on, and the fixed known target echo signal may be set or configured in the programmable logic circuit 120 in advance, so that the programmable logic circuit 120 can also use the target echo signal to complete the phase adjustment function for the clock domain 2 after the power-on.
Further, taking the example that the signal to be tested includes the emission control signal, considering that the real emission control signal may also change in the service interaction process of the clock domain 2 and the clock domain 4, the clock adjusting device 500 disposed in the emission module 140 may reuse the N second clock signals to perform the sampling operation on the real emission control signal at intervals after obtaining the third clock signal, and re-determine the target phase according to the preset rule and the sampling results corresponding to the N second clock signals obtained by re-sampling. When the phase difference between the re-determined target phase and the currently used target phase (which may be the target phase determined at power-on or the target phase determined in a previous period of time) is not large, it means that the actual transmission control signal changes slightly although it changes, and a better sampling result can be obtained even though the current target phase is still used. In this case, the clock adjusting apparatus 500 may not update the target phase, that is, the third clock signal is still used to continue sampling the subsequent transmission control signal, so that when the acquisition result meets the preset rule, unnecessary phase adjustment operation is saved as much as possible, and processing resources are saved. When the phase difference between the re-determined target phase and the currently used target phase is large, it means that the real transmission control signal is changed more drastically, and if the current target phase is still used, a better sampling result may not be obtained, which is not favorable for accurately implementing the subsequent control operation. In this case, the clock adjusting apparatus 500 may update the target phase, that is, perform phase adjustment on the initial clock signal generated by the clock domain 4 again to obtain a new third clock signal with the phase being the re-determined target phase, and sample the subsequent transmission control signal using the new third clock signal, so that when the transmission control signal changes greatly, the third clock signal is re-adjusted to adapt to the changed transmission control signal, and the accuracy and stability of asynchronous sampling are maintained as much as possible.
It should be noted that the resampling operation may be performed once every a preset or configured period of time, or may be performed by a certain convention between the clock domains 2 and 4. For example, in order to avoid the influence of resampling on the real sampling process, it may be possible that the programmable logic circuit 120 in the clock domain 2 sends the last sent historical transmission control signal to the clock adjusting apparatus 500 in the clock domain 4 according to a preset or configured cycle in a period in which the transmission control signal is not really sent, or sends a transmission control signal to be sent in the future predicted based on the last sent historical transmission control signals. Therefore, by resampling with reference to the historical transmission control signal with higher value in the time period when the transmission control signal is not really transmitted, the influence of phase adjustment on real sampling operation can be reduced, the redetermined target phase can be matched with the future transmission control signal as much as possible, and the accuracy of real sampling and the flexibility of readjustment are both considered.
Based on the above, it can be known that, with the clock adjusting device as illustrated in fig. 5, the clock signal of each phase is used to pre-sample the signal to be tested before the signal to be tested is formally sampled, which is helpful for obtaining the target phase with a better sampling result in each phase, and the target phase with a better sampling result is used, so that the sampling accuracy and the sampling stability of formally sampled signal to be tested can be improved. Furthermore, when the signal to be detected is an asynchronous signal, the design can also enable a clock domain receiving the asynchronous signal to have the capacity of flexibly adjusting the clock phase, and the adjusted clock phase can be always matched with the received asynchronous signal, so that the sampling accuracy of the asynchronous signal transmitted across the clock domain is effectively improved, the metastable state risk of the asynchronous signal transmitted across the clock domain is reduced, and the stability of the whole circuit system is improved. And when the clock adjusting device is applied to one or more clock domains of the laser radar, the one or more clock domains can timely and accurately acquire asynchronous signals sent by other clock domains, so that the laser radar can be helped to accurately acquire environmental information in the driving process, and the driving accuracy and safety are effectively improved.
In the embodiment of the present application, the phase adjusting unit 520 may be any device or device having a phase adjusting function, such as:
in a possible implementation manner, fig. 6 exemplarily shows a schematic structural diagram of a phase adjustment unit provided in an embodiment of the present application, as shown in fig. 6, in this implementation manner, the phase adjustment unit 520 may include N delay links L 1 、L 2 、L 3 、……、L N-1 、L N N delay links L 1 ～L N Each delay chain of (1) may include a switch component, and any two delay chains may further include a different number of delay units (i.e., triangular devices as shown in fig. 6), where each delay unit is capable of inputting a clock signalThe phase of (a) is delayed by a preset time length (the preset time length may also be referred to as a preset phase) and then output. E.g. a delay link L 1 Comprises a switch component K 1 And does not include a delay unit, such that when the phase adjustment unit 520 turns on the delay chain L 1 Switch assembly K on 1 Clock, first clock signal CLK 0 Can be directly along the delay link L 1 To the phase control unit 530, thereby delaying the link L 1 Output second clock signal CLK 1 And the first clock signal CLK 0 Are the same in phase; delay link L 2 Comprises a switch component K 2 And 1 delay unit, such that when the phase adjustment unit 520 turns on the delay chain L 2 Switch assembly K on 2 Clock, first clock signal CLK 0 Along the delay link L 2 In the transmission process, the delay unit 1 delays for a preset time period before transmitting to the phase control unit 530, so as to delay the link L 2 Output second clock signal CLK 2 Compared to the first clock signal CLK 0 Is delayed by a preset time; 823060, 8230; delay link L N Comprises a switch component K N-1 And N-1 delay units, such that when the phase adjustment unit 520 turns on the delay chain L N Switch assembly K on N Clock, first clock signal CLK 0 Along the delay link L N-1 In the transmission process, the delay time is delayed by N-1 times of the preset time length by N-1 delay units and then transmitted to the phase control unit 530, so as to delay the link L N Output second clock signal CLK N-1 Compared to the first clock signal CLK 0 Is delayed by N-1 times the preset duration.
Further, when the phase adjustment unit 520 adopts the structure illustrated in fig. 6, the phase adjustment unit 520 receives the first clock signal CLK transmitted from the clock generation unit 510 0 Thereafter, the N delay links may be traversed, with each delay link traversed: the switch elements on the delay chain are controlled to be turned on, and the N-1 delay chains except the delay chain are controlled to be turned off, so that the phase control unit 530 can use the second delay chain corresponding to the delay chainThe clock signal samples the signal to be tested, and obtains a sampling result of the second clock signal corresponding to the delay link, and then after it is determined that the phase control unit 530 finishes sampling the second clock signal corresponding to the delay link, the phase adjustment unit 520 may start traversing one of the remaining delay links that is not traversed. Further, after the N delay links are traversed, the phase control unit 530 may determine a target delay link with a better sampling result based on a preset rule and a sampling result of a second clock signal corresponding to each of the N delay links, send a first phase adjustment instruction indicating the entry target delay link to the phase adjustment unit 520, turn on a switch component on the entry target delay link according to the first phase adjustment instruction by the phase adjustment unit 520, and turn off switch components on N-1 delay links except the entry target delay link, so that the target delay link with a better sampling result is subsequently used to sample the signal to be measured.
In another possible implementation manner, fig. 7 exemplarily shows a schematic structural diagram of another phase adjusting unit provided in an embodiment of the present application, in this example, the phase adjusting unit 520 may be a phase-locked loop, and the phase-locked loop is a negative feedback control system for tuning a voltage-controlled oscillator by using a voltage generated by phase synchronization to generate a target frequency, and the negative feedback control system controls a frequency and a phase of an internal oscillation signal of the loop by using an externally input reference signal to achieve automatic tracking of an input signal frequency by an output signal frequency. As shown in fig. 7, the phase adjustment unit 520 may include a phase detector 521, a low pass filter 522, a voltage controlled oscillator 523, a phase shifter 524, and a 1/T counter 525, T being a positive integer. One input end of the phase detector 521 corresponds to the first input end a of the phase adjusting unit 520 1 The output end of the phase detector 521 is connected to the input end of the low-pass filter 522, the output end of the low-pass filter 522 is connected to the input end of the voltage-controlled oscillator 523, the output end of the voltage-controlled oscillator 523 is connected to the input end of the phase shifter 524, the output end of the phase shifter 524 is connected to the input end of the 1/T counter 525, and the output ends of the 1/T counter 525 are respectively connected to the other input end of the phase detector 521 and the output end a of the phase adjusting unit 520 3 . WhereinThe phase shifter 524 is configured with a plurality of delay units in advance, any two of the plurality of delay units correspond to the same delay time length (e.g., 1 °), and each of the plurality of delay units may have two states of being disabled or enabled. When a clock signal is inputted to the phase shifter 524, the phase of the clock signal is delayed by the effective delay unit, and then the clock signal is converted into another clock signal with a phase different from the phase of the input clock signal but still having the frequency of the input clock signal and outputted. For example, assuming that 180 delay units are collectively configured in the phase shifter 524, and the delay time length of each delay unit is 1 °, then: if none of the 180 delay cells are active, the phase of the output clock signal is the same as the phase of the input clock signal; if 60 of the 180 delay cells are active, the phase of the output clock signal is delayed by 60 compared to the phase of the input clock signal; if 100 of the 180 delay cells are active, the phase of the output clock signal is delayed by 100 compared to the phase of the input clock signal.
In an implementation, the phase detector 521 may receive the first clock signal CLK 0 A first clock signal CLK sent to a low pass filter 522 and also input to two inputs 0 The phase of the clock signal fed back by the 1/T counter 525 is compared with the phase of the clock signal, and the phase difference is obtained and sent to the low pass filter 522. The low pass filter 522 may filter out a high frequency signal of the received signal and transmit a low frequency signal of the received signal to the voltage controlled oscillator 523, wherein the low frequency signal includes the first clock signal CLK 0 And the above phase difference. The voltage-controlled oscillator 523 can adjust the working voltage of the clock domain where the phase adjustment unit 520 is located according to the phase difference to obtain the first clock signal CLK with the frequency 0 T times the frequency of the fourth clock signal. After the fourth clock signal generated by the vco 523 is transmitted to the phase shifter 524, the phase of the fourth clock signal is delayed by the effective delay unit in the phase shifter 524, and the phase difference of the first clock signal CLK is obtained 0 And a frequency of T times of the first clock signal CLK 0 The fifth clock signal of the frequency of (2) is then output to the 1/T counter 525, and the fifth clock signal is output to the 1/T counterThe signal is down-converted to the first clock signal CLK by the 1/T counter 525 0 The second clock signal with the same frequency is output to the phase control unit 530 for sampling on the one hand, and is fed back to the phase detector 521 on the other hand, so that the above phase feedback operation is performed in a circulating manner, and accurate adjustment of the phase and the frequency is achieved. The present application does not specifically describe these several components with respect to their specific implementations.
Further, when the phase adjustment unit 520 adopts the structure illustrated in fig. 7, the phase adjustment unit 520 receives the first clock signal CLK transmitted from the clock generation unit 510 0 Then, all delay units in the phase shifter 524 may be set to fail first, so that the phase control unit 530 can directly sample the signal to be tested using the first clock signal to obtain the first clock signal CLK 0 And sampling results of the signals to be tested. Thereafter, the phase adjustment unit 520 may obtain a phase different from the first clock signal CLK by changing the number of effective delay units in the phase shifter 524N-1 times 0 N-1 second clock signals of the phase of (a). For example, assuming that 180 delay units are provided in the phase shifter 524, and the delay time corresponding to each delay unit is 1 °, when the phase adjustment unit 520 adjusts the phase in a step manner, if the minimum unit of each step is 1 delay unit, the phase adjustment unit 520 may obtain 181 second clock signals which are respectively shifted by 0 °,1 °, 2 °, 3 °, \ 8230 \ 8230;, 178 °, 179 °, 180 ° compared to the phase of the first clock signal by not changing and by changing the number of effective delay units 180 times, and the phase control unit 530 may obtain the sampling result of the signal to be measured by the 181 second clock signals. Or, if the minimum unit of each step is 2 delay units, the phase adjustment unit 520 may obtain 91 second clock signals respectively shifted by 0 °, 2 °, 4 °, 6 °, \ 8230; \ 8230;, 176 °, 178 °, and 180 ° compared to the phase of the first clock signal by not changing and by changing the number of effective delay units 90 times, and the phase control unit 530 may obtain the sampling results of the 91 second clock signals on the signal to be measured.
The number of delay cells included in the phase shifter 524 and the delay time corresponding to each delay cell may be fixed values that are preset or configured, and the minimum unit of each step may be a fixed value that is preset or configured, or may be variable values that support a user to modify according to an actual scene. For example, when the requirement on the accuracy in the current scenario is not high, in order to save the computational complexity, the user may also set the minimum unit for each step to be 10 delay units, in this case, the phase adjustment unit 520 may obtain, through not changing and through changing the number of effective delay units 18 times, 19 second clock signals whose phases are respectively shifted by 0 °, 10 °, 20 °, 30 °, \ 8230 \ 8230;, 160 °, 170 °, and 180 ° compared to the first clock signal, and the phase control unit 530 may obtain the sampling results of the 19 second clock signals for the signal to be measured, which is simpler to compute and more efficient in phase adjustment compared to the scheme in which the minimum unit is 1 delay unit or 2 delay units.
It should be noted that the phase adjusting unit 520 illustrated in fig. 6 or fig. 7 is only an exemplary illustration, and in actual operation, the phase adjusting unit 520 may further have more or fewer components than those illustrated in fig. 6 or fig. 7, or a plurality of components in fig. 6 or fig. 7 may be integrated on one physical unit or distributed on a plurality of physical units, or other devices with a phase shifting function besides fig. 6 or fig. 7 may be adopted as the phase adjusting unit 520, and the like, and this application is not limited in this respect.
In one possible implementation, with continued reference to fig. 5, the phase control unit 530 may include a flip-flop 531 and a sampling control unit 532, wherein a clock input terminal of the flip-flop 531 (for example, in the case that the flip-flop 531 includes a D flip-flop, the clock input terminal refers to a port including a triangular mark in fig. 5) corresponds to the first input terminal b of the phase control unit 530 1 The data input of the flip-flop 531 (e.g., where the flip-flop 531 comprises a D flip-flop, the data input refers to the port on the same side of the triangle labeled port in FIG. 5. In actual practice, the data input and the clock input of the flip-flop 531 may be on the same sideOne side, or two opposite sides, or two adjacent sides, etc., without limitation) corresponding to the second input terminal b of the phase control unit 530 2 The output terminal of the flip-flop 531 is connected to the input terminal of the sampling control unit 532, and the output terminal of the sampling control unit 532 corresponds to the output terminal b of the phase control unit 530 3 . In implementation, the flip-flop 531 may sample the signal S to be measured input by the data input end using each second clock signal received by the clock input end, obtain an output signal corresponding to each second clock signal and output the output signal through the output end of the flip-flop, the sampling control unit 532 may obtain the output signal corresponding to each second clock signal output by the output end of the flip-flop, determine a target phase according to a preset rule and the output signals corresponding to the N second clock signals, and further send a first phase adjustment instruction indicating the target phase to the phase adjustment unit 520. Therefore, in the implementation mode, the trigger can sample only at the clock edge and does not sample at the non-clock edge, so that the trigger is used for sampling the signal to be detected, thereby being beneficial to reducing the occurrence probability of circuit glitches (the circuit glitches refer to the situation that one or more than one jump crosses the logic threshold in the sampling period) and reducing the sampling power consumption.
It should be noted that, when the flip-flop 531 includes a D flip-flop, the output terminal of the flip-flop 531 may include the output terminal Q and/or the output terminal Q of the D flip-flop
Figure BDA0003151854370000151
For example, it may comprise an output Q but no output as illustrated in FIG. 5
Figure BDA0003151854370000152
Or may also include an output
Figure BDA0003151854370000153
But does not include the output terminal Q, or may include both the output terminal Q and the output terminal Q
Figure BDA0003151854370000154
In addition, touchThe transmitter 531 may further include, in addition to a clock input terminal, a data input terminal and an output terminal, other functional ports, such as one or more of a reset port (CLR), a set port PRE, an enable port ENA, and the like, without limitation.
For example, in an implementation, the preset rule may relate to sampling a correct sampling result, for example, the preset rule may be used to indicate that the target phase is a phase corresponding to the second clock signal with a correct output signal. In this case, after obtaining the output signal corresponding to each second clock signal, the sampling control unit 532 may compare the output signal with the reference signal, and if the output signal and the reference signal match, it indicates that the second clock signal is sampled correctly, and if the output signal and the reference signal do not match, it indicates that the second clock signal is sampled incorrectly. In this way, after comparing the N second clock signals, the sampling control unit 532 may select a target second clock signal from the correctly sampled second clock signals, and use a phase corresponding to the target second clock signal as a target phase. The reference signal may be a signal indicating that the output signal is sampled correctly, the reference signal may be a fixed signal preset or configured in the sampling control unit 532, or may be a signal that a clock domain sending the signal to be tested notifies the sampling control unit 532 before sending the signal to be tested, which is not limited in particular. The output signal and the reference signal are matched, that is, the output signal is identical to a signal to be output theoretically corresponding to the signal to be measured. For example, when the flip-flop 531 includes a D flip-flop and the signal to be tested is level 1, if the output end of the flip-flop 531 is the output end Q of the D flip-flop, the signal to be output by the output end Q of the D flip-flop is level 1 theoretically when the signal to be tested is sampled at the clock rising edge, therefore, when the output signal corresponding to a second clock signal is level 1, it is considered that the output signal of the second clock signal matches the reference signal, the output signal of the second clock signal is correct, and the second clock signal is relatively suitable for sampling the signal to be tested S; when an output signal corresponding to a second clock signal is level 0, the output signal of the second clock signal is considered to be not matched with the reference signal, the output signal of the second clock signal is wrong, and the second clock signal is not suitable for sampling the signal to be tested.
For further example, considering that there may be a contingency problem in evaluating the N second clock signals by using the single sampling result, the preset rule may also be used to indicate that the target phase is a phase corresponding to a second clock signal whose output signal is correct and whose number is not less than the number threshold. In this case, the sampling control unit 532 may further obtain M output signals obtained by sampling the signal S to be measured by the flip-flop 531 for M times (M is a positive integer greater than or equal to 2) under each second clock signal, and compare the M output signals corresponding to each second clock signal with the reference signal, thereby determining the number of output signals matching the reference signal in the M output signals. If the number is not less than the number threshold, it indicates that the sampling accuracy of the second clock signal to the signal S to be tested is higher, and the second clock signal is more suitable for sampling the signal S to be tested. If the number is smaller than the number threshold, it indicates that the sampling accuracy of the second clock signal on the signal S to be tested is low, and the second clock signal is not suitable for sampling the signal S to be tested. Thus, after comparing the N second clock signals, the sampling control unit 532 may further select a target second clock signal from the second clock signals suitable for sampling the signal S to be detected, and then use a phase corresponding to the second clock signal as a target phase, so as to improve the accuracy of sampling the signal to be detected by using a target phase that is more accurate after multiple times of sampling.
It should be understood that the preset rule may also be another rule set according to the above idea, for example, the preset rule may also be used to indicate that the target phase is a phase corresponding to a second clock signal whose sampling success rate (which may be characterized by a ratio of the number of correct output signals to M) is not less than a success rate threshold, or may also be used to indicate that the target phase is a most stable phase among phases corresponding to respective second clock signals whose number of correct output signals is not less than a number threshold, or indicate that the target phase is a most stable phase among phases corresponding to respective second clock signals whose sampling success rate is not less than the success rate threshold, or indicate that the target phase is a most stable phase among phases corresponding to respective second clock signals whose other sampling indexes are greater than an index threshold, and the other sampling indexes are positively correlated with the number of correct output signals. In addition, the above description is only given by taking the example that the N second clock signals correspond to the same sampling number M, and in other embodiments, the N second clock signals may also correspond to two or more sampling numbers.
For convenience of understanding, the sampling index is described as an example, and other sampling indexes may be directly referred to and executed, which is not repeated in this application.
In one possible implementation manner, as shown in fig. 5, the sampling control unit 532 may include a sampling unit 5321 and an evaluation control unit 5322, and the first input end (c) of the sampling unit 5321 1 ) The output terminal of the flip-flop 531, and the output terminal (c) of the sampling unit 5321 are connected 3 ) An input terminal (d) connected to the evaluation control unit 5322 1 ) A first output terminal (d) of the evaluation control unit 5322 2 ) A second input end a connected with the phase adjusting unit 2 . In an implementation, for each of the N second clock signals, the sampling unit 5321 may collect M output signals obtained by sampling the signal to be measured S by the flip-flop 531 for M times under the second clock signal, and output M output signals corresponding to each second clock signal to the evaluation control unit 5322 through the output end of the sampling unit 5321, and the evaluation control unit 5322 may obtain the number of output signals matching the reference signal from the M output signals after receiving the M output signals corresponding to each second clock signal, and determine a sampling success rate of the phase corresponding to the second clock signal for sampling the signal to be measured S according to the number and the total number M of output signals, and then determine a target second clock signal according to the sampling success rates corresponding to the N second clock signals, take the phase corresponding to the target second clock signal as a target phase, and further send a first phase adjustment indication indicating the target phase to the phase adjustment unit. Thus, it is aThe sampling operation is executed by using the sampling unit, the evaluation control unit is used for executing the operation of evaluating the sampling success rate and controlling the phase adjustment, the sampling operation and the evaluation and phase adjustment operation after sampling can be decoupled, the working pressure of each unit is reduced, the influence of the execution of the evaluation operation and the phase adjustment operation on the sampling operation is reduced, the accuracy of a sampling output result is effectively improved, and the accuracy of the evaluation and the phase adjustment is further improved.
For example, in the above implementation, the operation of the sampling unit 5321 sampling M output signals of the flip-flop 531 at every second clock signal may be further controlled by the evaluation control unit 5322. In practice, with continued reference to FIG. 5, the second output (d) of the evaluation control unit 5322 3 ) A second input (c) of the sampling unit 5321 may be connected 2 ) Before the sampling unit 5321 samples the M output signals of the flip-flop 531 under each second clock signal, the evaluation control unit 5322 may further output the M output signals through a second output terminal d 3 An enable signal for instructing the sampling unit 5321 to sample the output signal of the flip-flop 531 for an instruction message valid period is sent to the sampling unit 5321. The enable signal may be determined according to an upcoming time period of the signal S to be measured, the upcoming time period of the signal S to be measured may be preset or configured in the evaluation control unit 5322, or a clock domain that generates the signal S to be measured is notified to the evaluation control unit 5322 before the signal S to be measured is sent, which is not limited specifically. The indication message valid period is used to indicate in which period the sampling unit samples the output signal of the flip-flop 531, and the period may have many possibilities, for example, in a case, the indication message valid period may be used to indicate a period of time when the enable signal is received, in this case, the evaluation control unit 5322 may send the enable signal to the sampling unit 5321 once before the high level of the signal S to be tested comes each time, and the sampling unit 5321 may enable its sampling capability after receiving one enable signal each time, so as to start the sampling operation of the output signal of the flip-flop 531 in a period of time. Wherein the duration of the period of time can be preset or configured in the sampling unit 5321Alternatively, when the enable signal has the capability of carrying information, the evaluation control unit 5322 may carry information that is notified to the sampling unit 5321 in the enable signal, and the present invention is not limited to this. In another case, the indication message valid period may be used to indicate the initial sampling time and the sampling time interval, in this case, the evaluation control unit 5322 may further send an enable signal including the initial sampling time and the sampling time interval to the sampling unit 5321 before sampling the M output signals corresponding to any one of the second clock signals, and after the sampling unit 5321 receives the enable signal, the output signal of the flip-flop may be sampled once at the initial sampling time indicated in the enable signal, and then the output signal of the flip-flop 531 may be sampled once at every sampling time interval. It should be understood that there are many possible implementations of the enable signal, which are not listed here.
Further illustratively, the N second clock signals may include one second clock signal having the same phase as the first clock signal and N-1 second clock signals having a different phase from the first clock signal. In any adjustment, the evaluation control unit 5322 may further send a second phase adjustment indication to the phase adjustment unit 520 after determining that the sampling unit 5321 samples M output signals corresponding to the current second clock signal, where the second phase adjustment indication is used to indicate that: the phase adjustment unit 520 performs phase adjustment on the first clock signal from the clock generation unit 510 to obtain a next second clock signal, where the phase of the next second clock signal is one of the N phases that has not been adjusted yet. For any one of the second clock signals, the evaluation control unit 5322 may determine whether the sampling unit 5321 samples M output signals corresponding to the second clock signal in multiple ways, for example, in one possible way, the sampling unit 5321 may record the number of times of sampling an output signal corresponding to a certain second clock signal, when it is determined that M times of sampling are performed, the sampling unit 5322 may send a notification message of the end of sampling to the evaluation control unit 5322, and the evaluation control unit 5322 may instruct the phase adjustment unit 520 to perform adjustment of the next phase once receiving the notification message of the end of sampling. In another possible manner, the evaluation control unit 5322 may count the number of times that the sampling unit 5321 samples the output signal corresponding to a certain second clock signal, and when M times are determined to be indicated, the sampling unit 5321 is no longer instructed to sample, and the phase adjustment unit 520 is instructed to adjust the next phase. In another possible manner, the evaluation control unit 5322 may further instruct the sampling unit 5321 to perform M times of sampling through an enable signal, start timing after the enable signal is sent, and instruct the phase adjustment unit 520 to perform adjustment of the next phase after the estimated sampling unit 5321 samples M times. And so on. There are many possible implementations, and they are not listed here.
Further exemplarily, any two adjacent phases of the N phases may have the same phase interval in an order from large to small or from small to large, where the phase interval may be a fixed value preset or configured, or may be a variable value supporting user modification according to an actual scene. For example, in one possible design, when the phase adjustment unit 520 adopts the structure illustrated in fig. 7, it is assumed that the first clock signal CLK is 0 Is 0 °, the phase interval set by the user is 3 °, M is 5000, and n is 10, the evaluation control unit 5322 determines that the phase adjustment unit 520 receives the first clock signal CLK 0 Then, the output signal of the flip-flop 531 may be sampled in 5000 periods coming from the level 1 of the signal to be measured by first sending an enable signal to the sampling unit 5321 to control the sampling unit 5321 to obtain the first clock signal CLK 0 Sampling 5000 output signals obtained by a signal S to be detected; thereafter, the evaluation control unit 5323 may send a second phase adjustment indication to the phase adjustment unit 520, and after the phase adjustment unit 520 receives the second phase adjustment indication, the first clock signal CLK from the clock generation unit 510 may be validated by controlling the 3 delay units in the phase shifter 524 to be valid 0 Is delayed to 3 deg., a second clock signal with a phase of 3 deg. is obtained; then, the control sheet is evaluatedThe unit 5322 may further send an enable signal to the sampling unit 5321, control the sampling unit 5321 to sample the output signal of the flip-flop 531 in 5000 time periods when the level 1 of the signal to be measured comes, obtain 5000 output signals obtained by sampling the signal to be measured S using the second clock signal with the phase of 3 °, then send the second phase adjustment instruction to the phase adjustment unit 520, and repeat this until 5000 output signals corresponding to the second clock signal with the phase of 30 ° are obtained.
Further, assuming that the signal S to be measured is level 1, the flip-flop 531 comprises a D flip-flop as illustrated in fig. 5, and the output Q of the D flip-flop operates and the output Q thereof is output
Figure BDA0003151854370000181
If the sampling unit 5321 samples the output signal of the signal S to be measured, the evaluation control unit 5322 obtains 5000 output signals corresponding to each phase, and then theoretically, for each second clock signal, the D flip-flop samples the output signal obtained by sampling the signal S to be measured using the clock rising edge of the second clock signal should be level 1 (i.e., the reference signal is set to be level 1), so if the output signal obtained by sampling by the sampling unit 5321 is not level 1, the output signal is sampled incorrectly, and if the output signal obtained by sampling by the sampling unit 5321 is level 1, the output signal is sampled correctly. Based on this, the evaluation control unit 5322 may obtain output signals output as level 1 from the 5000 output signals after receiving the 5000 output signals corresponding to each second clock signal sent by the sampling unit 5321, and then use the ratio of the number of these output signals to 5000 as the sampling success rate of the phase corresponding to each second clock signal. Then, the evaluation control unit 5322 may obtain the target phase according to various rules according to the sampling success rate corresponding to each phase, for example:
rule one, the target phase is one of the N phases whose sampling success rate is not less than the success rate threshold. In implementation, the evaluation control unit 5322 may sequentially compare each of the N phases with the success rate threshold according to a preset or configured sequence, and once the sampling success rate of a certain phase is found to be not less than the sampling success rate threshold, the phase may be used as a target phase without comparing other phases, so as to save computation resources. Alternatively, the evaluation control unit 5322 may also compare the sampling success rate of the N phases with the success rate threshold to obtain alternative phases in which the sampling success rate is not less than the success rate threshold, and then randomly select one of the alternative phases as the target phase, or select an alternative phase with the largest sampling success rate from the alternative phases as the target phase, and so on. In this case, the target phase is one of N phases.
And according to a second rule, the target phase is obtained according to a phase interval formed by continuous adjacent phases with the sampling success rate not less than the success rate threshold, wherein the adjacent phases refer to adjacent phases in the N phases according to the sequence that the phases are from large to small or from small to large. In implementation, the evaluation control unit 5322 may compare the sampling success rate and the success rate threshold of the N phases to obtain candidate phases, where the sampling success rate is not less than the success rate threshold, and construct a phase interval according to each part of the consecutive adjacent phases in each of the candidate phases, and select a target phase from the constructed phase interval, for example, randomly select a phase from any one of the phase intervals as the target phase to simplify the calculation process, or select a phase located inside the phase interval as much as possible without selecting a phase located at the edge of the phase interval to improve the stability of the target phase, and so on. In this case, the target phase may be one of the N phases, or may be one other than the N phases. By adopting the rule, the phase in the constructed phase interval can meet the requirement of the sampling success rate, so that the phase interval can be considered as an interval with stable sampling success rate, the target phase is selected in the interval, and even if the phase slightly deviates due to the change of the environment, a certain sampling success rate can be ensured as long as the phase does not exceed the range of the phase interval.
Based on the second rule, in a specific implementation, the phase interval may be obtained based on an association relationship between the phase and the sampling success rate, and the association relationship may be in the form of an association relationship diagram, an association relationship table, an association relationship database, an association relationship stack, and the likeAny form of the formula. For example, assuming that the association relationship is characterized in the form of an association relationship graph, fig. 8 exemplarily shows an association relationship diagram of a phase and a sampling success rate provided by an embodiment of the present application, in this example, an abscissa of the association relationship graph is used to represent the phase, and an ordinate of the association relationship graph is used to represent the sampling success rate. As shown in fig. 8, the correlation diagram includes sampling points corresponding to the phase and the sampling success rate of each second clock signal, and the sampling points corresponding to the phase and the sampling success rate may also be connected by a curve. In practice, assuming that the success rate threshold is set to 100% (or may be set to another value, such as 99%, in practice), the evaluation control unit 5322 may draw a reference line L from a position where the ordinate value is 100% 01 Falling on the reference line L 01 The upper sampling point is the sampling point with the sampling success rate not less than 100 percent and falls on the reference line L 01 The lower sampling points belong to sampling points with a sampling success rate of less than 100%. Further, the evaluation control unit 5322 may fall on the reference line L 01 And obtaining sampling points with continuous phases from the upper sampling points, and constructing a phase interval by using each part of sampling points with continuous phases. Further, when there is only one phase interval, the evaluation control unit 5322 may determine the target phase based on the one phase interval; when there are a plurality of phase intervals, the evaluation control unit 5322 may select one phase interval from the plurality of phase intervals at random or according to some rule, and further determine a target phase based on the selected phase interval. Wherein, a rule may be, for example: the selected phase interval is the phase interval with the largest included phase range. For example, in fig. 8, there are two phase zones { U1} and { U2} and the phase zone { U1} is significantly larger than the phase range of the phase zone { U2}, so the evaluation control unit 5322 can determine the target phase based on the phase zone { U1 }. In this way, since the phase section having the largest phase range belongs to the phase region having the best stability, the target phase is selected based on the phase region having the best stability, and even if the target phase is slightly shifted in actual operation, the target phase is shifted to the adjacent phase on the left or right sideThe phase adjacent to the left side or the right side of the phase interval with the maximum phase range can have a better sampling success rate, namely, the phase based on the offset can also ensure better sampling accuracy as much as possible.
Further, assuming that the phase interval { U1} is used to determine the target phase, the target phase may be any one of the following possibilities:
it may be that the target phase is the central phase of the phases contained in the phase interval { U1}, i.e. the central point A of those sampling points falling within the phase interval { U1} 1 The corresponding phase. Wherein the central phase can be obtained by calculating an average phase of the minimum phase and the maximum phase in the phase interval { U1}, the average phase may be one of N phases or one other than N phases, for example, the central sampling point a illustrated in fig. 8 1 The corresponding phase is a phase other than the N phases.
And secondly, the target phase is a phase corresponding to a gravity center point of a phase region, wherein the phase region is constructed according to each phase positioned in the phase interval { U1} and at least two corresponding phases positioned at two sides of the phase interval { U1}, and the two corresponding phases positioned at two sides of the phase interval { U1} have the same sampling success rate or the closest sampling success rate. In practice, the evaluation control unit 5322 may be based on the reference line L 01 Reference line L falling within the phase interval { U1} 01 Two curves at two sides and an abscissa axis construct a closed graph to obtain an area marked with oblique lines, which is illustrated in fig. 8, and the area is a phase area, and then the evaluation control unit 5322 can find the center of gravity a of the area 2 Centering on the point A 2 The corresponding phase is taken as the target phase.
Probably three, the target phase is the central phase of the two corresponding phases located on either side of the phase interval U1. Wherein, two corresponding phases at two sides of the phase interval { U1} have the same sampling success rate or the closest sampling success rate. For example, assuming that two corresponding phases are obtained based on a sampling success rate of 50%, the evaluation control unit 5322 may first obtain a bit with a vertical coordinate value of 50%A reference line L is led out from the position 02 Then from the reference line L falling within the phase interval { U1} 01 Two curves at two sides are obtained from the reference line L 02 Two intersecting or closest sample points P 1 And P 2 And two sampling points P are taken 1 And P 2 Central point A of 3 The corresponding phase is taken as the target phase.
In the above description, when the sampling environment becomes worse (for example, the temperature rises), the phase interval gradually erodes inward from the edge phase to the most central phase, and the sampling success rate of the eroded phase is lowered, and it is known that the central phase or the center-of-gravity phase of the phase interval belongs to the most stable phase point in the phase interval. In this way, by setting the center phase or the center-of-gravity phase of the phase section as the target phase, the third clock signal obtained based on the target phase can have the optimum environment-coping capability, and the third clock signal does not need to be adjusted even if the environment slightly changes, thereby contributing to improvement of stability in sampling the signal to be measured using the third clock signal. Further, the center phase or the center-of-gravity phase may be a phase other than the N phases, so that when the N phases have the same phase interval, the target phase may have an accuracy at least not smaller than the phase interval, and may even be larger than the phase interval, that is, the target phase obtained according to the above rule may have a better resolution. For example, if N phases are obtained by stepping in units of 1 delay cell and the delay time of one delay cell is 1 °, when the target phase is the center phase of two phases of delay time 1 ° and delay time 4 °, the delay time of the target phase is finally calculated to be 2.5 °, obviously, the resolution of the target phase is 0.5 °, which is significantly higher than the resolution of 1 ° of one delay cell, and the accuracy of the target phase is better.
In addition, it should be noted that, selecting the center phase or the center-of-gravity phase as the target phase is only an optional embodiment, and in actual operation, other phases may also be selected as the target phase, for example, phases corresponding to other characteristic sampling points, or phases close to the center phase or the center-of-gravity phase, and the like, which is not specifically limited in this application.
In one possible implementation, the phase range of the N phases is not less than the phase range of one clock cycle of the first clock signal, and preferably, may be not less than the phase range of two clock cycles of the first clock signal. For example, when the phase range of one clock cycle of the first clock signal is 180 °, the phase range of the N phases may be preset or configured to be 360 °. Thus, by enabling the N phases to cover two clock cycles of the first clock signal, the correspondence diagram can simultaneously contain sampling results in two repeated clock cycles, which not only can avoid the accidental problem of determining the target phase by adopting one clock cycle, but also can consider the critical phase between the two clock cycles, thereby being beneficial to more accurately selecting the target phase.
For example, when the clock adjusting apparatus 500 further has a function of updating the target phase, the evaluation control unit 5322 may further control the sampling unit 5321 and the phase adjusting unit 520 to repeat the above operations at intervals, that is, to obtain an association relationship between N phases and N sampling success rates again, and then compare the newly obtained association relationship with the currently used association relationship. If the difference between the two exceeds the maximum tolerable difference (for example, if the phase difference between the starting points of the phase intervals with the largest phase ranges in the two correlation graphs is greater than the maximum tolerable phase difference, or the phase difference between the ending points of the phase intervals with the largest phase ranges in the two correlation graphs is greater than the maximum tolerable phase difference, or the phase difference between other characteristic points that can characterize the phase position of the phase interval with the largest phase range is greater than the maximum tolerable phase difference), the target phase may be re-determined according to the newly obtained correlation, and a first phase adjustment indication may be generated based on the newly determined target phase, and sent to the phase adjustment unit 520, so as to update the third clock signal to the clock signal suitable for the current signal to be measured. If the difference between the two signals does not exceed the maximum tolerable difference which is preset or configured, the current target phase can be kept, that is, the current third clock signal is continuously used for sampling the current signal to be tested. Therefore, by comparing the intermediate information used in determining the target phase, one step of operation for determining the target phase according to the association relation can be saved under the condition that the target phase does not need to be updated, and the calculation resources are saved.
It should be understood that the above division of the units of the clock adjusting apparatus 500 is only a division of logic functions, and the actual implementation may be wholly or partially integrated into one physical entity, or may be physically separated. For example, in another implementation, the evaluation control unit 5322 may be further divided into an evaluation unit and a control unit, the evaluation unit is configured to complete evaluation operations on the N second clock signals, for example, M output results corresponding to each of the second clock signals sampled by the sampling unit 5321 and M output signals corresponding to the N second clock signals, and the control unit is configured to complete related control operations, for example, the sampling unit may be controlled to obtain M output signals corresponding to each of the second clock signals sampled by the flip-flop, the phase adjustment unit may be controlled to obtain the N second clock signals, and the phase adjustment unit 520 may be controlled to obtain the third clock signal based on the target phase determined by the evaluation unit. Of course, the units of the clock adjusting apparatus 500 may be divided in other ways, and the present application is not limited thereto.
The flip-flop 531 may be an additional device provided to implement the phase adjustment function, or may be a device originally existing in the clock domain. When the device originally exists in the clock domain, the original trigger is utilized, the phase adjusting unit 520 is added to one side of the input end of the trigger, and the sampling control unit 532 is added to one side of the output end of the trigger, so that the clock domain can have the function of accurately sampling the signal to be detected only by slightly adjusting the original circuit structure of the clock domain, and the complexity of circuit design is facilitated to be simplified.
In addition, the clock regulation scheme provided by the application can be popularized to any circuit information system which needs to accurately identify stably-appearing asynchronous signals and eliminate metastable states. For example, in some possible application scenarios, after the clock domain accurately samples the signal to be detected according to the clock adjustment scheme in the present application, an output signal having a certain time interval with the signal to be detected may be generated, or the phase of the clock signal used for sampling the signal to be detected may be adjusted according to a certain period, so that the time difference between the input signal to be detected and the output signal exhibits a certain specific change rule, so as to implement a pulse coding function and the like. It should be understood that all the technical solutions for implementing accurate sampling by using the clock adjustment solution provided in the present application are within the protection scope of the present application, and the present application does not list the technical solutions one by one.
According to the clock adjustment scheme provided by the embodiment of the present application, the present application further provides a lidar including a first circuit and a second circuit located in different clock domains, where the second circuit includes the clock adjustment apparatus described above. The first circuit is used for sending a signal to be detected to the second circuit, and the second circuit can sample the signal to be detected by using the target clock signal regulated by the clock regulation device and execute corresponding control operation according to an output signal obtained by sampling the signal to be detected.
According to the clock adjustment scheme provided by the embodiment of the application, the application also provides a terminal device, which comprises the laser radar introduced in the above content. Examples of some terminal devices include, but are not limited to: smart home devices (such as televisions, floor sweeping robots, smart table lamps, sound systems, smart lighting systems, electrical appliance control systems, home background music, home theater systems, intercom systems, video monitoring and the like), smart transportation devices (such as automobiles, ships, unmanned planes, trains, trucks and the like), smart manufacturing devices (such as robots, industrial devices, smart logistics, smart factories and the like), smart terminals (mobile phones, computers, tablet computers, palmtops, desktops, earphones, sounds, wearable devices, vehicle-mounted devices, virtual reality devices, augmented reality devices and the like).
As used in this specification, the terms "component," "module," "system," and the like are intended to refer to a computer-related entity, either hardware, firmware, a combination of hardware and software, or software in execution. For example, a component may be, but is not limited to being, a process running on a processor, an object, an executable, a thread of execution, a program, and/or a computer. By way of illustration, both an application running on a computing device and the computing device can be a component. One or more components can reside within a process and/or thread of execution and a component may be localized on one computer and/or distributed between two or more computers. In addition, these components can execute from various computer readable media having various data structures stored thereon. The components may communicate by way of local and/or remote processes such as in accordance with a signal having one or more data packets (e.g., data from two components interacting with another component in a local system, distributed system, and/or across a network such as the internet with other systems by way of the signal).
Those of ordinary skill in the art will appreciate that the various illustrative logical blocks and steps (step) described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the technical solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
It can be clearly understood by those skilled in the art that, for convenience and simplicity of description, the specific working processes of the above-described systems, apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one type of logical functional division, and other divisions may be realized in practice, for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.
The functions may be stored in a computer-readable storage medium if they are implemented in the form of software functional units and sold or used as separate products. Based on such understanding, the technical solution of the present application or portions thereof that substantially contribute to the prior art may be embodied in the form of a software product stored in a storage medium and including instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a read-only memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily think of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (15)

1. A clock adjustment apparatus, comprising:
a clock generating unit for generating a first clock signal;
the phase adjusting unit is used for adjusting the phase of the first clock signal from the clock generating unit to obtain N second clock signals, wherein the N second clock signals correspond to N phases, and N is a positive integer greater than or equal to 2;
the phase control unit is used for obtaining the N second clock signals from the phase adjusting unit, sampling a signal to be detected according to a preset rule and the N second clock signals, and sending a first phase adjusting instruction to the phase adjusting unit; the first phase adjustment indication is indicative of a target phase;
the phase adjusting unit is further configured to perform phase adjustment on the first clock signal from the clock generating unit according to the first phase adjustment instruction to obtain a third clock signal, where a phase of the third clock signal is the target phase.
2. The clock adjusting apparatus according to claim 1, wherein the phase control unit comprises a flip-flop and a sampling control unit, a first input terminal of the flip-flop is configured to receive the signal to be measured, a second input terminal of the flip-flop is connected to an output terminal of the phase adjusting unit, an output terminal of the flip-flop is connected to an input terminal of the sampling control unit, and an output terminal of the sampling control unit is connected to an input terminal of the phase adjusting unit;
the flip-flop is configured to sample the signal to be detected by using each second clock signal output by the phase adjustment unit, so as to obtain an output signal corresponding to each second clock signal;
the sampling control unit is configured to: and sending the first phase adjustment instruction to the phase adjustment unit according to the preset rule and the output signals corresponding to the N second clock signals.
3. The clock adjustment apparatus of claim 2, wherein the predetermined rule relates to sampling a correct sampling result;
the sampling control unit includes:
the sampling unit is connected with the output end of the trigger and is used for acquiring M output signals obtained by sampling the signal to be detected for M times under each second clock signal by the trigger, wherein M is a positive integer greater than or equal to 2;
and the evaluation control unit is connected with the phase adjusting unit and used for sending the first phase adjusting instruction to the phase adjusting unit according to the reference signal and the M output signals corresponding to each second clock signal from the sampling unit based on the preset rule, wherein the reference signal is used for indicating the output signals with correct sampling.
4. The clock adjusting apparatus according to claim 3, wherein the evaluation control unit is further configured to:
sending an enable signal to the sampling unit, wherein the enable signal is used for instructing the sampling unit to acquire the output signal of the trigger in an instruction message valid period.
5. The clock adjustment apparatus of claim 3 or 4, wherein the N second clock signals are obtained by N-1 phase adjustments, and in any phase adjustment:
the evaluation control unit is further configured to send a second phase adjustment indication to the phase adjustment unit after the sampling unit is determined to obtain the M output signals corresponding to the current second clock signal;
the phase adjusting unit is further configured to perform phase adjustment on the first clock signal from the clock generating unit according to the second phase adjustment indication to obtain a next second clock signal, where a phase of the next second clock signal is an unadjusted one of the N phases.
6. The clock adjustment apparatus of claim 5, wherein any two adjacent ones of the N phases have the same phase interval in order of phase from large to small or phase from small to large.
7. The clock adjustment apparatus according to any one of claims 3 to 6, wherein the preset rule is used to indicate that the target phase is obtained from a phase interval consisting of consecutive adjacent phases having a sampling index value not less than an index threshold value, the sampling index value of any phase is positively correlated with the number of output signals identical to the reference signal in the M output signals corresponding to the phase, and the adjacent phases are adjacent phases in the N phases in order of increasing phase to decreasing phase or decreasing phase to increasing phase.
8. The clock adjustment apparatus of any of claims 1 to 7, wherein after the phase adjustment unit obtains the third clock signal, the phase control unit is further to:
the target phase is re-determined.
9. The clock adjustment device according to any one of claims 1 to 8, wherein a phase range of a phase section constituted by the N phases is not less than a phase range of one clock cycle of the first clock signal.
10. The clock adjustment device of any one of claims 1 to 9, wherein the phase adjustment unit is a phase locked loop or comprises N delay chains, and any two of the N delay chains comprise a different number of delay units.
11. The clock conditioning apparatus of any of claims 1 to 10, wherein the third clock signal is used to transmit control signals for the transmit module sampling the programmable logic circuit.
12. The clock conditioning apparatus of any of claims 1 to 10, wherein the third clock signal is used for programmable logic to sample a target echo signal of the receive module.
13. Clock conditioning device according to any of claims 1 to 12, characterized in that the signal to be measured comprises a target echo signal and/or a transmit control signal.
14. A lidar comprising first and second circuits located in different clock domains, the second circuit comprising the clock adjustment apparatus of any of claims 1 to 13;
the first circuit is used for sending a signal to be tested to the second circuit.
15. A terminal device, characterized in that it comprises a lidar according to claim 14.
CN202110766477.0A 2021-07-07 2021-07-07 Clock adjusting device, laser radar and terminal equipment Pending CN115598960A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117076372A (en) * 2023-10-12 2023-11-17 北京华峰测控技术股份有限公司 Communication signal receiving interface circuit and communication method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117076372A (en) * 2023-10-12 2023-11-17 北京华峰测控技术股份有限公司 Communication signal receiving interface circuit and communication method
CN117076372B (en) * 2023-10-12 2023-12-26 北京华峰测控技术股份有限公司 Communication signal receiving interface circuit and communication method

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