CN115598413A - Phase synchronization method for voltage and current simulation channels on power distribution terminal product - Google Patents
Phase synchronization method for voltage and current simulation channels on power distribution terminal product Download PDFInfo
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Abstract
A voltage and current simulation channel phase synchronization method on a power distribution terminal product relates to the field of distribution network electric energy calculation. In order to overcome the defects of large error and low precision of the conventional electric energy calculation method, an external voltage signal and an external current signal are respectively input into a voltage transformer and a current transformer to reduce the signal amplitude in proportion, the voltage signal and the current signal with reduced amplitudes are input into a second-order filter network to be filtered and then input into a sampling chip, and sampling is carried out according to a preset sampling frequency to obtain the actual phase difference between the current sampled current signal and the current sampled voltage signal; and performing phase synchronization according to the comparison result of the actual phase difference and the unit phase difference, thereby correcting the phase offset between the voltage signal and the current signal. The method is mainly used for correcting the phase asynchronism caused by the phase deviation during the electric energy calculation of the power distribution terminal product.
Description
Technical Field
The invention relates to the field of distribution network electric energy calculation, in particular to a voltage and current simulation channel phase synchronization method on a distribution terminal product.
Background
In current power distribution terminal products, access of voltage signals and current signals is indispensable, and the voltage signals and the current signals are required to be used for calculating power signals, and further calculating electric energy. For the convenience of calculation, the voltage and current signals need to be firstly subjected to analog-to-digital conversion and converted into digital signals. In an analog-to-digital conversion hardware circuit, due to characteristics of devices such as a voltage transformer, a current transformer, a capacitor inductor in a filter circuit and the like, a voltage current signal generates smaller phase shift compared with an original input voltage current signal before entering a sampling chip, and angles of the voltage current signal generating the phase shift are inconsistent, so that an included angle θ is generated between a voltage channel and a current channel. Because P = UIcos theta and Q = UIsin theta, when voltage and current signals with same frequency and phase are input externally, the value of theta is 0,P which is the maximum UI theoretically, and the value of Q is 0; and because the included angle exists, namely the value of theta is not zero, the value of P becomes small, the value of Q is not 0, and when the power is calculated, errors are inevitably generated due to the included angle, so that the electric energy is not accurately calculated.
Therefore, there is a need for a method of phase synchronization of voltage and current analog channels on a distribution terminal product that reduces errors and makes electrical energy calculations more accurate.
Disclosure of Invention
The invention aims to overcome the defects of large error and low precision of the conventional electric energy calculation method, and provides a voltage and current analog channel phase synchronization method on a power distribution terminal product, which can reduce the error and enable the electric energy calculation to be more accurate.
The invention relates to a phase synchronization method for voltage and current simulation channels on a power distribution terminal product, which comprises the following steps:
s1, inputting an external voltage signal into a voltage transformer, inputting an external current signal into a current transformer, wherein the voltage transformer is used for reducing the signal amplitude of the voltage signal in proportion, and the current transformer is used for reducing the signal amplitude of the current signal in proportion, so that the voltage signal and the current signal meet the voltage requirement of an AD conversion chip interface after a second-order filter network;
s2, inputting the amplitude-reduced voltage signal and current signal into a second-order filter network for filtering, thereby filtering interference and burrs;
s3, inputting the filtered voltage signal and the filtered current signal into a sampling chip, and sampling according to the preset sampling frequency of the sampling chip to obtain the actual phase difference between the current sampled current signal and the current sampled voltage signal;
and S4, determining a unit phase difference according to the preset sampling frequency, and performing phase synchronization according to a comparison result of the actual phase difference and the unit phase difference, so as to correct the phase offset between the voltage signal and the current signal.
Further: in S1, both the voltage signal and the current signal are first analog-to-digital converted into digital signals.
Further: in S2, the sampling chip is controlled by the FPGA chip.
Further: in S4, the phase of the sampled current signal is synchronized to the voltage signal with the sampled voltage signal as a reference, that is, the relationship between the actual phase difference and the unit phase difference includes the following 4 cases:
(1) The current signal leads the voltage signal within 1 unit phase difference;
(2) The current signal leads the voltage signal and is out of 1 unit phase difference and within 2 unit phase differences;
(3) The lagging voltage signal of the current signal is within 1 unit phase difference;
(4) The current signal lags the voltage signal by 1 unit phase difference and by 2 unit phase differences.
Further: in S4, the phase synchronization uses a linear interpolation algorithm, that is, linear interpolation calculation is performed according to current sampling values of two fixed points before and after the synchronization time.
The beneficial effects of the invention are: the invention utilizes the sampling chip to carry out high-frequency uniform sampling on the current signal and the voltage signal and carry out high-precision and high-real-time processing on the sampling data. Aiming at the electric energy metering function on a power distribution terminal product, the invention synchronizes the current sampling value of the phase deviation generated by the hardware circuit to the sampling time of the voltage channel through a linear interpolation algorithm, thereby improving the power calculation precision and further improving the electric energy metering precision. The sampling frequency of 256 points per cycle controlled by the FPGA is very high, and the FPGA can perform very uniform sampling, so that adjacent sampling data are utilized to perform linear interpolation, the error between the result obtained by interpolation and the true value is very small, and the precision required by power calculation is completely met.
Drawings
FIG. 1 is an overall functional block diagram of the present method;
FIG. 2 is a circuit diagram of a filter network;
FIG. 3 is a schematic diagram of the calculation of phase difference;
FIG. 4 is a diagram illustrating the current phase behind the voltage phase by 1 unit phase difference with reference to the voltage;
FIG. 5 is a schematic diagram of a current phase behind a voltage phase by 1 unit phase difference and within 2 unit phase differences with respect to a voltage reference;
FIG. 6 is a schematic diagram of current phase advancing voltage by within 1 unit phase difference with reference to voltage;
FIG. 7 is a schematic diagram of current phase advancing the voltage by 1 unit phase difference and within 2 unit phase differences with reference to the voltage;
FIG. 8 is a data plot comparing data for each current channel to voltage channel after phase synchronization.
Detailed Description
The following are only preferred embodiments of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are also included in the scope of the present invention. The following examples are provided for illustrative purposes only and are not to be construed as limiting the invention, which is to be controlled by the scope of the appended claims. Embodiments of the present invention are described in detail below, and for convenience of describing the present invention and simplifying the description, technical terms used in the description of the present invention should be interpreted broadly, including but not limited to conventional alternatives not mentioned in the present application, including both direct and indirect implementations.
Example 1
The present embodiment is described with reference to fig. 1 to fig. 3, and the present embodiment discloses a method for synchronizing phases of voltage and current analog channels on a power distribution terminal product, which includes the following steps:
s1, firstly, both external voltage signals and current signals are subjected to analog-to-digital conversion to form digital signals, the external voltage signals are input into a voltage transformer, the external current signals are input into a current transformer, the voltage transformer is used for reducing the signal amplitude of the voltage signals in proportion, and the current transformer is used for reducing the signal amplitude of the current signals in proportion, so that the voltage signals and the current signals meet the interface voltage requirements of an AD conversion chip after a second-order filter network; the reduction ratio is determined according to the bearing capacity of the interface voltage of the AD conversion chip after the second-order filter network;
s2, inputting the voltage signal and the current signal after amplitude reduction into a second-order filter network for filtering, so as to filter burrs; the filter circuit of the AD conversion sampling channel is shown in fig. 2, in which,
u, I: analog quantity output by the secondary side of the mutual inductor;
GND: a ground signal;
L2-L5, L15, L29-L31: paster magnetic bead CBG201209U360T;
r33, R10-R16: 0805-2K +/-5% of chip resistor;
c4, C14-C16: a patch capacitor 0805-50V-682K (0805 CG682K 500);
CH1+, CH1-, CH2+, CH2-; the signal output via the filter network.
S3, inputting the filtered voltage signal and the filtered current signal into a sampling chip, and sampling according to the preset sampling frequency of the sampling chip to obtain the actual phase difference between the current sampled current signal and the current sampled voltage signal; the sampling chip is controlled by an FPGA chip; namely, the control of the sampling chip and the processing of the sampling data are finished by the FPGA, and the realization of the algorithm is also realized in the FPGA;
and S4, determining a unit phase difference according to the preset sampling frequency, and performing phase synchronization according to a comparison result of the actual phase difference and the unit phase difference, so as to correct the phase offset between the voltage signal and the current signal. When the power supply frequency is 50Hz, the FPGA controls a sampling chip to convert an analog signal into a digital signal according to the frequency of sampling 256 points per cycle (20 ms), and the analog-to-digital conversion chip adopts an AD7606 BSTZ chip of ADI company in America, so that the time interval between adjacent sampling points is 78.125us (20 ms/256), and the conversion angle is 1.40625 degrees (360 degrees/256).
As shown in fig. 3, after the same-frequency and same-phase voltage and current signals are applied to the external circuit, when the received sampling data of the voltage and current channels are analyzed, respective zero-crossing points (from a negative value to a positive value of a sampling value or from a positive value to a negative value of a sampling value) are found. And then calculating respective zero crossing point time according to an interpolation algorithm, and then calculating time difference and whether the current phase leads the voltage or lags the voltage according to the respective zero crossing point time. As shown in fig. 3, it is found in the sample sequence that the sample value Y (a) at point a is positive, and the sample value Y (b) at point b of the next sample point is negative, and it is considered that a zero-crossing point occurs, and the time at which the zero-crossing point needs to be calculated. From fig. 3, it can be seen that point a and point b are adjacent sampling points, the time difference is 78.125us, and Y (a) and Y (b) are sampling values, and the magnitude is known, so that the time of the zero-crossing point c can be calculated by an interpolation algorithm. Thus, the zero crossing time of the voltage and current channels can be calculated, namely the phase difference between U, I can be calculated.
Example 2
Referring to fig. 4-7 and embodiment 1 to explain this embodiment, in S4, in order to perform power calculation, a voltage signal is specifically selected as a reference, and the phase of a current signal is synchronized to the voltage signal, so that there are 4 possibilities of the phase relationship between the voltage and the current, that is, the current leads the voltage by 1 point and within, the current leads the voltage by 2 points within 1 point, the current lags the voltage by 1 point and within, and the current lags the voltage by 2 points within 1 point. The phase difference between the voltage signal and the current signal can be represented by the deviation of the zero crossing point of a sine wave described by the sampled data. Because the phase shift generated by the voltage and current signals is inconsistent, the voltage may lead the current, and the current may lead the voltage, and the phase difference between the voltage and the current does not exceed 2.8125 degrees (2 points) according to empirical analysis; taking the sampled voltage signal as a reference, synchronizing the phase of the sampled current signal to the voltage signal, that is, the relationship between the actual phase difference and the unit phase difference includes the following 4 cases:
(1) The current signal leads the voltage signal within 1 unit phase difference; namely the phase position of the current lead voltage is 1.40625 degrees and less;
(2) The current signal leads the voltage signal and is out of 1 unit phase difference and within 2 unit phase differences; namely, the phase of the current lead voltage is not more than 1.40625 degrees and is within 2.8125 degrees (2 points);
(3) The lagging voltage signal of the current signal is within 1 unit phase difference; namely the phase position of the current lagging voltage is 1.40625 degrees (1 point) and less;
(4) The lagging voltage signal of the current signal is out of 1 unit phase difference and within 2 unit phase differences; namely the phase position of the current lagging voltage is outside 1.40625 degrees and within 2.8125 degrees (2 points);
since parameters of the mutual inductor, the capacitor, the inductor and other devices in the loop are kept unchanged under the condition that the temperature does not change greatly, the phase difference generated by the parameters is also a fixed value. In order to calculate the fixed phase difference, before each device leaves the factory, the phase difference needs to be measured by a tooling platform.
The method for measuring and calculating the phase difference comprises the following steps:
(1) And applying rated voltage and current values with same frequency and phase to the loop by using a standard tester.
(2) The FPGA controls the AD chip to sample 256 points of each cycle, the sampled discrete data are sent to the FPGA, and the FPGA does not process the data, namely the default phase difference is 0; the sampled data is sent to the CPU as it is.
(3) After receiving the sampling data of the voltage and current channels, the CPU calculates the sequence of the voltage and current signals at the zero crossing point and the time value (delta t) of the phase difference of the zero crossing point according to a zero crossing point detection method, because the sampling is carried out according to 256 points per cycle, each sampling period is 78.125us, the corresponding angle of each sampling period is 360 degrees/256 =1.40625 degrees, and the delta t also represents the phase difference according to the proportion calculation.
(4) After the CPU measures the phase difference (delta t), the value is stored in an EEPROM (electrically erasable programmable read-Only memory) chip of the plate, and the phase difference measuring and calculating process is finished.
(5) The above steps and processes are also referred to as a phase tuning process.
When the device is used, after the device is initially electrified, the FPGA acquires the phase difference (leading or lagging) of current relative to voltage from the EEPROM, and uses the phase difference to carry out phase synchronization according to an interpolation synchronization algorithm.
Example 3
In S4, the phase synchronization adopts a linear interpolation algorithm, that is, linear interpolation is performed according to current sampling values of two fixed points before and after the calculation time. In the phase synchronization process, an algorithm of linear interpolation between two points is adopted, namely sampling values of voltage and current are recorded at sampling points at fixed intervals, but the voltage value at the moment is involved in the calculation when the algorithm is used for calculating power, the current value at the moment is not involved in the calculation, and the current values involved in the calculation are calculated by linear interpolation from the current sampling values of two fixed points before and after the calculation moment. Namely, two sampling points on two sides of the current channel at the time needing interpolation are found, and the two points are utilized to carry out interpolation calculation.
In fig. 4 to 7, the vertical axis Y represents the magnitude of the voltage current, and the horizontal axis is the time axis. And taking the voltage U at the moment a as a reference, and synchronizing the current channels to the moment a. a. b, c, d and e represent fixed-frequency sampling points, and Y (a), Y (b), Y (c), Y (d) and Y (e) represent sampling values at corresponding moments; i represents the calculation time when the current channel needs to be interpolated, and Y (i) is the interpolation calculation value at the corresponding time. Δ t represents a time representation of the phase difference between U and I.
FIG. 4 is referenced to voltage U, with I being later than the voltage, but differing by less than 1.40625.
Fig. 5 is referenced to voltage U, I is later than voltage, but differs by more than 1.40625 °, less than 2 x 1.40625 °.
FIG. 6 is referenced to voltage U, with I phase advanced from the voltage, but less than 1.40625.
Fig. 7 is referenced to voltage U, I is in phase advance of the voltage, but differs by more than 1.40625 °, but less than 2 x 1.40625 °.
4-7, the interpolation calculation method in each case will be described below.
(1) Since the current phase lags behind the voltage phase, it can be seen that at the time a, the sampling value Ua of the voltage is greater than the sampling value Ia of the current, and therefore, to obtain a current value corresponding to the current at the time a, a future point b of the current needs to be used for interpolation calculation; meanwhile, as the phase difference is delta t, the difference between tb and ta is 78.125us; and the current sampling values at the moments a and b are obtained by linear interpolation to obtain y (i), and the obtained y (i) corresponds to the current value of the voltage a point, namely the y (i) is synchronous with the moment Ua. At this time, the actual sampling time point has already reached the point b, so that the synchronized y (i) is 1 sampling interval later than the actual sampling time point.
(2) Because the current I is 1 sampling point later than the voltage U, the current value corresponding to the U at the moment a needs to be calculated by using two points in the future, namely two points b and c; since the phase difference between the voltage and the current is Δ t, which is greater than 78.125us, it is necessary to calculate the interpolation data y (i) at time i using two points b and c and y (b), y (c), and Δ t when data synchronization is performed on the current channels. At this time, the actual sampling time point has already reached point c, so that the synchronized y (i) is 2 sampling intervals later than the actual sampling time point.
(3) With the voltage U as the reference, I is phase advanced from the voltage, but differs by less than 1.40625 °. In this case, the sampling time a of the voltage is still used as a reference, because the current leads the voltage, and to calculate the current value corresponding to the voltage at the time a, an interpolation calculation should be performed by using the current sampling point d after the point a, that is, the interpolation data y (i) of the current channel at i is calculated by using the sampling values of the current channel at the points a and d and Δ t. At this time, the actual sampling time point has already reached point a, so that the synchronized y (i) is synchronized with the actual sampling time point.
(4) With reference to voltage U, I is phase advanced from the voltage, but differs by more than 1.40625 ° but less than 2 x 1.40625 °. In this case, the sampling time a of the voltage is still used as a reference, because the current leads the voltage, and the current value corresponding to the voltage at the time a is calculated, because Δ t is greater than one sampling interval, the current sampling points d and e after the point a should be used for interpolation calculation, that is, the sampling values of the current channel at the points e and d and Δ t are used for calculating the interpolation data y (i) of the current channel at the point i. At this time, the actual sampling time point has already reached point a, so that the synchronized y (i) is synchronized with the actual sampling time point.
Simulation verification:
in the simulation diagram of fig. 8, a0_ out, a1_ out, a2_ out, a3_ out, and a4_ out represent the sampled data inputs of the different channels, and have a peak value of 32767; wherein a1_ out is voltage channel data and is also a synchronous reference, and the others are current channels;
a0_ out =32767sinwt; current path 1, hysteresis voltage 0.5 °.
a1_ out =32767sin (wt +0.5 °); voltage channel, synchronous reference.
a2_ out =32767sin (wt +1 °); current path 2, leading voltage 0.5 °.
a3_ out =32767sin (wt +2 °); current path 3, leading voltage by 1.5 °.
a4_ out =32767sin (wt-1 °); current path 4, hysteresis voltage 1.5 °.
a0_ data, a1_ data, a2_ data, a3_ data and a4_ data are respectively output data after interpolation of corresponding current and voltage channels. As can be seen from fig. 8, after the 5 th sampling point is completely acquired, the interpolation operation is started, and the result of the interpolation operation is output (data _ done high pulse) after the next ad sampling is started, so that the interpolated data is also output at fixed intervals.
From the simulation, it can be seen that, at the amplitude of 32767, the sampled values of the current path and the voltage path (a 1_ out) are still relatively different before phase synchronization, the maximum value is 848, and it can be seen that due to the phase difference, some sampled values are larger than those of the voltage path and some sampled values are smaller than those of the voltage path. After the phase synchronization adjustment, the sampling value of each current channel is the same as the voltage channel (a 1_ data) or has a difference of 1 value, so that the power calculation by using the synchronized sampling data can greatly improve the calculation accuracy of power and energy.
Claims (5)
1. A method for synchronizing the phases of voltage and current analog channels on a power distribution terminal product is characterized by comprising the following steps:
s1, inputting an external voltage signal into a voltage transformer, inputting an external current signal into a current transformer, wherein the voltage transformer is used for reducing the signal amplitude of the voltage signal in proportion, and the current transformer is used for reducing the signal amplitude of the current signal in proportion, so that the voltage signal and the current signal meet the voltage requirement of an AD conversion chip interface after a second-order filter network;
s2, inputting the amplitude-reduced voltage signal and current signal into a second-order filter network for filtering, so as to filter interference and burrs;
s3, inputting the filtered voltage signal and the filtered current signal into a sampling chip, and sampling according to a preset sampling frequency of the sampling chip to obtain an actual phase difference between the current sampled current signal and the current sampled voltage signal;
and S4, determining a unit phase difference according to the preset sampling frequency, and performing phase synchronization according to a comparison result of the actual phase difference and the unit phase difference, so as to correct the phase offset between the voltage signal and the current signal.
2. The method of claim 1, wherein in S1, the voltage signal and the current signal are both first analog-to-digital converted into digital signals.
3. The method of claim 1, wherein in S2 the sampling chip is controlled by an FPGA chip.
4. The method of claim 1, wherein in S4, the sampled voltage signal is used as a reference to synchronize the phase of the sampled current signal to the voltage signal, i.e. the relationship between the actual phase difference and the unit phase difference includes 4 cases as follows:
(1) The current signal leads the voltage signal within 1 unit phase difference;
(2) The current signal leads the voltage signal and is out of 1 unit phase difference and within 2 unit phase differences;
(3) The lagging voltage signal of the current signal is within 1 unit phase difference;
(4) The current signal lagging voltage signal is outside 1 unit phase difference and within 2 unit phase differences.
5. The method of claim 1, wherein in step S4, the phase synchronization is performed by a linear interpolation algorithm, that is, a linear interpolation calculation is performed according to the current sampling values of two fixed points before and after the synchronization time.
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| CN111458564A (en) * | 2020-04-14 | 2020-07-28 | 深圳蓄能发电有限公司 | Method and device for synchronizing secondary sampling values of different types of current transformers of generator set |
| CN217639341U (en) * | 2022-05-10 | 2022-10-21 | 黑龙江坤正科技有限公司 | Synchronous signal source display phase device |
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| CN1992501A (en) * | 2005-12-30 | 2007-07-04 | 中国科学院电工研究所 | Grid-Connected Power inverter and control method of output current |
| CN110244116A (en) * | 2018-03-19 | 2019-09-17 | 深圳市航智精密电子有限公司 | The metering circuit of direct current instantaneous power and its plesiochronous calculation method |
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Application publication date: 20230113 |