CN115589729A - Preparation method of embedded flash memory device - Google Patents

Abstract

The invention provides a preparation method of an embedded flash memory device, which comprises the following steps: providing a substrate comprising a storage region and a peripheral logic region, wherein a gate oxide layer, a floating gate, an ONO dielectric layer, a control gate and a first silicon nitride layer are formed on the substrate; in the process of preparing some film layers in the storage region, the floating gate of the peripheral logic region has smile effect; forming a second silicon nitride layer and a photoresist layer; removing the photoresist layer on the peripheral logic area; removing the second silicon nitride layer, the first silicon nitride layer, the control gate, the ONO dielectric layer and the floating gate on the peripheral logic region, wherein floating gate polycrystalline silicon materials are remained in the gate oxide layer on the STI side of the peripheral logic region; removing the residual photoresist layer on the peripheral logic area; a rapid thermal oxidation process is performed. The floating gate polycrystalline silicon residue and the gate oxide layer are integrated by adopting a rapid thermal oxidation process, the floating gate polycrystalline silicon residue is eliminated, and the situation that the floating gate polycrystalline silicon residue is peeled off after the subsequent wet acid tank operation is avoided.

Description

Method for preparing embedded flash memory device

Technical Field

The application relates to the technical field of semiconductor manufacturing, in particular to a preparation method of an embedded flash memory device.

Background

In the manufacturing process of the embedded flash memory device, in the process of forming the selective gate oxide layer on the surface of the selective gate of the storage region by a thermal oxidation process, the situation that the floating gate close to the shallow trench isolation structure in the peripheral logic region is oxidized into the gate oxide layer often inevitably occurs, so that the phenomenon that the thickness of the floating gate close to the shallow trench isolation structure is thinned and the gate oxide layer is thickened is caused, and the phenomenon is called smiling effect (smiling effect).

However, after the etching process for removing the floating gate in the peripheral logic region, due to the characteristics of the etching process, the floating gate is generally etched vertically downwards, and floating gate polysilicon residue is easily generated in the gate oxide layers on both sides of the shallow trench isolation structure. Furthermore, after the subsequent wet acid tank operation, the peripheral gate oxide layer part or the peripheral gate oxide layer part is completely etched to form floating gate polysilicon residue to be peeled off, and the dropped floating gate polysilicon residue may scratch the surface of the device, thereby affecting the performance of the embedded flash memory device.

Disclosure of Invention

The application provides a preparation method of an embedded flash memory device, which can solve at least one of the problems that floating gate polysilicon material residue generated by smile effect in a peripheral logic area cannot be etched and removed, floating gate polysilicon material residue falls after acid washing and scratches the device and the like.

In one aspect, an embodiment of the present application provides a method for manufacturing an embedded flash memory device, including:

providing a substrate, wherein the substrate comprises a storage area and a peripheral logic area, a plurality of shallow trench isolation structures are formed in the substrate, and a stacked gate oxide layer, a floating gate, an ONO dielectric layer, a control gate and a first silicon nitride layer are formed on the substrate;

sequentially forming a first side wall structure, a second side wall structure, a tunneling oxide layer, a selection gate and a selection gate oxide layer on the storage region, wherein the first side wall structure is positioned in the first silicon nitride layer; the second side wall structure is positioned in the control gate and the ONO dielectric layer and covers partial side face of the first side wall structure; the tunneling oxide layer is positioned in the floating gate and the gate oxide layer and covers the second side wall structure and the rest side face of the first side wall structure, and the tunneling oxide layer is U-shaped; the selection gate fills a U-shaped space formed by the inner side of the tunneling oxide layer; the selection gate oxide layer covers the surface of the selection gate; at this time, smiling effect occurs on the floating gates on two sides of the shallow trench isolation structure in the peripheral logic area;

sequentially forming a second silicon nitride layer and a photoresist layer on the surface of the selection gate oxide layer on the storage region and the surface of the first silicon nitride layer on the peripheral logic region;

removing the photoresist layer on the peripheral logic area;

removing the second silicon nitride layer, the first silicon nitride layer, the control gate, the ONO dielectric layer and the floating gate on the peripheral logic region, wherein the polycrystalline silicon material of the floating gate is remained in the gate oxide layers on two sides of the shallow trench isolation structure on the peripheral logic region;

removing the residual photoresist layer on the peripheral logic area by adopting an ashing process;

performing a wet cleaning process on the shallow trench isolation structure and the gate oxide layer on the peripheral logic area;

and performing a rapid thermal oxidation process to integrate the polysilicon material and the gate oxide layer.

Optionally, in the preparation method of the embedded flash memory device, the process parameters of the rapid thermal oxidation process include: the oxidation temperature is 600-800 ℃; the oxidation time is 5min to 10min; the oxygen flow is 5 SLM-7 SLM.

Optionally, in the preparation method of the embedded flash memory device, in the process of performing a rapid thermal oxidation process to integrate the polysilicon material and the gate oxide, the oxidation temperature is 800 ℃; the oxidation time is 10min; the oxygen flow was 6SLM.

Optionally, in the method for manufacturing an embedded flash memory device, the ONO dielectric layer sequentially includes, from top to bottom: a top silicon oxide layer, a middle silicon nitride layer, and a bottom silicon oxide layer.

Optionally, in the method for manufacturing an embedded flash memory device, the step of removing the second silicon nitride layer, the first silicon nitride layer, the control gate, the ONO dielectric layer, and the floating gate on the peripheral logic region includes:

etching the second silicon nitride layer, the first silicon nitride layer, the control gate and the top silicon oxide layer on the peripheral logic region by adopting a dry etching process;

etching the middle silicon nitride layer on the peripheral logic area by adopting a wet etching process;

and etching the bottom silicon oxide layer and the floating gate on the peripheral logic region by adopting a dry etching process.

Optionally, in the preparation method of the embedded flash memory device, the step of forming the first sidewall structure, the second sidewall structure, the tunneling oxide layer, the select gate, and the select gate oxide layer in the storage region includes:

etching the first silicon nitride layer of the storage region to form a first groove;

forming a first side wall structure in the first groove, wherein the first side wall structure covers the side wall of the first groove;

etching the control gate and the ONO dielectric layer on the bottom wall of the first groove to form a second groove;

forming a second side wall structure in the second groove, wherein the second side wall structure covers part of the side wall of the second groove;

etching the floating gate and the gate oxide layer on the bottom wall of the second groove to form a third groove;

forming a tunneling oxide layer, wherein the tunneling oxide layer covers the bottom wall and the side wall of the third groove;

forming a selection gate, wherein the selection gate fills the third groove; and the number of the first and second groups,

and forming a selection gate oxide layer which covers the selection gate.

Optionally, in the preparation method of the embedded flash memory device, after performing a rapid thermal oxidation process to fuse the polysilicon material and the gate oxide layer into a whole, the preparation method of the embedded flash memory device further includes:

and removing the gate oxide layer on the upper surface of the shallow trench isolation structure of the peripheral logic area and the surface of the substrate.

Optionally, in the preparation method of the embedded flash memory device, after performing a rapid thermal oxidation process to integrate the polysilicon material and the gate oxide layer, the preparation method of the embedded flash memory device further includes:

and performing an active region ion implantation process on the substrate of the storage region.

The technical scheme at least comprises the following advantages:

after the photoresist layer which is remained on the peripheral logic area is removed, the polysilicon material and the gate oxide layer are integrated by adopting a rapid thermal oxidation process, the purpose of eliminating the polysilicon material residue of the floating gate is achieved, the condition that the floating gate polysilicon residue is peeled off after the subsequent wet acid tank operation is avoided, the condition that the peeled floating gate polysilicon residue scratches the surface of a device is avoided, and the device yield is improved.

Drawings

In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.

Fig. 1 is a flowchart of a method of manufacturing an embedded flash memory device according to an embodiment of the present invention;

FIGS. 2-5 are schematic views of semiconductor structures in various process steps for fabricating an embedded flash memory device according to an embodiment of the present invention;

wherein the reference numerals are as follows:

a-memory area, B-peripheral logic area;

100-substrate, 101-shallow trench isolation structure, 110-gate oxide layer, 120-floating gate, 121-polysilicon material/floating gate polysilicon residue, 130-ONO dielectric layer, 140-control gate, 150-first silicon nitride layer, 160-first side wall structure, 170-second side wall structure, 180-tunneling oxide layer, 190-selection gate, 200-second silicon nitride layer, 210-photoresist layer and 300-selection gate oxide layer.

Detailed Description

The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on orientations or positional relationships shown in the drawings, and are only for convenience of description and simplification of description, but do not indicate or imply that the device or element referred to must have a particular orientation, be constructed in a particular orientation, and operate, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in this application will be understood to be a specific case for those of ordinary skill in the art.

In addition, the technical features mentioned in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

An embodiment of the present application provides a method for manufacturing an embedded flash memory device, and referring to fig. 1, fig. 1 is a flowchart of a method for manufacturing an embedded flash memory device according to an embodiment of the present invention, where the method for manufacturing an embedded flash memory device includes:

step S10: as shown in fig. 2, a substrate 100 is provided, the substrate 100 includes a storage region a and a peripheral logic region B, a plurality of shallow trench isolation Structures (STI) 101 are formed in the substrate 100 of the storage region a and the peripheral logic region B, fig. 1 shows only one shallow trench isolation structure 101 in the substrate 100 of the peripheral logic region B, the shallow trench isolation structure 101 in the storage region a is not shown, and a stacked gate oxide layer 110, a floating gate 120, an ONO dielectric layer 130, a control gate 140, and a first silicon nitride layer 150 are formed on the substrate 100.

Step S20: as shown in fig. 2, a first sidewall structure 160, a second sidewall structure 170, a tunneling oxide layer 180, a select gate 190, and a select gate oxide layer 300 are sequentially formed on the storage region a, wherein the first sidewall structure 160 is located in the first silicon nitride layer 150; the second sidewall structure 170 is located in the control gate 140 and the ONO dielectric layer 130 and covers a portion of the side surface of the first sidewall structure 160; the tunneling oxide layer 180 is located in the floating gate 120 and the gate oxide layer 110 and covers the second sidewall structure 170 and the remaining side of the first sidewall structure 160, and the tunneling oxide layer 180 is U-shaped; the selection gate 190 fills a U-shaped space formed inside the tunneling oxide layer 180; the select gate oxide 300 covers the surface of the select gate 190.

In this embodiment, the step of forming the first sidewall structure 160, the second sidewall structure 170, the tunneling oxide layer 180, the select gate 190, and the select gate oxide layer 300 on the storage area a may specifically include:

etching the first silicon nitride layer 150 of the storage region a to form a first trench;

forming a first sidewall structure 160 in the first trench, the first sidewall structure 160 covering sidewalls of the first trench;

etching the control gate 140 and the ONO dielectric layer 130 on the bottom wall of the first trench to form a second trench;

forming a second sidewall structure 170 in the second trench, wherein the second sidewall structure 170 covers a part of the sidewall of the second trench;

etching the floating gate 120 and the gate oxide layer 110 on the bottom wall of the second trench to form a third trench;

forming a tunneling oxide layer 180, wherein the tunneling oxide layer 180 covers the bottom wall and the side wall of the third trench;

forming a selection gate 190, wherein the selection gate 190 fills the third trench; and the number of the first and second groups,

forming a selection gate oxide layer 300, wherein the selection gate oxide layer 300 covers the selection gate 190.

As shown in fig. 3, in the process of forming the selection gate oxide layer 300, the present embodiment adopts a thermal oxidation process to oxidize the polysilicon on the surface of the selection gate 190 into a layer of the selection gate oxide layer 300, and at the same time of forming the selection gate oxide layer 300 by thermal oxidation, the floating gates 120 on both sides of the shallow trench isolation structure 101 in the peripheral logic region B have a smiling effect, that is, the floating gate 120 in the peripheral logic region B close to the shallow trench isolation structure 101 is oxidized into the gate oxide layer 110, and the thickness of the floating gate 120 close to the shallow trench isolation structure 101 is thinner and the gate oxide layer 110 is thicker.

Further, the ONO dielectric layer 130 sequentially includes, from top to bottom: a top silicon oxide layer, a middle silicon nitride layer, and a bottom silicon oxide layer.

Step S30: sequentially forming a second silicon nitride layer 200 and a photoresist layer 210 on the surface of the selection gate oxide layer 300 on the storage area A and the surface of the first silicon nitride layer 150 on the peripheral logic area B;

step S40: the photoresist layer 210 is exposed to expose the photoresist layer 210 on the peripheral logic region B, that is, the region where the peripheral logic region B is located is opened.

Step S50: as shown in fig. 4, the second silicon nitride layer 200, the first silicon nitride layer 150, the control gate 140, the ONO dielectric layer 130 and the floating gate 120 in the peripheral logic region B are removed, and at this time, the polysilicon material 121 of the floating gate 120 remains in the gate oxide layer 110 on both sides of the shallow trench isolation structure 101 in the peripheral logic region B.

The step of removing the second silicon nitride layer, the first silicon nitride layer, the control gate, the ONO dielectric layer, and the floating gate on the peripheral logic region may specifically include:

etching the second silicon nitride layer 200, the first silicon nitride layer 150, the control gate 140 and the top silicon oxide layer in the ONO dielectric layer 130 on the peripheral logic region B by adopting a dry etching process;

etching the middle silicon nitride layer in the ONO dielectric layer 130 on the peripheral logic region B by adopting a wet etching process;

and etching the bottom silicon oxide layer in the ONO dielectric layer 130 and the floating gate 120 on the peripheral logic region by adopting a dry etching process.

It is noted that in step S50, since the plurality of film layers on the upper surface of the shallow trench isolation structure 101 are thin, the gate oxide layer 110 on the upper surface of the shallow trench isolation structure 101 is also substantially removed by etching during the process of etching the floating gate 120. The gate oxide layer 110 with a certain thickness is still remained on both sides of the shallow trench isolation structure 101 and on the surface of the substrate 100, and due to the characteristics of the dry etching process, the polysilicon material 121 of the floating gate 120 is certainly remained in the gate oxide layer 110 on both sides of the shallow trench isolation structure 101.

Step S60: and removing the residual photoresist layer 210 on the peripheral logic region B by using an ashing process. Specifically, oxygen with a certain flow rate can be introduced to participate in the ashing process, and the oxygen introduction time is not more than 30s, for example, the oxygen introduction time is 30s.

Step S70: and performing a wet cleaning process on the shallow trench isolation structure 101 and the gate oxide layer 110 on the peripheral logic region B to completely remove the residual photoresist layer 210 on the peripheral logic region B.

Step S80: as shown in fig. 5, a rapid thermal oxidation process is performed to fuse the polysilicon material 121 and the gate oxide layer 110 into a whole, and at this time, the polysilicon material 120 and the gate oxide layer 110 on both sides of the shallow trench isolation structure 110 are fused into a whole with the shallow trench isolation structure 101. The material of the polysilicon material 120, the gate oxide layer 110 and the shallow trench isolation structure 101 after thermal oxidation is silicon dioxide. Specifically, the process parameters of the rapid thermal oxidation process include: the oxidation temperature is 600-800 ℃; the oxidation time is 5min to 10min; the oxygen flow is 5 SLM-7 SLM.

Preferably, during the rapid thermal oxidation process to integrate the polysilicon material 121 and the gate oxide layer 110, the oxidation temperature is 800 ℃; the oxidation time is 10min; the oxygen flow was 6SLM.

Further, after performing a rapid thermal oxidation process to integrate the polysilicon material 120 with the gate oxide layer 110, the method for manufacturing the embedded flash memory device may further include: and removing the gate oxide layer on the upper surface of the shallow trench isolation structure 110 and the surface of the substrate 100 in the peripheral logic region B by adopting a wet cleaning process. At this time, the gate oxide layer 110 and the oxidized polysilicon material 120 with partial thickness are remained on both sides of the shallow trench isolation structure 110, and the gate oxide layer 110 and the oxidized polysilicon material 120 with partial thickness become a part of the shallow trench isolation structure 110.

In the application, after the photoresist layer 210 remaining on the peripheral logic region B is removed, the polysilicon material 121 and the gate oxide layer 110 are integrated by using a rapid thermal oxidation process, so that the purpose of eliminating the polysilicon material 121 remaining on the floating gate is achieved, meanwhile, the situation that the floating gate polysilicon residue 121 is peeled off after a wet acid tank operation (wet cleaning process) is avoided, the situation that the peeled floating gate polysilicon residue 121 scratches the surface of a device is avoided, and the device yield is improved.

In this embodiment, after performing a rapid thermal oxidation process to integrate the polysilicon material and the gate oxide layer, the method for manufacturing the embedded flash memory device may further include: and protecting the peripheral logic area B by taking the photoresist as a mask, and executing an active area ion implantation process on the substrate of the storage area A.

It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of the invention are intended to be covered by the present invention.

Claims (8)

1. A method for manufacturing an embedded flash memory device, comprising:

providing a substrate, wherein the substrate comprises a storage area and a peripheral logic area, a plurality of shallow trench isolation structures are formed in the substrate, and a stacked gate oxide layer, a floating gate, an ONO dielectric layer, a control gate and a first silicon nitride layer are formed on the substrate;

sequentially forming a first side wall structure, a second side wall structure, a tunneling oxide layer, a selection gate and a selection gate oxide layer on the storage region, wherein the first side wall structure is positioned in the first silicon nitride layer; the second side wall structure is positioned in the control gate and the ONO dielectric layer and covers partial side face of the first side wall structure; the tunneling oxide layer is positioned in the floating gate and the gate oxide layer and covers the remaining side faces of the second side wall structure and the first side wall structure, and the tunneling oxide layer is U-shaped; the selection gate fills a U-shaped space formed by the inner side of the tunneling oxide layer; the selection gate oxide layer covers the surface of the selection gate; at this time, smiling effect occurs on the floating gates on two sides of the shallow trench isolation structure in the peripheral logic area;

sequentially forming a second silicon nitride layer and a photoresist layer on the surface of the selection gate oxide layer on the storage region and the surface of the first silicon nitride layer on the peripheral logic region;

removing the photoresist layer on the peripheral logic area;

removing the second silicon nitride layer, the first silicon nitride layer, the control gate, the ONO dielectric layer and the floating gate on the peripheral logic region, wherein the polycrystalline silicon material of the floating gate is remained in the gate oxide layers on two sides of the shallow trench isolation structure on the peripheral logic region;

removing the residual photoresist layer on the peripheral logic area by adopting an ashing process;

performing a wet cleaning process on the shallow trench isolation structure and the gate oxide layer on the peripheral logic area;

a rapid thermal oxidation process is performed to fuse the polysilicon material and the gate oxide layer together.

2. The method of claim 1, wherein the process parameters of the rapid thermal oxidation process comprise: the oxidation temperature is 600-800 ℃; the oxidation time is 5min to 10min; the oxygen flow is 5 SLM-7 SLM.

3. The method of claim 2, wherein an oxidation temperature is 800 ℃ during the rapid thermal oxidation process to integrate the polysilicon material and the gate oxide; the oxidation time is 10min; the oxygen flow was 6SLM.

4. The method of claim 1, wherein the ONO dielectric layer comprises, in order from top to bottom: a top silicon oxide layer, a middle silicon nitride layer, and a bottom silicon oxide layer.

5. The method of claim 4, wherein the step of removing the second silicon nitride layer, the first silicon nitride layer, the control gate, the ONO dielectric layer, and the floating gate on the peripheral logic region comprises:

etching the second silicon nitride layer, the first silicon nitride layer, the control gate and the top silicon oxide layer on the peripheral logic region by adopting a dry etching process;

etching the middle silicon nitride layer on the peripheral logic area by adopting a wet etching process;

and etching the bottom silicon oxide layer and the floating gate on the peripheral logic region by adopting a dry etching process.

6. The method of claim 1, wherein the step of forming the first sidewall structure, the second sidewall structure, the tunneling oxide layer, the select gate, and the select gate oxide layer in the storage region comprises:

etching the first silicon nitride layer of the storage region to form a first groove;

forming a first side wall structure in the first groove, wherein the first side wall structure covers the side wall of the first groove;

etching the control gate and the ONO dielectric layer on the bottom wall of the first groove to form a second groove;

forming a second side wall structure in the second groove, wherein the second side wall structure covers partial side walls of the second groove;

etching the floating gate and the gate oxide layer on the bottom wall of the second groove to form a third groove;

forming a tunneling oxide layer, wherein the tunneling oxide layer covers the bottom wall and the side wall of the third groove;

forming a selection gate, wherein the selection gate fills the third groove; and (c) a second step of,

and forming a selection gate oxide layer which covers the selection gate.

7. The method of manufacturing an embedded flash memory device according to claim 1, wherein after performing a rapid thermal oxidation process to integrate the polysilicon material with the gate oxide layer, the method further comprises:

and removing the gate oxide layer on the upper surface of the shallow trench isolation structure of the peripheral logic area and the surface of the substrate.

8. The method of claim 1, wherein after performing a rapid thermal oxidation process to integrate the polysilicon material with the gate oxide layer, the method further comprises:

and performing an active region ion implantation process on the substrate of the storage region.

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