CN115589722A - Vertical grid transistor structure and preparation method thereof - Google Patents
Vertical grid transistor structure and preparation method thereof Download PDFInfo
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- CN115589722A CN115589722A CN202211246221.8A CN202211246221A CN115589722A CN 115589722 A CN115589722 A CN 115589722A CN 202211246221 A CN202211246221 A CN 202211246221A CN 115589722 A CN115589722 A CN 115589722A
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Abstract
The invention provides a vertical grid transistor structure and a preparation method thereof, wherein the vertical grid transistor structure comprises: the substrate comprises a plurality of vertical grid type transistors which are arranged in an array, the vertical grid type transistors are separated by a plurality of first isolation structures in the Y direction, are separated by a plurality of fifth isolation structures in the X direction, and are connected with corresponding second isolation structures in the Z direction; the word lines extend along the Y direction and are arranged in parallel in the X direction, a third isolation structure is arranged between every two adjacent word lines, the two adjacent word lines and the corresponding second isolation structure are isolated through a fourth isolation structure, and a second distance is reserved between the two adjacent word lines and the surface of the substrate, wherein the X direction, the Y direction and the Z direction are perpendicular to each other. According to the invention, the isolation structure is embedded between adjacent word lines, so that the complete separation of the word lines in the vertical grid transistor structure is ensured, and the isolation reliability is improved.
Description
Technical Field
The invention relates to the field of semiconductors, in particular to a vertical gate transistor structure and a preparation method thereof.
Background
In the semiconductor field, in order to realize higher memory density, as many transistors as possible need to be formed per unit area. The traditional method for reducing the size is close to the physical limit, and in a novel vertical grid transistor structure, a source electrode and a drain electrode can be respectively arranged at the upper end and the lower end, so that the area of the transistor can be reduced.
However, in this structure, there is a word separation process, and since the connection position of the two word lines is deep in the trench, it is difficult to completely separate the word lines on both sides. When the self-separation process is performed, leakage current can be caused only when two word lines at one position are not completely separated along the direction of the groove, and the yield of products is lost.
Therefore, how to ensure the complete separation of the word lines and improve the isolation reliability becomes a technical problem to be solved urgently.
Disclosure of Invention
The invention provides a vertical grid transistor structure and a preparation method thereof, which are used for ensuring the complete separation of word lines and improving the isolation reliability.
In order to solve the above problems, the present invention provides a method for manufacturing a vertical gate transistor structure, including: providing a substrate, wherein the substrate comprises a plurality of active regions arranged in an array, the active regions are separated by a plurality of first isolation structures in a Y direction and are separated by a plurality of grooves in an X direction, and the X direction is perpendicular to the Y direction; forming a second isolation structure at the bottom of each groove; forming a grid electrode oxidation layer on the side wall of each groove, wherein the grid electrode oxidation layer is connected with the second isolation structure; forming a sacrificial layer on the side wall and the bottom of each groove, wherein the sacrificial layer at least covers the second isolation structure and the gate oxide layer; filling an isolation material in each groove and flattening to form a third isolation structure; and removing part of the sacrificial layer, depositing a conductive material and processing to form two mutually insulated word lines in each groove, wherein the remained sacrificial layer is used as a fourth isolation structure to enable the two word lines to have a first distance from the second isolation structure, and the two word lines have a second distance from the surface of the substrate.
The present invention also provides a vertical gate transistor structure comprising: the substrate comprises a plurality of vertical grid type transistors which are arranged in an array, the vertical grid type transistors are separated by a plurality of first isolation structures in the Y direction, are separated by a plurality of fifth isolation structures in the X direction, and are connected with corresponding second isolation structures in the Z direction; the word lines extend along the Y direction and are arranged in parallel in the X direction, a third isolation structure is arranged between every two adjacent word lines, the two adjacent word lines and the corresponding second isolation structures are isolated through a fourth isolation structure, and a second distance is reserved between the two adjacent word lines and the surface of the substrate, wherein the X direction, the Y direction and the Z direction are perpendicular to each other. According to the invention, the isolation structure is embedded between adjacent word lines, so that the complete separation of the word lines in the vertical grid transistor structure is ensured, and the isolation reliability is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the embodiments of the present invention will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained based on these drawings without inventive efforts.
Fig. 1 is a schematic diagram illustrating a method for fabricating a vertical gate transistor structure according to an embodiment of the invention;
fig. 2A to fig. 2K are schematic views illustrating device structures formed in the main steps of a method for fabricating a vertical gate transistor structure according to an embodiment of the invention;
fig. 3 is a schematic diagram of a device structure formed in the main steps of a method for fabricating a vertical gate transistor structure according to an embodiment of the invention;
fig. 4 is a schematic view of a vertical gate transistor according to an embodiment of the invention;
FIGS. 5A-5B are schematic views of the device structure formed in the main steps after the step of forming two word lines insulated from each other according to an embodiment of the present invention;
fig. 6A to 6E are schematic views of device structures formed in the main steps of a method for manufacturing a vertical gate transistor structure according to another embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1 to fig. 3, fig. 1 is a schematic diagram illustrating a method for fabricating a vertical gate transistor structure according to an embodiment of the invention, and fig. 2A to fig. 2K and fig. 3 are schematic diagrams illustrating device structures formed by main steps of the method for fabricating a vertical gate transistor structure according to an embodiment of the invention.
As shown in fig. 1, the preparation method of this embodiment includes: step S10, providing a substrate, wherein the substrate comprises a plurality of active regions arranged in an array, the plurality of active regions are separated by a plurality of first isolation structures in a Y direction and are separated by a plurality of grooves in an X direction, and the X direction is perpendicular to the Y direction; step S11, forming a second isolation structure at the bottom of each groove; step S12, forming a grid oxide layer on the side wall of each groove, wherein the grid oxide layer is connected with the second isolation structure; step S13, forming a sacrificial layer on the side wall and the bottom of each groove, wherein the sacrificial layer at least covers the second isolation structure and the grid oxide layer; step S14, filling an isolation material in each groove and flattening to form a third isolation structure; s15, removing part of the sacrificial layer, depositing a conductive material and processing to form two mutually insulated word lines in each groove; and the sacrificial layer is kept to be used as a fourth isolation structure, so that the two word lines have a first distance from the second isolation structure, and the two word lines have a second distance from the surface of the substrate.
Referring to step S10, fig. 2A and fig. 2B, a substrate 20 is provided, where the substrate 20 includes a plurality of active regions 200 arranged in an array, the plurality of active regions 200 are separated by a plurality of first isolation structures 201 in a Y direction (as shown in fig. 2A), and are separated by a plurality of trenches 202 in an X direction (as shown in fig. 2B), and the X direction is perpendicular to the Y direction.
Fig. 2A shows the substrate 20 formed with the first isolation structure 201, where (a) is a top view along the Z direction, and (b) is an XY-direction cross-sectional view taken along the AA' line in (a); fig. 2B shows the substrate 20 with the groove 202 formed therein, where (a) is a top view along the Z direction, and (B) is an XZ direction cross-sectional view taken along the line BB' in (a).
In this embodiment, the material of the active region 200 is monocrystalline silicon, and the material of the first isolation structure 201 is silicon oxide; in other embodiments of the present invention, the material of the first isolation structure 201 may also be selected from silicon nitride or polysilicon.
Referring to step S11 and fig. 2C, a second isolation structure 203 is formed at the bottom of each trench 202. In fig. 2C, a part (a) is a plan view along the Z direction, and a part (b) is an XZ direction cross-sectional view taken along the BB' line in the part (a).
In this embodiment, the second isolation structure 203 is made of silicon oxide; in other embodiments of the present invention, the material of the second isolation structure may also be selected from silicon nitride or polysilicon.
Referring to step S12 and fig. 2D, a gate oxide layer 204 is formed on the sidewall of each trench 202, and the gate oxide layer 204 is connected to the second isolation structure 203. In fig. 2D, (a) is a plan view taken along the Z direction, and (b) is an XZ direction cross-sectional view taken along the BB' line in (a).
In this embodiment, the gate oxide layer 204 may be formed by thermal oxidation. The thermal oxidation belongs to an oxidation treatment method, and an oxidant such as oxygen or water vapor reacts with the exposed substrate 20 at a high temperature to generate silicon dioxide, thereby forming an oxide layer, which serves as the gate oxide layer 204. The gate oxide layer 204 formed by thermal oxidation has high repeatability and stability, which is beneficial to improving the reliability of the semiconductor device.
Referring to step S13 and fig. 2E, a sacrificial layer 205 is formed on the sidewall and the bottom of each trench 202, and the sacrificial layer 205 at least covers the second isolation structure 203 and the gate oxide layer 204. In fig. 2E, (a) is a plan view taken along the Z direction, and (b) is a cross-sectional view taken along the BB' line in (a) in the XZ direction.
In this embodiment, the sacrificial layer 205 also covers the surface of the active region 200, and the material of the sacrificial layer 205 is silicon nitride; in other embodiments of the present invention, the material of the sacrificial layer 205 may also be selected from silicon oxide polysilicon; the material of the sacrificial layer 205 may be the same as or different from the first isolation structure 201 and the second isolation structure 203.
Referring to step S14 and fig. 2F, an isolation material is filled in each of the trenches 202 and planarized to form a third isolation structure 206. In the present embodiment, the trench 202 is filled with an isolation material and planarized such that the upper surface of the third isolation structure 206 is flush with the upper surface of the sacrificial layer 205. In fig. 2F, part (a) is a plan view taken along the Z direction, and part (b) is a cross-sectional view taken along the BB' line in part (a) in the XZ direction.
In this embodiment, the third isolation structure 206 is made of silicon oxide; in other embodiments of the present invention, the material of the third isolation structure 206 may also be selected from silicon nitride or polysilicon; however, the material of the third isolation structure 206 is different from the material of the sacrificial layer 205, so that the sacrificial layer 205 can be processed separately later.
Referring to step S15 and fig. 3, a portion of the sacrificial layer 205 is removed, and a conductive material is deposited and processed to form two word lines 2091 and 2092 insulated from each other in each of the trenches 202; the sacrificial layer 205 is remained as the fourth isolation structure 208, so that the two word lines 2091, 2092 are located at a first distance H1 from the second isolation structure 203, and the two word lines 2091, 2092 are located at a second distance H2 from the substrate surface. In fig. 3, (a) is a plan view taken along the Z direction, (b) is an XZ direction cross-sectional view taken along the BB 'line in (a), and (c) is an XZ direction cross-sectional view taken along the CC' line in (a).
Referring to fig. 2G, in an embodiment, the step S15 further includes: the sacrificial layer 205 is removed to a first distance H1 from the second isolation structure 203 to form a word line void 207 in each of the trenches 202, leaving the sacrificial layer 205 as a fourth isolation structure 208. In fig. 2G, a part (a) is a plan view taken along the Z direction, and a part (b) is an XZ direction cross-sectional view taken along the BB' line in the part (a).
The existence of the fourth isolation structure 208 ensures that the word lines deposited in the subsequent trench 202 can be completely separated, thereby avoiding the problem in the prior art that the bottoms of the two word lines are not completely separated. In this embodiment, the fourth isolation structure 208 is a U-shaped structure; in other embodiments of the present invention, the fourth isolation structure 208 may also have a straight structure or an irregular shape.
In some embodiments of the present invention, the material of the first isolation structure, the second isolation structure, the third isolation structure and the sacrificial layer is selected from silicon nitride, silicon oxide or polysilicon, wherein the material of the third isolation structure is different from the material of the sacrificial layer.
Referring to fig. 2H, in the above embodiment, step S15 further includes: a conductive material 220 is deposited within the word line void 207. Alternatively, the conductive material 220 may fill the word line void 207 and cover the surface of the active region 200. In fig. 2H, a part (a) is a plan view taken along the Z direction, and a part (b) is an XZ direction cross-sectional view taken along the BB' line in the part (a).
Referring to fig. 2I, in the above embodiment, step S15 further includes: portions of the conductive material 220 are removed to form a ring-shaped wordline 209 within each of the trenches 202 having the second distance H2 from the substrate surface. In fig. 2I, part (a) is a top view along the Z direction, and part (b) is an XZ direction cross-sectional view taken along the BB' line in part (a).
Referring to fig. 2J, in the above embodiment, step S15 further includes: isolation material 210 is filled in the word line void 207 and planarized. In fig. 2J, a portion (a) is a plan view taken along the Z direction, and a portion (b) is an XZ direction cross-sectional view taken along the line BB' in the portion (a).
The ring word line 209 is then disconnected, forming two word lines 2091, 2092 that are insulated from each other, as shown in fig. 3.
Referring to fig. 2K, the step of disconnecting the ring-shaped word line 209 to form two word lines 2091 and 2092 insulated from each other further includes: etching at opposite ends of the ring-shaped word line 209 until the corresponding sacrificial layer 205 is partially or completely removed, thereby disconnecting the ring-shaped word line 209 and forming two word lines 2091, 2092 insulated from each other, wherein etching is performed at least at one side of each of the ends; and filling the post-etch region with an isolation material 221 and planarizing. In fig. 2K, (a) is a plan view taken along the Z direction, and (b) is a cross-sectional view taken along the line CC' in the (a) portion in the XZ direction.
In the present embodiment, each ring word line 209 is disconnected at both 212A and 212B.
Fig. 2G to 2K illustrate a preparation method of forming the ring-shaped word line 209 first and then disconnecting the two word lines 2091 and 2092 insulated from each other. In the embodiment of the present invention, a preparation method of forming the disconnection structure first and then forming the two word lines 2091 and 2092 insulated from each other may also be adopted.
Referring to fig. 6A, in an embodiment, the step S15 further includes: respectively performing partial etching on two opposite end portions of the sacrificial layer 205 to form grooves; wherein etching is performed on at least one side of each of the end portions. That is, the sacrificial layer 205 is disconnected, and two portions of sacrificial layer separated from each other are formed at each of the trenches. In fig. 6A, a portion (a) is a plan view taken along the Z direction, and a portion (b) is an XZ direction cross-sectional view taken along a line CC' in the portion (a). In this embodiment, the sacrificial layer 205 is disconnected at both the grooves 601A and 601B.
With reference to fig. 6B, in the above embodiment, step S15 further includes: the trench is filled with an isolation material 602 and planarized. In fig. 6B, part (a) is a plan view taken along the Z direction, and part (B) is a cross-sectional view taken along the CC' line in part (a) in the XZ direction.
With reference to fig. 6C, in the above embodiment, the step S15 further includes: portions of the sacrificial layer 205 are removed to form word line voids 207 within each of the trenches. Wherein, the remaining part of the sacrificial layer 205 except the part under the groove is used as a fourth isolation structure 208; the sacrificial layer 205 remaining below the recess serves as a sixth isolation structure 603 for isolating two word lines formed in the same trench. In fig. 6C, (a) is a plan view taken along the Z direction, (b) is an XZ direction cross-sectional view taken along the BB 'line in (a), and (C) is an XZ direction cross-sectional view taken along the CC' line in (a).
Referring to fig. 6D, in the above embodiment, step S15 further includes: a conductive material 220 is deposited within the word line void 207. The conductive material 220 is disconnected at the sixth isolation structure 603 and the grooves 601A and 601B. In fig. 6D, part (a) is a plan view taken along the Z direction, part (b) is an XZ direction cross-sectional view taken along the BB 'line in part (a), and part (c) is an XZ direction cross-sectional view taken along the CC' line in part (a).
Referring to fig. 6E, in the above embodiment, step S15 further includes: removing a portion of the conductive material 220 to form two word lines 2091, 2092 insulated from each other and having the second distance H2 from the substrate surface within each of the trenches; wherein the two word lines 2091, 2092 are insulated from each other by the sacrificial layer 205 (i.e., the sixth isolation structure 603) remaining under the groove; and filling an isolation material in the region where the portion of the conductive material 220 is removed and planarizing. In fig. 6E, (a) is a plan view taken along the Z direction, (b) is an XZ direction cross-sectional view taken along the BB 'line in (a), and (c) is an XZ direction cross-sectional view taken along the CC' line in (a).
In this embodiment, the two word lines 2091, 2092 are broken at both the recesses 601A and 601B.
Further, in some embodiments, referring to fig. 4, a plurality of fifth isolation structures 400 are formed in the active region 200, each fifth isolation structure 400 is disposed between two adjacent second isolation structures 203, and an extending direction of the fifth isolation structure 400 is the same as an extending direction of the second isolation structures 203. The fifth isolation structure 400 and the first isolation structure 201 together perform a separation and isolation function.
The material of the fifth isolation structure is selected from silicon nitride, silicon oxide or polysilicon, or the fifth isolation structure is isolated by air.
Source/drain S/D, and a gate are also formed in the active region 200, so that a plurality of vertical gate transistors 401 arranged in an array are formed in the active region 200.
After the step of disconnecting the ring-shaped word line and forming two mutually insulated word lines is completed by any of the above methods, the method further includes:
referring to fig. 5A, the substrate 20 is turned over, and the substrate 20 is thinned on the side of the substrate 20 close to the second isolation structure 203 until the second isolation structure 203 is exposed.
Referring to fig. 5B, a bit line 500 is formed on the surface of the thinned substrate 20, and the bit line 500 covers the second isolation structure 203.
The present invention further provides a vertical gate transistor structure, as shown in fig. 4, the vertical gate transistor structure is formed by any one of the above methods, including:
a substrate 20, wherein the substrate 20 comprises a plurality of vertical gate type transistors 401 arranged in an array, the plurality of vertical gate type transistors 401 are separated by a plurality of first isolation structures 201 in a Y direction, separated by a plurality of fifth isolation structures 400 in an X direction, and connected with a second isolation structure 203 in a Z direction;
a plurality of word lines 2091, 2092, the word lines 209 extend along the Y direction and are arranged in parallel in the X direction, a third isolation structure 206 is arranged between two adjacent word lines 2091, 2092, and the two adjacent word lines 2091, 2092 are isolated from the corresponding second isolation structure 203 by a fourth isolation structure 208 and have a second distance H2 from the substrate surface. Two adjacent word lines 2091, 2092 are separated from the second isolation structure 203 by a first distance H1 (i.e., the height of the fourth isolation structure 208), and the X-direction, the Y-direction, and the Z-direction are all perpendicular to each other.
According to the technical scheme, the isolation structure is embedded between the adjacent word lines, so that the complete separation of the word lines in the vertical gate transistor structure is ensured, and the isolation reliability is improved.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (10)
1. A method for manufacturing a vertical gate transistor structure, comprising:
providing a substrate, wherein the substrate comprises a plurality of active regions arranged in an array, the active regions are separated by a plurality of first isolation structures in a Y direction and are separated by a plurality of grooves in an X direction, and the X direction is perpendicular to the Y direction;
forming a second isolation structure at the bottom of each groove;
forming a gate oxide layer on the side wall of each groove, wherein the gate oxide layer is connected with the second isolation structure;
forming a sacrificial layer on the side wall and the bottom of each groove, wherein the sacrificial layer at least covers the second isolation structure and the gate oxide layer;
filling an isolation material in each groove and flattening to form a third isolation structure;
and removing part of the sacrificial layer, depositing a conductive material and processing to form two word lines which are insulated from each other in each groove, wherein the sacrificial layer which is remained serves as a fourth isolation structure enables the two word lines to have a first distance from the second isolation structure, and the two word lines have a second distance from the surface of the substrate.
2. The method of claim 1 wherein said step of forming two word lines insulated from each other in each of said trenches further comprises:
removing the sacrificial layer to a position having the first distance from the second isolation structure so as to form a word line gap in each groove, and keeping the sacrificial layer as a fourth isolation structure;
depositing a conductive material within the word line void;
removing portions of the conductive material to form annular word lines within each of the trenches having the second distance from the substrate surface;
filling an isolation material in the word line gap and flattening; and
and disconnecting the annular word lines to form two mutually insulated word lines.
3. The method of claim 2, wherein said step of disconnecting said ring-shaped word lines to form two word lines insulated from each other comprises:
etching at two opposite ends of the annular word line until the corresponding sacrificial layer is partially or completely removed, thereby disconnecting the annular word line and forming two mutually insulated word lines, wherein etching is performed at least on one side of each end; and
and filling the etched area with an isolation material and flattening.
4. The method of claim 2, wherein the fourth isolation structure is a U-shaped structure.
5. The method of claim 1 wherein said step of forming two word lines insulated from each other in each of said trenches further comprises:
respectively carrying out partial etching on two opposite end parts of the sacrificial layer to form grooves, wherein at least one side of each end part is etched;
filling an isolation material in the groove and flattening;
removing part of the sacrificial layer to form word line gaps in each groove, wherein the part of the sacrificial layer, except the part below the groove, is reserved as a fourth isolation structure;
depositing a conductive material within the word line void;
removing part of the conductive material to form two mutually insulated word lines with the second distance from the surface of the substrate in each groove, wherein the two word lines are mutually insulated by the sacrificial layer remained below the groove; and
and filling an isolation material in the region where part of the conductive material is removed and flattening.
6. The method of claim 1, wherein the first, second, third and sacrificial layers are made of a material selected from the group consisting of silicon nitride, silicon oxide and polysilicon, and wherein the material of the sacrificial layer is different from the material of the third isolation structure.
7. The method of claim 1, wherein after the step of forming two word lines insulated from each other in each of the trenches, further comprising:
turning over the substrate, and thinning the substrate on the side of the substrate close to the second isolation structure until the second isolation structure is exposed;
and forming a bit line on the thinned surface of the substrate, wherein the bit line covers the second isolation structure.
8. The method of claim 1, further comprising:
and forming a plurality of fifth isolation structures in the active region, wherein each fifth isolation structure is arranged between two adjacent second isolation structures, and the extending direction of the fifth isolation structures is the same as that of the second isolation structures.
9. The method of claim 8, wherein the material of the fifth isolation structure is selected from silicon nitride, silicon oxide or polysilicon, or the fifth isolation structure uses air isolation.
10. A vertical gate transistor structure formed by the method of any of claims 1-9, comprising:
the substrate comprises a plurality of vertical grid type transistors which are arranged in an array, the vertical grid type transistors are separated by a plurality of first isolation structures in the Y direction, are separated by a plurality of fifth isolation structures in the X direction, and are connected with corresponding second isolation structures in the Z direction;
the word lines extend along the Y direction and are arranged in parallel in the X direction, a third isolation structure is arranged between every two adjacent word lines, the two adjacent word lines and the corresponding second isolation structures are isolated through a fourth isolation structure, and a second distance is reserved between the two adjacent word lines and the surface of the substrate, wherein the X direction, the Y direction and the Z direction are perpendicular to each other.
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| CN116193856B (en) * | 2023-04-23 | 2023-10-17 | 长鑫存储技术有限公司 | Semiconductor structure and preparation method thereof |
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