CN115588454A

CN115588454A - Data writing method and device of memory, electronic equipment and storage medium

Info

Publication number: CN115588454A
Application number: CN202211482337.1A
Authority: CN
Inventors: 刘家齐
Original assignee: Beijing Unigroup Tsingteng Microsystems Co Ltd
Current assignee: Beijing Unigroup Tsingteng Microsystems Co Ltd
Priority date: 2022-11-24
Filing date: 2022-11-24
Publication date: 2023-01-10

Abstract

The application relates to the technical field of data storage, and discloses a data writing method of a memory. Before writing the data to be written into the memory, the method compares the data to be written with the existing data in the memory according to the bit, only if the existing data is 1 and the data to be written is 0, the writing operation is executed, and the writing is not executed under other conditions, thereby avoiding multiple invalid writing, improving the utilization rate of the memory and effectively prolonging the service life of the memory. The application also discloses a data writing device, electronic equipment and a storage medium of the memory.

Description

Data writing method and device of memory, electronic equipment and storage medium

Technical Field

The present application relates to the field of data storage technologies, and for example, to a data writing method and apparatus for a memory, an electronic device, and a storage medium.

Background

As integrated circuit process dimensions continue to shrink, device capacitance further shrinks, but for memory devices, the shrinking of node capacitance means that the difference in charge amount for stored 0 or 1 data is further reduced. Therefore, more precise control is required for erasing and writing.

Generally, the written data of the nonvolatile memory is in units of bytes, and there is a usage scenario that individual bit data in one byte in the nonvolatile memory is already written as 0, and only 0 needs to be written to other bits in the byte.

In the process of implementing the embodiments of the present disclosure, it is found that at least the following problems exist in the related art:

in the related art, writing is usually performed directly by byte, and if repeated data, for example, 0, is repeatedly written to one byte, data that has been written earlier may be over-written, which affects the endurance and reliability of the chip.

Disclosure of Invention

The following presents a simplified summary in order to provide a basic understanding of some aspects of the disclosed embodiments. This summary is not an extensive overview and is intended to neither identify key/critical elements nor delineate the scope of such embodiments, but is intended to be a prelude to the more detailed description that is presented later.

The embodiment of the disclosure provides a data writing method and device of a memory, electronic equipment and a storage medium, so as to prevent the memory from being over-written and prolong the service life of the memory.

In some embodiments, the method comprises: acquiring data to be written and existing data in the memory; comparing the data to be written with the existing data according to corresponding bits; generating updating data according to the comparison result; each bit in the updated data is used for representing a comparison result between the data to be written and the existing data, when a first bit in the data to be written is 0 and a second bit corresponding to the first bit in the existing data is 1, the comparison result between the first bit and the second bit is a first preset value, otherwise, the comparison result is a second preset value; and according to the bit corresponding to the first preset value in the updating data, executing data writing operation to the memory.

Optionally, the step of obtaining data to be written and existing data in the memory includes: receiving a programming instruction; the programming instruction comprises data to be written and a target address; and reading the data stored in the storage unit corresponding to the target address in the memory as the existing data.

Optionally, the step of comparing the data to be written and the existing data according to corresponding bits includes: if the first bit in the data to be written is 0 and the corresponding second bit in the existing data is 1, the comparison result is a first preset value; otherwise, the comparison result is the second preset value.

Optionally, the step of performing a data write operation to the memory according to the bit corresponding to the first preset value in the update data includes: determining whether each byte needs to execute a write operation according to the value of a bit contained in each byte in the update data; and if the current byte in the updated data needs to execute the write operation, writing 0 into the corresponding storage unit in the memory based on the bit corresponding to the first preset value in the current byte.

Optionally, the step of determining whether each byte needs to perform a write operation according to a value of a bit included in each byte in the update data includes: judging each byte in the updated data, and if a first preset value exists in the bit of the byte, executing write operation on the byte; otherwise, it is determined that the byte does not require a write operation.

Optionally, the step of executing a data write operation to the memory includes: writing 0 into a memory cell corresponding to a byte needing to perform a write operation in the updating data in the memory at a write voltage smaller than a preset voltage value each time; or writing 0 into the memory unit corresponding to the byte needing to execute the write operation in the updating data in the memory with the write time less than the preset write time each time.

Optionally, the method further comprises: comparing the updated existing data with the data to be written according to bits; if the comparison result represents that the data are inconsistent, the updated existing data are used as the existing data, and the comparison between the data to be written and the existing data according to the corresponding bit positions is executed again; generating updating data according to the comparison result; and according to the bit corresponding to the first preset value in the updated data, executing data writing operation on the memory until the updated existing data is consistent with the data to be written.

Optionally, the method further comprises: and storing the data to be written and the updated data to a cache region in the memory.

In some embodiments, the apparatus comprises: the acquisition module is used for acquiring data to be written and existing data in the memory; the comparison module is used for comparing the data to be written with the existing data according to corresponding bits; the updating data generating module is used for generating updating data according to the comparison result; each bit in the updated data is used for representing a comparison result between the data to be written and the existing data, when a first bit in the data to be written is 0 and a second bit corresponding to the first bit in the existing data is 1, the comparison result between the first bit and the second bit is a first preset value, otherwise, the comparison result is a second preset value; and the writing module is used for executing data writing operation to the memory according to the bit corresponding to the first preset value in the updating data.

In some embodiments, the electronic device includes a processor and a memory storing program instructions, and the processor is configured to execute the data writing method of the memory when executing the program instructions.

The data writing method and device for the memory, the electronic device and the storage medium provided by the embodiment of the disclosure can realize the following technical effects:

before writing the data to be written into the memory, firstly comparing the data to be written with the existing data in the memory according to bit positions, executing the writing operation only when the existing data is 1 and the data to be written is 0, and not executing the writing in other conditions, thereby avoiding multiple invalid writing, improving the utilization rate of the memory and effectively prolonging the service life of the memory.

The foregoing general description and the following description are exemplary and explanatory only and are not restrictive of the application.

Drawings

One or more embodiments are illustrated by way of example in the accompanying drawings, which correspond to the accompanying drawings and not in limitation thereof, in which elements having the same reference numeral designations are shown as like elements and not in limitation thereof, and wherein:

FIG. 1 is a schematic diagram of a non-volatile memory;

FIG. 2 is a schematic diagram of device currents in a memory;

FIG. 3 is a flow chart illustrating a data writing method of a memory according to the related art;

FIG. 4 is a flow chart illustrating a method for writing data into a memory according to an embodiment of the present disclosure;

FIG. 5 is a flowchart illustrating another method for writing data into a memory according to an embodiment of the disclosure;

FIG. 6 is a flowchart illustrating a method for writing data in a memory in an application scenario according to an embodiment of the present disclosure;

FIG. 7 is a schematic diagram of multiple writes of different data to a byte provided by an embodiment of the disclosure;

FIG. 8 is a schematic diagram of multiple writes of the same data to multiple bytes provided by an embodiment of the present disclosure;

FIG. 9 is a schematic structural diagram of an apparatus for writing data in a memory according to an embodiment of the present disclosure;

fig. 10 is a schematic structural diagram of an electronic device according to an embodiment of the present disclosure.

Detailed Description

So that the manner in which the features and elements of the disclosed embodiments can be understood in detail, a more particular description of the disclosed embodiments, briefly summarized above, may be had by reference to the embodiments, some of which are illustrated in the appended drawings. In the following description of the technology, for purposes of explanation, numerous details are set forth in order to provide a thorough understanding of the disclosed embodiments. However, one or more embodiments may be practiced without these details. In other instances, well-known structures and devices may be shown in simplified form in order to simplify the drawing.

The terms "first," "second," and the like in the description and in the claims, and the above-described drawings of embodiments of the present disclosure, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It should be understood that the data so used may be interchanged under appropriate circumstances such that embodiments of the present disclosure described herein may be made. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion.

The term "plurality" means two or more, unless otherwise specified.

The memory comprises a memory array, wherein the memory array is composed of a plurality of memory cells, each memory cell is a binary bit, and one bit can store a binary number of 0 or 1. Every 8 bits constitute one byte. One binary number is one BIT (BIT), which is the minimum unit of information amount. Fig. 1 shows a nonvolatile memory structure, as shown in fig. 1, in which S301 and S302 share a source, and are referred to as cell _11 when S301 is 1 and S302 is 1, cell _10 when S301 is 1 and S302 is 0, cell _01 when S301 is 0 and S302 is 1, and cell _00 when S301 is 0 and S302 is 0.

Fig. 2 shows the device current situation in the memory under different memory contents. When the device current is greater than the Reference current Reference, it is identified as 1. When the device current is less than the Reference current Reference, it is identified as 0. As shown in FIG. 2, if over-writing occurs, it will cause the cell _10 distribution to shift left, resulting in a 1 being misidentified.

Fig. 3 is a schematic flow chart of a data writing method of a memory in the related art, and as shown in fig. 3, the data writing method includes:

s301, receiving a programming instruction sent by a user, and writing data into a buffer area.

S302, writing the data in the buffer area into the nonvolatile memory by taking bytes as units.

And S303, repeating the step 302 until all the user written data are written into the nonvolatile memory.

S304, judging whether the data is written to the programming threshold value. S302 to S304 are repeated if the program threshold is not reached, and it jumps to S305 if the program threshold is reached.

S305, the writing operation is finished.

As can be seen from the above steps, in the related art, the data writing method of the memory directly writes the byte, and if repeated data is repeatedly written into a byte, the data that has been written earlier will be over-written, which affects the endurance and reliability of the memory chip.

The disclosed embodiments prevent the generation of over-writing by preprocessing data. The method only carries out write operation on data of which the bits are really written, compares the data to be written with the existing data in the memory according to the bits before the write operation is executed, and executes the write operation on the memory cell in the memory according to the comparison result, thereby ensuring that the write operation does not have the over-write problem and prolonging the durability of the use of the memory chip.

With reference to fig. 4, an embodiment of the present disclosure provides a data writing method for a memory, where the method is applied to a processor in the memory, and the memory includes a storage area and a cache area, as shown in fig. 4, the method includes:

s401: the processor obtains data to be written and existing data in the memory.

The data to be written is a binary number readable by a computer, and the data to be written may be data of one byte or data of a plurality of bytes, each byte includes 8 bits, and each bit is 0 or 1.

The write operation to the memory is to replace existing data with data to be written. Therefore, there is also a target address at which data to be written is written in the memory, corresponding to the data to be written. The existing data of the memory is therefore the existing data indicated in the instruction received by the electronic device that is to write the data to be written to the specified location in the memory.

S402: and comparing the data to be written with the existing data according to corresponding bit.

The length of the data to be written is the same as that of the existing data, so that during comparison, the bit of each pair of corresponding positions is compared to obtain a comparison result.

S403: generating updating data according to the comparison result; each bit in the updated data is used for representing a comparison result between the data to be written and the existing data, when a first bit in the data to be written is 0 and a second bit corresponding to the first bit in the existing data is 1, the comparison result between the first bit and the second bit is a first preset value, otherwise, the comparison result is a second preset value;

the length of the comparison result is the same as the data to be written, and each bit of the comparison result represents the comparison result of a pair of bits whose positions correspond to each other.

The first preset value may be 1 or 0, and similarly, the second preset value may also be 1 or 0. It should be noted that the first preset value and the second preset value are used to represent two different comparison results of whether the bit can be written, and therefore, the first preset value and the second preset value are not equal. That is, if the first preset value is 0, the second preset value is 1, and if the first preset value is 1, the second preset value is 0. The first preset value is used for representing that the writing operation can be executed on the memory cell corresponding to the bit. That is, the value of the bit of the data to be written is 0, and the value of the bit of the existing data is 1.

The second preset value is used for representing that the writing operation cannot be executed on the storage unit corresponding to the bit. When the following situation occurs, the corresponding bit in the update data is the second preset value.

(1) The data to be written is 1, and the existing data is 1;

(2) The data to be written is 1, and the existing data is 0;

(3) The data to be written is 0, and the existing data is 0.

Table 1 below is the values of the bits in the corresponding update data when comparing the data to be written and the existing data.

TABLE 1

Data to be written	Existing data	Updating data
			0	1	0
1	1	1
			1	0	1
0	0	1

In this way, since only 0 can be written into the memory, only the memory cell with data to be written being 0 and existing data being 1 is written into, but the memory cell already being 0 does not perform the write operation, that is, only the memory cell is written into 1 from 0, and is not written into in other situations, so that the write efficiency is improved, the influence of unnecessary over-writing on the memory is reduced, and the service life of the memory is prolonged.

S404: and according to the bit corresponding to the first preset value in the updating data, executing data writing operation to the memory.

When data is written, the data is also written according to bits, if one bit in the updating data is the first preset value, the bit can be written, and 0 is written into the memory. And if the other bit in the updating data is the second preset value, the bit does not need to be written, the bit is skipped, and the next bit in the updating data is continuously judged.

In some examples, performing a data write operation may be performing a write operation each time a byte is compared. In other embodiments, the write operation may be performed after all bytes are compared. It can be understood that, in order to improve the efficiency of the write operation, before performing the write operation, it may also be determined whether all bytes are the second preset value, and if all bytes are the second preset value, it is characterized that there is no bit to be written in the byte, and then the write operation is not required to be performed, and the write operation of the next byte is directly performed.

According to the method provided by the embodiment of the disclosure, before the data to be written is written into the memory, the data to be written and the existing data in the memory are compared according to the bit, only the memory cell with the existing data of 1 and the data to be written of 0 is subjected to the writing operation, and the writing operation is not performed under other conditions, so that multiple invalid writing is avoided, the utilization rate of the memory is improved, and the service life of the memory is effectively prolonged.

Optionally, the step of acquiring the data to be written and the existing data in the memory includes: receiving a programming instruction; the programming instruction comprises data to be written and a target address; and reading the data stored in the storage unit corresponding to the target address in the memory as existing data.

Since the write operation of the memory takes a certain amount of time, in order to avoid data loss, the data to be written may be first stored quickly, and then the write operation may be performed based on the stored data. Based on this, optionally, the method further includes: and storing the data to be written and the updated data to a buffer area in the memory. Therefore, the data to be written is written into the cache region, data loss caused by untimely data writing is avoided, and the storage precision of the memory is improved. Meanwhile, the updated data is also written into the cache region, so that the memory space is saved.

Optionally, the step of performing a data write operation to the memory according to the bit corresponding to the first preset value in the update data includes: determining whether each byte needs to execute a write operation according to the value of a bit contained in each byte in the update data; and if the current byte in the updating data needs to execute the writing operation, writing 0 into the corresponding storage unit in the memory based on the bit corresponding to the first preset value in the current byte.

For convenience of description, the first preset value is 0, and the second preset value is 1. There are two cases for a byte in the update data, the first case is that there is both a 0 and a 1 in the byte, in which case this indicates that the byte in the update data needs to be written. In the second case, all of the bytes are 1, which indicates that the byte does not need to perform a write operation.

For example, the first byte of data to be written is hFE (11111110), and the first byte of existing data is hFF (11111111).

First, the data to be written is compared with each bit of the existing data, and for the 0 th bit, the data to be written is 1, and the existing data is 1, the 0 th bit in the update data is set to 1 (no writing is required). For the 7 th bit, the data to be written is 0, the existing data is 1, the 7 th bit in the update data is set to 0 (write is required), and the finally obtained update data is (11111111110).

Further, the second byte of the data to be written is h3C (00111100), and the first byte of the existing data is h18 (00011000).

First, the data to be written is compared with each bit of the existing data, and for the 0 th bit, the data to be written is 0, and the existing data is 0, and 1 is set at the 0 th bit in the update data (writing is not required). For the 2 nd bit, the data to be written is 1, the existing data is 0, the 1 st bit in the update data is set to 1 (no writing is required), and the finally obtained update data is (11111111111).

In this way, if the determination of writing is made on a byte-by-byte basis and there is a 0 in the first byte of the update data, that is, if the byte has a bit to be written, the writing operation is performed based on the value of each bit of the byte in the update data. In the second byte of the update data, all bits are 1, which indicates that the byte does not need to be written, the byte is skipped, thereby further reducing the operation of writing for many times and prolonging the service life of the memory.

For example, for a certain 1bit, fail is judged when the buffer area is 0 and the nonvolatile memory is 1, and the rest conditions are judged pass; after all bits pass, the comparison is considered to be successful, otherwise, the comparison is considered to be failed.

During specific comparison, determining the storage data of each byte according to the voltage value of the storage unit corresponding to each bit of each byte in the target address and the threshold voltage of the memory; and judging the consistency of the storage data of the byte and the corresponding byte in the data to be written.

If the voltage of the memory cell corresponding to the bit reaches the threshold voltage, it indicates that the value of the bit is 0, i.e. the writing is successful.

Therefore, the value of the bit is determined through the threshold voltage of the storage unit, the data consistency in the two corresponding bytes is further determined, the judgment result is more accurate, and the accuracy of data writing is further improved.

Optionally, the step of performing a data write operation to the memory includes: and writing 0 into the memory cell corresponding to the byte needing to be written in the updating data in the memory at a writing voltage smaller than a preset voltage value each time. Or writing 0 into the memory unit corresponding to the byte needing to execute the write operation in the updating data in the memory with the write time less than the preset write time each time.

Since each write operation is performed on the memory cell at a weaker write voltage, the write is performed a plurality of times until a preset programming threshold is reached. Or, the time for executing the write operation each time is shorter, for example, shorter than the preset write time, so that the situation that other memory cells are over-written at the same time due to a single strong write can be avoided, and the over-write problem is further effectively avoided while the write accuracy is ensured.

Referring to fig. 5, another data writing method for a memory according to an embodiment of the present disclosure is provided, where on the basis of the foregoing method, attention is focused on how to determine accuracy of written data, and the method includes:

s501: and acquiring data to be written and the existing data in the memory.

S502: and comparing the data to be written with the existing data according to corresponding bit.

S503: generating updating data according to the comparison result; each bit in the updated data is used for representing a comparison result between the data to be written and the existing data, when a first bit in the data to be written is 0 and a second bit corresponding to the first bit in the existing data is 1, the comparison result between the first bit and the second bit is a first preset value, otherwise, the comparison result is a second preset value;

s504: and executing data writing operation to the memory according to the bit corresponding to the first preset value in the updating data.

S505: and judging whether the updated existing data and the data to be written represent data consistency according to the comparison result of the bit positions. And if the comparison result represents that the data are inconsistent, taking the updated existing data as the existing data, and re-executing the steps S502-S504 until the updated existing data is consistent with the data to be written. If the comparison result indicates that the data are consistent, step S506 is executed.

S506: and finishing the execution of the writing operation.

In an actual write operation, all data to be written cannot be successfully written into the memory at one time, and a plurality of bytes in the data to be written may be successfully written only by a few bytes at one time or successfully written only by a few bits, so that the written data needs to be compared with the data to be written.

It should be understood that the comparison here is also a bit-wise comparison. The comparison method is the same as the bit-by-bit comparison method in the above embodiments of the present disclosure, and is not described herein again.

Therefore, after all bytes of the data to be written are subjected to one-time writing operation, the data consistency is compared, the situation of one-time writing error when the data volume is large can be avoided, and the accuracy of data writing is ensured.

With reference to fig. 6, a method for writing data into a memory in an actual application scenario provided by the embodiment of the present disclosure is described by taking the memory as a nonvolatile memory as an example, and the method is applied to a processor of an electronic device, where the electronic device includes the nonvolatile memory, and the method includes the following steps:

s601: and the processor receives a programming instruction sent by a user and writes the user writing data into the volatile buffer area.

S602: the processor reads the non-volatile memory data.

S603: the processor compares the buffered data with the non-volatile memory read data.

It should be understood that the cache data is data to be written in the above-described embodiments of the present disclosure, and the nonvolatile memory data is existing data in the above-described embodiments of the present disclosure.

S604: the processor updates the buffer data by bit according to the comparison result, and updates the buffer data to 0 only when the buffer data is 0 and the nonvolatile memory data is 1. Updating the buffer data to 1 when the buffer data is 1 and the nonvolatile memory data is 1; updating the buffer data to 1 when the buffer data is 1 and the nonvolatile memory data is 0; the buffer data is updated to 1 for the case where the buffer data is 0 and the nonvolatile memory data is 0.

S605: and the processor writes the updated buffer data into the nonvolatile memory by taking the bytes as units.

S606: the processor judges the written byte, and skips the write operation of the byte if all bits in the byte do not need to be written.

S607: and after the processor executes the write operation, reading the data of the nonvolatile memory again and comparing the data written in the buffer area to confirm whether the data is written correctly.

Here, a tight read is used to ensure that the data passing the comparison reaches the programming threshold. If the data has not been correctly written, repeating S602-S606 for writing again. If the data is written correctly, the data writing process ends.

For ease of understanding, the following description is made with respect to the writing process in two different scenarios.

Scenario 1: the user repeats writing different data to byte 0. As shown in FIG. 7a, the initial states of the buffer and the nonvolatile memory are both (11111111). As shown in fig. 7b, the first data to be written is hFE. As shown in fig. 7c, the data to be written for the second time is hFC. As shown in fig. 7d, the data to be written for the third time is hAE.

Scenario 2: the user writes "h00" to byte 0, byte 1 and byte 2. As shown in fig. 8a, the initial states of the buffer and the nonvolatile memory are shown. As shown in fig. 8b, the write-once was not successful. As shown in fig. 8c, for the second write, byte 0 and byte 2, which failed the last write, are rewritten. As shown in fig. 8d, the second write-failed byte 2 is rewritten, the data is identical, and the write operation is ended.

As shown in fig. 9, an embodiment of the present disclosure provides a data writing apparatus for a memory, where the apparatus includes: an obtaining module 901, a comparing module 902, an update data generating module 903 and a writing module 904. Wherein, the first and the second end of the pipe are connected with each other,

an obtaining module 901, configured to obtain data to be written and existing data in the memory;

a comparing module 902, configured to compare the data to be written with the existing data according to corresponding bits;

an update data generation module 903, configured to generate update data according to the comparison result; each bit in the updated data is used for representing a comparison result between the data to be written and the existing data, when a first bit in the data to be written is 0 and a second bit corresponding to the first bit in the existing data is 1, the comparison result between the first bit and the second bit is a first preset value, otherwise, the comparison result is a second preset value;

a writing module 904, configured to perform a data writing operation on the memory according to the bit corresponding to the first preset value in the update data.

By adopting the data writing device of the memory provided by the embodiment of the disclosure, before the data to be written is written into the memory, the data to be written and the existing data in the memory are compared according to the bit, only when the existing data is 1 and the data to be written is 0, the writing operation is executed, and the writing operation is not executed in other situations, so that multiple invalid writing is avoided, the utilization rate of the memory is improved, and the service life of the memory is effectively prolonged.

Optionally, the obtaining module 901 is further configured to: receiving a programming instruction; the programming instruction comprises data to be written and a target address; and reading the data stored in the storage unit corresponding to the target address in the memory as the existing data.

Optionally, the comparing module 902 is further configured to: if the first bit in the data to be written is 0 and the corresponding second bit in the existing data is 1, the comparison result is a first preset value; otherwise, the comparison result is the second preset value.

Optionally, the writing module 904 is further configured to: determining whether each byte needs to execute a write operation according to the value of a bit contained in each byte in the update data; and if the current byte in the updated data needs to execute the write operation, writing 0 into the corresponding storage unit in the memory based on the bit corresponding to the first preset value in the current byte.

Optionally, the determining whether each byte needs to perform a write operation according to a value of a bit included in each byte in the update data includes: judging each byte in the updating data, if the bit of the byte has a first preset value, the byte needs to execute the writing operation; otherwise, it is determined that the byte does not require a write operation.

Optionally, the apparatus further comprises: the second comparison module is used for comparing the updated existing data with the data to be written according to bits; the circulating module is used for taking the updated existing data as the existing data if the representation data of the comparison result are inconsistent, and re-executing the comparison of the data to be written and the existing data according to corresponding bits; generating updating data according to the comparison result; and according to the bit corresponding to the first preset value in the updated data, executing data writing operation on the memory until the updated existing data is consistent with the data to be written.

Optionally, the writing module 904 is specifically configured to: and writing 0 into the memory cell corresponding to the byte needing to be written in the updating data in the memory at a writing voltage smaller than a preset voltage value each time.

Optionally, the apparatus further comprises: and the storage module is used for storing the data to be written and the updated data to a cache region in the memory.

As shown in fig. 10, an embodiment of the present disclosure provides an electronic device including a processor (processor) 100 and a memory (memory) 101. Optionally, the electronic device may further include a Communication Interface (Communication Interface) 102 and a bus 103. The processor 100, the communication interface 102, and the memory 101 may communicate with each other via a bus 103. The communication interface 102 may be used for information transfer. The processor 100 may call the logic instructions in the memory 101 to execute the data writing method of the memory of the above-described embodiment.

In addition, the logic instructions in the memory 101 may be implemented in the form of software functional units and stored in a computer readable storage medium when the logic instructions are sold or used as independent products.

The memory 101, which is a computer-readable storage medium, may be used for storing software programs, computer-executable programs, such as program instructions/modules corresponding to the methods in the embodiments of the present disclosure. The processor 100 executes functional applications and data processing by executing program instructions/modules stored in the memory 101, that is, implements the data writing method of the memory in the above-described embodiments.

The memory 101 may include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function; the storage data area may store data created according to the use of the terminal device, and the like. In addition, the memory 101 may include a high-speed random access memory, and may also include a nonvolatile memory.

The disclosed embodiments provide a computer-readable storage medium storing computer-executable instructions configured to perform the data writing method of the above memory.

The disclosed embodiments provide a computer program product comprising a computer program stored on a computer readable storage medium, the computer program comprising program instructions that, when executed by a computer, cause the computer to perform the data writing method of the above-mentioned memory.

The computer-readable storage medium described above may be a transitory computer-readable storage medium or a non-transitory computer-readable storage medium.

The technical solution of the embodiments of the present disclosure may be embodied in the form of a software product, where the computer software product is stored in a storage medium and includes one or more instructions to enable a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method of the embodiments of the present disclosure. And the aforementioned storage medium may be a non-transitory storage medium comprising: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes, and may also be a transient storage medium.

The above description and drawings sufficiently illustrate embodiments of the disclosure to enable those skilled in the art to practice them. Other embodiments may incorporate structural, logical, electrical, process, and other changes. The examples merely typify possible variations. Individual components and functions are optional unless explicitly required, and the sequence of operations may vary. Portions and features of some embodiments may be included in or substituted for those of others. Furthermore, the words used in the specification are words of description only and are not intended to limit the claims. As used in the description of the embodiments and the claims, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Similarly, the term "and/or" as used in this application is meant to encompass any and all possible combinations of one or more of the associated listed. Furthermore, the terms "comprises" and/or "comprising," when used in this application, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Without further limitation, an element defined by the phrase "comprising one of 8230," does not exclude the presence of additional like elements in a process, method or device comprising the element. In this document, each embodiment may be described with emphasis on differences from other embodiments, and the same and similar parts between the respective embodiments may be referred to each other. For methods, products, etc. of the embodiment disclosures, reference may be made to the description of the method section for relevance if it corresponds to the method section of the embodiment disclosure.

Those of skill in the art would appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software may depend upon the particular application and design constraints imposed on the technical solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the disclosed embodiments. It can be clearly understood by the skilled person that, for convenience and brevity of description, the specific working processes of the system, the apparatus and the unit described above may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.

In the embodiments disclosed herein, the disclosed methods, products (including but not limited to devices, apparatuses, etc.) may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units may be only one type of logical functional division, and there may be other divisions in actual implementation, for example, multiple units or components may be combined or may be integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form. The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to implement the present embodiment. In addition, functional units in the embodiments of the present disclosure may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.

The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. In the description corresponding to the flowcharts and block diagrams in the figures, operations or steps corresponding to different blocks may also occur in different orders than disclosed in the description, and sometimes there is no specific order between the different operations or steps. For example, two sequential operations or steps may in fact be executed substantially concurrently, or they may sometimes be executed in the reverse order, depending upon the functionality involved. Each block of the block diagrams and/or flowchart illustrations, and combinations of blocks in the block diagrams and/or flowchart illustrations, can be implemented by special purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

Claims

1. A data writing method of a memory, comprising:

acquiring data to be written and existing data in the memory;

comparing the data to be written with the existing data according to corresponding bit;

generating updating data according to the comparison result; each bit in the updated data is used for representing a comparison result between the data to be written and the existing data, when a first bit in the data to be written is 0 and a second bit corresponding to the first bit in the existing data is 1, the comparison result between the first bit and the second bit is a first preset value, otherwise, the comparison result is a second preset value;

and according to the bit corresponding to the first preset value in the updating data, executing data writing operation to the memory.

2. The method of claim 1, wherein the step of retrieving the data to be written and the existing data in the memory comprises:

receiving a programming instruction; the programming instruction comprises data to be written and a target address;

and reading the data stored in the storage unit corresponding to the target address in the memory as the existing data.

3. The method according to claim 1, wherein the step of comparing the data to be written and the existing data according to corresponding bits comprises:

if the first bit in the data to be written is 0 and the corresponding second bit in the existing data is 1, the comparison result is a first preset value;

otherwise, the comparison result is the second preset value.

4. The method according to claim 1, wherein the step of performing a data write operation to the memory according to the bit corresponding to the first preset value in the update data comprises:

determining whether each byte needs to execute a write operation according to the value of a bit contained in each byte in the update data;

and if the current byte in the updated data needs to execute the write operation, writing 0 into the corresponding storage unit in the memory based on the bit corresponding to the first preset value in the current byte.

5. The method according to claim 4, wherein the step of determining whether each byte needs to perform a write operation according to the value of the bit contained in each byte in the update data comprises:

judging each byte in the updating data, if the bit of the byte has a first preset value, the byte needs to execute the writing operation;

otherwise, it is determined that the byte does not require a write operation.

6. The method of claim 1, wherein the step of performing a data write operation to the memory comprises:

writing 0 into a storage unit corresponding to a byte needing to be written in the updating data in the memory at a writing voltage smaller than a preset voltage value each time; alternatively, the first and second electrodes may be,

and writing 0 into the memory corresponding to the byte needing to be written in the updating data in the memory at a writing time less than the preset writing time each time.

7. The method according to any one of claims 1-5, further comprising:

comparing the updated existing data with the data to be written according to bit;

if the comparison result represents that the data are inconsistent, the updated existing data are used as the existing data, and the comparison between the data to be written and the existing data according to the corresponding bit positions is executed again; generating updating data according to the comparison result; and according to the bit corresponding to the first preset value in the updated data, executing data writing operation on the memory until the updated existing data is consistent with the data to be written.

8. A data writing apparatus of a memory, comprising:

the acquisition module is used for acquiring data to be written and existing data in the memory;

the comparison module is used for comparing the data to be written with the existing data according to corresponding bit positions;

the updating data generating module is used for generating updating data according to the comparison result; each bit in the updated data is used for representing a comparison result of the to-be-written data and the existing data, when a first bit in the to-be-written data is 0 and a second bit corresponding to the first bit in the existing data is 1, the comparison result of the first bit and the second bit is a first preset value, otherwise, the comparison result is a second preset value;

and the writing module is used for executing data writing operation to the memory according to the bit corresponding to the first preset value in the updating data.

9. An electronic device comprising a processor and a memory storing program instructions, wherein the processor is configured to perform the data writing method of the memory according to any one of claims 1 to 7 when executing the program instructions.

10. A storage medium having stored thereon computer-executable instructions configured to perform a method of writing data to a memory as claimed in any one of claims 1 to 7.