CN111916141B - Flash memory management method and flash memory - Google Patents
Flash memory management method and flash memory Download PDFInfo
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- CN111916141B CN111916141B CN201910619159.4A CN201910619159A CN111916141B CN 111916141 B CN111916141 B CN 111916141B CN 201910619159 A CN201910619159 A CN 201910619159A CN 111916141 B CN111916141 B CN 111916141B
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- 238000007726 management method Methods 0.000 title claims abstract description 22
- 238000000034 method Methods 0.000 claims description 8
- 238000010586 diagram Methods 0.000 description 2
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/38—Response verification devices
- G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
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Abstract
The invention provides a flash memory management method and a flash memory. The flash memory management method comprises the following steps: receiving a first reading instruction to read a first page of a first block, wherein the first block corresponds to a single-level storage mode; when the first block is a data block and the error correction code value of the first page is greater than a first threshold value, performing exchange operation on the first block and the exchange block; and performing swapping operation on the first block and the swap block when the first block is a system block and the number of times of reading the first block is greater than the second threshold or the ECC value of the first page is greater than the third threshold.
Description
Technical Field
The present invention relates to a flash memory management method and a flash memory, and more particularly, to a flash memory management method and a flash memory for handling read disturb.
Background
When a page of the flash memory is read a certain number of times, the Error Correction Code (ECC) value of the read page gradually increases, and the same happens to the adjacent pages of the page. This is because after a large number of read cycles, the memory cells of the flash memory may be soft programmed (soft programmed) to other states, resulting in errors in stored data. The above problem is also called read disturb. Therefore, how to deal with read disturb of flash memory is an objective that should be addressed by those skilled in the art.
Disclosure of Invention
The invention provides a flash memory management method and a flash memory, which can solve the problem of reading interference of the flash memory.
The invention provides a flash memory management method and a flash memory. The flash memory management method comprises the following steps: receiving a first reading instruction to read a first page of a first block, wherein the first block corresponds to a single-level storage mode; when the first block is a data block and the error correction code value of the first page is greater than a first threshold value, performing exchange operation on the first block and the exchange block; and when the first block is a system block and the reading times of the first block are more than a second threshold value or the error correction code value of the first page is more than a third threshold value, exchanging the first block and the exchange block.
The invention provides a flash memory, comprising: the memory unit module comprises a plurality of entity blocks, and each entity block comprises a plurality of entity pages; and the controller is coupled with the storage unit module. The controller receives a first reading instruction to read a first page of a first block, wherein the first block corresponds to a single-level storage mode; when the first block is a data block and the error correction code value of the first page is greater than a first threshold value, performing exchange operation on the first block and the exchange block; and when the first block is a system block and the reading times of the first block are more than a second threshold value or the error correction code value of the first page is more than a third threshold value, exchanging the first block and the exchange block.
Based on the above, the flash memory management method and the flash memory of the invention read the first page of the first block in the single-level storage mode. And performing swapping operation on the first block when the first block is a data block and the ECC value of the first page is greater than a first threshold value. When the first block is a system block and the reading times of the first block are greater than a second threshold value or the ECC value of the first page is greater than a third threshold value, performing swapping operation on the first block. Therefore, the reading interference caused by the increase of the page reading times can be avoided.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
FIG. 1 is a block diagram of a flash memory according to an embodiment of the present invention;
FIG. 2 is a flowchart of reading SLC blocks according to a flash memory management method of an embodiment of the invention;
FIG. 3 is a flowchart of reading TLC blocks according to a flash memory management method of the present invention;
fig. 4 is a flow chart of a block swapping sequence according to an embodiment of the invention.
The reference numbers illustrate:
100: flash memory
110: controller
120: memory cell module
S201 to S207: step of reading SLC block
S301 to S308: step of reading TLC Block
S401 to S405: step of block exchange sequence
Detailed Description
FIG. 1 is a block diagram of a flash memory according to an embodiment of the invention.
Referring to fig. 1, a flash memory 100 according to an embodiment of the invention includes a controller 110 and a memory cell module 120 coupled to the controller 110. The controller 110 may perform management operations with respect to the memory cell module 120. The memory cell module 120 includes a plurality of physical blocks, and each physical block includes a plurality of physical pages. Most of the physical blocks are used to store general data, also called data blocks. A few physical blocks are used to store system data such as page mapping tables, which are also called system blocks. The blocks may be further divided into Single Level Cell block (SLC block) and Triple Level Cell block (TLC block).
In an embodiment, when the controller 110 receives a first read command to read a first page of a first block of the single-level storage mode, the controller 110 first determines that the first block is a data block or a system block. When the first block is a data block, the controller 110 further determines whether the error correction code value (e.g., the number of error bits) of the first page is greater than a first threshold value (e.g., 70% of the maximum number of error bits). When the ECC value of the first page is greater than the first threshold, the controller 110 performs a swap operation on the first block and the swap block (e.g., swap the first block data to an erased new block). When the first block is a system block (i.e., the first block stores page mapping table information), the controller 110 further determines whether the number of times the first block is read is greater than a second threshold or whether the ECC value of the first page is greater than a third threshold. When the number of times of reading the first block is greater than the second threshold or the ECC value of the first page is greater than a third threshold (e.g., 100 ECC bits), the controller 110 performs a swap operation on the first block and the swap block (e.g., swap the first block data to an erased new block).
In one embodiment, when the controller 110 receives a second read command to read a second page of the second block of the third-order memory mode and the ecc check of the second page fails, the controller 110 performs a re-read (re-read) operation on the second page and determines whether the second page passes the ecc check. If the second page passes the ECC check after the re-read operation and the ECC value of the second page is greater than the fourth threshold (e.g., 200 ECC bits), the controller 110 performs a swap operation on the second block and the swap block. If the second page fails the ECC check after the re-read operation, the controller 110 performs a retry (retry) operation on the second page and determines whether the second page after the retry operation passes the ECC check. If the second page passes the ECC check after the retry operation, the controller 110 performs a swap operation on the second block and the swap block (e.g., swap the second block to a cache merge line). It is noted that the retry operation includes changing the read voltage of the second page and reading the second page with the changed read voltage.
Since the number of pages of the block in the third-order memory mode is greater than that of the block in the single-order memory mode, the controller 110 may spend more time performing the block swap operation in the third-order memory mode. Therefore, when another block (e.g., the third block corresponding to the third-order memory mode) is performing the swap operation, the controller 110 may first send the second block to the queue for waiting, and then perform the swap operation of the second block after the third block completes the swap operation. In one embodiment, the controller 110 may prioritize the swapping of important pages of blocks in the queue. The important page is, for example, the second page and the page with the page index value in the same block within a predetermined range before and after the second page (i.e., the neighboring page of the second page). In another embodiment, the system block may have the highest switching priority, the data block may have the next highest switching priority, and the third rank memory mode block has the lowest switching priority. In another embodiment, when the third-order memory mode blocks are switched, the switching operation of the system block or the data block is generated, and after the important pages in the third-order memory mode blocks are switched, the switching operation of the remaining pages except the important pages can be performed after the switching operation of the system block or the data block is finished in the queue and/or after the switching operation of the important pages in other third-order memory mode blocks in the queue is finished.
In addition, the second page after the retry operation passes the error correction code check to indicate that the controller 110 has available the correct data of the second page. Therefore, the controller 110 can perform the swap operation on the second page in advance before the swap operation between the second block and the swap block, that is, immediately after the retry operation passes the ECC check, the swap operation is performed on the second page. The swap operation is started before the first read instruction or the second read instruction ends.
It is noted that although the second block is described as belonging to the third-level memory mode, the invention is not limited thereto. In another embodiment, the second chunk may also belong to a multi-Level Cell (MLC) or a Quad-Level Cell (QLC) that is not a single-Level storage mode.
FIG. 2 is a flow chart of reading a block of SLC (single level cell) according to a flash memory management method of an embodiment of the invention.
Referring to fig. 2, in step S201, a first page of a single-level memory mode block of a flash memory is read.
In step S202, the read block is a data block.
In step S203, it is determined whether the ecc value of the first page is greater than a first threshold.
If the ECC value of the first page is greater than the first threshold, the block is swapped in step S204, and the process ends in step S205. If the ECC value of the first page is not greater than the first threshold, in step S205, the process ends.
In step S206, the read block is a system block.
In step S207, it is determined whether the number of times the block is read is greater than a second threshold or whether the ecc value of the first page is greater than a third threshold. If the number of times the block is read is greater than the second threshold or the ECC value of the first page is greater than the third threshold, the block is swapped in step S204, and the process ends in step S205. If the number of times the block is read is not greater than the second threshold and the ECC value of the first page is not greater than the third threshold, in step S205, the process ends.
Fig. 3 is a flowchart of reading a TLC (third order cell) block according to a flash memory management method of the present invention.
Referring to fig. 3, in step S301, a second page of a third-level block of the flash memory is read.
In step S302, when the error correction code check of the second page fails, a re-reading operation is performed on the second page.
In step S303, it is determined whether the second page passes the error correction code check.
If the second page passes the ECC check after the re-read operation, in step S304, it is determined whether the ECC value of the second page is greater than the fourth threshold.
If the ECC value of the second page is greater than the fourth threshold, the second block and the swap block are swapped in step S305, and the process ends in step S306.
If the ECC value of the second page is not greater than the fourth threshold, in step S306, the process ends.
If the second page fails the ECC check after the re-read operation, in step S307, a retry operation is performed on the second page. Next, in step S308, it is determined whether the second page after the retry operation passes the ECC check.
If the second page after the retry operation passes the ECC check, in step S305, the second block and the swap block are swapped.
If the second page after the retry operation does not pass the ECC check, in step S306, the process ends.
Fig. 4 is a flow chart of a block swapping sequence according to an embodiment of the invention.
Referring to fig. 4, in step S401, the priority of the block to be exchanged is determined according to the block type.
In step S402, the SLC system block has the highest priority.
In step S403, the SLC data block has the next highest priority.
In step S404, the TLC block has the lowest priority.
In step S405, a block swap operation is performed starting from the block with the highest priority.
In summary, the flash memory management method and the flash memory of the present invention read the first page of the first block in the single-level storage mode. And performing swapping operation on the first block when the first block is a data block and the ECC value of the first page is greater than a first threshold value. When the first block is a system block and the reading times of the first block are greater than a second threshold value or the ECC value of the first page is greater than a third threshold value, performing swapping operation on the first block. The flash memory management method and the flash memory can also read the second page of the second block of the third-order storage mode. And when the error correction code value of the second page is larger than the fourth threshold value or the second page after the retry operation passes the error correction code check, exchanging the second block and the exchange block. Therefore, reading interference caused by the increase of the page reading times can be avoided.
Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (10)
1. A method for flash memory management, comprising:
receiving a first reading instruction to read a first page of a first block, wherein the first block corresponds to a single-level storage mode;
when the first block is a data block and the error correction code value of the first page is greater than a first threshold value, performing an exchange operation on the first block and an exchange block; and
and when the first block is a system block and the reading times of the first block are greater than a second threshold value or the error correction code value of the first page is greater than a third threshold value, performing the swapping operation on the first block and the swap block.
2. The flash memory management method of claim 1, further comprising:
receiving a second read instruction to read a second page of a second block, wherein the second block corresponds to a three-level memory mode;
when the error correction code check of the second page fails, re-reading the second page and judging whether the second page passes the error correction code check;
if the second page passes the ECC check after the re-read operation and the ECC value of the second page is greater than a fourth threshold value, performing the swap operation on the second block and the swap block; and
if the second page does not pass the ECC check after the re-reading operation, performing a retry operation on the second page and determining whether the second page passes the ECC check, and if the second page passes the ECC check after the retry operation, performing the swap operation on the second block and the swap block, wherein the retry operation includes changing a read voltage of the second page and reading the second page with the changed read voltage.
3. The flash memory management method of claim 2, further comprising: when the third block corresponding to the third-order storage mode is performing the swap operation, the second block is transmitted to a queue, and the swap operation of the second block is performed after the third block completes the swap operation.
4. The flash memory management method of claim 2, further comprising: when the second page after the retry operation passes the error correction code check, performing the swap operation on the second page before the swap operation of the second block and the swap block.
5. The flash memory management method of claim 2, wherein the swap operation begins before the first read instruction or the second read instruction ends.
6. A flash memory, comprising:
the memory unit module comprises a plurality of entity blocks, and each entity block comprises a plurality of entity pages; and
a controller coupled to the memory cell module, wherein the controller
Receiving a first reading instruction to read a first page of a first block, wherein the first block corresponds to a single-level storage mode;
when the first block is a data block and the error correction code value of the first page is greater than a first threshold value, performing an exchange operation on the first block and an exchange block; and
and when the first block is a system block and the reading times of the first block are greater than a second threshold value or the error correction code value of the first page is greater than a third threshold value, performing the swapping operation on the first block and the swap block.
7. The flash memory of claim 6, wherein the controller receives a second read command to read a second page of a second block, wherein the second block corresponds to a third order memory mode;
when the error correction code check of the second page fails, the controller performs re-reading operation on the second page and judges whether the second page passes the error correction code check;
if the second page passes the ECC check after the re-read operation and the ECC value of the second page is greater than a fourth threshold value, the controller performs the swap operation on the second block and the swap block; and
if the second page does not pass the ECC check after the reread operation, the controller retries the second page and determines whether the second page passes the ECC check, and if the second page passes the ECC check after the retrial operation, the controller performs the swap operation on the second block and the swap block, wherein the retrial operation includes changing a read voltage of the second page and reading the second page with the changed read voltage.
8. The flash memory according to claim 7, wherein the controller transfers the second block to a queue while a third block corresponding to the third rank storage mode is performing the swap operation, and performs the swap operation of the second block after the third block completes the swap operation.
9. The flash memory of claim 7, wherein the controller performs the swap operation on the second page before the swap operation of the second block with the swap block when the second page after the retry operation passes the error correction code check.
10. The flash memory of claim 7, wherein the swap operation begins before the first read instruction or the second read instruction ends.
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| TW108116111A TWI697006B (en) | 2019-05-09 | 2019-05-09 | Flash memory management method and flash memory |
| TW108116111 | 2019-05-09 |
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| CN101252020A (en) * | 2007-02-22 | 2008-08-27 | 海力士半导体有限公司 | Read method of memory device |
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| CN111916141A (en) | 2020-11-10 |
| TW202042246A (en) | 2020-11-16 |
| TWI697006B (en) | 2020-06-21 |
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