CN115580273B - Signal generation circuit, signal generation method and voltage control method - Google Patents

Signal generation circuit, signal generation method and voltage control method Download PDF

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CN115580273B
CN115580273B CN202211569724.9A CN202211569724A CN115580273B CN 115580273 B CN115580273 B CN 115580273B CN 202211569724 A CN202211569724 A CN 202211569724A CN 115580273 B CN115580273 B CN 115580273B
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duty ratio
circuit
sampling
frequency
pulse signal
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CN115580273A (en
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请求不公布姓名
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Moore Thread Intelligent Technology Chengdu Co ltd
Moore Threads Technology Co Ltd
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Moore Thread Intelligent Technology Chengdu Co ltd
Moore Threads Technology Co Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/04—Shaping pulses by increasing duration; by decreasing duration
    • H03K5/05—Shaping pulses by increasing duration; by decreasing duration by the use of clock signals or other time reference signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K7/00—Modulating pulses with a continuously-variable modulating signal
    • H03K7/08—Duration or width modulation ; Duty cycle modulation

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Abstract

The disclosure relates to the field of signal control and discloses a signal generation circuit, a signal generation method and a voltage control method. The signal generating circuit comprises a duty ratio correcting circuit and a PWM pulse signal control circuit, the duty ratio correcting circuit corrects the expected duty ratio, the PWM pulse signal control circuit generates a control signal according to the corrected duty ratio, the expected frequency and the clock pulse signal, and the output circuit is controlled to output the PWM pulse signal according to the control signal. By correcting the duty ratio, an error between the actually output duty ratio and the desired duty ratio is reduced, thereby reducing an error between the output PWM pulse signal and the desired PWM pulse signal.

Description

Signal generating circuit, signal generating method and voltage control method
Technical Field
The present disclosure relates to the field of signal control, and in particular, to a signal generating circuit, a signal generating method, and a voltage control method.
Background
In a personal computer or a server, a fan is generally used to dissipate heat from the computer or the server, and a System Management Controller (SMC) of the computer or a Baseboard Management Controller (BMC) of the server outputs a Pulse Width Modulation (PWM) signal to control a wind speed of the fan, so as to dissipate heat properly.
This section is intended to provide a background or context to the disclosed embodiments as recited in the claims. The description herein is not admitted to be prior art by inclusion in this section.
Disclosure of Invention
The inventor finds that the duty ratio and frequency of the output PWM signal have some error with the desired duty ratio and desired frequency, which is mainly caused by the following three aspects: on the first hand, an 8-bit (bit) register is generally used for storing the expected duty ratio, the numerator and the denominator of the expected duty ratio are values from 0 to 255, and the denominator of the actually output duty ratio is 256 due to the hardware design, so that errors exist between the actually output duty ratio and the expected duty ratio; in a second aspect, the output PWM signal is based on the clock pulse signal, that is, the clock pulse needs to be sampled, and when determining the number of samples, the quotient between the clock frequency and the desired frequency, that is, the frequency division coefficient, is first calculated, and then the frequency division coefficient is rounded down to obtain the number of samples, thereby causing an error between the actual frequency and the desired frequency; in the third aspect, when determining the number of high-level clock pulses, it is necessary to re-round a number obtained by multiplying the actually output duty ratio by the number of samples, thereby causing an error.
To solve at least one of the above-described problems or other similar problems, embodiments of the present disclosure provide a signal generation circuit, a signal generation method, and a voltage control method.
The disclosed embodiment provides a signal generating circuit, which comprises:
an input circuit configured to receive a clock pulse signal;
an output circuit configured to output a PWM pulse signal;
the duty ratio correction circuit is configured to correct a desired duty ratio to obtain a corrected duty ratio, the desired duty ratio is stored in a register with a preset number of bits in advance, a denominator of the desired duty ratio is a maximum value corresponding to the preset number of bits, and a numerator of the desired duty ratio ranges from 0 to the maximum value; and
a PWM pulse signal control circuit configured to generate a control signal according to the correction duty ratio output by the duty ratio correction circuit, a desired frequency, and the clock pulse signal, and to control the output circuit to output the PWM pulse signal according to the control signal.
The disclosed embodiment also provides a signal generating circuit, which includes:
an input circuit configured to receive a clock pulse signal;
an output circuit configured to output a PWM pulse signal; and
a PWM pulse signal control circuit configured to generate a control signal according to a desired duty ratio, a desired frequency, and the clock pulse signal, control the output circuit to output the PWM pulse signal according to the control signal,
the PWM pulse signal control circuit includes:
a sampling number calculation circuit configured to calculate a division coefficient from the desired frequency and a clock frequency of the clock pulse signal, calculate a sampling number from the division coefficient;
a sampling circuit connected to the input circuit and the sampling number calculation circuit, and configured to sample the clock pulse signal according to the sampling number;
and the pulse control circuit is connected with the sampling number calculation circuit and the sampling circuit, and is configured to calculate the number of high-level clock pulses according to the expected duty ratio and the sampling number, generate the control signal according to the number of the high-level clock pulses and the clock pulse signal acquired by the sampling circuit, and control the output circuit to output the PWM pulse signal according to the control signal.
The embodiment of the present disclosure further provides a signal generating method, where the signal generating method includes: correcting the expected duty ratio to obtain a corrected duty ratio; calculating a sampling number according to the expected frequency and the clock frequency of the clock pulse signal, and sampling the clock pulse signal according to the sampling number; calculating the number of corrected high-level clock pulses according to the correction duty ratio and the sampling number; generating a control signal according to the corrected high-level clock pulse number and the acquired clock pulse signal; and generating a PWM pulse signal according to the control signal.
The embodiment of the present disclosure further provides a signal generating method, where the signal generating method includes: calculating a frequency division coefficient according to the expected frequency and the clock frequency of the clock pulse signal, and obtaining a sampling number according to the frequency division coefficient; sampling the clock pulse signal according to the sampling number; calculating the number of high-level clock pulses according to the expected duty ratio and the sampling number; generating a control signal according to the number of the high-level clock pulses and the collected clock pulse signals; and generating a PWM pulse signal according to the control signal.
The embodiment of the present disclosure further provides a voltage control method, where the voltage control method includes: correcting the expected duty ratio to obtain a corrected duty ratio; calculating a sampling number according to the expected frequency and the clock frequency of the clock pulse signal, and sampling the clock pulse signal according to the sampling number; calculating the number of corrected high-level clock pulses according to the correction duty ratio and the sampling number; generating a control signal according to the number of the corrected high-level clock pulses and the acquired clock pulse signal; generating a PWM pulse signal according to the control signal; and controlling a voltage signal for driving a load according to the PWM pulse signal.
The embodiment of the present disclosure further provides a voltage control method, where the voltage control method includes: calculating a frequency division coefficient according to the expected frequency and the clock frequency of the clock pulse signal, and obtaining a sampling number according to the frequency division coefficient; sampling the clock pulse signal according to the sampling number; calculating the number of high-level clock pulses according to the expected duty ratio and the sampling number; generating a control signal according to the number of the high-level clock pulses and the acquired clock pulse signals; generating a PWM pulse signal according to the control signal; and controlling a voltage signal for driving a load according to the PWM pulse signal.
The embodiment of the present disclosure further provides a computer device, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor, and the processor implements the signal generation method or the voltage control method when executing the computer program.
An embodiment of the present disclosure also provides a computer-readable storage medium storing a computer program, which when executed by a processor implements the above-mentioned signal generation method or voltage control method.
In the embodiment of the present disclosure, by correcting the duty ratio, an error between the actually output duty ratio and the desired duty ratio is reduced, thereby reducing an error between the output PWM pulse signal and the desired PWM pulse signal.
Drawings
In order to more clearly illustrate the embodiments of the present disclosure or technical solutions in related arts, the drawings used in the description of the embodiments or related arts will be briefly introduced below, it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative efforts. In the drawings:
fig. 1 is a schematic diagram of a signal generating circuit of an embodiment of a first aspect of the present disclosure.
Fig. 2 is another schematic diagram of a signal generating circuit of an embodiment of the first aspect of the present disclosure.
Fig. 3 is a schematic diagram of calculating a correction duty cycle according to an embodiment of the first aspect of the present disclosure.
Fig. 4 is a schematic diagram of the desired duty cycle and the error of the corrected duty cycle and the actual output duty cycle of an embodiment of the first aspect of the present disclosure.
Fig. 5 is yet another schematic diagram of a signal generating circuit of an embodiment of the first aspect of the present disclosure.
Fig. 6 is yet another schematic diagram of a signal generating circuit of an embodiment of the first aspect of the present disclosure.
Fig. 7 is yet another schematic diagram of a signal generating circuit of an embodiment of the first aspect of the present disclosure.
Fig. 8 is a schematic diagram of a signal generation method of an embodiment of a second aspect of the disclosure.
Fig. 9 is a schematic diagram of a voltage control method of an embodiment of a third aspect of the present disclosure.
Fig. 10 is a schematic diagram of an application of a voltage control method of an embodiment of a third aspect of the present disclosure.
Detailed Description
To make the objects, technical solutions and advantages of the embodiments of the present disclosure more clearly understood, the embodiments of the present disclosure are further described in detail below with reference to the accompanying drawings. The exemplary embodiments of the present disclosure and their description are provided herein for the purpose of explanation, but not limitation, of the disclosure.
Embodiments of the first aspect
Embodiments of the first aspect of the present disclosure provide a signal generating circuit, which can be used in any device or apparatus that needs to generate a PWM pulse signal. The signal generating circuit includes:
an input circuit configured to receive a clock pulse signal;
an output circuit configured to output a PWM pulse signal;
the duty ratio correction circuit is configured to correct a desired duty ratio to obtain a corrected duty ratio, the desired duty ratio is stored in a register with a preset number of bits in advance, a denominator of the desired duty ratio is a maximum value corresponding to the preset number of bits, and a numerator of the desired duty ratio ranges from 0 to the maximum value; and
a PWM pulse signal control circuit configured to generate a control signal according to the correction duty ratio output by the duty ratio correction circuit, a desired frequency, and the clock pulse signal, and to control the output circuit to output the PWM pulse signal according to the control signal.
The signal control circuit of the embodiment of the present disclosure reduces an error between an actually output duty ratio and a desired duty ratio by correcting the duty ratio, thereby reducing an error between an output PWM pulse signal and a desired PWM pulse signal.
Fig. 1 is a schematic diagram of a signal generating circuit of an embodiment of a first aspect of the present disclosure.
As shown in fig. 1, the signal generating circuit 1 may include an input circuit 11, an output circuit 12, and a PWM pulse signal control circuit 13, the PWM pulse signal control circuit 13 being connected to the input circuit 11 and the output circuit 12, respectively.
The input circuit 11 is used for receiving a CLOCK signal CLOCK having a frequency f clock . The CLOCK signal CLOCK is generated by, for example, a timer (timer) in a device or an apparatus, which may refer to the related art, and the embodiment of the disclosure does not limit this.
PWM pulse signal control circuit 13According to the input duty ratio D and the expected frequency f exp And a clock pulse signal generation control signal S ctr Control signal S ctr For controlling the output circuit 12 to output the PWM pulse signal S PWM . Duty cycle D and desired frequency f exp The information may be stored in advance, or may be input by a user in real time, and may be specifically set according to actual needs, which is not limited in the embodiment of the present disclosure.
In at least one embodiment, the duty cycle D may be a desired duty cycle or may be a corrected duty cycle after correcting the desired duty cycle.
Fig. 2 is another schematic diagram of a signal generation circuit of an embodiment of the first aspect of the present disclosure.
As shown in fig. 2, the signal generation circuit 2 may include a duty correction circuit 24.
In at least one embodiment, the duty cycle correction circuit 24 may correct the desired duty cycle D exp Correcting to obtain corrected duty ratio D cor The PWM pulse signal control circuit 13 corrects the duty ratio D according to the output of the duty ratio correction circuit 24 cor Desired frequency f exp And a clock pulse signal generation control signal S ctr Control the output circuit 12 to output the PWM pulse signal S PWM 。
In at least one embodiment, the desired duty ratio is pre-stored in a register with a predetermined number of bits, for example, the register is an 8-bit register, but the embodiment of the present disclosure is not limited thereto, and the register may also be 4 bits or other bits, and may be specifically designed according to actual needs.
The following describes the embodiments of the present disclosure by taking an 8-bit register as an example, but the embodiments of the present disclosure are not limited thereto, and those skilled in the art should understand that when other bit registers are used, the embodiments of the present disclosure can still be implemented correspondingly according to the principles of the embodiments of the present disclosure.
For example, in an 8-bit register, the denominator of the desired duty cycle is stored as 255 (i.e., an 8-bit sized decimal number), and the numerator of the desired duty cycle ranges from 0 to 255. However, due to hardware design, the denominator of the duty ratio output from the register is 256, and the numerator is not changed, so that the actual output duty ratio has inevitable error from the expected duty ratio.
Thus, by correcting the duty ratio input to the PWM pulse signal control circuit 13 by the duty ratio correction circuit 24, it is possible to reduce the error between the duty ratio of the PWM signal actually output and the desired duty ratio, and thus reduce the error between the output PWM pulse signal and the desired PWM pulse signal.
In some optional embodiments, the duty cycle correction circuit is configured to determine, as the correction duty cycle, a value obtained by adding 1 to a numerator of the desired duty cycle when the desired duty cycle is greater than 1/2.
Illustratively, at a desired duty cycle D exp Greater than 1/2, the duty cycle correction circuit 24 may adjust the desired duty cycle D exp Is added by 1 to obtain the corrected duty ratio D cor . This enables the correction duty to be obtained quickly. The embodiment can be applied to scenes with high response speed requirements.
For example, for a desired duty cycle D stored in an 8-bit register exp In other words, when D exp When the duty ratio is larger than 127/255, the correction duty ratio D calculated by the duty ratio correction circuit 24 cor Is D exp + (1/255). In addition, for example for a desired duty cycle D stored in a 4-bit register exp To say, when D is exp When the duty ratio is more than 7/15, the correction duty ratio D calculated by the duty ratio correction circuit 24 cor Is D exp + (1/15). And so on for other bit registers.
Furthermore, at the desired duty cycle D exp Less than or equal to 1/2, the duty cycle correction circuit 24 may output the desired duty cycle D exp As corrected duty cycle D cor . For example, when D exp Less than or equal to 127/255, the desired duty cycle D is not satisfied exp Carrying out correction; in addition, when D exp Equal to 127/255, 128/255 can be used as the correction duty ratio D cor And (6) outputting.
Fig. 3 is a schematic diagram of calculating a correction duty cycle of an embodiment of the first aspect of the present disclosure, and fig. 4 is a schematic diagram of errors of a desired duty cycle and the correction duty cycle with an actual output duty cycle of an embodiment of the first aspect of the present disclosure.
As shown in FIG. 3, for example, the duty cycle correction circuit 24 determines the desired duty cycle D exp If the molecular weight of (1) is less than 127, no correction is carried out when the molecular weight of (1) is less than 127, so that the actually output duty ratio is 0/256 to 126/256, and if the molecular weight of (1) is more than or equal to 127, the actually output duty ratio is 128/256 to 256/256.
As shown in fig. 4, the dotted line indicates an error between the desired duty ratio and the actually output duty ratio when the duty ratio is not corrected, and the solid line indicates an error between the duty ratio obtained by adding 1 to the numerator of the desired duty ratio and the actually output duty ratio. Wherein, the horizontal axis Vid is a molecule, and the vertical axis Accuracy represents an error.
As shown in fig. 4, after the correction shown in fig. 3 is performed, the error between the actually output duty ratio and the desired duty ratio is limited to the triangular region a, and thus, by limiting the error between the actually output duty ratio and the desired duty ratio, the error between the output PWM pulse signal and the desired PWM pulse signal can be limited.
Fig. 5 is yet another schematic diagram of a signal generating circuit of an embodiment of the first aspect of the present disclosure.
In at least one embodiment, as shown in fig. 5, the signal generation circuit 5 may include a duty cycle correction circuit 54. Wherein the duty cycle correction circuit 54 calculates the desired duty cycle D exp Before and after the molecule of (2) corresponds to the first duty ratio D 1 And a second duty cycle D 2 Calculating a first duty ratio D 1 And a second duty cycle D 2 Corresponding first output duty cycle D 1 ' and second output duty cycle D 2 ', selecting a first output duty cycle D 1 ' and second output duty cycle D 2 Closer to the desired duty cycle D exp First duty ratio D corresponding to one of 1 Or the second duty cycle D 2 As corrected duty cycle D cor . That is, the first output duty cycle D is selected 1 ' and second output duty cycle D 2 ' intermediate and desired duty cycleD exp The smaller difference value.
First output duty cycle D 1 ' and second output duty cycle D 2 The numerator of' is respectively associated with a first duty cycle D 1 And a second duty cycle D 2 Is the same, the first output duty cycle D 1 ' and second output duty cycle D 2 The denominator of' is respectively greater than the first duty ratio D 1 And a second duty cycle D 2 The denominator of (a) is 1.
E.g. at a desired duty cycle D exp Calculation of correction duty cycle D for duty cycle correction circuit 54 for the example of 25/255 cor To illustrate, the duty correction circuit 54 calculates the desired duty ratio D exp Before and after the first duty ratio D corresponding to the front and back values of the molecule 1 And a second duty cycle D 2 Respectively (25-1)/255 and (25 + 1)/255, a first output duty ratio D 1 ' and second output duty cycle D 2 ' 24/(255 + 1) and 26/(255 + 1) respectively, comparing which one of 24/(255 + 1) and 26/(255 + 1) is closer to the desired duty ratio 25/255, with the result that 26/(255 + 1) is closer to the desired duty ratio 25/255, and the duty correction circuit 54 selects the second duty ratio D 2 I.e. 26/255 as corrected duty cycle D cor 。
Thus, by selecting a duty ratio at which the actual output duty ratio is closer to the desired duty ratio as the correction duty ratio, the error between the output PWM pulse signal and the desired PWM pulse signal is further reduced.
In at least one embodiment, as shown in fig. 2, the signal generating circuit 2 further includes an input circuit 11, an output circuit 12, and a PWM pulse signal control circuit 13. As shown in fig. 5, the signal generation circuit 5 further includes an input circuit 11, an output circuit 12, and a PWM pulse signal control circuit 13.
The functions of the input circuit 11, the output circuit 12, and the PWM pulse signal control circuit 13 in fig. 2 and fig. 5 are the same as or similar to the functions of the input circuit 11, the output circuit 12, and the PWM pulse signal control circuit 13 in fig. 1, and reference may be made to the foregoing specifically, and details are not repeated here.
In addition, it should be noted that, in the embodiment of the present disclosure, a part identified by the same or similar reference numerals indicates that the part may implement the same or similar function, for example, the input circuit 11 in fig. 1 has the same function as the input circuit 11 in fig. 2, the pulse control circuit 133 in fig. 1 has the same or similar function as the pulse control circuit 233 in fig. 2 and 5, and the like. This is not specifically described in the following examples unless otherwise stated.
In at least one embodiment, as shown in fig. 1, the PWM pulse signal control circuit 13 may include a sampling number calculation circuit 131, a sampling circuit 132, and a pulse control circuit 133.
The sampling number calculating circuit 131 calculates the frequency f according to the desired frequency exp And the clock frequency f of the clock pulse signal clock Calculating a frequency division coefficient N, and calculating a sampling number N according to the frequency division coefficient N sample 。
The sampling circuit 132 is connected to the input circuit 11 and the sampling number calculation circuit 131, and calculates the number of samples N sample The CLOCK signal CLOCK is sampled.
The pulse control circuit 133 is connected to the sampling number calculation circuit 131 and the sampling circuit 132, and is based on the duty ratio D and the sampling number N sample Calculating the number H of high-level clock pulses, and generating a control signal S based on the number H of high-level clock pulses and the clock pulse signal collected by the sampling circuit 132 ctr Controlling the output circuit 12 to output the PWM pulse signal S PWM 。
In at least one embodiment, the sample number calculation circuit 131 may, for example, round the sample number N sample . Thus, the number of samples N is obtained by rounding the frequency-division coefficient N sample The error between the actual frequency from rounding down to the number of samples and the desired frequency can be reduced.
In at least one embodiment, as shown in fig. 2 and 5, the PWM pulse signal control circuit 13 may include a sampling number calculation circuit 131, a sampling circuit 132, and a pulse control circuit 233. The functions of the sampling number calculating circuit 131 and the sampling circuit 132 are the same as those of the sampling number calculating circuit 131 and the sampling circuit 132 in fig. 1, and reference may be made to the foregoing specifically, which is not described herein again.
In at least one embodiment, the pulse control circuit 233 can be configured to output a corrected duty cycle D according to the duty cycle correction circuit 24 (shown in FIG. 2) or the duty cycle correction circuit 54 (shown in FIG. 5) cor And the number of samples N sample Calculating and correcting high-level clock pulse number H cor According to the number H of corrected high-level clock pulses cor And a clock pulse signal generation control signal S collected by the sampling circuit 132 ctr Control the output circuit 12 to output the PWM pulse signal S PWM 。
Fig. 6 is yet another schematic diagram of a signal generating circuit of an embodiment of the first aspect of the present disclosure.
In at least one embodiment, as shown in fig. 6, the signal generation circuit 6 may include an input circuit 11, an output circuit 12, a PWM pulse signal control circuit 13, a frequency calculation circuit 65, and a proportion calculation circuit 66.
The PWM pulse signal control circuit 13 includes a sampling number calculation circuit 631, a sampling circuit 632, and a pulse control circuit 633.
As shown in fig. 6, the sampling number calculating circuit 631 obtains the second sampling number N by respectively rounding down and rounding up the frequency dividing coefficient N sample2 And a third number of samples N sample3 The frequency calculating circuit 65 calculates and compares the second sampling number N with the first sampling number N sample2 And a third number of samples N sample3 Second pulse frequency f corresponding to equal frequency division coefficient 2 And a third pulse frequency f 3 (ii) a The ratio calculation circuit 66 calculates the second pulse frequency f 2 And a third pulse frequency f 3 So that the second pulse frequency f is mixed in proportion to n/m 2 And a third pulse frequency f 3 Resulting mixed pulse frequency and desired frequency f exp Are equal.
The sampling circuit 632 samples the ratio N/m calculated by the ratio calculation circuit 66 by a second sampling number N sample2 And a third number of samples N sample3 Sampling a CLOCK pulse signal CLOCK; pulse control circuit 633 according to a desired duty cycle D exp And a second number of samples N sample2 Calculating the second highest powerNumber of flat clock pulses H 2 According to the desired duty cycle D exp And a third number of samples N sample3 Calculating the number H of the third high level clock pulses 3 According to the number H of second high level clock pulses 2 And by the sampling circuit 632 according to a second number of samples N sample2 The collected clock pulse signal and the number H of the third high level clock pulse 3 And a third number of samples N by the sampling circuit 632 sample3 The collected clock pulse signals respectively generate second control signals S ctr2 And a third control signal S ctr3 Controlling the output circuit 12 to output the PWM pulse signal S PWM 。
Thus, the error between the output PWM pulse signal and the desired PWM pulse signal can be further reduced by mixing PWM pulses of different frequencies.
Fig. 7 is yet another schematic diagram of a signal generating circuit of an embodiment of the first aspect of the present disclosure.
In at least one embodiment, as shown in fig. 7, the signal generation circuit 7 may include an input circuit 11, an output circuit 12, a PWM pulse signal control circuit 13, a frequency calculation circuit 75, and a proportion calculation circuit 76.
The PWM pulse signal control circuit 13 includes a sampling number calculation circuit 631, a sampling circuit 632, and a pulse control circuit 733.
As shown in fig. 7, the sampling number calculating circuit 631 obtains the second sampling number N by respectively rounding down and rounding up the frequency dividing coefficient N sample2 And a third number of samples N sample3 The frequency calculation circuit 65 calculates the second sampling number N respectively sample2 And a third number of samples N sample3 Second pulse frequency f corresponding to equal frequency division coefficient 2 And a third pulse frequency f 3 (ii) a The ratio calculation circuit 66 calculates the second pulse frequency f 2 And a third pulse frequency f 3 So that the second pulse frequency f is mixed in proportion to n/m 2 And a third pulse frequency f 3 Resulting mixed pulse frequency and desired frequency f exp Equal; the sampling circuit 632 samples the second number of samples N according to the ratio N/m calculated by the ratio calculation circuit 66 sample2 And a third number of samples N sample3 The CLOCK signal CLOCK is sampled.
As shown in fig. 7, the signal generating circuit 7 may further include a duty ratio correcting circuit 74, and the duty ratio correcting circuit 74 corrects the desired duty ratio D exp Correcting to obtain corrected duty ratio D cor 。
The pulse control circuit 733 is operated in accordance with the correction duty ratio D cor And a second number of samples N sample2 Calculating the number Hcor of second corrected high level clock pulses 2 According to the correction duty ratio D cor And a third number of samples N sample3 Calculating the third corrected high level clock pulse number Hcor3, and calculating the second corrected high level clock pulse number Hcor 2 And by the sampling circuit 632 according to the second sampling number N sample2 The collected clock pulse signal, and the number Hcor3 of high-level clock pulses according to the third correction and the third sampling number N by the sampling circuit 632 sample3 The collected clock pulse signals respectively generate second control signals S ctr2 And a third control signal S ctr3 Controlling the output circuit 12 to output the PWM pulse signal S PWM 。
The duty correction circuit 74 in fig. 7 may be the duty correction circuit 24 shown in fig. 2, or may be the duty correction circuit 54 shown in fig. 5.
In addition, in the above embodiment, the example that PWM pulses of two different frequencies are mixed to obtain PWM pulses approximately equal to the desired frequency is taken as an example for explanation, but the embodiment of the present disclosure is not limited thereto, and PWM pulses approximately equal to the desired frequency may also be obtained by mixing PWM pulses of three or more different frequencies.
In at least one embodiment, the signal generating circuit 7 may further store the desired duty ratio corresponding to the actually measured voltage of the PWM pulse signal, for example, in NOR Flash, for the convenience of user's invocation; or the display device can be controlled to display the expected duty ratio and the actual voltage of the corresponding PWM pulse signal. Therefore, the user can intuitively know whether the output pulse signal achieves the expected effect. And a convenient and fast learning way can be provided for a user under the condition that the actual voltage of the PWM pulse signal cannot be measured in real time.
In addition, the application scenarios of the signal generating circuit are not limited in the embodiments of the present disclosure, and may be implemented alone or in combination according to actual needs. For example, the signal generating circuit 1 can be applied to a case where a demand for calculation speed is high; the signal generation circuit 2 and the signal generation circuit 5 can be applied to the case where the frequency division coefficient is smaller than 255; the signal generation circuit 5, the signal generation circuit 6, and the signal generation circuit 7 can be applied to a case where the accuracy requirement for the PWM pulse signal is high.
According to an embodiment of the first aspect, by correcting the duty ratio, an error between the actually output duty ratio and the desired duty ratio is reduced, thereby reducing an error between the output PWM pulse signal and the desired PWM pulse signal.
The embodiment of the present disclosure also provides a signal generating circuit, which can be used in any device or apparatus that needs to generate a PWM pulse signal. The signal generating circuit includes:
an input circuit configured to receive a clock pulse signal;
an output circuit configured to output a PWM pulse signal; and
a PWM pulse signal control circuit configured to generate a control signal according to a desired duty ratio, a desired frequency, and the clock pulse signal, control the output circuit to output the PWM pulse signal according to the control signal,
the PWM pulse signal control circuit includes:
a sampling number calculation circuit configured to calculate a frequency division coefficient from the desired frequency and a clock frequency of the clock pulse signal, and calculate a sampling number from the frequency division coefficient;
a sampling circuit connected to the input circuit and the sampling number calculation circuit, and configured to sample the clock pulse signal according to the sampling number;
and the pulse control circuit is connected with the sampling number calculation circuit and the sampling circuit, and is configured to calculate the number of high-level clock pulses according to the expected duty ratio and the sampling number, generate the control signal according to the number of the high-level clock pulses and the clock pulse signal acquired by the sampling circuit, and control the output circuit to output the PWM pulse signal according to the control signal.
The signal generation circuit of the embodiment of the disclosure can reduce the error between the output PWM pulse signal and the expected PWM pulse signal.
In some alternative embodiments, the first and second electrodes may be, among other things,
the desired duty ratio is stored in a register with a predetermined number of bits in advance, the denominator of the desired duty ratio is a maximum value corresponding to the predetermined number of bits, the numerator of the desired duty ratio ranges from 0 to the maximum value,
the signal generating circuit further includes:
a duty cycle correction circuit configured to correct the desired duty cycle to obtain a corrected duty cycle;
the pulse control circuit is configured to calculate the number of correction high-level clock pulses according to the correction duty ratio output by the duty ratio correction circuit and the sampling number, generate the control signal according to the number of correction high-level clock pulses and the clock pulse signal acquired by the sampling circuit, and control the output circuit to output the PWM pulse signal according to the control signal.
In some optional embodiments, the duty cycle correction circuit is configured to determine, as the correction duty cycle, a value obtained by adding 1 to a numerator of the desired duty cycle in a case where the desired duty cycle is greater than 1/2.
In some optional embodiments, the duty correction circuit is configured to calculate a first duty ratio and a second duty ratio corresponding to preceding and following values of a numerator of the desired duty ratio, calculate a first output duty ratio and a second output duty ratio corresponding to the first duty ratio and the second duty ratio, select the first duty ratio or the second duty ratio corresponding to one of the first output duty ratio and the second output duty ratio which is closer to the desired duty ratio as the correction duty ratio,
wherein numerators of the first and second output duty cycles are respectively the same as numerators of the first and second duty cycles, and denominators of the first and second output duty cycles are respectively greater than denominators of the first and second duty cycles by 1.
In some optional embodiments, the sampling number calculation circuit is configured to round the division coefficient to obtain the sampling number.
In some optional embodiments, the sampling number calculation circuit is configured to obtain the second sampling number and the third sampling number by rounding down and rounding up respectively for the division coefficient,
the signal generating circuit further includes:
a frequency calculation circuit configured to calculate a second pulse frequency and a third pulse frequency corresponding to a frequency division coefficient equal to the second sampling number and the third sampling number, respectively; and
a ratio calculation circuit configured to calculate a ratio of the second pulse frequency to the third pulse frequency such that a mixed pulse frequency obtained by mixing the second pulse frequency and the third pulse frequency in the ratio is equal to the desired frequency;
the sampling circuit configured to sample the clock pulse signal by the second sampling number and the third sampling number in accordance with the ratio calculated by the ratio calculation circuit;
the pulse control circuit is configured to calculate a second number of high-level clock pulses according to the desired duty ratio and the second number of samples, calculate a third number of high-level clock pulses according to the desired duty ratio and the third number of samples, generate a second control signal according to the second number of high-level clock pulses and the clock pulse signal collected by the sampling circuit according to the second number of samples, generate a third control signal according to the third number of high-level clock pulses and the clock pulse signal collected by the sampling circuit according to the third number of samples, and control the output circuit to output the PWM pulse signal according to the second control signal and the third control signal.
In some optional embodiments, the sampling number calculation circuit is configured to obtain the second sampling number and the third sampling number by rounding down and rounding up respectively for the division coefficient,
the signal generating circuit further includes:
a frequency calculation circuit configured to calculate a second pulse frequency and a third pulse frequency corresponding to a frequency division coefficient equal to the second sampling number and the third sampling number, respectively; and
a ratio calculation circuit configured to calculate a ratio of the second pulse frequency to the third pulse frequency such that a mixed pulse frequency obtained by mixing the second pulse frequency and the third pulse frequency in the ratio is equal to the desired frequency;
the sampling circuit configured to sample the clock pulse signal by the second sampling number and the third sampling number in accordance with the ratio calculated by the ratio calculation circuit;
the pulse control circuit is configured to calculate a second number of corrected high-level clock pulses from the correction duty ratio and the second number of samples, calculate a third number of corrected high-level clock pulses from the correction duty ratio and the third number of samples, generate a second control signal from the second number of corrected high-level clock pulses and the clock pulse signal collected by the sampling circuit according to the second number of samples, generate a third control signal from the third number of corrected high-level clock pulses and the clock pulse signal collected by the sampling circuit according to the third number of samples, and control the output circuit to output the PWM pulse signal according to the second control signal and the third control signal.
The implementation of the signal generating circuit is as described above, and is not described herein again.
Embodiments of the second aspect
Embodiments of the second aspect of the present disclosure provide a signal generation method having the same principle as the signal generation circuit described in embodiments of the first aspect, and the same contents are incorporated herein.
The signal generating method comprises the following steps:
correcting the expected duty ratio to obtain a corrected duty ratio;
calculating a sampling number according to the expected frequency and the clock frequency of the clock pulse signal, and sampling the clock pulse signal according to the sampling number;
calculating the number of corrected high-level clock pulses according to the correction duty ratio and the sampling number;
generating a control signal according to the corrected high-level clock pulse number and the acquired clock pulse signal; and
and generating a PWM pulse signal according to the control signal.
By the signal generation method of the embodiment of the disclosure, the duty ratio is corrected, and the error between the actually output duty ratio and the expected duty ratio is reduced, so that the error between the output PWM pulse signal and the expected PWM pulse signal is reduced.
The disclosed embodiments also provide a signal generation method, which has the same principle as the signal generation circuit described in the embodiments of the first aspect, and the same contents are incorporated herein.
The signal generating method comprises the following steps:
calculating a frequency division coefficient according to the expected frequency and the clock frequency of the clock pulse signal, and obtaining a sampling number according to the frequency division coefficient;
sampling the clock pulse signal according to the sampling number;
calculating the number of high-level clock pulses according to the expected duty ratio and the sampling number;
generating a control signal according to the number of the high-level clock pulses and the collected clock pulse signals; and
and generating a PWM pulse signal according to the control signal.
By the signal generation method of the embodiment of the disclosure, the error between the output PWM pulse signal and the desired PWM pulse signal can be reduced.
Fig. 8 is a schematic diagram of a signal generation method of an embodiment of the present disclosure.
As shown in fig. 8, the signal generation method 800 may include:
step 801: calculating a frequency division coefficient according to the expected frequency and the clock frequency of the clock pulse signal, and obtaining a sampling number by rounding the frequency division coefficient;
step 802: sampling the clock pulse signal according to the sampling number;
step 803: calculating the number of high-level clock pulses according to the expected duty ratio and the sampling number;
step 804: generating a control signal according to the number of the high-level clock pulses and the collected clock pulse signals;
step 805: and generating a PWM pulse signal according to the control signal.
Thus, by rounding the frequency-dividing coefficient to obtain the sample number, it is possible to reduce the error between the actual frequency and the desired frequency due to rounding down the sample number, thereby reducing the error between the output PWM pulse signal and the desired PWM pulse signal.
In at least one embodiment, the signal generating method may further include: correcting the expected duty ratio to obtain a corrected duty ratio; calculating a sampling number according to the expected frequency and the clock frequency of the clock pulse signal, and sampling the clock pulse signal according to the sampling number; calculating the number of corrected high-level clock pulses according to the correction duty ratio and the sampling number; generating a control signal according to the corrected high-level clock pulse number and the acquired clock pulse signal; and generating a PWM pulse signal according to the control signal.
Thus, by correcting the duty ratio, the error between the desired duty ratio and the actual duty ratio is reduced, thereby reducing the error between the output PWM pulse signal and the desired PWM pulse signal.
In at least one embodiment, the signal generating method may further include: calculating a frequency division coefficient according to the expected frequency and the clock frequency of the clock pulse signal, and respectively adopting a downward rounding mode and an upward rounding mode to the frequency division coefficient to obtain a second sampling number and a third sampling number; calculating a second pulse frequency and a third pulse frequency corresponding to a frequency division coefficient equal to the second sampling number and the third sampling number according to the second sampling number and the third sampling number; calculating a ratio of the second pulse frequency to the third pulse frequency such that a mixed pulse frequency resulting from mixing the second pulse frequency and the third pulse frequency in the ratio is equal to the desired frequency; sampling the clock pulse signal by the second sampling number and the third sampling number according to the proportion; calculating the number of second high-level clock pulses according to the expected duty ratio and the second sampling number, and calculating the number of third high-level clock pulses according to the expected duty ratio and the third sampling number; generating a second control signal according to the number of the second high-level clock pulses and the clock pulse signal acquired according to the second sampling number, and generating a third control signal according to the number of the third high-level clock pulses and the clock pulse signal acquired according to the third sampling number; and generating a PWM pulse signal according to the second control signal and the third control signal.
Thus, by mixing PWM pulses of different frequencies, it is possible to reduce an error between a desired frequency and a frequency of a pulse signal actually output, thereby reducing an error between the output PWM pulse signal and the desired PWM pulse signal.
According to the embodiment of the second aspect, by correcting the duty ratio, the error between the actually output duty ratio and the desired duty ratio is reduced, thereby reducing the error between the output PWM pulse signal and the desired PWM pulse signal.
Examples of the third aspect
Embodiments of the third aspect of the present disclosure provide a voltage control method including the same contents as the signal generation method described in embodiments of the second aspect, and the same contents are incorporated herein.
The voltage control method comprises the following steps:
correcting the expected duty ratio to obtain a corrected duty ratio;
calculating a sampling number according to the expected frequency and the clock frequency of the clock pulse signal, and sampling the clock pulse signal according to the sampling number;
calculating the number of corrected high-level clock pulses according to the correction duty ratio and the sampling number;
generating a control signal according to the number of the high-level clock pulses and the collected clock pulse signals;
generating a PWM pulse signal according to the control signal; and
and controlling a voltage signal for driving a load according to the PWM pulse signal.
Embodiments of the present disclosure also provide a voltage control method, which includes the same contents as the signal generation method described in the embodiments of the second aspect, and the same contents are incorporated herein.
The voltage control method comprises the following steps:
calculating a frequency division coefficient according to the expected frequency and the clock frequency of the clock pulse signal, and obtaining a sampling number according to the frequency division coefficient;
sampling the clock pulse signal according to the sampling number;
calculating the number of high-level clock pulses according to the expected duty ratio and the sampling number;
generating a control signal according to the number of the high-level clock pulses and the collected clock pulse signals;
generating a PWM pulse signal according to the control signal; and
and controlling a voltage signal for driving a load according to the PWM pulse signal.
Fig. 9 is a schematic diagram of a voltage control method of an embodiment of a third aspect of the present disclosure.
As shown in fig. 9, voltage control method 900 may include:
step 901: calculating a frequency division coefficient according to the expected frequency and the clock frequency of the clock pulse signal, and obtaining a sampling number by rounding the frequency division coefficient;
step 902: sampling the clock pulse signal according to the sampling number;
step 903: calculating the number of high-level clock pulses according to the expected duty ratio and the sampling number;
step 904: generating a control signal according to the number of the high-level clock pulses and the collected clock pulse signals;
step 905: generating a PWM pulse signal according to the control signal;
step 906: and controlling a voltage signal for driving a load according to the PWM pulse signal.
Therefore, the error between the actual frequency and the expected frequency caused by rounding down the frequency division coefficient to obtain the sampling number can be reduced, the error between the output PWM pulse signal and the expected PWM pulse signal can be reduced, and accurate driving voltage can be provided for the load.
In at least one embodiment, the voltage control method may further include: correcting the expected duty ratio to obtain a corrected duty ratio; calculating a sampling number according to the expected frequency and the clock frequency of the clock pulse signal, and sampling the clock pulse signal according to the sampling number; calculating the number of corrected high-level clock pulses according to the correction duty ratio and the sampling number; generating a control signal according to the number of the corrected high-level clock pulses and the acquired clock pulse signal; generating a PWM pulse signal according to the control signal; and controlling a voltage signal for driving a load according to the PWM pulse signal.
Therefore, by correcting the duty ratio, the error between the expected duty ratio and the actual duty ratio is reduced, so that the error between the output PWM pulse signal and the expected PWM pulse signal is reduced, and the accurate driving voltage can be provided for the load.
In at least one embodiment, the voltage control method may further include: calculating a frequency division coefficient according to the expected frequency and the clock frequency of the clock pulse signal, and respectively adopting a downward rounding mode and an upward rounding mode to the frequency division coefficient to obtain a second sampling number and a third sampling number; calculating a second pulse frequency and a third pulse frequency corresponding to a frequency division coefficient equal to the second sampling number and the third sampling number according to the second sampling number and the third sampling number; calculating a ratio of the second pulse frequency to the third pulse frequency such that a mixed pulse frequency resulting from mixing the second pulse frequency and the third pulse frequency in the ratio is equal to the desired frequency; sampling the clock pulse signal by the second sampling number and the third sampling number according to the ratio; calculating the number of second high-level clock pulses according to the expected duty ratio and the second sampling number, and calculating the number of third high-level clock pulses according to the expected duty ratio and the third sampling number; generating a second control signal according to the number of the second high-level clock pulses and the clock pulse signal acquired according to the second sampling number, and generating a third control signal according to the number of the third high-level clock pulses and the clock pulse signal acquired according to the third sampling number; generating a PWM pulse signal according to the second control signal and the third control signal; and controlling a voltage signal for driving a load according to the PWM pulse signal.
Thus, by mixing PWM pulses of different frequencies, an error between a desired frequency and a frequency of an actually output pulse signal can be reduced, thereby reducing an error between an output PWM pulse signal and a desired PWM pulse signal, and thus enabling a precise driving voltage to be supplied to a load.
Fig. 10 is a schematic diagram of an application of a voltage control method of an embodiment of a third aspect of the present disclosure.
In at least one embodiment, the voltage control method may be implemented, for example, by a System Management Controller (SMC) 1002 of a computer executing a corresponding program to drive a load, such as to drive a fan 1003.
For example, as shown in fig. 10, the PWM module 1021 in the SMC 1002 can perform the functions of steps 901 to 906, and output a voltage signal, for example, a voltage for driving a load.
Further, the voltage control method 900 may also include the step of receiving an input desired frequency and/or a desired duty cycle. For example, as shown in fig. 10, a desired duty ratio (VID) may be input from the user side (HOST side) 1001. The embodiments of the present disclosure are not limited thereto, and the desired frequency and/or the desired duty ratio may be stored in the memory in advance.
According to the embodiment of the third aspect, by correcting the duty ratio, the error between the actually output duty ratio and the desired duty ratio is reduced, so that the error between the output PWM pulse signal and the desired PWM pulse signal can be reduced, and thus an accurate drive voltage can be supplied to the load.
The embodiments of the present disclosure also provide a computer device, which includes a memory, a processor, and a computer program stored on the memory and executable on the processor, and the processor implements the signal generation method of the embodiment of the second aspect or the voltage control method of the embodiment of the third aspect when executing the computer program.
Embodiments of the present disclosure also provide a computer-readable storage medium, which stores a computer program, and the computer program, when executed by a processor, implements the signal generation method of the embodiment of the second aspect or the voltage control method of the embodiment of the third aspect.
Embodiments of the present disclosure also provide a computer program product, which includes a computer program, and when the computer program is executed by a processor, the computer program implements the signal generation method of the embodiment of the second aspect or the voltage control method of the embodiment of the third aspect.
In the embodiments of the present disclosure, the steps in the signal generation method and the voltage control method are labeled with numbers, but the order of the numbers does not represent the execution order of the steps, and the execution order of the steps may be arbitrarily combined according to the actual situation, which is not limited by the embodiments of the present disclosure.
As will be appreciated by one of skill in the art, embodiments of the present disclosure may be provided as a method, system, or computer program product. Accordingly, the present disclosure may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present disclosure may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and so forth) having computer-usable program code embodied therein.
The present disclosure is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the disclosure. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
The above-mentioned embodiments are intended to illustrate the objects, aspects and advantages of the present disclosure in further detail, and it should be understood that the above-mentioned embodiments are only illustrative of the present disclosure and are not intended to limit the scope of the present disclosure, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present disclosure should be included in the scope of the present disclosure.

Claims (17)

1. A signal generation circuit, comprising:
an input circuit configured to receive a clock pulse signal;
an output circuit configured to output a PWM pulse signal;
the duty ratio correction circuit is configured to correct a desired duty ratio to obtain a corrected duty ratio, the desired duty ratio is stored in a register with a preset number of bits in advance, a denominator of the desired duty ratio is a maximum value corresponding to the preset number of bits, and a numerator of the desired duty ratio ranges from 0 to the maximum value; and
a PWM pulse signal control circuit configured to generate a control signal according to the corrected duty ratio output by the duty ratio correction circuit, a desired frequency, and the clock pulse signal, control the output circuit to output the PWM pulse signal according to the control signal,
the duty correction circuit is configured to determine a value obtained by adding 1 to a numerator of the desired duty ratio as the correction duty ratio, or,
the duty correction circuit is configured to calculate a first duty ratio and a second duty ratio corresponding to front and rear values of a numerator of the desired duty ratio, calculate a first output duty ratio and a second output duty ratio corresponding to the first duty ratio and the second duty ratio, select the first duty ratio or the second duty ratio corresponding to one of the first output duty ratio and the second output duty ratio that is closer to the desired duty ratio as the correction duty ratio, wherein the numerator of the first output duty ratio and the numerator of the second output duty ratio are respectively the same as the numerator of the first duty ratio and the second duty ratio, and the denominator of the first output duty ratio and the second output duty ratio are respectively greater than the denominator of the first duty ratio and the second duty ratio by 1.
2. The signal generating circuit according to claim 1,
the PWM pulse signal control circuit includes:
a sampling number calculation circuit configured to calculate a frequency division coefficient from the desired frequency and a clock frequency of the clock pulse signal, and calculate a sampling number from the frequency division coefficient;
a sampling circuit connected to the input circuit and the sampling number calculation circuit, and configured to sample the clock pulse signal according to the sampling number;
and the pulse control circuit is connected with the sampling number calculation circuit and the sampling circuit, and is configured to calculate the number of high-level clock pulses according to the correction duty ratio output by the duty ratio correction circuit and the sampling number, generate the control signal according to the number of the high-level clock pulses and the clock pulse signal acquired by the sampling circuit, and control the output circuit to output the PWM pulse signal according to the control signal.
3. The signal generating circuit according to claim 2,
the sampling number calculation circuit is configured to round the frequency division coefficient to obtain the sampling number.
4. The signal generating circuit according to claim 2,
the sampling number calculation circuit is configured to obtain a second sampling number and a third sampling number by respectively adopting a downward rounding mode and an upward rounding mode for the frequency division coefficient,
the signal generating circuit further includes:
a frequency calculation circuit configured to calculate a second pulse frequency and a third pulse frequency corresponding to a frequency division coefficient equal to the second sampling number and the third sampling number, respectively; and
a ratio calculation circuit configured to calculate a ratio of the second pulse frequency to the third pulse frequency such that a mixed pulse frequency obtained by mixing the second pulse frequency and the third pulse frequency in the ratio is equal to the desired frequency;
the sampling circuit configured to sample the clock pulse signal by the second sampling number and the third sampling number in accordance with the ratio calculated by the ratio calculation circuit;
the pulse control circuit is configured to calculate a second number of correction high-level clock pulses from the correction duty ratio and the second number of samples, calculate a third number of correction high-level clock pulses from the correction duty ratio and the third number of samples, generate a second control signal from the second number of correction high-level clock pulses and the clock pulse signal collected by the sampling circuit according to the second number of samples, generate a third control signal from the third number of correction high-level clock pulses and the clock pulse signal collected by the sampling circuit according to the third number of samples, and control the output circuit to output the PWM pulse signal according to the second control signal and the third control signal.
5. A signal generation circuit, the signal generation circuit comprising:
an input circuit configured to receive a clock pulse signal;
an output circuit configured to output a PWM pulse signal; and
a PWM pulse signal control circuit configured to generate a control signal according to a desired duty ratio, a desired frequency, and the clock pulse signal, control the output circuit to output the PWM pulse signal according to the control signal,
the PWM pulse signal control circuit includes:
a sampling number calculation circuit configured to calculate a frequency division coefficient from the desired frequency and a clock frequency of the clock pulse signal, and calculate a sampling number from the frequency division coefficient;
a sampling circuit connected to the input circuit and the sampling number calculation circuit, and configured to sample the clock pulse signal according to the sampling number;
and the pulse control circuit is connected with the sampling number calculation circuit and the sampling circuit, and is configured to calculate the number of high-level clock pulses according to the expected duty ratio and the sampling number, generate the control signal according to the number of the high-level clock pulses and the clock pulse signal acquired by the sampling circuit, and control the output circuit to output the PWM pulse signal according to the control signal.
6. The signal generating circuit of claim 5,
the desired duty ratio is stored in a register with a predetermined number of bits in advance, the denominator of the desired duty ratio is a maximum value corresponding to the predetermined number of bits, the numerator of the desired duty ratio ranges from 0 to the maximum value,
the signal generating circuit further comprises:
a duty cycle correction circuit configured to correct the desired duty cycle to obtain a corrected duty cycle;
the pulse control circuit is configured to calculate the number of correction high-level clock pulses according to the correction duty ratio output by the duty ratio correction circuit and the sampling number, generate the control signal according to the number of correction high-level clock pulses and the clock pulse signal acquired by the sampling circuit, and control the output circuit to output the PWM pulse signal according to the control signal.
7. The signal generating circuit according to claim 6,
the duty ratio correction circuit is configured to determine a value obtained by adding 1 to a numerator of the desired duty ratio as the correction duty ratio when the desired duty ratio is greater than 1/2.
8. The signal generating circuit according to claim 7,
the duty correction circuit configured to calculate a first duty ratio and a second duty ratio corresponding to preceding and following values of a numerator of the desired duty ratio, calculate a first output duty ratio and a second output duty ratio corresponding to the first duty ratio and the second duty ratio, select either the first duty ratio or the second duty ratio corresponding to one of the first output duty ratio and the second output duty ratio that is closer to the desired duty ratio as the correction duty ratio,
wherein numerators of the first and second output duty cycles are respectively the same as numerators of the first and second duty cycles, and denominators of the first and second output duty cycles are respectively greater than denominators of the first and second duty cycles by 1.
9. The signal generating circuit according to any one of claims 5 to 8,
the sampling number calculation circuit is configured to round the frequency division coefficient to obtain the sampling number.
10. The signal generating circuit according to claim 5,
the sampling number calculation circuit is configured to obtain a second sampling number and a third sampling number by respectively adopting a downward rounding mode and an upward rounding mode for the frequency division coefficient,
the signal generating circuit further includes:
a frequency calculation circuit configured to calculate a second pulse frequency and a third pulse frequency corresponding to a frequency division coefficient equal to the second sampling number and the third sampling number, respectively; and
a ratio calculation circuit configured to calculate a ratio of the second pulse frequency to the third pulse frequency such that a mixed pulse frequency obtained by mixing the second pulse frequency and the third pulse frequency in the ratio is equal to the desired frequency;
the sampling circuit configured to sample the clock pulse signal by the second sampling number and the third sampling number in accordance with the ratio calculated by the ratio calculation circuit;
the pulse control circuit is configured to calculate a second number of high-level clock pulses according to the desired duty ratio and the second number of samples, calculate a third number of high-level clock pulses according to the desired duty ratio and the third number of samples, generate a second control signal according to the second number of high-level clock pulses and the clock pulse signal collected by the sampling circuit according to the second number of samples, generate a third control signal according to the third number of high-level clock pulses and the clock pulse signal collected by the sampling circuit according to the third number of samples, and control the output circuit to output the PWM pulse signal according to the second control signal and the third control signal.
11. The signal generating circuit according to any one of claims 6 to 8,
the sampling number calculation circuit is configured to obtain a second sampling number and a third sampling number by respectively adopting a downward rounding mode and an upward rounding mode for the frequency division coefficient,
the signal generating circuit further includes:
a frequency calculation circuit configured to calculate a second pulse frequency and a third pulse frequency corresponding to a frequency division coefficient equal to the second sampling number and the third sampling number, respectively; and
a ratio calculation circuit configured to calculate a ratio of the second pulse frequency to the third pulse frequency such that a mixed pulse frequency obtained by mixing the second pulse frequency and the third pulse frequency in the ratio is equal to the desired frequency;
the sampling circuit configured to sample the clock pulse signal by the second sampling number and the third sampling number in accordance with the ratio calculated by the ratio calculation circuit;
the pulse control circuit is configured to calculate a second number of corrected high-level clock pulses from the correction duty ratio and the second number of samples, calculate a third number of corrected high-level clock pulses from the correction duty ratio and the third number of samples, generate a second control signal from the second number of corrected high-level clock pulses and the clock pulse signal collected by the sampling circuit according to the second number of samples, generate a third control signal from the third number of corrected high-level clock pulses and the clock pulse signal collected by the sampling circuit according to the third number of samples, and control the output circuit to output the PWM pulse signal according to the second control signal and the third control signal.
12. A signal generation method, comprising:
correcting the expected duty ratio to obtain a corrected duty ratio;
calculating a sampling number according to the expected frequency and the clock frequency of the clock pulse signal, and sampling the clock pulse signal according to the sampling number;
calculating the number of corrected high-level clock pulses according to the correction duty ratio and the sampling number;
generating a control signal according to the corrected high-level clock pulse number and the acquired clock pulse signal; and
and generating a PWM pulse signal according to the control signal.
13. A signal generation method, comprising:
calculating a frequency division coefficient according to the expected frequency and the clock frequency of the clock pulse signal, and obtaining a sampling number according to the frequency division coefficient;
sampling the clock pulse signal according to the sampling number;
calculating the number of high-level clock pulses according to the expected duty ratio and the sampling number;
generating a control signal according to the number of the high-level clock pulses and the collected clock pulse signals; and
and generating a PWM pulse signal according to the control signal.
14. A voltage control method, comprising:
correcting the expected duty ratio to obtain a corrected duty ratio;
calculating a sampling number according to the expected frequency and the clock frequency of the clock pulse signal, and sampling the clock pulse signal according to the sampling number;
calculating the number of corrected high-level clock pulses according to the correction duty ratio and the sampling number;
generating a control signal according to the number of the high-level clock pulses and the acquired clock pulse signals;
generating a PWM pulse signal according to the control signal; and
and controlling a voltage signal for driving a load according to the PWM pulse signal.
15. A voltage control method, comprising:
calculating a frequency division coefficient according to the expected frequency and the clock frequency of the clock pulse signal, and obtaining a sampling number according to the frequency division coefficient;
sampling the clock pulse signal according to the sampling number;
calculating the number of high-level clock pulses according to the expected duty ratio and the sampling number;
generating a control signal according to the number of the high-level clock pulses and the collected clock pulse signals;
generating a PWM pulse signal according to the control signal; and
and controlling a voltage signal for driving a load according to the PWM pulse signal.
16. A computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the processor implements the method of any one of claims 12 to 15 when executing the computer program.
17. A computer-readable storage medium, characterized in that the computer-readable storage medium stores a computer program which, when executed by a processor, implements the method of any one of claims 12 to 15.
CN202211569724.9A 2022-12-08 2022-12-08 Signal generation circuit, signal generation method and voltage control method Active CN115580273B (en)

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US7202722B2 (en) * 2004-05-17 2007-04-10 Agere System Inc. Duty-cycle correction circuit
US7330061B2 (en) * 2006-05-01 2008-02-12 International Business Machines Corporation Method and apparatus for correcting the duty cycle of a digital signal
KR20110003189A (en) * 2009-07-03 2011-01-11 삼성전자주식회사 Duty-cycle error correction circuit
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