CN115580114A

CN115580114A - Switching power supply

Info

Publication number: CN115580114A
Application number: CN202211386985.7A
Authority: CN
Inventors: 刘鑫; 骆盛; 朱伟
Original assignee: Xinzhou Technology Beijing Co ltd
Current assignee: Xinzhou Technology Beijing Co ltd
Priority date: 2022-11-07
Filing date: 2022-11-07
Publication date: 2023-01-06

Abstract

The present disclosure relates to a switching power supply, including: a switching module comprising at least one switch configured to cause the switching power supply to charge or discharge when closed; the switch control module is configured to generate a control signal which corresponds to the switching frequency and is used for controlling the switching module to be opened or closed, the input end of the switch control module is electrically connected with the output end of the frequency locking module, and the switch control module is further configured to lock the switching frequency corresponding to the control signal at a first frequency which is greater than or equal to a preset frequency threshold value according to the input frequency locking signal; and the input end of the frequency locking module is electrically connected with the output end of the switch control module, and the frequency locking module is configured to generate and output a frequency locking signal from the output end of the frequency locking module when the switching frequency corresponding to the control signal output by the switch control module is smaller than a preset frequency threshold value. The switching power supply can effectively avoid audio noise.

Description

Switching power supply

Technical Field

Embodiments of the present disclosure relate generally to switching power supplies, and more particularly to a switching power supply.

Background

Switching power supplies are widely used in the field of power supplies. With conventional switching power supplies, the switching power supply operates in a PWM (pulse width modulation) mode when the external load is under, for example, a heavy load condition. When the external load becomes light to a certain extent, the switching power supply usually enters a PFM (pulse frequency modulation) mode, and the switching frequency of the switching power supply is reduced to reduce the switching loss, so as to improve the conversion efficiency of the power supply. However, when the external load becomes further light, the switching frequency of the switching power supply may be lowered below 20kHz (kilohertz), entering an audible frequency range (20 Hz to 20 kHz) that can be heard by the human ear, thus generating audio noise.

In summary, the conventional switching power supply has a problem of easily generating audio noise.

Disclosure of Invention

In view of the above problems, the present disclosure provides a switching power supply that can effectively avoid audio noise.

According to one aspect of the present disclosure, a switching power supply is provided. The switching power supply includes: a switching module comprising at least one switch configured to cause the switching power supply to charge or discharge when closed; the switch control module is configured to generate a control signal corresponding to the switching frequency and used for controlling the switching module to be opened or closed, the input end of the switch control module is electrically connected with the output end of the frequency locking module, and the switch control module is further configured to lock the switching frequency corresponding to the control signal at a first frequency which is greater than or equal to a preset frequency threshold value according to the input enabled frequency locking signal; and the input end of the frequency locking module is electrically connected with the output end of the switch control module, and the frequency locking module is configured to enable the frequency locking signal output by the output end of the frequency self-locking module when the switching frequency corresponding to the control signal output by the switch control module is smaller than a preset frequency threshold value.

In some embodiments, the outputs of the switch control module include a first control output and a second control output, the at least one switch including: a first switch configured to cause the switching power supply to charge when closed, the first switch comprising: the first contact is electrically connected with the third contact of the second switch; the second contact is electrically connected with the grounding end of the switching power supply; the first control end is electrically connected with the first control output end; and a second switch configured to discharge the switching power supply when closed, the second switch including: a third contact; the fourth contact is electrically connected with the output end of the switching power supply; and the second control end is electrically connected with the second control output end.

In some embodiments, the switching power supply further comprises: a closed cycle control module configured to generate a closed cycle control signal according to a difference between an output voltage feedback voltage of the switching power supply and a reference voltage and a magnitude relationship between the output voltage of the switching power supply and a voltage of the first contact, the closed cycle control module including: the first voltage input end is electrically connected with the output end of the switching power supply; a second voltage input end electrically connected with the first contact; the closed cycle control signal output end is electrically connected with the closed cycle control signal input end of the switch control module and is used for outputting a closed cycle control signal; the switch control module is further configured to generate and output a second control signal from a second control output in accordance with the closed-cycle control signal, the switch control module further comprising a closed-cycle control signal input.

In some embodiments, the closed cycle control module further comprises: an error amplification unit configured to generate an error current based on a difference between a feedback voltage of an output voltage of the switching power supply and a reference voltage; a current adjustment unit configured to generate a negative current according to the error current, a negative current output terminal of the current adjustment unit being electrically connected to one end of the first resistor; the other end of the first resistor is electrically connected with the first contact; and a comparison unit configured to generate an enabled closed-cycle control signal when a voltage of one end of the first resistor and a voltage of an output end of the switching power supply satisfy a first predetermined condition; the switch control module is further configured to generate a corresponding second switch control signal to cause the second switch to open according to the enabled close cycle control signal.

In some embodiments, the direction of the negative current is opposite to the direction of the error current, and the magnitude of the negative current is proportional to the magnitude of the error current.

In some embodiments, the comparison unit comprises a zero crossing detection unit.

In some embodiments, the error amplification unit further comprises: the inverting input end of the operational amplifier is configured to receive a feedback voltage of the output voltage of the switching power supply, the positive input end of the operational amplifier is configured to receive a reference voltage, and the output end of the operational amplifier is electrically connected with the grid electrode of the first PMOS tube and one end of the first capacitor respectively; the other end of the first capacitor is electrically connected with a grounding end; the source electrode of the first PMOS tube is electrically connected with the power supply end of the switching power supply, and the drain electrode of the first PMOS tube is electrically connected with the drain electrode of the first NMOS tube, the grid electrode of the first NMOS tube and the grid electrode of the second NMOS tube respectively; the source electrode of the first NMOS tube is respectively and electrically connected with the source electrode of the second NMOS tube and the grounding end; and the drain electrode of the second NMOS tube is used for outputting error current.

In some embodiments, the operational amplifier is of the type transconductance amplifier.

In some embodiments, the predetermined frequency threshold is any value between 20kHz and 35 kHz.

In some embodiments, the switching power supply is any one of a boost (boost) switching power supply, a buck (buck) switching power supply, and a buck-boost (buck-boost) switching power supply.

It should be understood that the statements in this section are not intended to identify key or critical features of the embodiments of the present disclosure, nor are they intended to limit the scope of the present disclosure. Other features of the present disclosure will become apparent from the following description.

Drawings

The above and other features, advantages and aspects of various embodiments of the present disclosure will become more apparent by referring to the following detailed description when taken in conjunction with the accompanying drawings. In the drawings, like or similar reference numbers indicate like or similar elements.

Fig. 1 shows a partial schematic structure of a conventional boost switching power supply.

Fig. 2 is a waveform diagram illustrating an inductor current flowing through an inductor in a PWM mode of a conventional boost switching power supply.

Fig. 3 is a waveform diagram illustrating an inductor current flowing through an inductor in a PFM mode of a conventional boost switching power supply.

Fig. 4 shows a block schematic diagram of a portion of a switching power supply of an embodiment of the present disclosure.

Fig. 5 shows a waveform diagram of the control signal and the frequency locking signal when the switching frequency is greater than the predetermined frequency threshold according to the embodiment of the disclosure.

Fig. 6 shows a waveform diagram of the control signal and the frequency-locked signal when the switching frequency corresponding to the load is less than the predetermined frequency threshold according to the embodiment of the disclosure.

Fig. 7 shows a partial schematic structure diagram of a switching power supply of an embodiment of the present disclosure.

Fig. 8 shows waveform diagrams of the control signal and the frequency locking signal when the switching frequency is greater than the predetermined frequency threshold according to an embodiment of the disclosure.

Fig. 9 shows waveforms of the control signal and the frequency-locked signal when the switching frequency corresponding to the load is less than the predetermined frequency threshold according to the embodiment of the disclosure.

Fig. 10 shows a partial schematic structure of a switching power supply of an embodiment of the present disclosure.

Fig. 11 shows a partial schematic structure diagram of a switching power supply of an embodiment of the present disclosure.

Fig. 12 shows a schematic structural diagram of an error amplification unit of an embodiment of the present disclosure.

Fig. 13 shows a signal waveform diagram of an error amplification unit of an embodiment of the present disclosure.

Fig. 14 shows a signal waveform diagram associated with a comparison unit of an embodiment of the disclosure.

Fig. 15 shows a waveform schematic of an inductor current of an embodiment of the present disclosure.

Detailed Description

Exemplary embodiments of the present disclosure are described below with reference to the accompanying drawings, in which various details of the embodiments of the disclosure are included to assist understanding, and which are to be considered as merely exemplary. Accordingly, those of ordinary skill in the art will recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope and spirit of the disclosure. Also, descriptions of well-known functions and constructions are omitted in the following description for clarity and conciseness.

The term "include" and variations thereof as used herein is meant to be inclusive in an open-ended manner, i.e., "including but not limited to". Unless specifically stated otherwise, the term "or" means "and/or". The term "based on" means "based at least in part on". The terms "one example embodiment" and "one embodiment" mean "at least one example embodiment". The term "another embodiment" means "at least one additional embodiment". The terms "first," "second," and the like may refer to different or the same object. Other explicit and implicit definitions are also possible below.

As described above, the conventional switching power supply has a problem in that audio noise is easily generated.

It should be understood that the input-output power relationship of the switching power supply is shown in the following equation (1):

V _IN *V _IN *η＝V _OUT *I _LOAD (1)

wherein, V _IN Characterizing the input voltage of a switching power supply, I _IN Characterizing the input current, V, of a switching power supply _OUT Characterizing the output voltage of a switching power supply, I _LOAD The load current of the switching power supply is represented, and eta represents the conversion efficiency of the switching power supply.

When the load is in a certain range, the conversion efficiency of the switching power supply does not change greatly. Therefore, for convenience of explanation, the influence of the conversion efficiency is neglected in the following analysis. The reason why the audio noise occurs will be briefly described below by taking a step-up switching power supply circuit as an example.

Fig. 1 shows a partial schematic diagram of a conventional boost switching power supply 100. Boost switching power supply 100 includes inductance L, first switch K1, second switch K2 at least, and wherein, inductance L's one end is connected with boost switching power supply 100's voltage input end VIN electricity, and inductance L's the other end is connected with first switch K1 and second switch K2 electricity respectively, and first switch K1 sets up between inductance L and switching power supply 100's voltage output end VOUT, and second switch K2 sets up between inductance L and earthing terminal GND. It will be appreciated that when the second switch K2 is closed and the first switch K1 is open, the inductor L is charged; when the second switch K2 is turned off and the first switch K1 is turned on, the inductor L outputs electric energy (discharges) to the load 110 via the voltage output terminal VOUT of the switching power supply 100. It should be noted that, not shown in fig. 1, a circuit configuration for adjusting the switching frequency of the step-up switching power supply 100 according to the load and controlling the first switch K1 and the second switch K2 to be turned on/off accordingly is omitted.

Fig. 2 shows a waveform diagram of an inductor current IL flowing through an inductor L in the PWM mode of the conventional boost switching power supply 100. The vertical axis represents the inductor current IL of the boost switching power supply 100, and the horizontal axis represents the time t. The first waveform curve L1 represents a waveform curve of the inductor current IL of the boost switching power supply 100 corresponding to the first load, and IL1_ avg represents an average value of the inductor current IL corresponding to the first load. The second waveform curve L2 represents a waveform curve of the inductor current IL of the boost switching power supply 100 corresponding to the second load, and IL2_ avg represents an average value of the inductor current IL corresponding to the second load. Wherein the second load is lighter than the first load. It should be appreciated that the boost switching power supply 100 operates in the PWM mode corresponding to the first load as well as the second load. T _ PWM characterizes the switching period of the boost switching power supply 100. In a switching period T _ PWM, the stage of the rising of the inductance current IL corresponds to the stage of the closing of the second switch K2, the disconnection of the first switch K1 and the charging of the inductance L; the stage of the inductor current IL decreasing corresponds to the stage of the second switch K2 being open, the first switch K1 being closed, and the inductor L discharging.

Fig. 3 shows a waveform diagram of an inductor current IL flowing through an inductor L in the PFM mode of the conventional boost switching power supply 100. The third waveform curve L3 represents a waveform curve of the inductor current IL of the boost switching power supply 100 corresponding to the third load, and IL3_ avg represents an average value of the inductor current IL corresponding to the third load. The fourth waveform curve L4 represents a waveform curve of the inductor current IL of the boost switching power supply 100 corresponding to the fourth load, and IL4_ avg represents an average value of the inductor current IL corresponding to the fourth load. Wherein the fourth load is lighter than the third load. It should be understood that the boost switching power supply 100 operates in the PFM mode corresponding to the third load and the fourth load. T _ PFM _ pre represents a switching period of the boost switching power supply 100 corresponding to the third load, T _ PFM _ new represents a switching period of the boost switching power supply 100 corresponding to the fourth load, and T _ PFM _ new is greater than T _ PFM _ pre.

It should be appreciated that as the load becomes lighter, for example, the load becomes lighter from the second load to the third load, the boost switching power supply 100 will switch from the PWW mode to the PFM mode to ensure the conversion efficiency. In PFM mode, the PEAK I _ PEAK of the inductor current IL is locked to a predetermined minimum value. The inductor current IL is in a discontinuous conduction state (DCM), and there is no negative current in the inductor current IL during the switching period (i.e. the inductor current IL has no negative value). It will be appreciated that the inductor current IL continues to be zero during part of the switching cycle. While the inductor current IL continues to be zero, both the second switch K2 and the first switch K1 are turned off. As the load becomes lighter, in PFM mode, boost switching power supply 100 increases the duration of the switching cycle by increasing the time that inductor current IL is zero, thereby reducing the switching frequency. It should be appreciated that the inductor current average value (e.g., IL4_ avg is less than IL3_ avg) may be reduced by extending the switching period to stabilize the output voltage VOUT.

When the load becomes further light, the switching frequency of the step-up switching power supply 100 may be lowered below 20kHz into an audible range of human ears, thus generating audio noise.

To address, at least in part, one or more of the above problems and other potential problems, example embodiments of the present disclosure propose a switching power supply scheme. In the disclosure, the switching power supply includes a switching module, a switching control module, and a frequency locking module, where the switching control module is configured to generate a control signal corresponding to a switching frequency and used for controlling the switching module to be turned on or turned off, an input end of the switching control module is electrically connected to an output end of the frequency locking module, the switching control module is further configured to lock a switching frequency corresponding to the control signal at a first frequency greater than or equal to a predetermined frequency threshold according to the input frequency locking signal, and the frequency locking module is configured to generate the frequency locking signal when the switching frequency corresponding to the control signal output by the switching control module is less than the predetermined frequency threshold. By means of the frequency locking module, the frequency locking signal is generated when the switching frequency is smaller than the preset frequency threshold value, and the switching control module locks the switching frequency at the first frequency which is larger than or equal to the preset frequency threshold value according to the input frequency locking signal.

The switching power supply of the embodiment of the present disclosure is explained in detail below.

Fig. 4 shows a block schematic diagram of a portion of a switching power supply 400 of an embodiment of the present disclosure. The switching power supply 400 includes a switching module 402, a switching control module 404, and a frequency locking module 406.

With respect to the switch module 402, it includes at least one switch configured to cause the switching power supply to charge or discharge when closed.

Regarding the switch control module 404, it is configured to generate a control signal corresponding to the switching frequency for controlling the switching module to open or close, an input terminal of the switch control module is electrically connected to an output terminal of the frequency locking module, and the switch control module 404 is further configured to lock the switching frequency corresponding to the control signal at a first frequency greater than or equal to a predetermined frequency threshold according to the input enabled frequency locking signal.

Regarding the frequency locking module 406, an input end of the frequency locking module 406 is electrically connected to an output end of the switch control module 404, and the frequency locking module 406 is configured to enable the frequency locking signal output from the output end of the frequency locking module 406 when a switching frequency corresponding to the control signal output by the switch control module 404 is less than a predetermined frequency threshold.

It should be appreciated that in some embodiments, the switching control module 404 determines the switching frequency based on the load condition of the switching power supply 400 to generate the control signal based on the determined switching frequency. If the switching frequency, as determined by the switching control module 404, for example, based on the load condition of the switching power supply 400, is less than the predetermined frequency threshold, the frequency locking module 406 causes the output frequency locked signal to be enabled to cause the switching control module 404 to generate the control signal based on the first frequency. For illustration, the control signal output by the switch control module 404 is represented by ctrl, and the frequency-locked signal output by the frequency-locked module 406 is represented by EN _ freq, for example.

It should be appreciated that the switch control module 404 outputs a control signal from its output that is used to control at least one switch in the switch module 402 to close/open so that the at least one switch, when closed, causes the switching power supply to charge or discharge. The frequency locking module 406 receives the control signal output by the switch control module 404 through an input terminal thereof, so as to determine whether the switching frequency corresponding to the control signal output by the switch control module 404 is smaller than a predetermined frequency threshold according to the control signal.

The switching power supply 400 is, for example, any one of a step-up switching power supply, a step-down switching power supply, and a step-down-step-up switching power supply.

In some embodiments, the at least one switch in the switch module 402 includes a first switch and a second switch. The first switch is configured to cause the switching power supply to charge when closed, and the second switch is configured to cause the switching power supply to discharge when closed.

In some embodiments, the control signal output by the switch control module 404 is, for example, a pulse signal as shown in fig. 5. Fig. 5 shows waveforms of the control signal ctrl and the frequency-locked signal EN _ freq when the switching frequency is greater than the predetermined frequency threshold according to the embodiment of the disclosure. Wherein, the at least one switch is controlled to be closed during the period when the control signal ctrl is at a high level, and the at least one switch is controlled to be opened during the period when the control signal ctrl is at a low level. The frequency locking module 406 determines whether the switching frequency corresponding to the control signal ctrl is less than a predetermined frequency threshold according to a time interval Ts1 between two adjacent rising edges of the control signal ctrl. In some embodiments, the frequency locking module 406 includes a timing unit that resets at the rising edge of the control signal ctrl and then starts timing. As shown in fig. 5, the timing unit is reset at the first rising edge t1 of the control signal ctrl and then starts timing. The time interval Ts1 between two adjacent rising edges of the control signal ctrl is smaller than the predetermined timing threshold (which means that the switching frequency of the switching power supply 400 is greater than or equal to the predetermined frequency threshold), and the timing value of the timing unit has not reached the predetermined timing threshold, and is reset at the second rising edge t2 of the control signal ctrl, and is re-timed. If the timing value of the timing unit does not reach (i.e., is smaller than) the predetermined timing threshold, the frequency-locked signal EN _ freq output by the frequency-locked module 406 remains low. During the period when the frequency locking signal EN _ freq is kept at the low level, no rising edge of the frequency locking signal EN _ freq is generated, which indicates that the frequency locking signal EN _ freq is not enabled, i.e. no frequency locking effect is generated. The switching control module 404 generates a control signal based on a switching frequency determined by, for example, the load condition of the switching power supply 400.

Fig. 6 illustrates waveforms of the control signal ctrl and the frequency-locked signal EN _ freq when the switching frequency corresponding to the load is less than the predetermined frequency threshold according to the embodiment of the disclosure. For convenience of explanation, fig. 6 also shows a waveform of the control signal ctrl _0 that may occur in the case where the frequency locking module 406 is not present. It should be appreciated that, assuming that the frequency locking module 406 is not present, the switching frequency determined only by the switching control module may be below the predetermined frequency threshold, a control signal ctrl _0 may be generated, which may occur. The time interval Ts2 between two adjacent rising edges corresponding to the control signal ctrl _0 that may occur is greater than the predetermined timing threshold Tlock, that is, the switching frequency corresponding to the control signal ctrl _0 that may occur is less than the predetermined frequency threshold. As shown in fig. 6, the timing unit of the frequency locking module 406 is reset at the first rising edge t3 of the control signal ctrl and then starts timing. Since the time interval Ts2 is greater than the predetermined count threshold Tlock, the count unit has not been reset at time t4, and the count value of the count unit reaches the predetermined count threshold Tlock. At this time, since the timing value of the timing unit reaches the predetermined timing threshold Tlock, the frequency locking module 406 inverts the output frequency locking signal EN _ freq from low level to high level, and the inversion of the frequency locking signal EN _ freq from low level to high level (i.e. the rising edge of the frequency locking signal EN _ freq) indicates that the frequency locking signal EN _ freq is enabled, i.e. the frequency locking effect is generated. The switch control module 404 immediately turns the control signal ctrl from low level to high level after receiving the enabled frequency-locked signal EN _ freq (e.g., a rising edge of the frequency-locked signal EN _ freq). Therefore, by the frequency locking module 406, the switching frequency corresponding to the control signal ctrl output by the switching control module 404 is not lower than the predetermined frequency threshold, and thus, the above-mentioned scheme can effectively avoid the audio noise. It should be noted that when the control signal ctrl output by the switch control module 404 is inverted from low level to high level, a rising edge of the control signal ctrl is generated, and then the timing unit is reset and then re-timed. Accordingly, the frequency locking module 406 detects a rising edge of the control signal ctrl, and inverts the frequency locking signal EN _ freq from high level to low level according to the rising edge of the control signal ctrl.

In the above scheme, the frequency locking module 406 can ensure that the switching frequency of the switching power supply is not less than the predetermined frequency threshold, thereby effectively avoiding generating audio noise.

Fig. 7 shows a partial schematic structure diagram of a switching power supply 700 according to an embodiment of the present disclosure. Wherein the output of the switch control module 704 comprises a first control output and a second control output. The at least one switch of the switch module 702 includes a first switch and a second switch. The first switch is configured to cause the switching power supply 700 to charge, for example, when closed. The first switch comprises a first contact, a second contact and a first control end. The first contact of the first switch is electrically connected to the third contact of the second switch, the second contact of the first switch is electrically connected to the ground GND of the switching power supply 700, and the first control terminal of the first switch is electrically connected to the first control output terminal. The second switch is configured to discharge the switching power supply, for example, when closed. The second switch comprises a third contact, a fourth contact and a second control end. The third contact of the second switch is electrically connected with the first contact of the first switch, the fourth contact of the second switch is electrically connected with the output end VOUT of the switching power supply, and the second control end of the second switch is electrically connected with the second control output end. Wherein the first control signal output by the first control output is characterized by ctrl1, and the second control signal output by the second control output is characterized by ctrl2.

In some embodiments, the first switch is implemented by a first MOS transistor Q1, a drain of the first MOS transistor Q1 serves as a first contact of the first switch, a source of the first MOS transistor Q1 serves as a second contact of the first switch, and a gate of the first MOS transistor Q1 serves as a first control terminal of the first switch. The second switch is realized by a second MOS transistor Q2, a drain of the second MOS transistor Q2 serves as a third contact of the second switch, a source of the second MOS transistor Q2 serves as a fourth contact of the second switch, and a gate of the second MOS transistor Q2 serves as a second control end of the second switch.

Referring to fig. 7, the switching power supply 700 includes an inductor L, one end of the inductor L is electrically connected to the voltage input terminal VIN, and the other end of the inductor L is electrically connected to the first contact of the first switch and the third contact of the second switch.

Fig. 8 shows a waveform diagram of the control signal and the frequency-locked signal when the switching frequency is greater than the predetermined frequency threshold according to the embodiment of the disclosure. For convenience of illustration, fig. 8 also shows a waveform curve of the inductor current IL flowing through the inductor L. It should be understood that fig. 8 illustrates a case where the switching frequency corresponding to the load is greater than the predetermined frequency threshold (the time interval Ts3 between two adjacent rising edges corresponding to the first control signal ctrl1 is less than the predetermined timing threshold Tlock). At a time a1, the switch control module 704 outputs the first control signal ctrl1 at a high level and the second control signal ctrl2 at a low level. During the period when the first control signal ctrl1 is at a high level, the first MOS transistor Q1 is turned on, the second MOS transistor Q2 is turned off, the inductor L is charged, and the inductor current IL gradually increases. At the time b1, when the inductor current IL satisfies the first predetermined current condition, the switch control module 704 sets the first control signal ctrl1 to a low level and sets the second control signal ctrl2 to a high level. Then, the first MOS transistor Q1 is turned off, the second MOS transistor Q2 is turned on, the inductor L discharges, and the switching power supply 700 outputs electric energy to the load. At time c1, when the inductor current IL satisfies the second predetermined current condition (e.g., the inductor current IL is zero), the switch control module 704 sets the second control signal ctrl2 to a low level as well. Thus, the first MOS transistor Q1 and the second MOS transistor Q2 are both turned off. According to the determined switching frequency, at the time d1, the switching control module 704 outputs the first control signal ctrl1 at a high level and the second control signal ctrl2 at a low level, thereby starting the next switching cycle.

It should be appreciated that the frequency locking module 706 determines whether the switching frequency is less than the predetermined frequency threshold according to a time interval Ts3 between corresponding adjacent two rising edges of the first control signal ctrl 1. As described above, the switching frequency corresponding to fig. 8 is greater than the predetermined frequency threshold, so the frequency-locked signal EN _ freq output by the frequency-locking module 706 keeps at the low level all the time, and no rising edge of the frequency-locked signal EN _ freq is generated, that is, the frequency-locked signal EN _ freq is not enabled.

Fig. 9 illustrates a waveform diagram of the control signal and the frequency locking signal when the switching frequency corresponding to the load is less than the predetermined frequency threshold according to the embodiment of the disclosure. For convenience of illustration, fig. 9 also shows a waveform curve of the inductor current IL flowing through the inductor L. It should be understood that fig. 9 illustrates a case where the switching frequency corresponding to the load is less than the predetermined frequency threshold. At a time a2, the switch control module 704 outputs the first control signal ctrl1 at a high level and the second control signal ctrl2 at a low level. During the period when the first control signal ctrl1 is at a high level, the first MOS transistor Q1 is turned on, the second MOS transistor Q2 is turned off, the inductor L is charged, and the inductor current IL gradually increases. At time b2, when the inductor current IL satisfies the first predetermined current condition, the switch control module 704 sets the first control signal ctrl1 to a low level and sets the second control signal ctrl2 to a high level. Then, the first MOS transistor Q1 is turned off, the second MOS transistor Q2 is turned on, the inductor L discharges, and the switching power supply 700 outputs electric energy to the load. At time c, when the inductor current IL satisfies the second predetermined current condition (e.g., the inductor current IL is zero), the switch control module 704 sets the second control signal ctrl2 to a low level as well. Thus, the first MOS transistor Q1 and the second MOS transistor Q2 are both turned off. At the time d2, for example, the timing value of the timing unit of the frequency locking module 706 reaches the predetermined timing threshold Tlock, so that the frequency locking module 706 inverts the output frequency locking signal EN _ freq from low level to high level, and the inversion of the frequency locking signal EN _ freq from low level to high level (i.e., the rising edge of the frequency locking signal EN _ freq) indicates that the frequency locking signal EN _ freq is enabled. Therefore, the switch control module 704 outputs the first control signal ctrl1 at a high level and the second control signal ctrl2 at a low level in response to the enabled frequency-locked signal EN _ freq (e.g., a rising edge of the frequency-locked signal EN _ freq), thereby enabling a next switching cycle.

In the above scheme, the frequency locking module 706 can ensure that the switching frequency of the switching power supply is not less than the predetermined frequency threshold, thereby effectively avoiding generating audio noise.

Based on the frequency locking function of the frequency locking module, the average inductor current IL _ avg flowing through the inductor L is fixed. According to the input-output power relation of the switching power supply, when the average inductive current IL _ avg is fixed, the input voltage V is _IN When the load is further reduced, the output voltage V of the switching power supply is further reduced _OUT And (4) rising. In order to stabilize the output voltage, in some embodiments, the switching power supply of the present disclosure also has a function of stabilizing the output voltage. The following will be described in detail with reference to fig. 10 to 15.

Fig. 10 shows a partial schematic structure diagram of a switching power supply 900 according to an embodiment of the present disclosure. The switching power supply 900 includes a switching module 902, a switching control module 904, a frequency locking module 906, and a closed cycle control module 908. The closed-cycle control module 908 is configured to generate a closed-cycle control signal pctrl according to a difference between an output voltage feedback voltage of the switching power supply and a reference voltage, and a magnitude relationship between the output voltage of the switching power supply and a voltage of the first contact. The closed-cycle control module 908 includes a first voltage input, a second voltage input, and a closed-cycle control signal output. The first voltage input end is electrically connected with the output end VOUT of the switching power supply, the second voltage input end is electrically connected with the first contact, and the closed cycle control signal output end is electrically connected with the closed cycle control signal input end of the switch control module and used for outputting a closed cycle control signal pctrl. Correspondingly, the switch control module 904 is further configured to generate and output a second control signal ctrl2 from a second control output in dependence on the closed-cycle control signal pctrl, the switch control module 904 further comprising a closed-cycle control signal input.

Fig. 11 shows a partial schematic structure diagram of the switching power supply 900 according to the embodiment of the present disclosure. The closed-cycle control module 908 further includes an error amplifying unit 912, a current adjusting unit 914, a first resistor R1, and a comparing unit 916.

The error amplifying unit 912 is configured to generate an error current I _ USM based on a difference between a feedback voltage of an output voltage of the switching power supply and a reference voltage. The current adjustment unit 914 is configured to generate a negative current I _ neg according to the error current. The negative current output terminal of the current adjusting unit 914 is electrically connected to one end of the first resistor R1. The other end of the first resistor R1 is electrically connected to the first contact. The comparison unit 916 is configured to generate the enabled closed-cycle control signal pctrl when a voltage of one end of the first resistor R1 and a voltage of an output terminal of the switching power supply satisfy a first predetermined condition. The switch control module 904 is further configured to generate a corresponding second switch control signal ctrl2 according to the enabled closed-cycle control signal pctrl to cause the second switch to open.

Fig. 12 shows a schematic structural diagram of the error amplifying unit 912 of the embodiment of the present disclosure. The error amplifying unit 912 further includes an operational amplifier 920, a first PMOS transistor P1, a first NMOS transistor N1, and a second NMOS transistor N2. An amplifier inverting input terminal of the operational amplifier 920 is configured to receive a feedback voltage FB of an output voltage of the switching power supply, an amplifier forward input terminal of the operational amplifier 920 is configured to receive a reference voltage VREF, and an amplifier output terminal of the operational amplifier 920 is electrically connected to a gate of the first PMOS transistor P1 and one end of the first capacitor, respectively. The other end of the first capacitor C is electrically connected to the ground GND. The source electrode of the first PMOS tube P1 is electrically connected with the power supply end of the switching power supply, and the drain electrode of the first PMOS tube P1 is respectively and electrically connected with the drain electrode of the first NMOS tube N1, the grid electrode of the first NMOS tube N1 and the grid electrode of the second NMOS tube N2. The source electrode of the first NMOS transistor N1 is electrically connected to the source electrode of the second NMOS transistor N2 and the ground GND, respectively. The drain electrode of the second NMOS tube N2 is used for outputting an error current I _ USM. It should be understood that the source of the first PMOS transistor P1 may be electrically connected to the power supply terminal of the switching power supply via the third resistor R3, for example.

In some embodiments, the feedback voltage FB of the output voltage of the switching power supply is a voltage value of the output voltage of the switching power supply divided by the voltage dividing network. In some embodiments, the feedback voltage FB of the output voltage of the switching power supply is equal to the output voltage of the switching power supply. The reference voltage VREF can be set as appropriate as required.

For convenience of explanation, fig. 13 shows a signal waveform diagram of the error amplification unit 912 of the embodiment of the present disclosure. It should be understood that the feedback voltage FB of the output voltage of the switching power supply and the output voltage V of the switching power supply _OUT Is in direct proportion. The operational amplifier 920 is a transconductance amplifier, and the operational amplifier 920 transconductance amplifies the voltage signal variation inputted from the inverting input terminal and the positive input terminal of the amplifier, converts the voltage signal into a current signal, and outputs the current signal via the amplifier output terminal of the operational amplifier 920. For example, after the switching frequency of the switching power supply 900 is locked at the first frequency, as the load further decreases, the average inductor current increases, resulting in the output voltage V of the switching power supply _OUT And thus the feedback voltage FB of the output voltage of the switching power supply rises. When the feedback voltage FB of the output voltage of the switching power supply is greater than the reference voltage VREF, the operational amplifier 920 generates a current I3 according to a difference between the feedback voltage FB of the output voltage of the switching power supply and the reference voltage VREF. The I3 current discharges the first capacitor C, and the voltage Vg at the gate of the first PMOS transistor P1 decreases. The voltage Vg of the gate of the first PMOS transistor P1 is the driving voltage of the first PMOS transistor P1, and thus, as the voltage Vg of the gate of the first PMOS transistor P1 decreases, the current flowing through the first PMOS transistor P1 increases. It should be understood that the first NMOS transistor N1 and the second NMOS transistor N2 form a current mirror structure. The current flowing through the first PMOS transistor P1 is mirrored to the second NMOS transistor N2 by the current mirror structure formed by the first NMOS transistor N1 and the second NMOS transistor N2, thereby forming an error current I _ USM. It should be appreciated that the error current I _ USM increases following the current flowing through the first PMOS transistor P1.

In some embodiments, the current adjusting unit 914 and the branch of the error amplifying unit 912 (e.g., the branch corresponding to the second NMOS transistor N2) for outputting the error current form a current mirror structure. Accordingly, the current adjusting unit 914 generates a negative current I _ neg according to the error current I _ USM by current mirroring of the current mirror structure. The direction of the negative current I _ neg is opposite to the direction of the error current I _ USM, and the magnitude of the negative current I _ neg is proportional to the magnitude of the error current I _ USM.

The error current I _ USM is transmitted to the subsequent current adjusting unit 914, and the average inductor current is reduced by increasing the negative current of the inductor L, so as to prevent the output voltage of the switching power supply from increasing, thereby playing a role in stabilizing the output voltage of the switching power supply.

The current adjustment unit 914 generates a negative current when the current value of the error current I _ USM is greater than zero. The comparison unit 916 is a zero-crossing detection unit. The condition for the on-period control signal output by the comparing unit 916 to flip (from high to low or from low to high) is that the voltage at the forward input end of the comparing unit 916 is equal to the voltage at the reverse input end, i.e., SW _ IN = VOUT _ IN, i.e., SW + I _ neg × R0= VOUT.

Therefore, the negative current I _ neg and the inductor current IL have a relationship shown in the following formula (2):

I_neg*R0＝VOUT-SW＝-IL*Rds_Q1 (2)

as can be seen from equation (2), when the inductor current IL is a negative current and reaches a peak value, SW _ IN = VOUT _ IN, the closed-cycle control signal pctrl output by the comparing unit 916 is inverted. The closed-cycle control signal pctrl output by the comparison unit 916 when SW _ IN = VOUT _ IN is the enabled closed-cycle control signal pctrl.

Fig. 14 shows a schematic diagram of a signal waveform associated with the comparison unit 916 of the embodiment of the disclosure. For ease of understanding, the current amplitude corresponding to I _ neg × R0 is also illustrated, as well as the voltage SW of the first contact. At a time a3, the switch control module 904 sets the first control signal ctrl1 to a low level and sets the second control signal ctrl2 to a high level, so as to turn off the first MOS transistor Q1 and turn on the second MOS transistor Q2. Then, the switching power supply 900 discharges and outputs electric power to the load. At time b3, the inductor current IL equals zero. At this time, SW _ IN is greater than VOUT _ IN, and the on-period control signal pctrl (the off-period control signal pctrl that is not enabled) output by the comparing unit 916 at this time is used to indicate that the second MOS transistor Q2 is continuously maintained to be turned on (i.e., the second switch is maintained to be turned on). Accordingly, the switch control module 904 continuously maintains the second control signal ctrl2 set to the high level in response to the non-enabled close-period control signal pctrl, so that the second MOS transistor Q2 maintains the on-state.

Next, between time b3 and time c3, the inductor L starts to form a negative current, and as shown in fig. 14, the inductor current IL has a negative value, which indicates that the current flows from the load to the switching power supply. At time c3, SW _ IN equals VOUT _ IN, the closed-cycle control signal pctrl output by the comparing unit 916 is inverted, and the closed-cycle control signal pctrl (the enabled closed-cycle control signal pctrl) output by the comparing unit 916 at this time is used to indicate that the second switch should be turned off at this time. Then, the switching control module 904 sets the second control signal ctrl2 to a low level in response to the enabled closed-cycle control signal pctrl, so that the second MOS transistor Q2 is turned off.

Next, between time c3 and time d3, the inductor current IL returns to zero through the body diode of the first MOS transistor Q1 in spite of the second MOS transistor Q2. Then, the first MOS transistor Q1 and the second MOS transistor Q2 remain in the off state until the switching control module 904 starts the next switching cycle according to the locked first frequency.

It should be understood that the error current I _ USM varies synchronously with the feedback voltage FB of the output voltage of the switching power supply, and the larger the feedback voltage FB of the output voltage of the switching power supply, the larger the error current I _ USM, and thus the larger the magnitude of the adjustment of the negative current of the inductance L. Accordingly, the smaller the feedback voltage FB of the output voltage of the switching power supply, the smaller the error current I _ USM, and thus the smaller the magnitude of the adjustment of the negative current of the inductance L. When the final loop is stable, the error current I _ USM is stable, and the amplitude of the adjustment of the negative current of the inductor L is stable, so that the average inductor current is stable, and therefore, the output voltage of the switching power supply is stable.

It should be noted that, IN the case that frequency locking has not occurred (i.e. the switching frequency is greater than the predetermined frequency threshold), the negative current I _ neg generated by the current adjusting unit 914 is 0, the on-period control module 908 also outputs the enabled on-period control signal pctrl when SW _ IN is equal to VOUT _ IN, and outputs the disabled on-period control signal pctrl when SW _ IN is not equal to VOUT _ IN. Likewise, the switch control module 904 sets the second control signal ctrl2 to a low level in response to the enabled closed-cycle control signal pctrl, so that the second MOS transistor Q2 is turned off. It should be appreciated that IN the case where the switching frequency is greater than the predetermined frequency threshold, when the inductor current IL is 0 (i.e., the switching power supply 900 discharges until the inductor current IL is 0), SW _ IN is equal to VOUT _ IN, and at this time, the closed-cycle control module 908 outputs the enabled closed-cycle control signal pctrl. Therefore, based on the closed-cycle control module 908, the enabled closed-cycle control signal pctrl may also be output appropriately when the switching frequency is greater than a predetermined frequency threshold, in order to implement, for example, PFM mode of the switching unit 900.

In the above scheme, the peak value of the negative current of the inductor L can be controlled by the negative current I _ neg generated by the current adjusting unit 914, so that the negative current of the inductor L can be reasonably adjusted in a fixed switching period, and thus, the effect of adjusting the average inductor current IL _ avg is achieved, and therefore, the output voltage of the switching power supply can be effectively stabilized.

Fig. 15 shows a waveform diagram of the inductor current IL according to an embodiment of the present disclosure. The fifth waveform curve L5 corresponds to a fifth load, for example, and the sixth waveform curve L6 corresponds to a sixth load, for example, which is lighter than the fifth load. As can be seen from the figure, by means of the frequency locking module 904, the switching frequency is locked, and accordingly, the switching period is locked at the predetermined timing threshold Tlock. As the load becomes lighter from the fifth load to the sixth load, the positive current peak value Ipeak corresponding to the inductor current IL remains unchanged, the negative current peak value corresponding to the inductor current IL changes from expect _ pre to expect _ new, and the amplitude value of expect _ new (i.e., the absolute value of expect _ new) is greater than the amplitude value of expect _ pre (i.e., the absolute value of expect _ pre). Based on this, the lighter the load, the more negative the inductance L is, and correspondingly, the smaller the average inductor current. Therefore, in the above scheme, the average inductor current becomes smaller as the load becomes lighter, so that the output voltage of the switching power supply is stabilized.

Having described embodiments of the present disclosure, the foregoing description is intended to be exemplary, not exhaustive, and not limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen in order to best explain the principles of the embodiments, the practical application, or improvements made to the technology in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

The above are merely alternative embodiments of the present disclosure and are not intended to limit the present disclosure, which may be modified and varied by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present disclosure should be included in the protection scope of the present disclosure.

Claims

1. A switching power supply, comprising:

a switching module comprising at least one switch configured to charge or discharge a switching power supply when closed;

the switch control module is configured to generate a control signal corresponding to the switching frequency and used for controlling the switching module to be opened or closed, the input end of the switch control module is electrically connected with the output end of the frequency locking module, and the switch control module is further configured to lock the switching frequency corresponding to the control signal at a first frequency which is greater than or equal to a preset frequency threshold value according to the input enabled frequency locking signal;

and the input end of the frequency locking module is electrically connected with the output end of the switch control module, and the frequency locking module is configured to enable the frequency locking signal output by the output end of the frequency locking module when the switching frequency corresponding to the control signal output by the switch control module is smaller than a preset frequency threshold value.

2. The switching power supply of claim 1, wherein the output of the switch control module comprises a first control output and a second control output, and wherein the at least one switch comprises:

a first switch configured to cause the switching power supply to charge when closed, the first switch comprising:

the first contact is electrically connected with the third contact of the second switch;

the second contact is electrically connected with the grounding end of the switch power supply; and

the first control end is electrically connected with the first control output end; and

a second switch configured to discharge the switching power supply when closed, the second switch comprising:

a third contact;

the fourth contact is electrically connected with the output end of the switching power supply; and

and the second control end is electrically connected with the second control output end.

3. The switching power supply according to claim 2, further comprising:

a closed cycle control module configured to generate a closed cycle control signal according to a difference between an output voltage feedback voltage of the switching power supply and a reference voltage and a magnitude relationship between the output voltage of the switching power supply and a voltage of the first contact, the closed cycle control module including:

the first voltage input end is electrically connected with the output end of the switching power supply;

a second voltage input end electrically connected with the first contact; and

the closed cycle control signal output end is electrically connected with the closed cycle control signal input end of the switch control module and used for outputting a closed cycle control signal;

the switch control module is further configured to generate and output a second control signal from a second control output in accordance with the closed-cycle control signal, the switch control module further comprising a closed-cycle control signal input.

4. The switching power supply according to claim 3, wherein the closed cycle control module further comprises:

an error amplification unit configured to generate an error current based on a difference between a feedback voltage of an output voltage of the switching power supply and a reference voltage;

a current adjustment unit configured to generate a negative current according to the error current, a negative current output terminal of the current adjustment unit being electrically connected to one end of the first resistor;

the other end of the first resistor is electrically connected with the first contact; and

a comparison unit configured to generate an enabled closed-cycle control signal when a voltage of one end of the first resistor and a voltage of an output terminal of the switching power supply satisfy a first predetermined condition;

the switch control module is further configured to generate a corresponding second switch control signal to cause the second switch to open according to the enabled close cycle control signal.

5. The switching power supply according to claim 4, wherein the direction of the negative current is opposite to the direction of the error current, and the magnitude of the negative current is proportional to the magnitude of the error current.

6. The switching power supply according to claim 4, wherein the comparison unit comprises a zero-crossing detection unit.

7. The switching power supply according to claim 4, wherein the error amplifying unit further comprises:

the inverting input end of the operational amplifier is configured to receive a feedback voltage of the output voltage of the switching power supply, the positive input end of the operational amplifier is configured to receive a reference voltage, and the output end of the operational amplifier is electrically connected with the grid electrode of the first PMOS tube and one end of the first capacitor respectively;

the other end of the first capacitor is electrically connected with a grounding end;

the source electrode of the first PMOS tube is electrically connected with the power supply end of the switching power supply, and the drain electrode of the first PMOS tube is electrically connected with the drain electrode of the first NMOS tube, the grid electrode of the first NMOS tube and the grid electrode of the second NMOS tube respectively;

the source electrode of the first NMOS tube is respectively and electrically connected with the source electrode of the second NMOS tube and the grounding end; and

and the drain electrode of the second NMOS tube is used for outputting error current.

8. The switching power supply according to claim 7, wherein the operational amplifier is of the transconductance amplifier type.

9. The switching power supply according to claim 1, wherein the predetermined frequency threshold is any value between 20kHz and 35 kHz.

10. The switching power supply according to claim 1, wherein the switching power supply is any one of a step-up switching power supply, a step-down switching power supply, and a step-down-step-up switching power supply.