CN115579295A - Method for manufacturing semiconductor packaging structure - Google Patents

Method for manufacturing semiconductor packaging structure Download PDF

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Publication number
CN115579295A
CN115579295A CN202110687869.8A CN202110687869A CN115579295A CN 115579295 A CN115579295 A CN 115579295A CN 202110687869 A CN202110687869 A CN 202110687869A CN 115579295 A CN115579295 A CN 115579295A
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China
Prior art keywords
package
sub
conductive
circuit
conductive element
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Pending
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CN202110687869.8A
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Chinese (zh)
Inventor
李森阳
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Shunsin Technology Zhongshan Ltd
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Shunsin Technology Zhongshan Ltd
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Priority to CN202110687869.8A priority Critical patent/CN115579295A/en
Priority to TW110123296A priority patent/TW202301629A/en
Publication of CN115579295A publication Critical patent/CN115579295A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

A method for manufacturing a semiconductor packaging structure comprises providing a substrate having a bottom surface; arranging a first circuit component, a second circuit component, a first conductive component and a second conductive component on a substrate, wherein the first conductive component and the second conductive component are arranged on two sides of the first circuit component, and the second conductive component is arranged between the first circuit component and the second circuit component; forming a sealing adhesive layer to cover the first circuit assembly, the second circuit assembly, the first conductive assembly and the second conductive assembly to form a packaging body, and exposing the first conductive assembly and the second conductive assembly; cutting the package to form a first sub-package and a second sub-package; turning over the first sub-package; and finally, contacting the bottom surface of the first sub-packaging body with the bottom surface of the second sub-packaging body. The semiconductor packaging body is cut and then is assembled in a stacking mode, so that the assembling procedure can be simplified, and the reliability of the packaged product can be improved.

Description

Method for manufacturing semiconductor packaging structure
Technical Field
The present application relates to a method for manufacturing a semiconductor package, and more particularly, to a method for manufacturing a semiconductor package by cutting a semiconductor package and stacking the semiconductor package.
Background
In recent years, as semiconductor technology has been rapidly developed, the functions of chips have been increasingly changed and the sizes thereof have been increasingly reduced. For a single chip, more and more functions require more signal transmission pins, and on the other hand, smaller size means more dense chip and signal transmission pins. However, with such a large and high-density design, the simplification of the process is an important research topic for the continuous development of semiconductor technology because the intensive structure greatly increases the complexity of the process and affects the reliability of the product.
Disclosure of Invention
In view of the above, in one embodiment of the present disclosure, a method for manufacturing a semiconductor package structure is provided, which improves reliability of a packaged product by cutting a semiconductor package and performing lamination assembly, and simplifies assembly processes to improve stability of the product.
An embodiment of the present application discloses a method for manufacturing a semiconductor package structure, which includes the following steps: providing a substrate having a bottom surface; arranging a first circuit component and a second circuit component on the substrate; disposing a first conductive element and a second conductive element on the substrate, wherein the first conductive element and the second conductive element are disposed on two sides of the first circuit element, and the second conductive element is disposed between the first circuit element and the second circuit element; forming a sealant layer to cover the first and second circuit elements, the first and second conductive elements, and the substrate to form a package body, and expose the first and second conductive elements; cutting the package to form a first sub-package and a second sub-package; turning over the first sub-package; and contacting the bottom surface of the first sub-package with the bottom surface of the second sub-package.
An embodiment of the present application discloses a method for manufacturing a semiconductor package structure, which includes the following steps: providing a substrate having a first surface and a second surface opposite to the first surface; arranging a first circuit component and a second circuit component on the first surface; disposing a first conductive element and a second conductive element on the first surface, wherein the first conductive element and the second conductive element are disposed on two sides of the first circuit element, and the second conductive element is disposed between the first circuit element and the second circuit element; forming a sealant layer to cover the first and second circuit assemblies, the first and second conductive assemblies, and the substrate to form a package, and expose the first and second conductive assemblies; cutting the package to form a first sub-package and a second sub-package; and contacting the second surfaces of the first sub-package and the second sub-package with each other.
According to an embodiment of the present invention, the method further includes disposing a plurality of bonding pads on the bottom surface, wherein the bonding pads of the first sub-package are in contact with the bonding pads of the second sub-package.
According to an embodiment of the present invention, the first sub-package is rotated 180 ° and then bonded to the second sub-package.
According to an embodiment of the present disclosure, the cutting portion of the package body is located between the second conductive element and the second circuit element.
According to an embodiment of the present application, the first conductive element and the second conductive element are solder balls.
According to the semiconductor package structure manufacturing method provided by the embodiment of the application, the semiconductor package body is cut and then the semiconductor package body is assembled in a stacking mode, so that the semiconductor double-sided package structure is realized, in the manufacturing process, the components of the upper layer and the lower layer of the semiconductor package structure can be installed on the substrate in the same placing procedure, the assembling procedure is effectively simplified, in addition, compared with the method of directly folding the substrate, the influence on the product quality caused by the deformation or the fragmentation of the substrate is avoided through the cutting mode, and the reliability and the production efficiency of the semiconductor package product are greatly improved.
Drawings
Fig. 1 is a flowchart illustrating a method of fabricating a semiconductor package according to an embodiment of the present application.
Fig. 2A-2F are schematic cross-sectional views illustrating a method for fabricating a semiconductor package structure according to an embodiment of the present application.
Description of the main elements
10. 10A, 10B: substrate board
101: first surface
102: second surface 102A, 102B
12. 12A, 12B: bonding pad
14A: first circuit assembly
14B: second circuit assembly
16A: first conductive component
16B: second conductive assembly
18: adhesive sealing layer
19: at the cutting part
20: package body
22A: first sub-package
22B: second sub-package
S10-S15: flow process steps
The following detailed description will further illustrate the invention in conjunction with the above-described figures.
Detailed Description
To facilitate an understanding and appreciation of the application by those of ordinary skill in the art, the following detailed description of the application in connection with the accompanying drawings and examples should be understood to provide many applicable inventive concepts that can be embodied in a wide variety of specific forms. Those of skill in the art may now appreciate that the invention may be practiced with other structural, logical, and electrical changes that may be made without departing from the spirit and scope of the present application.
The present specification provides various examples to illustrate the technical features of various embodiments of the present application. The arrangement of the components in the embodiments is illustrative and not intended to limit the present application. And the repetition of certain reference numbers in the following examples is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various examples. Wherein like reference numerals are used throughout the drawings and the description to refer to the same or like parts. The illustrations in this specification are in simplified form and are not drawn to precise scale. For clarity and ease of description, directional terms (e.g., top, bottom, up, down, and diagonal) are used with accompanying figures. Furthermore, the directional terms used in the following description should not be construed as limiting the scope of the present application unless expressly recited in the claims below.
Further, in describing some embodiments of the application, the specification may have presented the method and/or process of the application as a particular sequence of steps. However, the methods and processes are not necessarily limited to the particular order of steps described, as such may not necessarily be performed in the particular order of steps described. One skilled in the art will recognize that other sequences are possible implementations. Accordingly, the particular order of the steps set forth in the specification is not intended to be construed as limitations on the claimed subject matter. Moreover, the claimed methods and/or processes are not limited by the order of execution, and one skilled in the art will recognize that the order of execution does not depart from the spirit and scope of the present disclosure.
Fig. 1 is a flowchart illustrating a method for manufacturing a semiconductor package according to an embodiment of the present disclosure. Fig. 2A-2F are schematic cross-sectional views illustrating a method for fabricating a semiconductor package structure according to an embodiment of the present application. Referring to fig. 1, a substrate 10 is provided (step S10). As shown in fig. 2A, the substrate 10 may be a substrate having two or more circuit layers after pre-processing, that is, a substrate having multiple circuit layers is formed by providing a core plate, forming a first conductive metal layer on the surface of the core plate, patterning the first conductive metal layer to form a first circuit layer, performing a build-up process to form an insulating layer on the first circuit layer, forming a second conductive metal layer on the insulating layer, and patterning the second conductive metal layer to form a second circuit layer. The insulating layer in the substrate 10 may be made of an insulating organic material or a ceramic material such as epoxy resin (epoxy), polyimide (Polyimide), cyanate Ester (Cyanate Ester), glass fiber, bismaleimide Triazine (BT), or a mixture of epoxy resin and glass fiber; the material of the conductive metal layer in the substrate 10 may be gold, silver, copper, aluminum, tungsten, tin, alloy or other suitable conductive material, generally copper with high conductivity is used as the main material of the conductive wire of the substrate for transmitting signals, and a plurality of conductive vias (Via) are formed in the insulating layer in the substrate 10 to electrically connect the adjacent circuit layers. In addition, the substrate 10 may be formed by a lamination method (bonded) or a Build-up method (Build-up), which is well known to those skilled in the art and will not be described herein for brevity. The substrate 10 has a first surface 101 (a top surface in fig. 2A) and a second surface 102 (a bottom surface in fig. 2A) opposite to the first surface 101, a plurality of bonding pads 12 are formed on the second surface 102, and the bonding pads 12 are conductors and electrically connected to the conductive metal layer in the substrate 10.
Next, the first circuit element 14A, the second circuit element 14B, the first conductive element 16A and the second conductive element 16B are disposed on the substrate 10 (step S11). As shown in fig. 2B, a first circuit component 14A is provided in the left half of fig. 2B and a second circuit component 14B is provided in the right half of fig. 2B. According to an embodiment of the present disclosure, the first circuit element 14A and the second circuit element 14B may include various electronic components (electronic components) including active components (active devices) or integrated circuits (passive devices) including resistors, capacitors, inductors, filters, oscillators, etc., digital circuits or analog circuits (digital or analog circuits), such as optoelectronic devices (optoelectronic devices), micro-electro-mechanical Systems (MEMS), power amplification chips, power management chips, biometric devices, micro-fluidic Systems (Micro-fluidic Systems), or Physical sensors (Physical sensors) that measure changes in Physical quantities such as heat, light, and pressure. In particular, a Wafer Scale Package (WSP) process can be selectively used for semiconductor chips such as an image sensor, light-emitting diodes (LEDs), solar cells (solar cells), accelerometers (accelerometers), gyroscopes (gyroscopes), fingerprint sensors, micro actuators (micro actuators), surface acoustic wave devices (surface acoustic wave devices), pressure sensors (process sensors), or inkjet heads (ink printer heads).
According to an embodiment of the present disclosure, the first circuit element 14A and the second circuit element 14B may be disposed on the first surface 101 of the substrate 10 in a flip-chip manner and electrically connected to the conductive metal layer in the substrate 10, and in addition, the first circuit element 14A and the second circuit element 14B may also be disposed on the first surface 101 of the substrate 10 by an adhesive and electrically connected to the conductive metal layer in the substrate 10 by a Wire bonding manner (Wire bonding), that is, the present disclosure may be implemented in a flip-chip manner or a Wire bonding manner, which is an equivalent implementation that can be derived by those skilled in the art. In addition, a first conductive member 16A and a second conductive member 16B are provided in the left half of fig. 2B. According to an embodiment of the present disclosure, the first conductive element 16A and the second conductive element 16B may be solder balls. As shown in fig. 2B, the first conductive element 16A and the second conductive element 16B are disposed on two sides of the first circuit element 14A, and the second conductive element 16B is disposed between the first circuit element 14A and the second circuit element 14B. It should be noted that fig. 2B shows a single first circuit element 14A as an example, and when there are a plurality of first circuit elements 14A, all of the first circuit elements 14A are disposed between the first conductive element 16A and the second conductive element 16B.
Next, an adhesive layer 18 is conformally formed on the substrate 10 (step S12). The sealant layer 18 can provide mechanical stability and protection against oxidation, humidity, and other environmental conditions. According to an embodiment of the present application, the molding compound layer 18 may be formed of a molding material (molding material). The encapsulant may include an acid-based resin (Novolac-based resin), an epoxy-based resin (epoxy-based resin), a silicone-based resin (silicone-based resin), or other suitable coating agent. The encapsulating material may also include a suitable filler (filler), such as powdered silicon dioxide. The encapsulating material may be a pre-impregnated material, such as a pre-impregnated dielectric material. As shown in fig. 2C, an adhesive layer 18 is conformally formed on the substrate 10, and covers the first circuit element 14A and the second circuit element 14B and covers a portion of the first conductive element 16A and the second conductive element 16B, and in fig. 2C, a portion of the first conductive element 16A and a portion of the second conductive element 16B are not covered by the adhesive layer 18 and are exposed outside the adhesive layer 18. After the adhesive layer 18 is formed, the package body 20 according to an embodiment of the present application is completed. Next, the package 20 is cut at the cutting position 19 between the second conductive element 16B and the second circuit element 14B (step S13), as shown in fig. 2D.
Referring to fig. 2D, the diced package 20 forms a first sub-package 22A and a second sub-package 22B which are separated. For convenience of illustration, in fig. 2D, the substrate 10 at the first sub-package 22A is re-labeled with 10A, the second surface 102 is re-labeled with 102A, and the bonding pads 12 are re-labeled with 12A, and similarly, the substrate 10 at the second sub-package 22B is re-labeled with 10B, the second surface 102 is re-labeled with 102B, and the bonding pads 12 at the second sub-package 22B are re-labeled with 12B.
Next, the first sub-package 22A is rotated by 180 ° (step S14), and the rotated state is shown in fig. 2E. It should be noted that, in the embodiment, the first sub-package 22A is turned over as an example, and in practical implementation, the second sub-package 22B may also be turned over, and the turned over sub-package may be selected according to actual device characteristics or process limitations. Next, the second surface 102A of the flipped first sub-package 22A and the second surface 102B of the second sub-package 22B are contacted with each other (step S15), as shown in fig. 2F, after the first sub-package 22A and the second sub-package 22B are combined, the bonding pads 12B on the second surface 102B and the bonding pads 12A on the second surface 102A are contacted and electrically connected to each other, so as to transmit the electrical signal between the first sub-package 22A and the second sub-package 22B. According to an embodiment of the present invention, all the bonding pads 12B on the second surface 102B are in one-to-one contact with the bonding pads 12A on the second surface 102A. In addition, in the position where the second surface 102A of the first sub-package 22A contacts the second surface 102B of the second sub-package 22B, the insulating portion of the non-bonding pad can be bonded through the adhesive. According to an embodiment of the present disclosure, the adhesive layer may include Polyimide (PI), polyethylene Terephthalate (PET), teflon (Teflon), liquid Crystal Polymer (LCP), polyethylene (PE), polypropylene (PP), polystyrene (PS), polyvinyl Chloride (PVC), nylon (Nylon or Polyamides), polymethyl methacrylate (PMMA), ABS plastic (Acrylonitrile-Butadiene-Styrene), phenol resin (Phenolic resin), epoxy resin (Epoxy), polyester (Polyester), silicone (Silicone), polyurethane (PU), polyamide-imide (PAI), or a combination thereof, as long as the adhesive layer has the above characteristics.
According to the semiconductor package structure manufacturing method provided by the embodiment of the application, the semiconductor double-sided package structure is realized by cutting the semiconductor package body and then performing lamination assembly, in the manufacturing process, the components of the upper layer and the lower layer of the semiconductor package structure can be installed on the substrate in the same piece placing procedure, so that the assembly procedure is effectively simplified, and in addition, compared with the method of directly folding the substrate, the method of cutting avoids the influence on the product quality caused by the deformation or the fragmentation of the substrate, and the reliability and the production efficiency of the semiconductor package product are greatly improved.
It will be apparent to those skilled in the art that other changes and modifications can be made in the invention and its practical application based on the combination of the inventive concept of the present application without departing from the scope of the invention as defined in the appended claims.

Claims (10)

1. A method for manufacturing a semiconductor packaging structure is characterized by comprising the following steps:
providing a substrate having a bottom surface;
arranging a first circuit component and a second circuit component on the substrate;
arranging a first conductive element and a second conductive element on the substrate, wherein the first conductive element and the second conductive element are arranged on two sides of the first circuit element, and the second conductive element is arranged between the first circuit element and the second circuit element;
forming a sealant layer to cover the first and second circuit elements, the first and second conductive elements, and the substrate to form a package body, and expose the first and second conductive elements;
cutting the package body to form a first sub-package body and a second sub-package body which are separated;
turning over the first sub-package; and
contacting the bottom surface of the first sub-package with the bottom surface of the second sub-package to bond the first sub-package and the second sub-package.
2. The method of claim 1, further comprising disposing a plurality of bonding pads on the bottom surface, wherein the bonding pads on the first sub-package are in contact with the bonding pads on the second sub-package.
3. The method for manufacturing a semiconductor package structure according to claim 1, wherein the first sub-package is joined to the second sub-package after being rotated by 180 °.
4. The method of manufacturing a semiconductor package structure of claim 1, wherein the cut of the package body is located between the second conductive element and the second circuit element.
5. The method for manufacturing a semiconductor package according to claim 1, wherein the first conductive element and the second conductive element are solder balls.
6. A method for manufacturing a semiconductor packaging structure is characterized by comprising the following steps:
providing a substrate having a first surface and a second surface opposite to the first surface;
arranging a first circuit component and a second circuit component on the first surface;
arranging a first conductive element and a second conductive element on the first surface, wherein the first conductive element and the second conductive element are arranged on two sides of the first circuit element, and the second conductive element is arranged between the first circuit element and the second circuit element;
forming a sealant layer to cover the first and second circuit assemblies, the first and second conductive assemblies, and the substrate to form a package body, and expose the first and second conductive assemblies;
cutting the package body to form a first sub-package body and a second sub-package body which are separated; and
contacting the second surfaces of the first and second sub-packages with each other to bond the first and second sub-packages.
7. The method of claim 6, further comprising disposing a plurality of bonding pads on the second surface, wherein the bonding pads on the first sub-package are in contact with the bonding pads on the second sub-package.
8. The method for manufacturing a semiconductor package structure according to claim 6, wherein the first sub-package body is joined to the second sub-package body after being rotated 180 °.
9. The method of manufacturing a semiconductor package structure of claim 6, wherein the cut of the package body is located between the second conductive element and the second circuit element.
10. The method of claim 6, wherein the first conductive element and the second conductive element are solder balls.
CN202110687869.8A 2021-06-21 2021-06-21 Method for manufacturing semiconductor packaging structure Pending CN115579295A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN202110687869.8A CN115579295A (en) 2021-06-21 2021-06-21 Method for manufacturing semiconductor packaging structure
TW110123296A TW202301629A (en) 2021-06-21 2021-06-25 Method for manufacturing semiconductor package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202110687869.8A CN115579295A (en) 2021-06-21 2021-06-21 Method for manufacturing semiconductor packaging structure

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Publication Number Publication Date
CN115579295A true CN115579295A (en) 2023-01-06

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