CN115578979A

CN115578979A - Drive circuit, display panel and display device

Info

Publication number: CN115578979A
Application number: CN202211216230.2A
Authority: CN
Inventors: 吴常志
Original assignee: Xiamen Tianma Microelectronics Co Ltd
Current assignee: Xiamen Tianma Microelectronics Co Ltd
Priority date: 2022-09-30
Filing date: 2022-09-30
Publication date: 2023-01-06

Abstract

The embodiment of the application provides a driving circuit, a display panel and a display device, wherein the driving circuit comprises a plurality of scanning units and a control module; the scanning unit comprises a shift register and an output module, wherein the output end of the shift register is electrically connected with the output module, and the output module is used for outputting scanning signals; the control module is electrically connected with at least part of the output modules and is used for controlling the output modules not to output effective scanning signals in the first working period of the driving circuit and outputting effective scanning signals in the second working period of the driving circuit. Under the condition that the signal transmission of the output end of the shift register is not influenced, the display panel can be stopped refreshing data, and the display panel is prevented from displaying wrong pictures; when the display panel displays the picture again, the situation that a plurality of scanning units output effective scanning signals simultaneously is avoided, so that the problem of double images of the displayed picture is avoided, and the display quality of the display panel can be effectively improved.

Description

Drive circuit, display panel and display device

[ technical field ] A

The application relates to the technical field of display, in particular to a driving circuit, a display panel and a display device.

[ background of the invention ]

With the continuous development of display technologies, the appearance of various screen technologies provides infinite possibilities for display devices, the display devices are more closely related to the lives of people, and the application scenes of the display devices are more and more complex.

In the prior art, when a display device is interfered by an external signal (such as static electricity), a display picture usually has a flicker problem, and the display quality is affected.

[ contents of application ]

In view of the above, embodiments of the present application provide a driving circuit, a display panel and a display device to solve the above problems.

In a first aspect, an embodiment of the present application provides a driving circuit, which includes a plurality of scanning units and a control module; the scanning unit comprises a shift register and an output module, wherein the output end of the shift register is electrically connected with the output module, and the output module is used for outputting scanning signals; the control module is electrically connected with at least part of the output modules and is used for controlling the output modules not to output effective scanning signals in the first working period of the driving circuit and outputting effective scanning signals in the second working period of the driving circuit.

In one implementation form of the first aspect, the control module comprises a first input and a second input; the first input end is electrically connected with the first signal wire, the second input end is electrically connected with the second signal wire, and the output end of the control module is electrically connected with the output module; in a first working period, the control module transmits a first signal on the first signal line to the output module; in the second working period, the control module transmits the second signal on the second signal line to the output module.

In one implementation manner of the first aspect, the control module includes a first transistor and a second transistor, a first pole of the first transistor is electrically connected to the first signal line, a second pole of the first transistor is electrically connected to the output terminal of the control module, a first pole of the second transistor is electrically connected to the second signal line, and a second pole of the second transistor is electrically connected to the output terminal of the control module.

In an implementation manner of the first aspect, in the same control module, the gate of the first transistor and the gate of the second transistor are electrically connected to the same control signal line, and the channel type of the first transistor is different from the channel type of the second transistor.

In one implementation form of the first aspect, at least some of the different control modules are electrically connected to the same control signal line.

In an implementation manner of the first aspect, the output module includes a first and gate, a first input end of the first and gate is electrically connected to the output end of the shift register, a second input end of the first and gate is electrically connected to the clock signal line, a third input end of the first and gate is electrically connected to the output end of the control module, and an output end of the first and gate is electrically connected to the output end of the output module.

In an implementation manner of the first aspect, the first and gate includes a first nand gate and a first inverter unit, a first input end of the first nand gate is electrically connected to an output end of the shift register, a second input end of the first nand gate is electrically connected to the clock signal line, a third input end of the first nand gate is electrically connected to an output end of the control module, an output end of the first nand gate is electrically connected to an input end of the first inverter unit, and an output end of the first inverter unit is electrically connected to an output end of the output module.

In an implementation manner of the first aspect, the first and gate includes a first and second sub and gate, a first input end of the first and gate is electrically connected to an output end of the shift register, a second input end of the first and gate is electrically connected to the clock signal line, and an output end of the first and gate is electrically connected to a first input end of the second and gate; the second input end of the second sub AND gate is electrically connected with the output end of the control module, and the output end of the second sub AND gate is electrically connected with the output end of the output module.

In an implementation manner of the first aspect, the first sub and gate includes a first nand gate and a first inverter unit, a first input end of the first nand gate is electrically connected to an output end of the shift register, a second input end of the first nand gate is electrically connected to the clock signal line, an output end of the first nand gate is electrically connected to an input end of the first inverter unit, and an output end of the first inverter unit is electrically connected to a first input end of the second sub and gate; the second sub AND gate comprises a second NAND gate and a second inverter unit, a first input end of the second NAND gate is electrically connected with an output end of the first inverter unit, a second input end of the second NAND gate is electrically connected with an output end of the control module, an output end of the second NAND gate is electrically connected with an input end of the second inverter unit, and an output end of the second inverter unit is electrically connected with an output end of the output module.

In an implementation manner of the first aspect, the effective scan signal output by the output module is a high-level signal, the first signal transmitted by the first signal line is a low-level signal, and the second signal transmitted by the second signal line is a high-level signal.

In a second aspect, an embodiment of the present application provides a display panel including the driving circuit as provided in the first aspect.

In a third aspect, embodiments of the present application provide a display device, including the display panel provided in the second aspect.

In the embodiment of the application, in the first working period of the driving circuit, the control module controls the output module electrically connected with the control module not to output the effective scanning signal, so that the display panel can be stopped refreshing data under the condition that the output end of the shift register is not influenced to transmit signals, and the display panel is prevented from displaying wrong pictures. In the second working period of the driving circuit, the control module controls the output module electrically connected with the control module to output an effective scanning signal, namely, the output module can restore the conventional working state, because the signal output by the output end of the shift register is not influenced, when the output module restores the conventional working state, the driving circuit can immediately restore the conventional working state, and the condition that a plurality of scanning units output the effective scanning signal simultaneously when the display panel displays a picture again is avoided, so that the problem that double images appear in the display picture is avoided, and the display quality of the display panel can be effectively improved.

In addition, after the external interference signal disappears, the driving circuit can immediately recover to the normal working state, namely, the scanning units in the driving circuit can immediately output the effective scanning signals in sequence according to the level transmission sequence, and the effective scanning signals do not need to be output in sequence until the display panel displays the next frame of picture, thereby being beneficial to further improving the display quality of the display panel.

[ description of the drawings ]

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a schematic diagram of a driving circuit according to an embodiment of the present disclosure;

fig. 2 is an application scenario of a driving circuit according to an embodiment of the present application;

fig. 3 is a schematic circuit connection diagram of a scan unit and a control module according to an embodiment of the present disclosure;

FIG. 4 is a timing diagram of a control module according to an embodiment of the present disclosure;

FIG. 5 is a schematic diagram of another driving circuit provided in the embodiment of the present application;

FIG. 6 is a schematic diagram illustrating a circuit connection between another scan unit and a control module according to an embodiment of the present disclosure;

FIG. 7 is a schematic diagram illustrating a circuit connection between another scan cell and a control module according to an embodiment of the present disclosure;

FIG. 8 is a timing diagram of the circuit of FIG. 7;

fig. 9 is a timing diagram of a driving circuit according to an embodiment of the present disclosure;

fig. 10 is a schematic view of a display device according to an embodiment of the present disclosure.

[ detailed description ] A

In order to better understand the technical solution of the present application, the following detailed description is made with reference to the accompanying drawings.

It should be understood that the embodiments described are only a few embodiments of the present application, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The terminology used in the embodiments of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in the examples of this application and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

It should be understood that the term "and/or" as used herein is merely one type of association that describes an associated object, meaning that three relationships may exist, e.g., a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.

In the description herein, it is to be understood that the terms "substantially", "approximately", "about", "substantially", and the like, as used in the claims and the examples herein, are intended to be generally accepted as not being precise, within the scope of reasonable process operation or tolerance.

It is to be understood that although the terms first, second, etc. may be employed to describe signal lines, operating periods, transistors, input terminals, etc. in the embodiments of the present application, these signal lines, operating periods, transistors, input terminals, etc. should not be limited to these terms. These terms are only used to distinguish signal lines, operation periods, transistors, input terminals, and the like from one another. For example, a first signal line may also be referred to as a second signal line, and similarly, a second signal line may also be referred to as a first signal line, without departing from the scope of embodiments of the present application.

In the field of display technology, a pixel array of a display panel generally includes a plurality of rows of gate lines and a plurality of columns of data lines interleaved with the gate lines, and when a frame of picture is displayed, a driving circuit including a plurality of cascaded scanning units generally provides scanning signals to the plurality of rows of gate lines of the pixel array, so as to control the plurality of rows of gate lines to sequentially transmit enable signals, and simultaneously provides data signals to corresponding rows of pixel units in the pixel array through the data lines.

In the related art, when the display panel is interfered by an external signal (e.g., external static electricity), in order to prevent the transmission of an erroneous data signal to the pixel unit, the driving circuit is usually turned off, so as to stop refreshing the data of the display panel. However, because the logic inside the driving circuit is not cleared, when a picture is displayed again, the situation that a plurality of rows of grid lines transmit enable signals simultaneously exists, so that the picture generates double images instantly, the phenomenon of screen flashing is caused, and the display quality is influenced.

The applicant provides a solution to the problems of the prior art through intensive research.

Fig. 1 is a schematic diagram of a driving circuit according to an embodiment of the present disclosure; fig. 2 is an application scenario of a driving circuit according to an embodiment of the present application.

The embodiment of the present application provides a driving circuit 100, as shown in fig. 1, the driving circuit 100 includes a plurality of cascaded scanning units 10, each scanning unit 10 includes a shift register 11 and an output module 12, an output end of the shift register 11 is electrically connected to the output module 12, an output end of the shift register 11 is used for outputting a cascade signal, and the output module 12 is used for outputting a scanning signal.

As shown in fig. 2, the driving circuit 100 provided in the embodiment of the present application may be disposed in the non-display area NA of the display panel 01, and the plurality of cascaded scanning units 10 included in the driving circuit 100 may sequentially output the valid scanning signals to be provided to the scanning lines SL in the display area AA of the display panel 01.

With reference to fig. 1, the driving circuit 100 further includes a control module 20, and the control module 20 is electrically connected to at least a portion of the output module 12.

Optionally, the output modules 12 in each scanning unit 10 are electrically connected to the control modules 20 in a one-to-one correspondence.

Optionally, the output modules 12 in the partial scanning unit 10 are electrically connected to the control modules 20 in a one-to-one correspondence.

For example, the output module 12 in the odd line scanning unit 10 is electrically connected to the control module 20, and the output module 12 in the even line scanning unit 10 is not connected to the control module 20; or the output module 12 in the even line scanning unit 10 is electrically connected with the control module 20, and the output module 12 in the odd line scanning unit 10 is not connected with the control module 20.

The control module 20 is used for controlling the output module 12 to be incapable of outputting the valid scan signal in the first operation period T1 of the driving circuit 100 and capable of outputting the valid scan signal in the second operation period T2 of the driving circuit 100. The effective scan signal is that after the scan line SL electrically connected to the output terminal of the output module 12 receives the effective scan signal, the transistor controlled by the scan line SL is turned on.

The first operation period T1 of the driving circuit 100 may be an operation period of the driving circuit 100 when the display panel 01 detects an interference signal (such as external static electricity), and the second operation period T2 of the driving circuit 100 may be an operation period of the driving circuit 100 after the interference signal disappears.

In the embodiment of the present application, in the first working period T1 of the driving circuit 100, the control module 20 controls the output module 12 electrically connected thereto to be unable to output the valid scan signal, so that the display panel 01 can stop refreshing data without affecting the transmission of the cascade signal at the output end of the shift register 11, thereby preventing the display panel 01 from displaying an error picture. In the second working period T2 of the driving circuit 100, the control module 20 controls the output module 12 electrically connected to the control module to output an effective scanning signal, that is, the output module 12 can recover to the normal working state, because the cascade signal output by the output end of the shift register 11 is not affected, when the output module 12 recovers to the normal working state, the driving circuit 100 can immediately recover to the normal working state, and the situation that a plurality of scanning units 10 output effective scanning signals simultaneously when the display panel 01 redisplays a picture is avoided, thereby avoiding the problem of ghost image of the display picture, and effectively improving the display quality of the display panel 01.

In addition, after the external interference signal disappears, the driving circuit 100 can immediately return to the normal operating state, that is, the scanning units 10 in the driving circuit 100 immediately output the effective scanning signals in sequence according to the step transmission sequence, and do not need to wait until the display panel 01 displays the picture again to start outputting the effective scanning signals in sequence, which is beneficial to further improving the display quality of the display panel 01.

It should be noted that, in the embodiment of the present application, the normal operating state of the driving circuit 100 may refer to that the driving circuit 100 sequentially provides the active scan signals to the scan lines SL in the display area AA of the display panel 01.

Fig. 3 is a schematic circuit connection diagram of a scan unit and a control module according to an embodiment of the present disclosure.

In one embodiment of the present application, as shown in fig. 3, the control module 20 includes a first input terminal 20A1 and a second input terminal 20A2, the first input terminal 20A1 is electrically connected to the first signal line CL1, the second input terminal 20A2 is electrically connected to the second signal line CL2, and the output terminal 20B of the control module 20 is electrically connected to the output module 12.

During the first operation period T1, the control module 20 transmits the first signal VGL on the first signal line CL1 to the output module 12.

During the second operation period T2, the control module 20 transmits the second signal VGH on the second signal line CL2 to the output module 12.

Optionally, the effective scan signal output by the output module 12 is a high level signal, the first signal VGL transmitted on the first signal line CL1 is a low level signal, and the second signal VGH transmitted on the second signal line CL2 is a high level signal.

That is, the control module 20 controls the output module 12 not to output the valid scan signal during the first operation period T1 and to output the valid scan signal during the second operation period T2 by time-sharing transmitting the first signal VGL and the second signal VGH to the output module 12.

Specifically, as shown in fig. 3, the control module 20 includes a first transistor M1 and a second transistor M2, a first pole of the first transistor M1 is electrically connected to the first signal line CL1, and a second pole is electrically connected to the output terminal 20B of the control module 20; the first pole of the second transistor M2 is electrically connected to the second signal line CL2, and the second pole is electrically connected to the output terminal 20B of the control module 20.

Note that, the first pole of the first transistor M1 may be the source thereof, and the second pole may be the drain thereof; the first pole of the second transistor M2 may be its source and the second pole may be its drain. In some other embodiments, the first pole of the first transistor M1 may be its drain, the second pole may be its source; the first pole of the second transistor M2 may be its drain and the second pole its source.

Alternatively, in the same control module 20, the gate of the first transistor M1 and the gate of the second transistor M2 are electrically connected to the same control signal line EN, and the channel type of the first transistor M1 is different from the channel type of the second transistor M2.

Fig. 4 is a timing diagram of a control module according to an embodiment of the present disclosure.

The operation of the control module 20 is described below with reference to fig. 3 and 4:

in the embodiment of the present application, the first transistor M1 is a P-type transistor, and the second transistor M2 is an N-type transistor. Of course, in some other embodiments, the first transistor M1 may be an N-type transistor, and the second transistor M2 may be a P-type transistor.

In a first working period T1, a control signal line EN transmits a low-level signal, a first transistor M1 is turned on, and a second transistor M2 is turned off; the first signal VGL on the first signal line CL1 is transmitted to the output module 12 through the turned-on first transistor M1, thereby controlling the output module 12 not to output a valid scan signal.

In a second working period T2, the control signal line EN transmits a high level signal, the first transistor M1 is turned off, and the second transistor M2 is turned on; the second signal VGH on the second signal line CL2 is transmitted to the output module 12 through the turned-on second transistor M2, so as to control the output module 12 to output a valid scan signal, i.e., the output module 12 recovers to a normal operating state.

This application embodiment when guaranteeing that control module 20 can transmit first signal VGL and second signal VGH timesharing to output module 12, can reduce the quantity of control signal line EN to reduce drive circuit 100's the line quantity of walking, be favorable to reducing drive circuit 100's the preparation degree of difficulty, save the cost.

Fig. 5 is a schematic diagram of another driving circuit according to an embodiment of the present disclosure.

Further, in the driving circuit 100, at least some of the different control modules 20 are electrically connected to the same control signal line EN, thereby further reducing the number of control signal lines EN in the driving circuit 100.

Alternatively, as shown in fig. 5, in the driving circuit 100, all the control modules 20 are electrically connected to the same control signal line EN, that is, the gate of the first transistor M1 and the gate of the second transistor M2 in each control module 20 are connected to the same control signal line EN.

In an embodiment of the present application, please refer to fig. 3, the output module 12 includes a first and gate 121, a first input terminal of the first and gate 121 is electrically connected to the output terminal of the shift register 11, a second input terminal of the first and gate is electrically connected to the clock signal line CK, a third input terminal of the first and gate is electrically connected to the output terminal 20B of the control module 20, and an output terminal of the first and gate 121 is electrically connected to the output terminal OUT of the output module 12.

That is, the output module 12 may include only one first and gate 121, the first and gate 121 includes three input terminals and one output terminal, and the first and gate 121 outputs the scan signal in response to the cascade signal transmitted from the output terminal of the shift register 11, the clock signal transmitted from the clock signal line CK, and the signal transmitted from the output terminal 20B of the control module 20.

As can be seen from the characteristics of the and gates, when the first input terminal, the second input terminal, and the third input terminal of the first and gate 121 receive the same level signal, the level signal output by the output terminal of the first and gate 121 is the same as the level signal received by the input terminal thereof. When the level signals received by any two of the first input terminal, the second input terminal, and the third input terminal of the first and gate 121 are different, the output terminal of the first and gate 121 transmits a low level signal.

In this embodiment, the effective scan signal output by the output module 12 may be a high level signal, and when the first input terminal, the second input terminal, and the third input terminal of the first and gate 121 all receive the high level signal, the first and gate 121 may output the high level signal, that is, the effective scan signal.

In combination with the operation process of the control module 20, in the first operation period T1, the control module 20 transmits the first signal VGL on the first signal line CL1 to the output terminal 20B of the control module 20, that is, the third input terminal of the first and gate 121 receives the first signal VGL, and the first signal VGL may be a low level signal, and then the first and gate 121 cannot output a high level signal, that is, cannot output a valid scan signal. Thus, the control module 20 controls the output module 12 not to output the valid scan signal during the first operation period T1.

In the second working period T2, the control module 20 transmits the second signal VGH on the second signal line CL2 to the output terminal 20B of the control module 20, that is, the third input terminal of the first and gate 121 receives the second signal VGH, the second signal VGH may be a high level signal, the signal output by the output terminal of the first and gate 121 is controlled by the signal output by the output terminal of the shift register 11 and the signal on the clock signal line CK, the first and gate 121 may output a high level signal, that is, may output an effective scan signal, so that in the second working period T2, the control module 20 controls the output module 12 to output an effective scan signal, and the output module 12 recovers to a normal working state.

In an embodiment of the present application, as shown in fig. 3, the first and gate 121 includes a first nand gate 1211 and a first inverter unit 1212, a first input end of the first nand gate 1211 is electrically connected to the output end of the shift register 11, a second input end of the first nand gate 1211 is electrically connected to the clock signal line CK, a third input end of the first nand gate is electrically connected to the output end 20B of the control module 20, an output end of the first nand gate 1211 is electrically connected to the input end of the first inverter unit 1212, and an output end of the first inverter unit 1212 is electrically connected to the output end of the output module 12. The first inverter unit 1212 may include an odd number of inverters Q connected in series with each other.

It should be noted that fig. 3 only illustrates a case where the first inverter unit 1212 includes three inverters Q connected in series.

As can be seen from the characteristics of the nand gate and the inverter, when the first input terminal, the second input terminal, and the third input terminal of the first nand gate 1211 receive the high level signal, the output terminal of the first nand gate 1211 outputs the low level signal, and the low level signal can be converted into the high level signal through the first inverter unit 1212, that is, the output module 12 outputs the high level signal.

When any one of the first input terminal, the second input terminal and the third input terminal of the first nand gate 1211 receives a low level signal, the output terminal of the first nand gate 1211 outputs a high level signal, and the high level signal can be converted into a low level signal through the first inverter unit 1212, and is output, that is, the output module 12 outputs a low level signal.

In this technical solution, the effective scan signal output by the output module 12 may be a high level signal. In combination with the operation process of the control module 20, in the first operation period T1, the control module 20 transmits the first signal VGL on the first signal line CL1 to the output terminal 20B of the control module 20, that is, the third input terminal of the first nand gate 1211 receives the first signal VGL, and the first signal VGL may be a low level signal, so that the output terminal of the first nand gate 1211 outputs a high level signal, and the high level signal is converted into a low level signal by the first inverter unit 1212 for output, that is, the output module 12 outputs a low level signal in the first operation period T1, thereby ensuring that the control module 20 controls the output module 12 to be unable to output an effective scan signal in the first operation period T1.

In the second operation period T2, the control module 20 transmits the second signal VGH on the second signal line CL2 to the output end 20B of the control module 20, that is, the third input end of the first nand gate 1211 receives the second signal VGH, the second signal VGH may be a high level signal, the signal output by the output end of the first nand gate 1211 is controlled by the signal output by the output end of the shift register 11 and the signal on the clock signal line CK, the first nand gate 1211 may output a low level signal, the low level signal is converted into a high level signal by the first inverter unit 1212 and output, that is, the output module 12 may output an effective scan signal, so that in the second operation period T2, the control module 20 controls the output module 12 to output the effective scan signal, and the output module 12 recovers to a normal operation state.

Fig. 6 is a schematic circuit connection diagram of another scan unit and a control module according to an embodiment of the present disclosure.

In another technical solution of the embodiment of the present application, as shown in fig. 6, the first and gate 121 includes a first and gate sub-121A and a second and gate sub-121B, a first input terminal of the first and gate sub-121A is electrically connected to an output terminal of the shift register 11, a second input terminal of the first and gate sub-121A is electrically connected to the clock signal line, and an output terminal of the first and gate sub-121A is electrically connected to a first input terminal of the second and gate sub-121B; a second input end of the second sub and gate 121B is electrically connected to the output end 20B of the control module 20, and an output end is electrically connected to the output end of the output module 12.

Specifically, with reference to fig. 6, the first sub-and-gate 121A includes a first nand-gate 1211 and a first inverter unit 1212, a first input end of the first nand-gate 1211 is electrically connected to the output end of the shift register 11, a second input end of the first nand-gate is electrically connected to the clock signal line, an output end of the first nand-gate is electrically connected to the input end of the first inverter unit 1212, and an output end of the first inverter unit 1212 is electrically connected to the first input end of the second sub-and-gate 121B.

The second sub-and gate 121B includes a second nand gate 1213 and a second inverter unit 1214, wherein a first input of the second nand gate 1213 is electrically connected to the output of the first inverter unit 1212, a second input of the second nand gate is electrically connected to the output 20B of the control module 20, an output of the second nand gate is electrically connected to the input of the second inverter unit 1214, and an output of the second inverter unit 1214 is electrically connected to the output OUT of the output module 12.

Each of the first inverter unit 1212 and the second inverter unit 1214 may include an odd number of inverters Q connected in series. Fig. 6 only illustrates a case where each of the first inverter unit 1212 and the second inverter unit 1214 includes one inverter Q.

As can be seen from the analysis of the and gates, the signal output by the output terminal of the first sub and gate 121A is controlled by the signal output by the output terminal of the shift register 11 and the signal on the clock signal line CK, and the signal output by the output terminal of the second sub and gate 121B is controlled by the signal output by the output terminal of the first sub and gate 121A and the signal output by the output terminal 20B of the control module 20.

During the first operation period T1, the control module 20 transmits the first signal VGL on the first signal line CL1 to the output terminal 20B of the control module 20, that is, the second input terminal of the second sub-and gate 121B receives the first signal VGL, which may be a low level signal, and then the output terminal of the second sub-and gate 121B cannot output a high level signal, that is, the output module 12 cannot output a valid scan signal.

In the second operation period T2, the control module 20 transmits the second signal VGH on the second signal line CL2 to the output terminal 20B of the control module 20, that is, the second input terminal of the second sub-and gate 121B receives the second signal VGH, the second signal VGH may be a high level signal, the signal output by the output terminal of the second sub-and gate 121B is controlled by the signal output by the output terminal of the first sub-and gate 121A, that is, the signal output by the output terminal of the shift register 11 and the signal on the clock signal line CK, the output terminal of the second sub-and gate 121B may output a high level signal, that is, the output module 12 may output an effective scan signal, and the output module 12 recovers to the normal operation state in the second operation period T2.

In this embodiment, the first sub-and-gate 121A and the second sub-and-gate 121B may both be composed of nand-gate series inverters including two input ends, and the nand-gate including two input ends is more difficult to design than the nand-gate including three input ends, which is beneficial to reducing the difficulty in designing the first sub-and-gate 121A and the second sub-and-gate 121B, thereby reducing the difficulty in designing the output module 12.

It should be noted that, the above technical solution is only to illustrate the structure of the output module 12 and the connection manner between the output module 12 and the control module 20, in some other embodiments, the output module 12 may also be of other structures, only the signal transmitted by the control module 20 can control the output module 12 not to output the effective scan signal in the first working period T1, and the output module 12 can recover the normal working state in the second working period T2, which is not specifically limited in this application.

Fig. 7 is a schematic circuit diagram illustrating a connection between another scan cell and a control module according to an embodiment of the present disclosure, and fig. 8 is a timing diagram of the circuit shown in fig. 7.

In order to clarify the technical solution of the embodiment of the present application, the following describes the operation process of the driving circuit shown in fig. 7 in the normal operation state with reference to fig. 7 and 8.

As shown in fig. 7, the shift register 11 includes an input block 111 and a latch block 112, the input block 111 is electrically connected to the latch block 112 through a first node N1, an output end of the latch block 112 is electrically connected to the output block 12 through a second node N2, and an output end of the latch block 112 is electrically connected to an output end of the shift register 11.

The input module 111 includes a first clock inverter P1 and a first inverter Q1, an input end of the first clock inverter P1 is electrically connected to the trigger end IN, and an output end is electrically connected to the latch module 112 through a first node N1; the input end of the first inverter Q1 and the second control end CN1 of the first clock inverter P1 are both electrically connected to the first clock signal line CK1, and the output end of the first inverter Q1 is electrically connected to the first control end CP1 of the first clock inverter P1.

The latch module 112 includes a second clock inverter P2 and a second inverter Q2, an output end of the second clock inverter P2 and an input end of the second inverter Q2 are both connected to the first node N1, an output end of the second inverter Q2 and an input end of the second clock inverter P2 are both connected to the second node N2, a first control end CP2 of the second clock inverter P2 is electrically connected to the first clock signal line CK1, and a second control end CN2 of the second clock inverter P2 is electrically connected to an output end of the first inverter M1.

The output module 12 includes a first nand gate 1211 and a first inverter unit 1212, a first input end of the first nand gate 1211 is electrically connected to the output end of the latch module 112, a second input end of the first nand gate 1211 is electrically connected to the second clock signal line CK2, a third input end of the first nand gate is electrically connected to the output end 20B of the control module 20, an output end of the first nand gate 1211 is electrically connected to an input end of the first inverter unit 1212, an output end of the first inverter unit 1212 is electrically connected to the output end OUT of the output module 12, and the first inverter unit 1212 may include an odd number of inverters Q, such as 3 inverters Q3, Q4, and Q5 connected in series to each other in fig. 7.

The clock signal line CK in the above embodiment includes the first clock signal line CK1 and the second clock signal line CK2, and when the shift register 11 is connected to the first clock signal line CK1, the output block 12 electrically connected to the shift register 11 is electrically connected to the second clock signal line CK2, and when the shift register 11 is connected to the second clock signal line CK2, the output block 12 electrically connected to the shift register 11 is electrically connected to the first clock signal line CK 1. In the embodiment of the present application, the shift register 11 is connected to the first clock signal line CK1, and the output module 12 electrically connected to the shift register 11 is electrically connected to the second clock signal line CK 2.

As shown in fig. 8, the operation process of the shift register 11 and the output module 12 in the normal operation state includes five stages t1, t2, t3, t4, and t 5.

IN the period t1, the trigger terminal IN and the first clock signal line CK1 provide a high level signal, and the second clock signal line CK2 provides a low level signal. The start signal of the trigger terminal IN at a high level is input to the input terminal of the first clock inverter P1 of the input module 111; a high level signal on a first clock signal line CK1 is converted into a low level signal after passing through a first inverter Q1, and then the low level signal transmitted to a first control end CP1 of the first clock inverter P1 and a high level signal transmitted to a second control end CN1 of the first clock inverter P1 control the first clock inverter P1 to be turned on, the first clock inverter P1 converts a high level turn-on signal into a low level signal and outputs the low level signal to a first node N1, so that a signal of the first node N1 is a low level signal; then, the low level signal of the first node N1 passes through the second inverter Q2 and is converted into a high level start signal, which is output to the second node N2, so that the signal of the second node N2 is a high level signal, which is opposite to the level of the signal of the first node N1; at this time, the second clock inverter P2 is in an off state; the high level signal of the second node N2 and the low level signal on the second clock signal line CK2 control the first nand gate 1211 to output a high level signal, which is converted into a low level signal through the first inverter unit 1212 and output by the output terminal OUT of the output module 12.

At the stage t2, the trigger terminal IN provides a high level signal, and the first clock signal line CK1 and the second clock signal line CK2 provide a low level signal. The low level signal on the first clock signal line CK1 is converted into a high level signal after passing through the first inverter Q1, the high level signal is transmitted to the first control end CP1 of the first clock inverter P1, and the second control end CN1 of the first clock inverter P1 receives the low level signal of the first clock signal line CK1, so that the first clock inverter P1 is turned off; the low level signal transmitted to the first control terminal CP2 of the second clocked inverter P2 and the high level signal transmitted to the second control terminal CN2 of the second clocked inverter P2 control the second clocked inverter P2 to be turned on, the second clocked inverter P2 converts the high level turn-on signal of the second node N2 into a low level signal and outputs the low level signal to the first node N1, and the signal of the first node N1 is maintained as a low level signal and is opposite to the level of the signal of the second node N2; the high level signal of the second node N2 and the low level signal on the second clock signal line CK2 control the first nand gate 1211 to output a high level signal, which is converted into a low level signal through the first inverter unit 1212 and output from the output terminal OUT of the output module 12.

IN the period t3, the trigger terminal IN and the second clock signal line CK2 provide a high level signal, and the first clock signal line CK1 provides a low level signal. Since the signal levels at the trigger terminal IN and the first clock signal line CK1 are unchanged, the levels of the signals at the first node N1 and the second node N2 are opposite; the high level signal of the second node N2 and the high level signal on the second clock signal line CK2 control the first nand gate 1211 to output a low level signal, which is converted into a high level signal through the first inverter unit 1212 and output by the output terminal OUT of the output module 12, that is, the output module 12 outputs an effective scan signal.

At the stage t4, the trigger terminal IN provides a high level signal, the first clock signal line CK1 and the second clock signal line CK2 provide a low level signal, and the conduction conditions of the shift register 11 and the output module 12 are the same as those at the stage t2, which is not described herein again.

IN the period t5, the trigger terminal IN and the second clock signal line CK2 provide a low level signal, and the first clock signal line CK1 provides a high level signal. A low level signal of the trigger terminal IN is input to an input terminal of the first clock inverter P1 of the input module 111; a high level signal on a first clock signal line CK1 is converted into a low level signal after passing through a first inverter Q1, and then the low level signal transmitted to a first control end CP1 of the first clock inverter P1 and a high level signal transmitted to a second control end CN1 of the first clock inverter P1 control the first clock inverter P1 to be turned on, the first clock inverter P1 converts the low level signal into a high level signal and outputs the high level signal to a first node N1, so that a signal of the first node N1 is a high level signal; then, the high level signal of the first node N1 passes through the second inverter Q2 and is converted into a low level signal, and the low level signal is output to the second node N2, so that the signal of the second node N2 is a low level signal and is opposite to the level of the signal of the first node N1; at this time, the second clock inverter P2 is in an off state; the low level signal of the second node N2 and the low level signal on the second clock signal line CK2 control the first nand gate 1211 to output a high level signal, which is converted into a low level signal through the first inverter unit 1212 and output by the output terminal OUT of the output module 12.

In a normal operation state of the shift register 11 and the output module 12, i.e. in a second operation period T2 of the driving circuit 100, the control module 20 transmits the second signal VGH on the second signal line CL2 to the output module 12, where the second signal VGH is a high level signal, the third input terminal of the first nand gate 1211 receives the high level signal, and as can be seen from the characteristics of the nand gate, the signal output by the first nand gate 1211 is controlled by the signals received by the first input terminal and the second input terminal thereof, and the shift register 11 and the output module 12 normally execute five stages T1, T2, T3, T4 and T5.

When the display panel 01 detects an external interference signal, that is, in a first working period T1 of the driving circuit 100, the control module 20 transmits a first signal VGL on the first signal line CL1 to the output module 12, where the first signal VGL is a low level signal, the third input end of the first nand gate 1211 receives the low level signal, and as can be seen from the characteristics of the nand gate, the first nand gate 1211 outputs a high level signal under the control of the low level signal, the high level signal is converted into a low level signal through the first inverter unit 1212, and is output from the output end OUT of the output module 12, and the output module 12 cannot output a high level effective scanning signal.

Fig. 9 is a timing diagram of a driving circuit according to an embodiment of the present disclosure.

Referring to fig. 9, in a frame of a picture of the display panel 01, each stage of the output modules 12 in the driving circuit 100 sequentially outputs an effective scanning signal, when the display panel 01 detects an external interference signal (for example, when the output module 12 in the n-2 th row in fig. 9 detects an interference signal when transmitting a scanning signal), that is, in a first working period T1 of the driving circuit 100, the control signal line EN transmits a low-level effective signal to control the first transistor M1 to be turned on and the second transistor M2 to be turned off, the first signal VGL on the first signal line CL1 is transmitted to the output module 12, and each stage of the output modules 12 in the driving circuit 100 cannot output an effective scanning signal.

After the external interference signal disappears, that is, in the second operating period T2 of the driving circuit 100, the control signal line EN transmits the high-level effective signal to control the first transistor M1 to be turned off and the second transistor M2 to be turned on, the second signal VGH on the second signal line CL2 is transmitted to the output module 12, and the output module 12 recovers to the normal operating state.

The embodiment of the present application further provides a display panel 01, and as shown in fig. 2, the display panel 01 includes the driving circuit 100 provided in the foregoing embodiment. Illustratively, the display panel 01 may be a liquid crystal display panel, an organic light emitting diode display panel, a sub-millimeter light emitting diode display panel (mini-LED), a micro light emitting diode display panel (micro-LED), which is not limited in this embodiment.

In the display panel 01, in the first working period T1 of the driving circuit 100, the control module 20 controls the output module 12 electrically connected thereto not to output the valid scan signal, so that the display panel 01 can stop refreshing data without affecting the transmission of the cascade signal at the output end of the shift register 11, thereby preventing the display panel 01 from displaying an error picture. In the second working period of the driving circuit 100, the control module 20 controls the output module 12 electrically connected to the control module to output an effective scanning signal, that is, the output module 12 can recover to the normal working state, because the cascade signal output by the output end of the shift register 11 is not affected, when the output module 12 recovers to the normal working state, the driving circuit 100 can immediately recover to the normal working state, which avoids the situation that a plurality of scanning units 10 output effective scanning signals simultaneously when the display panel 01 displays a picture again, thereby avoiding the problem of ghosting of the display picture, and effectively improving the display quality of the display panel 01.

In addition, after the external interference signal disappears, the driving circuit 100 can immediately return to the normal operating state, that is, the scanning units 10 in the driving circuit 100 immediately output the effective scanning signals in sequence according to the level transmission sequence, and do not need to wait until the display panel 01 displays the picture again before outputting the effective scanning signals in sequence, which is beneficial to further improving the display quality of the display panel 01.

The embodiment of the present application provides a display device 02, as shown in fig. 10, including the display panel 01 provided in the previous embodiment. For example, the display device 02 may be an electronic device such as a mobile phone, a computer, a television, a smart wearable device (e.g., a smart watch), and an on-vehicle display device, which is not limited in this embodiment of the present application.

In the display device 02, in the first working period T1 of the driving circuit 100, the control module 20 controls the output module 12 electrically connected thereto not to output the valid scan signal, so that the display panel 01 can stop refreshing data without affecting the transmission of the cascade signal at the output end of the shift register 11, thereby preventing the display panel 01 from displaying an error picture. In the second working period of the driving circuit 100, the control module 20 controls the output module 12 electrically connected to the control module to output an effective scanning signal, that is, the output module 12 can recover to the normal working state, because the cascade signal output by the output end of the shift register 11 is not affected, when the output module 12 recovers to the normal working state, the driving circuit 100 can immediately recover to the normal working state, which avoids the situation that a plurality of scanning units 10 output effective scanning signals simultaneously when the display device 02 redisplays a picture, thereby avoiding the problem of ghosting of the displayed picture, and effectively improving the display quality of the display device 02.

The above description is only exemplary of the present application and should not be taken as limiting the present application, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the scope of protection of the present application.

Claims

1. A driving circuit disposed in a display panel, the driving circuit comprising:

the scanning units comprise a shift register and an output module, the output end of the shift register is electrically connected with the output module, and the output module is used for outputting scanning signals;

and the control module is electrically connected with at least part of the output modules and is used for controlling the output modules to be incapable of outputting effective scanning signals in the first working period of the driving circuit and capable of outputting effective scanning signals in the second working period of the driving circuit.

2. The driving circuit of claim 1, wherein the control module comprises a first input and a second input; the first input end is electrically connected with a first signal line, the second input end is electrically connected with a second signal line, and the output end of the control module is electrically connected with the output module;

during the first working period, the control module transmits a first signal on the first signal line to the output module;

in the second working period, the control module transmits a second signal on the second signal wire to the output module.

3. The driving circuit of claim 2, wherein the control module comprises a first transistor and a second transistor, wherein a first pole of the first transistor is electrically connected to the first signal line and a second pole of the first transistor is electrically connected to the output terminal of the control module, and wherein a first pole of the second transistor is electrically connected to the second signal line and a second pole of the second transistor is electrically connected to the output terminal of the control module.

4. The driving circuit according to claim 3, wherein in the same control module, the gate of the first transistor and the gate of the second transistor are electrically connected to the same control signal line, and the channel type of the first transistor is different from the channel type of the second transistor.

5. The driving circuit according to claim 4, wherein at least some of the different control modules are electrically connected to the same control signal line.

6. The driving circuit according to claim 2, wherein the output module comprises a first and gate, a first input terminal of the first and gate is electrically connected to the output terminal of the shift register, a second input terminal of the first and gate is electrically connected to the clock signal line, a third input terminal of the first and gate is electrically connected to the output terminal of the control module, and an output terminal of the first and gate is electrically connected to the output terminal of the output module.

7. The driving circuit of claim 6, wherein the first AND gate comprises a first NAND gate and a first inverter unit, a first input terminal of the first NAND gate is electrically connected to the output terminal of the shift register, a second input terminal of the first NAND gate is electrically connected to the clock signal line, a third input terminal of the first NAND gate is electrically connected to the output terminal of the control module, an output terminal of the first inverter unit is electrically connected to the input terminal of the first inverter unit, and an output terminal of the first inverter unit is electrically connected to the output terminal of the output module.

8. The driving circuit according to claim 6, wherein the first AND gate comprises a first sub AND gate and a second sub AND gate, a first input terminal of the first sub AND gate is electrically connected to the output terminal of the shift register, a second input terminal of the first sub AND gate is electrically connected to the clock signal line, and an output terminal of the first AND gate is electrically connected to a first input terminal of the second sub AND gate; and the second input end of the second sub AND gate is electrically connected with the output end of the control module, and the output end of the second sub AND gate is electrically connected with the output end of the output module.

9. The driving circuit according to claim 8, wherein the first sub-and-gate comprises a first nand gate and a first inverter unit, a first input terminal of the first nand gate is electrically connected to the output terminal of the shift register, a second input terminal of the first nand gate is electrically connected to the clock signal line, an output terminal of the first nand gate is electrically connected to the input terminal of the first inverter unit, and an output terminal of the first inverter unit is electrically connected to the first input terminal of the second sub-and-gate;

the second sub-AND gate comprises a second NAND gate and a second inverter unit, a first input end of the second NAND gate is electrically connected with an output end of the first inverter unit, a second input end of the second NAND gate is electrically connected with an output end of the control module, an output end of the second NAND gate is electrically connected with an input end of the second inverter unit, and an output end of the second inverter unit is electrically connected with an output end of the output module.

10. The driving circuit of claim 2, wherein the active scan signal output by the output module is a high signal, the first signal transmitted by the first signal line is a low signal, and the second signal transmitted by the second signal line is a high signal.

11. A display panel comprising the driver circuit according to any one of claims 1 to 10.

12. A display device comprising the display panel according to claim 11.