CN115576728A - Time sequence control method, device and equipment based on fault positioning - Google Patents

Time sequence control method, device and equipment based on fault positioning Download PDF

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Publication number
CN115576728A
CN115576728A CN202211259611.9A CN202211259611A CN115576728A CN 115576728 A CN115576728 A CN 115576728A CN 202211259611 A CN202211259611 A CN 202211259611A CN 115576728 A CN115576728 A CN 115576728A
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Prior art keywords
cpu
error signal
fault
power
timing control
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Chinese (zh)
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陈占良
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Suzhou Inspur Intelligent Technology Co Ltd
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Suzhou Inspur Intelligent Technology Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0766—Error or fault reporting or storing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
    • G06F11/3024—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system component is a central processing unit [CPU]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G06F11/3466—Performance evaluation by tracing or monitoring
    • G06F11/3476—Data logging

Abstract

The application relates to the technical field of servers, and particularly discloses a time sequence control method, a device, equipment and a computer readable storage medium based on fault location.

Description

Time sequence control method, device and equipment based on fault positioning
Technical Field
The present application relates to the field of server technologies, and in particular, to a method, an apparatus, a device, and a computer-readable storage medium for timing control based on fault location.
Background
In the operation process of the server, due to factors of each component or a Central Processing Unit (CPU), error information such as a Catastrophic Error (catrr) or an Internal Error (inter Error, IERR) often occurs, and both of these errors may cause a system downtime or have a potentially significant problem. When a system is down due to a catastrophic error, active recording of a Machine Check Architecture (MCA), a server error self-checking mechanism in which a CPU reports a hardware error to an operating system OS, is realized by a Baseboard Management Controller (BMC), so that fast log analysis can be performed, and the cause of the problem can be accurately located.
Fig. 1 is a schematic connection diagram of a part of devices on a main board.
As shown in fig. 1, several components on the device motherboard include a CPU 101, a BMC 102, a Complex Programmable Logic Device (CPLD) 103, a Platform Controller Hub (PCH) 104, and the like. The equipment failure information is mainly provided by the CPU 101, taking a catastrophic error CATERR as an example, the CPLD 103 monitors a CATERR signal of the CPU 101, and when the CATERR signal of the CPU 101 is triggered, the CPLD 103 forms an interrupt signal (interrupt) to inform the BMC 102; after receiving the interrupt signal (interrupt), the BMC 102 reads an MCA register inside the CPU 101 and records a log through a Platform Environment Control Interface (PECI) bus and a Joint Test Action Group (JTAG) bus, respectively, so as to facilitate subsequent log analysis and fast location of a fault cause. However, when a CATERR failure occurs during shutdown, this may cause problems in that BMC 102 cannot log or log incompletely. When the CPLD 103 triggers an interrupt signal to the BMC 102, the BMC 102 starts a log collection thread, but the CPU 101 is powered down or reset quickly due to the shutdown process of the system, thereby interrupting the log collection of the BMC 102. When a CATERR failure triggers and BMC 102 is doing log collection, it can also cause a problem of incomplete logging if the server is suddenly shut down or the AC is powered down.
Disclosure of Invention
The application aims to provide a time sequence control method, a time sequence control device, time sequence control equipment and a computer readable storage medium based on fault location, which are used for avoiding the situation that a fault log cannot be recorded due to shutdown of the equipment and improving the fault diagnosis capability of the equipment.
In order to solve the above technical problem, the present application provides a timing control method based on fault location, including:
monitoring a CPU error signal;
when the CPU error signal is monitored, triggering a power-off forbidding process;
and controlling the CPU and a power supply chip of the CPU to be in an activated state, and triggering the reading record of a fault log corresponding to the error signal of the CPU.
Optionally, the method further includes:
and shielding the shutdown command of the equipment after triggering the lower current trip forbidding.
Optionally, the shutdown command is specifically a shutdown key signal of a BMC of the device or a key signal of a power switch button of the device.
Optionally, the method further includes:
and after the current-down-flow prohibition process is triggered, popping up a prompt message for prohibiting shutdown on a display interface of the equipment.
Optionally, when the CPU error signal is monitored, the power-off prohibition process is triggered, specifically:
and after a shutdown command of the equipment is received, triggering the power-off forbidding process when the CPU error signal is monitored.
Optionally, the triggering is to read a record of a fault log corresponding to the CPU error signal, specifically:
and triggering a baseboard management controller BMC to read and record the fault log.
Optionally, the CPU is controlled to be in an activated state, specifically:
and controlling a reset pin of the CPU and a power supply pin of the CPU to be in a high level state.
Optionally, after the CPU error signal is monitored, before the triggering prohibition of the current descending process, the method further includes:
judging whether a reset pin of the CPU and a power supply pin of the CPU both correspond to the activation state of the CPU;
if yes, entering the step of triggering the power-off forbidding process;
if not, the error signal of the CPU is ignored.
Optionally, the method further includes:
and if a shutdown command is received before the power-down prohibition process is triggered or in the process of executing the power-down prohibition process, executing the shutdown command after the completion of the reading record of the fault log is confirmed.
In order to solve the above technical problem, the present application further provides a timing control device based on fault location, including:
the monitoring unit is used for monitoring the error signal of the CPU;
the triggering unit is used for triggering the power-off forbidding process when the CPU error signal is monitored;
and the execution unit is used for controlling the CPU and the power supply chip of the CPU to be in an activated state and triggering the reading record of the fault log corresponding to the error signal of the CPU.
In order to solve the above technical problem, the present application further provides a timing control apparatus based on fault location, including:
a memory for storing a computer program;
a processor for executing the computer program, wherein the computer program, when executed by the processor, implements the steps of the fault location based timing control method as described in any one of the above.
To solve the above technical problem, the present application further provides a computer-readable storage medium, on which a computer program is stored, where the computer program, when executed by a processor, implements the steps of the fault location-based timing control method according to any one of the above items.
According to the time sequence control method based on fault location, the power-off prohibition process is triggered when the CPU error signal is monitored, the reading record of the fault log corresponding to the CPU error signal is triggered when the CPU and the power supply chip of the CPU are both in an activated state, even if the CPU error signal is received in the equipment shutdown process, the complete record of the fault log corresponding to the CPU error signal can be ensured, the defect that the CPU error signal appearing in the equipment shutdown process cannot be recorded in the prior art is overcome, the integrity of collecting the fault log corresponding to the CPU error signal is improved, meanwhile, the visibility of the operation of the server is enhanced, the fault diagnosis capability of the server is greatly improved, and the fault of the server can be more comprehensively diagnosed in the subsequent log analysis.
The application also provides a time sequence control device, equipment and a computer readable storage medium based on fault location, which have the beneficial effects and are not repeated herein.
Drawings
For a clearer explanation of the embodiments or technical solutions of the prior art of the present application, the drawings needed for the description of the embodiments or prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 is a schematic diagram of the connection of a portion of devices on a motherboard;
fig. 2 is a flowchart of a timing control method based on fault location according to an embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of a timing control apparatus based on fault location according to an embodiment of the present disclosure;
fig. 4 is a schematic structural diagram of a timing control device based on fault location according to an embodiment of the present application.
Detailed Description
The core of the application is to provide a time sequence control method, a time sequence control device, equipment and a computer readable storage medium based on fault location, which are used for avoiding the situation that a fault log cannot be recorded due to shutdown of the equipment and improving the fault diagnosis capability of the equipment.
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Example one
Fig. 2 is a flowchart of a timing control method based on fault location according to an embodiment of the present disclosure. As shown in fig. 2, the method for timing control based on fault location provided in the embodiment of the present application includes:
s201: and monitoring the error signal of the CPU.
S202: and when the CPU error signal is monitored, triggering the power-off forbidding process.
S203: and controlling the CPU and the power supply chip of the CPU to be in an activated state, and triggering the reading record of the fault log corresponding to the error signal of the CPU.
In specific implementation, the timing control method based on fault location provided by the embodiment of the application can be applied to any controller on a device, and is preferably applied to a controller which is powered on before a CPU and powered off after the CPU. To implement the timing control in the embodiment of the present application, the timing control method is preferably applied to a Programmable controller, such as the architecture shown in fig. 1, and may be applied to a complex Programmable logic device CPLD, and may also be applied to other Programmable controllers existing on a device, such as a Field Programmable Gate Array (FPGA).
The fault positioning time sequence provided by the embodiment of the application is realized by adding a program script which triggers a power-off forbidding process based on a CPU error reporting signal and controls the CPU and a power chip of the CPU to be in an activated state in the power-off forbidding process. If the method is applied to the CPLD, a monitoring mechanism for reporting an error signal (such as a CATERR) of the CPU and a control mechanism for prohibiting a power-off process to be executed after the CPU is monitored to include the signal are introduced into a time sequence control module of the CPLD.
On a motherboard of a device such as a server, failure information of each component is generally recorded in a register of a CPU. When the CPU detects a predetermined fault type, it will send out a corresponding CPU Error signal, such as a Catastrophic Error (CATERR) or an Internal Error (IERR). The execution main body of the timing control method based on fault location, such as the CPLD, monitors the CPU error signal of the CPU, and when the CPU error signal is monitored, the CPLD forms an interrupt signal to trigger the reading record of the fault log corresponding to the CPU error signal.
Usually, the device for recording the fault log on the device motherboard is a baseboard management controller BMC, and then the reading record of the fault log corresponding to the CPU error signal is triggered in S203, specifically: and triggering the BMC to read and record the fault log. Specifically, the CPLD forms an interrupt signal to inform the BMC; after receiving the interrupt signal, the BMC reads an MCA register inside the CPU and records a fault log through a Platform Environment Control Interface (PECI) bus and a Joint Test Action Group (JTAG) bus, respectively.
However, if the CPU error signal is generated during shutdown, the problem that the fault log cannot be recorded or the fault log is not recorded completely may result. Or although the CPU error signal is generated before the device is shut down, if the shutdown process is entered during the process of recording the fault log, the fault log may not be completely recorded. Therefore, the time sequence control method based on fault location provided by the embodiment of the application optimizes the time sequence of recording the fault log and shutdown after the error report of the CPU is carried out, and triggers the current-down-forbidding process when the error report signal of the CPU is monitored, controls the CPU and the power chips of the CPU to be in the activated state in the power-down-forbidding process, and then triggers the reading and recording of the fault log corresponding to the error report signal of the CPU, that is, ensures that the reading and recording process of the fault log is carried out when the CPU and the power chips of the CPU are in the activated state, thereby ensuring that the fault log can be recorded completely.
Because the problem that the fault log corresponding to the error signal of the CPU cannot be completely recorded due to the CPU or the power supply chip of the CPU being suddenly powered off does not often occur in the normal operation process of the device, the time sequence control method based on fault location provided by the embodiment of the present application may be triggered based on the device power-off command. Namely S101: when the CPU error signal is monitored, the power-off forbidding process is triggered, which specifically comprises the following steps: and after a shutdown command of the equipment is received, triggering the power-off forbidding process when a CPU error signal is monitored. Specifically, when the device is in normal operation and does not receive a device shutdown command, if the CPU error signal is detected, the process is executed according to the existing flow for recording the fault log corresponding to the CPU error signal. If an equipment shutdown command is received in the process of recording the fault log, a power-off forbidding process is triggered directly according to a previously monitored CPU error signal until the recording of the fault log which is not recorded completely is completed. If the CPU error signal is monitored after the device shutdown command is received, the power-off forbidding process can be triggered at the same time, and the shutdown process is started after the reading record of the fault log corresponding to the CPU error signal is finished in the power-off forbidding process.
The method for timing control based on fault location provided in this embodiment of the present application may further include: and if a shutdown command is received before the power-down prohibition process is triggered or in the process of executing the power-down prohibition process, executing the shutdown command after the completion of the reading record of the fault log is confirmed.
In S203, controlling the CPU to be in an active state, which is usually to prohibit the CPU from being pulled down by a reset signal (RST #) and prohibit the CPU from turning off a power supply pin (CPUPWRGD), the controlling the CPU to be in an active state may specifically be: and controlling a reset pin of the CPU and a power supply pin of the CPU to be in a high level state.
According to the time sequence control method based on fault location, the power-off prohibition process is triggered when the CPU error signal is monitored, the reading record of the fault log corresponding to the CPU error signal is triggered when the CPU and the power supply chip of the CPU are both in the activated state, even if the CPU error signal is received in the equipment shutdown process, the complete record of the fault log corresponding to the CPU error signal can be ensured, the defect that the CPU error signal appearing in the equipment shutdown process cannot be recorded in the prior art is overcome, the integrity of collecting the fault log corresponding to the CPU error signal is improved, meanwhile, the visibility of the operation of the server is enhanced, the fault diagnosis capability of the server is greatly improved, and the fault of the server can be more comprehensively diagnosed in the subsequent log analysis.
Example two
Based on the timing control method introduced in the above embodiment of the present application, although the problem of triggering the recording of the fault log corresponding to the CPU error signal in the shutdown process can be solved, if the log is being collected by the BMC, the collection of the fault log is also interrupted if an artificial forced shutdown or unplugged ac power supply operation occurs.
On the basis of the foregoing embodiment, the method for timing control based on fault location provided in the embodiment of the present application further includes: and after the lower current trip is triggered and forbidden, shielding the shutdown command of the equipment.
In the specific implementation, in the power down prohibition process, the CPU and the power chip of the CPU are not only controlled to be in an activated state, but also the shutdown command of the device where the CPU is located is shielded. The shutdown command may specifically be a shutdown key (PWRBTN) signal of a BMC of the device or a key signal of a power switch button of the device, so as to prevent the device from being remotely shutdown or manually shutdown by a user, thereby implementing a multi-level guarantee.
Meanwhile, in order to avoid forced shutdown of the user, the user can be prompted to avoid shutdown in the power-off prohibition process in a prompting signal mode. On the basis of the foregoing embodiment, the method for timing control based on fault location provided in this embodiment may further include: and after the current-down-flow prohibition process is triggered, popping up a prompt message for prohibiting shutdown on a display interface of the equipment.
Or the prompting can be performed by controlling a power indicator lamp. After entering the power-off prohibition flow, the power indicator is controlled to enter a preset display state (for example, flashing at a frequency of 1 Hz) for informing the user that the collection of the fault log is currently performed, and the shutdown operation or the AC unplugging operation is not performed at will.
After the collection of the fault log is completed, the power-off prohibition process can be stopped, that is, the display of the prompt message for prohibiting the shutdown on the user interface can be stopped, and the preset display state of the power indicator lamp can be cancelled.
EXAMPLE III
On the basis of the foregoing embodiment, after the CPU error signal is monitored in S101 and before the current trip is triggered to be prohibited, the timing control method based on fault location provided in the embodiment of the present application may further include:
judging whether a reset pin of the CPU and a power supply pin of the CPU both correspond to the activation state of the CPU;
if yes, entering a step of triggering a power-off forbidding process;
if not, the error signal of the CPU is ignored.
If the CPU is not in the active state when the CPU error signal is detected, the reset pin of the CPU and/or the power supply pin of the CPU can be detected to be in the low level. At this time, the CPU is in an unstable working state, and a fault log corresponding to the error signal of the CPU at this time does not need to be recorded. Therefore, the state judgment of the reset pin of the CPU and the power supply pin of the CPU can be added before the power-off prohibition process is carried out, whether the states of the two pins correspond to the activated state of the CPU is judged, if so, the power-off prohibition process is executed, and if not, the error signal of the CPU is ignored.
According to the time sequence control method based on fault location, before the current-down-forbidden process is executed and the fault log is recorded, whether the CPU is in an activated state or not is judged, the fault log is prevented from being recorded when the CPU is in an unstable state, and useless fault log recording and extra fault analysis work are reduced.
On the basis of the above detailed description of various embodiments corresponding to the fault location-based timing control method, the application also discloses a fault location-based timing control device, equipment and a computer-readable storage medium corresponding to the above method.
Example four
Fig. 3 is a schematic structural diagram of a timing control apparatus based on fault location according to an embodiment of the present application.
As shown in fig. 3, the timing control apparatus based on fault location provided in the embodiment of the present application includes:
a monitoring unit 301, configured to monitor a CPU error signal;
the trigger unit 302 is used for triggering the power-off forbidding process when the CPU error signal is monitored;
and the execution unit 303 is configured to control the CPU and the power chip of the CPU to be in an activated state, and trigger reading of a fault log corresponding to the CPU error signal.
Further, the timing control device based on fault location provided by the embodiment of the present application further includes:
and the shielding unit is used for shielding the shutdown command of the equipment in the power-off forbidding process.
Specifically, the shutdown command may be a shutdown key signal of the BMC of the device or a key signal of a power switch button of the device.
Further, the timing control device based on fault location provided in the embodiment of the present application further includes:
and the prompting unit is used for popping up prompting information for prohibiting shutdown on a display interface of the equipment in the power-off prohibition process.
Further, when monitoring the CPU error signal, the triggering unit 302 triggers a power-off prohibition process, which specifically includes:
and after a shutdown command of the equipment is received, triggering the power-off forbidding process when a CPU error signal is monitored.
Further, the executing unit 303 triggers a reading record of a fault log corresponding to the CPU error signal, specifically:
and triggering the BMC to read and record the fault log.
Further, the execution unit 303 controls the CPU to be in an activated state, specifically:
and controlling a reset pin of the CPU and a power supply pin of the CPU to be in a high level state.
Further, the timing control device based on fault location provided by the embodiment of the present application further includes:
the judging unit is used for judging whether a reset pin of the CPU and a power supply pin of the CPU correspond to the activated state of the CPU or not after the CPU error signal is monitored and before the lower current process is triggered and forbidden; if yes, the step of triggering the power-off prohibition process by the trigger unit 302 is entered; if not, the error signal of the CPU is ignored.
Further, the timing control device based on fault location provided by the embodiment of the present application further includes:
and the shutdown unit is used for executing the shutdown command after the completion of the reading record of the fault log is confirmed if the shutdown command is received before the current-down process is forbidden or in the current-down process is forbidden.
Since the embodiments of the apparatus portion and the method portion correspond to each other, please refer to the description of the embodiments of the method portion for the embodiments of the apparatus portion, which is not repeated here.
According to the time sequence control device based on fault location, the power-off forbidding process is triggered when the CPU error signal is monitored, in the power-off forbidding process, the reading record of the fault log corresponding to the CPU error signal is triggered when the CPU and the power supply chip of the CPU are both in an activated state, even if the CPU error signal is received in the equipment power-off process, the complete record of the fault log corresponding to the CPU error signal can be ensured, the defect that the CPU error signal occurring in the equipment power-off process cannot be recorded in the prior art is overcome, the integrity of collecting the fault log corresponding to the CPU error signal is improved, the visibility of the operation and the operation of the server is enhanced, the fault diagnosis capability of the server is greatly improved, and the fault of the server can be more comprehensively diagnosed in the subsequent log analysis.
EXAMPLE five
Fig. 4 is a schematic structural diagram of a timing control device based on fault location according to an embodiment of the present application.
As shown in fig. 4, the timing control device based on fault location provided in the embodiment of the present application includes:
a memory 410 for storing a computer program 411;
a processor 420 for executing a computer program 411, the computer program 411, when executed by the processor 420, implementing the steps of the fault localization based timing control method according to any of the embodiments described above.
Among other things, processor 420 may include one or more processing cores, such as a 3-core processor, an 8-core processor, and so forth. The processor 420 may be implemented in at least one hardware form of a Digital Signal Processing (DSP), a Field-Programmable Gate Array (FPGA), and a Programmable Logic Array (PLA). Processor 420 may also include a main processor and a coprocessor, the main processor being a processor for Processing data in the wake state, also called a Central Processing Unit (CPU); a coprocessor is a low power processor for processing data in a standby state. In some embodiments, the processor 420 may be integrated with a Graphics Processing Unit (GPU), which is responsible for rendering and drawing the content that the display screen needs to display. In some embodiments, processor 420 may also include an Artificial Intelligence (AI) processor for processing computational operations related to machine learning.
Memory 410 may include one or more computer-readable storage media, which may be non-transitory. Memory 410 may also include high speed random access memory, as well as non-volatile memory, such as one or more magnetic disk storage devices, flash memory storage devices. In this embodiment, the memory 410 is at least used for storing the following computer program 411, wherein after the computer program 411 is loaded and executed by the processor 420, the relevant steps in the timing control method based on fault location disclosed in any of the foregoing embodiments can be implemented. In addition, the resources stored by the memory 410 may also include an operating system 412, data 413, and the like, and the storage may be transient storage or permanent storage. Operating system 412 may be Windows, among others. The data 413 may include, but is not limited to, data involved in the above-described methods.
In some embodiments, the fault location based timing control apparatus may further include a display 430, a power supply 440, a communication interface 450, an input output interface 460, a sensor 470, and a communication bus 480.
Those skilled in the art will appreciate that the configuration shown in FIG. 4 does not constitute a limitation of a fault location based timing control device and may include more or fewer components than those shown.
The time sequence control device based on fault location comprises a memory and a processor, wherein the processor can realize the time sequence control method based on fault location when executing a program stored in the memory, a power-off forbidding process is triggered when a CPU error signal is monitored, and in the power-off forbidding process, when a power chip controlling a CPU and a CPU are both in an activated state, reading and recording of a fault log corresponding to the CPU error signal is triggered.
EXAMPLE six
It should be noted that the above-described embodiments of the apparatus and device are merely illustrative, for example, the division of modules is only one division of logical functions, and there may be other divisions when actually implementing, for example, a plurality of modules or components may be combined or integrated into another system, or some features may be omitted or not executed. In addition, the shown or discussed coupling or direct coupling or communication connection between each other may be through some interfaces, indirect coupling or communication connection between devices or modules, and may be in an electrical, mechanical or other form. Modules described as separate parts may or may not be physically separate, and parts displayed as modules may or may not be physical modules, may be located in one place, or may be distributed on a plurality of network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, functional modules in the embodiments of the present application may be integrated into one processing module, or each of the modules may exist alone physically, or two or more modules are integrated into one module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode.
The integrated module, if implemented in the form of a software functional module and sold or used as a separate product, may be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application, which are essential or part of the prior art, or all or part of the technical solutions may be embodied in the form of a software product, which is stored in a storage medium and executes all or part of the steps of the methods described in the embodiments of the present application.
To this end, an embodiment of the present application further provides a computer-readable storage medium, where a computer program is stored, and when the computer program is executed by a processor, the computer program implements the steps of the timing control method based on fault location.
The computer-readable storage medium may include: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-Only Memory ROM (Read-Only Memory), a Random Access Memory RAM (Random Access Memory), a magnetic disk, or an optical disk.
The computer program included in the computer-readable storage medium provided in this embodiment can implement the steps of the above-described timing control method based on fault location when being executed by a processor, and trigger a power-off prohibition procedure when a CPU error signal is monitored, and trigger reading and recording of a fault log corresponding to the CPU error signal in the power-off prohibition procedure when both the CPU and a power chip of the CPU are in an activated state.
The method, the apparatus, the device and the computer readable storage medium for timing control based on fault location provided by the present application are described in detail above. The embodiments are described in a progressive manner in the specification, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The device, the apparatus and the computer-readable storage medium disclosed in the embodiments correspond to the method disclosed in the embodiments, so that the description is simple, and the relevant points can be referred to the description of the method. It should be noted that, for those skilled in the art, it is possible to make several improvements and modifications to the present application without departing from the principle of the present application, and such improvements and modifications also fall within the scope of the claims of the present application.
It is further noted that, in the present specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising a … …" does not exclude the presence of another identical element in a process, method, article, or apparatus that comprises the element.

Claims (12)

1. A time sequence control method based on fault location is characterized by comprising the following steps:
monitoring a CPU error signal;
when the CPU error signal is monitored, triggering a power-off forbidding process;
and controlling the CPU and a power supply chip of the CPU to be in an activated state, and triggering the reading record of a fault log corresponding to the error signal of the CPU.
2. The method for timing control based on fault location according to claim 1, further comprising:
and shielding the shutdown command of the equipment after triggering the lower current trip forbidding.
3. The method of claim 2, wherein the shutdown command is a shutdown key signal of a BMC of the device or a key signal of a power switch button of the device.
4. The method for timing control based on fault location according to claim 1, further comprising:
and after the current-down-flow prohibition process is triggered, popping up a prompt message for prohibiting shutdown on a display interface of the equipment.
5. The timing control method based on fault location according to claim 1, wherein when the CPU error signal is monitored, a power-off prohibition process is triggered, specifically:
and after a shutdown command of the equipment is received, triggering the power-off forbidding process when the CPU error signal is monitored.
6. The timing control method based on fault location according to claim 1, wherein the triggering is to read a fault log corresponding to the CPU error signal, specifically:
and triggering a baseboard management controller BMC to read and record the fault log.
7. The timing control method based on fault location according to claim 1, wherein the CPU is controlled to be in an active state, specifically:
and controlling a reset pin of the CPU and a power supply pin of the CPU to be in a high level state.
8. The timing control method based on fault location according to claim 1, wherein after the CPU error signal is monitored, before the triggering forbids a current-down pass, the method further comprises:
judging whether a reset pin of the CPU and a power supply pin of the CPU both correspond to the activation state of the CPU;
if yes, entering the step of triggering the power-off forbidding process;
if not, the error signal of the CPU is ignored.
9. The method for timing control based on fault location according to claim 1, further comprising:
and if a shutdown command is received before the power-down prohibition process is triggered or in the process of executing the power-down prohibition process, executing the shutdown command after the completion of the reading record of the fault log is confirmed.
10. A timing control device based on fault location is characterized by comprising:
the monitoring unit is used for monitoring the error signal of the CPU;
the triggering unit is used for triggering the power-off forbidding process when the CPU error signal is monitored;
and the execution unit is used for controlling the CPU and the power chip of the CPU to be in an activated state and triggering the reading record of the fault log corresponding to the error report signal of the CPU.
11. A fault location based timing control apparatus, comprising:
a memory for storing a computer program;
processor for executing the computer program, which computer program, when executed by the processor, carries out the steps of the method for fault localization based timing control according to any of claims 1 to 9.
12. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the method for fault localization based timing control according to any one of claims 1 to 9.
CN202211259611.9A 2022-10-14 2022-10-14 Time sequence control method, device and equipment based on fault positioning Pending CN115576728A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202211259611.9A CN115576728A (en) 2022-10-14 2022-10-14 Time sequence control method, device and equipment based on fault positioning

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202211259611.9A CN115576728A (en) 2022-10-14 2022-10-14 Time sequence control method, device and equipment based on fault positioning

Publications (1)

Publication Number Publication Date
CN115576728A true CN115576728A (en) 2023-01-06

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Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
CN (1) CN115576728A (en)

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