CN115575786A

CN115575786A - Probe test verification method and device, electronic equipment and storage medium

Info

Publication number: CN115575786A
Application number: CN202211170022.3A
Authority: CN
Inventors: 李金哲
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2022-09-22
Filing date: 2022-09-22
Publication date: 2023-01-06

Abstract

The embodiment of the disclosure discloses a verification method and a verification device for probe test, electronic equipment and a storage medium, wherein the method comprises the following steps: acquiring a first test result of performing probe test on a plurality of semiconductor devices on a wafer by using a first test facility; grouping the plurality of semiconductor devices according to the first test result; wherein, the characteristic difference of the semiconductor devices among the groups is within the range of the preset difference; and verifying the reliability of the probe test performed by the second test facility by using the grouped semiconductor devices. By the method, the verification efficiency and accuracy can be improved.

Description

Probe test verification method and device, electronic equipment and storage medium

Technical Field

The present disclosure relates to the field of probe testing technologies, and in particular, to a method and an apparatus for verifying a probe test, an electronic device, and a storage medium.

Background

After the wafer manufacturing process is finished, probe tests (including burn-in tests and non-burn-in tests) are performed on unpackaged chips, i.e., dies (Die), on the wafer to ensure the yield of the dies before packaging. Therefore, it is important that the test facilities (e.g., test programs and test machines) for performing the probe test are reliable.

Generally, the reliability of a test facility is verified, the same batch of chips on the same wafer are collected to perform repeated tests (re-probes) on different test facilities, whether the test facility is reliable or not is verified according to whether the test results are similar or not, and the verification efficiency is low because the number of bare chips to be tested is often large. When the same batch of chips are repeatedly subjected to aging tests on different test facilities, the accuracy of verifying whether the test facilities are reliable is low because the aging tests belong to destructive tests.

Disclosure of Invention

In view of this, the embodiments of the present disclosure provide a method and an apparatus for verifying a probe test, an electronic device, and a storage medium.

In a first aspect, an embodiment of the present disclosure provides a verification method for a probe test, including:

acquiring a first test result of performing probe test on a plurality of semiconductor devices on a wafer by using a first test facility; grouping the plurality of semiconductor devices according to the first test result; wherein, the characteristic difference of the semiconductor devices among the groups after grouping is within the preset difference range; and verifying the reliability of the probe test performed by the second test facility by using the grouped semiconductor devices.

In some embodiments, the first test results include a first set of results after performing a burn-in test on each of the semiconductor devices and a second set of results after performing a test other than the burn-in test on each of the semiconductor devices;

the grouping the plurality of semiconductor devices according to the first test result includes: grouping the plurality of semiconductor devices according to the first result set and the second result set;

the verifying reliability of the test using the second test facility using the grouped semiconductor devices includes: and verifying the reliability of the burn-in test by using the second test facility by using the grouped semiconductor devices.

In some embodiments, the first set of results includes results corresponding to a first test item, and the second set of results includes results corresponding to at least two second test items; the grouping the plurality of semiconductor devices according to the first result set and the second result set includes:

determining the correlation between the first test item and each second test item according to the result corresponding to the first test item and the results corresponding to the at least two second test items;

determining a target test item according to the correlation between each second test item and the first test item; wherein the degree of relevance of the target test item to the first test item is greater than the degree of relevance of test items other than the target test item to the first test item; and grouping the plurality of semiconductor devices according to the result corresponding to the target test item.

In some embodiments, the target test item includes a plurality, the method further comprising:

determining the weight corresponding to each target test item according to the correlation between each target test item and the first test item; wherein, the weight corresponding to the target test item is positively correlated with the degree of correlation between the target test item and the first test item;

the grouping the plurality of semiconductor devices according to the result corresponding to the target test item includes: weighting the result corresponding to the target test item by using the weight corresponding to the target test item to obtain a weighted result corresponding to the target test item; and grouping the plurality of semiconductor devices according to the weighting result corresponding to each target test item of each semiconductor device.

In some embodiments, the grouping the plurality of semiconductor devices according to the weighting result corresponding to each of the target test items of each semiconductor device includes:

adding the weighting results corresponding to the target test items of the semiconductor devices to obtain a weighting sum corresponding to the semiconductor devices; and grouping the plurality of semiconductor devices according to the weighted sum corresponding to each semiconductor device.

In some embodiments, the semiconductor device corresponds to a location identifier;

the grouping the plurality of semiconductor devices according to the weighted sum corresponding to each of the semiconductor devices includes:

and sorting the weighted sum corresponding to each semiconductor device, grouping the semiconductor devices indicated by the weighted sum with odd sorting serial number and the associated position identification into one group, and grouping the semiconductor devices indicated by the weighted sum with even sorting serial number and the associated position identification into another group.

In some embodiments, the method further comprises:

according to a preset data processing rule, performing data processing on results corresponding to the target test items in the second result set to obtain results after data processing; wherein the preset data processing rule comprises at least one of the following: data filtering rules and data normalization rules;

the weighting the result corresponding to the target test item by using the weight corresponding to the target test item to obtain the weighted result corresponding to the target test item includes:

and weighting the result after the data processing corresponding to the target test item by using the weight corresponding to the target test item to obtain the weighted result corresponding to the target test item.

In some embodiments, the grouping the plurality of semiconductor devices according to the result corresponding to the target test item includes:

under the condition that the target test item meets the preset test requirement, grouping the plurality of semiconductor devices according to the result corresponding to the target test item; wherein the preset test requirement comprises a test item included by the second test facility.

In some embodiments, the first set of results includes results for at least two first test items;

the determining the target test item according to the correlation between each second test item and the first test item comprises:

for each second test item, summing the correlation coefficients between the second test item and the first test items; wherein the correlation coefficient is used for characterizing the correlation, and the correlation coefficient is positively correlated with the degree of correlation; and determining the target test item according to the added correlation coefficient corresponding to each second test item.

In some embodiments, the grouped semiconductor devices comprise two groups of semiconductor devices;

the verifying the reliability of the probe test performed by the second test facility by using the grouped semiconductor devices comprises the following steps:

acquiring a second test result after the probe test is carried out on the grouped group of semiconductor devices by using the first test facility; acquiring a third test result after the probe test is carried out on the other group of grouped semiconductor devices by using the second test facility; determining a difference between the second test result and the third test result; determining that the second test facility is reliable under the condition that the difference meets a preset difference condition; determining that the second test facility is unreliable if the difference does not satisfy the preset difference condition.

In a second aspect, an embodiment of the present disclosure provides a verification apparatus for a probe test, including:

the system comprises an acquisition module, a test module and a control module, wherein the acquisition module is used for acquiring a first test result of probe testing of a plurality of semiconductor devices on a wafer by using a first test facility; a grouping module for grouping the plurality of semiconductor devices according to the first test result; wherein, the characteristic difference of the semiconductor devices among the groups after grouping is within the preset difference range; and the verification module is used for verifying the reliability of the probe test of the second test facility by using the grouped semiconductor devices.

In some embodiments, the first test results include a first set of results after performing a burn-in test on each of the semiconductor devices and a second set of results after performing a test other than the burn-in test on each of the semiconductor devices; the grouping module is configured to group the plurality of semiconductor devices according to the first result set and the second result set; the verification module is used for verifying the reliability of the burn-in test by using the second test facility by using the grouped semiconductor devices.

In some embodiments, the first set of results includes results corresponding to a first test item, and the second set of results includes results corresponding to at least two second test items; the grouping module is used for determining the correlation between the first test item and each second test item according to the result corresponding to the first test item and the results corresponding to the at least two second test items; determining a target test item according to the correlation between each second test item and the first test item; wherein the degree of correlation between the target test item and the first test item is greater than the degree of correlation between test items other than the target test item and the first test item; and grouping the plurality of semiconductor devices according to the result corresponding to the target test item.

In some embodiments, the target test item includes a plurality, the apparatus further including:

the determining module is used for determining the weight corresponding to each target test item according to the correlation between each target test item and the first test item; wherein the weight corresponding to the target test item is positively correlated with the degree of correlation between the target test item and the first test item; the grouping module is used for weighting the result corresponding to the target test item by using the weight corresponding to the target test item to obtain the weighted result corresponding to the target test item; and grouping the plurality of semiconductor devices according to the weighting result corresponding to each target test item of each semiconductor device.

In some embodiments, the grouping module is configured to, for each semiconductor device, add the weighting results corresponding to the target test items of the semiconductor device to obtain a weighted sum corresponding to the semiconductor device; and grouping the plurality of semiconductor devices according to the weighted sum corresponding to each semiconductor device.

In some embodiments, the semiconductor device corresponds to a location identifier; the grouping module is used for sorting the weighted sum corresponding to each semiconductor device, grouping the semiconductor devices indicated by the weighted sum and the associated position identification with the odd sorting serial number into one group, and grouping the semiconductor devices indicated by the weighted sum and the associated position identification with the even sorting serial number into another group.

In some embodiments, the apparatus further comprises:

the processing module is used for carrying out data processing on the results corresponding to the target test items in the second result set according to a preset data processing rule to obtain results after data processing; wherein the preset data processing rule comprises at least one of the following: data filtering rules and data normalization rules;

and the grouping module is used for weighting the result after the data processing corresponding to the target test item by using the weight corresponding to the target test item to obtain the weighted result corresponding to the target test item.

In some embodiments, the grouping module is configured to group the plurality of semiconductor devices according to a result corresponding to the target test item when the target test item meets a preset test requirement; wherein the preset test requirement comprises a test item included by the second test facility.

In some embodiments, the first set of results includes results for at least two first test items; the grouping module is used for summing up the correlation coefficients between the second test items and the first test items aiming at each second test item; wherein the correlation coefficient is used for characterizing the correlation, and the correlation coefficient is positively correlated with the degree of correlation; and determining the target test item according to the summed correlation coefficient corresponding to each second test item.

In some embodiments, the grouped semiconductor devices comprise two groups of semiconductor devices; the verification module is used for acquiring a second test result obtained after the probe test is carried out on the grouped group of semiconductor devices by using the first test facility; obtaining a third test result after the probe test is carried out on the other group of grouped semiconductor devices by using the second test facility; determining a difference between the second test result and the third test result; determining that the second test facility is reliable under the condition that the difference meets a preset difference condition; determining that the second test facility is unreliable if the difference does not satisfy the preset difference condition.

In a third aspect, an embodiment of the present disclosure provides an electronic device, including:

a memory for storing computer executable instructions; a processor, coupled to the memory, for implementing the method of the first aspect by executing the computer-executable instructions.

In a fourth aspect, embodiments of the present disclosure provide a storage medium having stored thereon computer-executable instructions; the computer-executable instructions, when executed by a processor, are capable of implementing the method as described in the first aspect above.

The technical scheme provided by the embodiment of the disclosure can have the following beneficial effects:

in the embodiment of the disclosure, the verification device divides the semiconductor devices into a plurality of groups with similar processes according to the first test result, so that the reliability of the second test facility is verified based on the difference between the test results of testing the groups with the similar processes, and the verification efficiency can be improved on the basis of considering the verification accuracy. In addition, in the related art, when verifying the reliability of the burn-in test performed by the test facility, the burn-in test is usually performed on different test facilities by collecting the same batch of semiconductor devices on the same wafer, and whether the test facility is reliable is verified according to whether the results of the burn-in test are similar; since the burn-in test is a destructive test, each burn-in test may cause a change in the characteristics of the semiconductor device, and therefore, the accuracy of verifying whether the test implementation (including the burn-in test and the non-burn-in test) is reliable or not is low according to the results of the plurality of burn-in tests. In this regard, the semiconductor devices are divided into multiple groups with similar processes, so that the test results of the semiconductor devices among the groups are comparable, and the accuracy of verifying the reliability of the burn-in test performed by the second test facility is higher according to the burn-in test performed on the grouped semiconductor devices.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the disclosure.

Fig. 1 is a first flowchart of a verification method for probe testing according to an embodiment of the present disclosure;

FIG. 2 is a second flowchart of a verification method for probe testing according to an embodiment of the disclosure;

FIG. 3 is a block diagram of a verification apparatus for probe testing according to an embodiment of the present disclosure;

fig. 4 is a schematic physical structure diagram of an electronic device according to an embodiment of the present disclosure.

Detailed Description

Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. The following description refers to the accompanying drawings in which the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the exemplary embodiments below are not intended to represent all implementations consistent with the present disclosure. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present disclosure, as detailed in the appended claims.

The probe test is to input a test signal to the semiconductor device through the probe, collect an output signal of the semiconductor device, and test the quality of the semiconductor device according to the output signal. In the verification method for probe test provided by the embodiment of the present disclosure, the execution main body may be a verification device, such as a test machine for performing probe test on a wafer, or a terminal with information processing capability; the terminal may be a User Equipment (UE), a mobile device, a Personal Digital Assistant (PDA), a handheld device, a computing device, or the like. If the verification device is a terminal, the terminal can obtain a test result of the semiconductor device tested by the testing machine in a wired or wireless manner, or a user can import the test result into the terminal after exporting the test result from the testing machine for testing the semiconductor device, so that the terminal verifies the reliability of the testing machine or the testing program according to the test result. In some possible implementations, the verification method of the probe test may be implemented by the processor invoking computer readable instructions stored in the memory.

Fig. 1 shows a flowchart of a verification method for probe testing according to an embodiment of the present disclosure, as shown in fig. 1, the method includes:

s11, acquiring a first test result of performing probe test on a plurality of semiconductor devices on a wafer by using a first test facility;

s12, grouping the plurality of semiconductor devices according to the first test result; wherein, the characteristic difference of the semiconductor devices among the groups after grouping is within the preset difference range;

and S13, verifying the reliability of the probe test performed by the second test facility by using the grouped semiconductor devices.

In the embodiment of the disclosure, the semiconductor devices may be dies on one or more wafers, the test facilities (including the first test facility and the second test facility) include test programs, test machines, and the like, and probe tests may be performed on the plurality of semiconductor devices on the wafers. The semiconductor device includes a device for storing information, such as a Dynamic Random Access Memory (DRAM), a Static Random Access Memory (SRAM), a flash Memory, and the like; the system may further include a device for Processing information, such as a Graphics Processing Unit (GPU), a Central Processing Unit (CPU), and the like, which is not limited in this disclosure.

In the embodiment of the disclosure, a verification device obtains a first test result of performing a probe test on a plurality of semiconductor devices on a wafer by using a first test facility, and verifies reliability of an aging test by using a second test facility by using grouped semiconductor devices, wherein the second test facility is the second test program under the condition that the first test facility is the first test program, the first test program and the second test program can be installed on the same test machine, and the corresponding verification device can be a terminal of the test machine or an associated test machine; or in the case that the first test facility is a first test machine, the second test facility is a second test machine, the same test program may be installed on the first test machine and the second test machine, and correspondingly, the verification device may be a terminal associated with the first test machine and the second test machine.

In step S11, the first test result obtained by the verification apparatus may include a burn-in test result after the burn-in test is performed on each semiconductor device, and a non-burn-in test result after the test other than the burn-in test is performed on each semiconductor device. The aging test is an electrical stress test for accelerating the fault of the semiconductor device by using high temperature, high voltage, high current and the like, and is used for verifying the service life of the semiconductor device so as to screen out the semiconductor device with short service life and poor performance in advance. The tests except the aging test comprise a DC test, an AC test, a function test and the like, wherein the DC test verifies whether the electric signal of the semiconductor device meets the requirement, the AC test verifies whether the semiconductor device can complete logic within the preset time constraint, and the function test verifies whether a series of logic functions in the semiconductor device are correct.

In an embodiment of the disclosure, the aging test results may include results corresponding to one or more aging test items corresponding to different sets of aging test parameters (e.g., test conditions, excitation signals, test durations, etc.), wherein the aging test conditions include, for example, an ambient temperature of 130 ℃, a humidity of 85%; the non-burn-in test results may include results corresponding to one or more non-burn-in test items, with different non-burn-in test items corresponding to different sets of non-burn-in test parameters. Each test result (including a burn-in test result and a non-burn-in test result) includes an electrical signal fed back by each semiconductor device in the test process, such as a voltage value, a current value, and the like, and may further include an identifier indicating whether the test result passes the requirement corresponding to the test item, for example, if the fed-back voltage value falls within a preset voltage range corresponding to the test item, the requirement indicating that the semiconductor device passes the requirement corresponding to the test item may be represented by an identifier "PASS"; if the fed-back voltage value does not fall within the preset voltage range corresponding to the test item, the representation that the semiconductor device does not pass the requirement corresponding to the test item can be represented by a label "FAIL".

In step S12, the verification device groups the plurality of semiconductor devices according to the obtained first test result, and obtains a plurality of groups of semiconductor devices in which the characteristic difference of the semiconductor devices between the groups is within a preset difference range. The characteristics of the semiconductor device include quiescent current, low power consumption current, dropped input voltage, power, electrostatic sensitivity, etc. of the semiconductor device, and may be based on inherent properties of the semiconductor device itself caused by process fabrication, and may be characterized based on an electrical signal (e.g., a first test result) output by the semiconductor device. In the embodiment of the present disclosure, the preset difference range may be set manually according to experience, and if the characteristic difference of the semiconductor devices between the groups is within the preset difference range, the processes representing the semiconductor devices between the groups are similar.

In some embodiments, in a case that the first test result includes a result corresponding to the burn-in test item, the verification device may determine whether each electrical signal in the first test result satisfies a requirement corresponding to the burn-in test item, and determine whether the burn-in test of the semiconductor device is qualified according to the determination result; therefore, the semiconductor devices qualified in the burn-in test are equally distributed into M groups, and the remaining semiconductor devices which are not grouped are equally distributed into the M groups. Where M is an integer greater than 1, the semiconductor devices may be divided into two groups, or three or more groups.

It can be understood that, in the grouped groups, the semiconductor devices which are passed through the partial burn-in test and the semiconductor devices which are failed through the partial burn-in test are determined to be included based on the corresponding results of the burn-in test items, the occupation ratios of the semiconductor devices which are passed through the whole burn-in test are the same among each group, the occupation ratios of the semiconductor devices which are failed through the burn-in test are also the same, and therefore the characteristic differences of the semiconductor devices among the groups are similar.

In some embodiments, in a case that the first test result includes a result corresponding to the non-aging test item, the verification device may determine whether each electrical signal in the first test result satisfies a requirement corresponding to the non-aging test item, and determine whether the non-aging test of the semiconductor device is qualified according to the determination result; therefore, the semiconductor devices which are qualified in the non-aging test are equally distributed into M groups, and the rest semiconductor devices which are not grouped are equally distributed into the M groups.

It can be understood that, in the grouped groups, the semiconductor devices which are passed through the partial non-aging test and the semiconductor devices which are failed through the partial non-aging test are determined to be included based on the corresponding results of the non-aging test items, the proportion of the semiconductor devices which are passed through the non-aging test in the whole group is the same, the proportion of the semiconductor devices which are failed through the non-aging test is also the same, and therefore the characteristic difference of the semiconductor devices among the groups is similar.

In some embodiments, in a case where the first test result includes a result corresponding to the burn-in test item and a result corresponding to the non-burn-in test item, the verification apparatus may, in combination with the determination result of whether the burn-in test of the semiconductor device is qualified or not and whether the non-burn-in test of the semiconductor device is qualified or not, equally divide the semiconductor devices that are qualified in both the burn-in test and the non-burn-in test (that are qualified in overall quality) into M groups, and equally divide the remaining non-grouped semiconductor devices into the aforementioned M groups, which is not limited by the present disclosure.

In step S13, after the verification device groups the plurality of semiconductor devices, the reliability of the probe test performed by the second test facility may be verified by using the grouped semiconductor devices. One of the important objectives of the test results for probe testing is to monitor the production process level, i.e., the results of the probe testing can reflect the process conditions of the semiconductor device to some extent. In contrast, according to the embodiment of the disclosure, the semiconductor devices on the wafer are divided into multiple groups with similar processes according to the first test result, so that the test results of the groups are comparable, and the reliability of the second test facility is verified by using the test results of the multiple groups of semiconductor devices with similar processes, so that the verification accuracy can be improved.

In the embodiment of the present disclosure, the verification of the reliability of the probe test performed by the second test implementation is substantially the verification of the reliability of the second test facility, for example, the verification of the reliability of the maintained test program or the new test machine. The verifying the reliability of the second test facility can be verifying the reliability of the second test facility through a burn-in test or verifying the reliability of the second test facility through a non-burn-in test.

In the embodiment of the present disclosure, P groups of semiconductor devices after grouping may be tested using a first test facility, the remaining (M-P) groups of semiconductor devices may be tested using a second test facility, and the reliability of the second test facility may be verified according to the difference between the test results of the groups; wherein P is a positive integer less than M.

In some embodiments, the verifying device determines the difference between the test results of the groups, which may be a difference between a percentage of semiconductor devices whose electrical signals satisfy requirements corresponding to the test items in the results of testing the P groups of semiconductor devices by using the first testing facility (that is, a percentage of semiconductor devices whose results correspond to the test items represent that the test is qualified), and a percentage of semiconductor devices whose electrical signals satisfy requirements corresponding to the test items in the results of testing the remaining (M-P) groups of semiconductor devices by using the second testing facility.

In some embodiments, the verification apparatus may further determine a difference between a mean value of each parameter in the results of testing the P groups of semiconductor devices using the first testing facility and a mean value of each parameter in the results of testing the remaining (M-P) groups of semiconductor devices using the second testing facility, which is not limited by the present disclosure.

In other embodiments, if the semiconductor devices are divided into two groups (i.e., M is 2), the verification device may determine that the second test facility is reliable after the two groups of semiconductor devices are respectively tested, and also under the condition that the difference between the two groups of test results is smaller than the preset difference threshold; in the event that the difference is greater than or equal to a preset difference threshold, determining that the second test facility is unreliable.

In addition, if the number of groups into which the semiconductor devices are divided is greater than 2 (i.e., M is greater than or equal to 3), the verification device may further determine whether a difference between test results of the semiconductor devices after the test between any two groups is less than a preset difference threshold, count a number proportion that the difference between any two groups is less than the preset difference threshold, and determine that the second test facility is reliable when the proportion is greater than the preset proportion threshold; in the event that the occupancy is less than or equal to a preset occupancy threshold, it is determined that the second test facility is unreliable.

The embodiment of the present disclosure does not limit the manner in which the verification device verifies the reliability of the second test facility using the grouped semiconductor devices.

As described above, in the related art, the same batch of semiconductor devices on the same wafer are collected and tested on different test facilities for multiple times, and whether the test facilities are reliable or not is verified according to whether the test results are similar or not. Since the number of semiconductor devices to be tested is often large, it is inefficient to repeatedly test the entire number of semiconductor devices multiple times to verify whether the probe test performed by the second test facility is reliable.

In contrast, in the embodiment of the present disclosure, the verification device divides the semiconductor device into multiple groups with similar processes according to the first test result, so that the reliability of the second test facility is verified based on the difference between the test results obtained by testing the groups with similar processes, and the verification efficiency can be improved based on the verification accuracy.

In addition, in the related art, when verifying the reliability of the burn-in test performed by the test facility, the burn-in test is usually performed on different test facilities by collecting the same batch of semiconductor devices on the same wafer, and whether the test facility is reliable is verified according to whether the results of the burn-in test are similar; since the burn-in test is a destructive test, each burn-in test may cause a change in the characteristics of the semiconductor device, and therefore, the accuracy of verifying whether the test implementation (including the burn-in test and the non-burn-in test) is reliable or not is low according to the results of the plurality of burn-in tests. In contrast, in the embodiment of the present disclosure, the semiconductor devices are divided into multiple groups with similar processes, so that the test results of the semiconductor devices between the groups are comparable, and therefore, the accuracy of verifying the reliability of the burn-in test performed by the second test facility is higher according to the result of the burn-in test performed on the grouped semiconductor devices.

the grouping the plurality of semiconductor devices according to the first test result comprises:

grouping the plurality of semiconductor devices according to the first result set and the second result set;

the verifying reliability of the test using the second test facility using the grouped semiconductor devices includes:

and verifying the reliability of the burn-in test by using the second test facility by using the grouped semiconductor devices.

In the embodiment of the present disclosure, the first result set corresponds to the foregoing aging test results, and includes results corresponding to one or more aging test items; the second result set corresponds to the non-burn-in test results, including results corresponding to one or more non-burn-in test items.

After the verification equipment obtains the first test result, the verification equipment groups the plurality of semiconductor devices according to the first result set and the second result set in the first test result, so that the reliability of the burn-in test of the second test facility is verified according to the grouped semiconductor devices.

In some embodiments, grouping may be performed with reference to the aforementioned manner of evenly dividing the semiconductor devices that pass both the burn-in test and the non-burn-in test (overall quality pass) into M groups, and evenly dividing the remaining ungrouped semiconductor devices into the aforementioned M groups. It is to be understood that within the grouped groups, based on the burn-in test and the non-burn-in test, the semiconductor devices including a part of the semiconductor devices that are entirely qualified in quality and a part of the semiconductor devices that are not qualified (including the burn-in test failing and/or the non-burn-in test failing) are determined, and the proportion of the semiconductor devices that are entirely qualified is the same between each group and the proportion of the semiconductor devices that are not qualified is the same between each group, so that the characteristic differences of the semiconductor devices are similar between the groups.

In other embodiments, the verification device may further perform screening on the second result set according to the first result set, that is, screening on non-burn-in test results according to burn-in test results, and grouping the semiconductor devices based on the screened second result set; thereby verifying the reliability of the burn-in test performed by the second test facility based on the grouped semiconductor devices.

It can be understood that, in the embodiment of the present disclosure, the semiconductor devices are grouped according to the aging test result and the non-aging test result, and since the combination of the aging test result and the non-aging test result can more comprehensively reflect the characteristics of the semiconductor devices, compared with a method of grouping the test results based on any one of the aging test result and the non-aging test result, the scheme of the embodiment of the present disclosure can improve the accuracy of dividing the semiconductor devices into multiple groups with similar processes, and further improve the accuracy of verifying the reliability of the aging test performed by the second test facility.

In some embodiments, the first set of results includes results corresponding to a first test item, and the second set of results includes results corresponding to at least two second test items;

the grouping the plurality of semiconductor devices according to the first result set and the second result set includes:

determining a target test item according to the correlation between each second test item and the first test item; wherein the degree of relevance of the target test item to the first test item is greater than the degree of relevance of test items other than the target test item to the first test item;

and grouping the plurality of semiconductor devices according to the result corresponding to the target test item.

In the embodiment of the present disclosure, the first test item corresponds to the foregoing burn-in test item, and includes a set of burn-in test parameters; the second test item corresponds to the non-burn-in test item, and comprises a non-burn-in test parameter group.

The verification device of the embodiment of the present disclosure may filter the second result set according to the first result set, and group the semiconductor devices based on the filtered second result set. For example, the correlation between the first test item and each test item can be determined according to a result corresponding to the first test item in the first result set and a result corresponding to at least two second test items in the second result set based on a correlation function, a covariance function, and the like, wherein each test item includes the first test item and at least two second test items; and determining the target test item according to the correlations. For example, according to the correlation function, determining a correlation coefficient between the first test item and each test item, sorting the magnitude of each correlation coefficient, and selecting a preset plurality of test items corresponding to the correlation coefficient which is sorted in the front as target test items; or determining the test item corresponding to the correlation coefficient larger than the preset correlation coefficient threshold value as the target test item. The correlation coefficient is positively correlated with the correlation degree, so that the correlation degree of the selected target test item and the first test item is greater than the correlation degree of the test items except the target test item and the first test item. It is understood that the target test item includes at least a first test item.

Illustratively, the first result set includes 1 column of test results corresponding to 1 aging test item, and the second result set includes N1 columns of test results corresponding to N1 DC test items, N2 columns of test results corresponding to N2 AC test items, and N3 columns of test results corresponding to N3 functional test items; wherein each DC test item in N1, each AC test item in N2, and each functional test item in N3 belongs to the second test item. Accordingly, by using, for example, a correlation function, correlation coefficients of 1-column results corresponding to each test item and 1-column results corresponding to the first test item are respectively determined, the correlation coefficients are taken as the correlation coefficients of the test item and the first test item, and the test item corresponding to the correlation coefficient larger than a preset correlation coefficient threshold (e.g., 0.6) is determined as a target test item; or according to the sorting result of the correlation coefficients from large to small, determining the N test items which are sorted at the top as target test items, so that the target test items are the test items with higher correlation degree with the first test items.

In the embodiment of the disclosure, after the verification device determines the target test item, the verification device groups the plurality of semiconductor devices according to a result corresponding to the target test item in the first test result. For example, the verification device may determine whether each electrical signal in the result corresponding to the target test item satisfies the requirement corresponding to the test direction, determine whether the test of the semiconductor devices is qualified according to the determination result, thereby equally dividing the semiconductor devices that are qualified in the test into M groups, and equally dividing the remaining semiconductor devices that are not grouped into the M groups.

It can be understood that, according to the correlation between the first test item and each test item, the verification device in the embodiment of the disclosure selects a target test item with a higher degree of correlation with the first test item, and groups the plurality of semiconductor devices according to the result corresponding to the target test item; because the first test item corresponds to the aging test, the target test item is a test item with a higher degree of correlation with the aging test, so that the verification equipment groups a plurality of semiconductor devices based on the result of the target test item with the higher degree of correlation with the aging test, and can reduce the interference of grouping the semiconductor devices according to the result corresponding to the test item with the lower degree of correlation with the aging test, thereby improving the accuracy of grouping, and further improving the accuracy of verifying the reliability of the aging test of the second test facility based on the difference of the results of the grouped semiconductor devices after the aging test.

the grouping the plurality of semiconductor devices according to the result corresponding to the target test item comprises:

weighting the result corresponding to the target test item by using the weight corresponding to the target test item to obtain a weighted result corresponding to the target test item;

and grouping the plurality of semiconductor devices according to the weighting result corresponding to each target test item of each semiconductor device.

In the embodiment of the present disclosure, the target test items include a plurality of test items, for example, at least two test items corresponding to the top-ranked correlation coefficients are selected as the target test items; after the verification equipment determines the correlation between each target test item and the first test item, the weight corresponding to each target test item is determined according to each correlation.

Taking the correlation coefficient characterization correlation as an example, in some embodiments, the verification device may determine, according to a preset correspondence between the correlation coefficient range and the weight, a weight corresponding to the correlation coefficient range in which the correlation coefficient between the target test item and the first test item falls as a weight corresponding to the target test item.

In some embodiments, the verification device may further calculate a weight corresponding to each target test item by using a preset weight function, where the preset weight function may be represented by the following formula (1):

wherein a (i) represents the weight corresponding to the ith target test item, b (i) represents the correlation coefficient between the ith target test item and the first test item, and n represents the total number of the target test items; the sum of the weights corresponding to all target test items is 1.

Based on the above formula (1), the weight corresponding to the target test item is positively correlated to the degree of correlation between the target test item and the first test item.

It can be understood that, according to the correlation between the target test item and the first test item, the verification device in the embodiment of the disclosure determines the weight positively correlated to the correlation, and determines the weighting result corresponding to the target test item, so that the correlation between the weighting result corresponding to the target test item and the burn-in test is positively correlated, thereby improving the influence of the weighting result corresponding to the target test item with higher correlation to the burn-in test on the grouping, and further improving the accuracy of verifying the reliability of the second test facility based on the result difference after the burn-in test is performed on the grouped semiconductor devices.

In some embodiments, after determining the weight corresponding to each target test item, the verification device may, for each semiconductor device, calculate a mean value of the weighting results corresponding to the semiconductor device, equally divide the semiconductor devices whose mean value is greater than a preset mean value threshold into M groups, and equally divide the semiconductor devices whose mean value is less than or equal to the preset mean value threshold into the M groups. The verification device thereby verifies the reliability of the second test facility based on the grouped semiconductor devices.

In some other embodiments, the grouping the plurality of semiconductor devices according to the weighting result corresponding to each of the target test items of each semiconductor device includes:

adding the weighting results corresponding to the target test items of the semiconductor devices to obtain the weighting sum corresponding to the semiconductor devices;

and grouping the plurality of semiconductor devices according to the weighted sum corresponding to each semiconductor device.

In the embodiment of the present disclosure, after the verification device determines the weighting results corresponding to the target test items of the semiconductor devices, the weighting results corresponding to the target test items of the semiconductor devices are added for each semiconductor device, so as to obtain a weighting sum corresponding to the semiconductor device, which can be represented by the following formula (2):

wherein y (i) represents a weighted sum corresponding to the ith target test item, m (i, j) represents a result corresponding to the ith target test item of the jth semiconductor device, and m (i, j) × a (i) represents a weighted result corresponding to the ith target test item of the jth semiconductor device.

After determining the weighted sum corresponding to each semiconductor device, the verification equipment groups the semiconductor devices according to the weighted sum corresponding to each semiconductor device. In some embodiments, the semiconductor devices whose weighted sums are greater than a preset weighted threshold may be equally divided into M groups, and the remaining ungrouped semiconductor devices may be equally divided into the aforementioned M groups. As can be seen from the foregoing, the characteristics of the semiconductor devices can be characterized based on the test results of the semiconductor devices, so that the smaller the difference between the weighted sums corresponding to the semiconductor devices is, the more similar the characteristics of the semiconductor devices are, the embodiments of the present disclosure group the semiconductor devices based on the weighted sums of the semiconductor devices, so that the distribution of the weighted sums corresponding to the semiconductor devices between the groups is similar, and thus the processes of the semiconductor devices between the groups can be similar.

In other embodiments, the weighted sum of the semiconductor devices may be sorted, and the semiconductor devices may be sequentially grouped into M groups according to the sorting result, where the sorting number of the semiconductor devices included in the p-th group is M × q + p, q is a natural number, and p is a positive integer; taking M as an example 2, the first group includes semiconductor devices with a rank of 2 × q +1 (odd number), and the second group includes semiconductor devices with a rank of 2 × q +2 (even number). The verification device thereby verifies the reliability of the second test facility based on the difference in the results of the grouped semiconductor devices after burn-in test. As can be seen from the foregoing, the smaller the weighting sum difference corresponding to the semiconductor devices, the closer the characteristics of the semiconductor devices are, and thus the smaller the characteristic difference between the weighting with the closer the sorting number and the corresponding semiconductor devices is, so that the semiconductor devices in the groups are grouped based on the weighting sum sorting of the semiconductor devices, and the processes of the semiconductor devices in the groups are also similar.

It can be understood that, according to the verification apparatus in the embodiment of the present disclosure, the semiconductor devices are grouped based on the weighted sum corresponding to each semiconductor device, so that the influence of the characteristics of the semiconductor devices represented by the multiple test item results (for example, the results corresponding to multiple second test items in the target test item) on the grouping can be considered, thereby improving the accuracy of verifying the reliability of the second test facility based on the grouped semiconductor devices.

In some embodiments, the semiconductor device corresponds to a position identifier;

In the embodiment of the present disclosure, the semiconductor devices correspond to position identifiers, such as coordinates of the semiconductor devices on the wafer, or serial numbers of the semiconductor devices arranged on the wafer determined according to a preset sequence. It should be noted that, when there are multiple wafers, different wafers may be distinguished through a wafer identifier, and the location identifier of the semiconductor device may also be a combination of the wafer identifier and a coordinate or serial number of the semiconductor device on the wafer indicated by the wafer identifier, where the wafer identifier may be a wafer name, or information of a unique identifier such as a letter or a number.

After determining the weighted sum corresponding to each semiconductor device, the verification device of the embodiment sorts the size of each weighted sum, groups the semiconductor devices indicated by the weighted sum associated with the odd-numbered sorted serial number into one group, and groups the semiconductor devices indicated by the weighted sum associated with the even-numbered sorted serial number into another group, wherein the sorting may be ascending or descending.

It will be appreciated from the foregoing that the characteristics of the semiconductor device may be characterized based on the electrical signals (e.g., the first result set and/or the second result set) of the operational output of the semiconductor device, such that the weighted sum of the semiconductor devices may characterize the characteristics of the semiconductor device, with the smaller the difference between corresponding weighted sums of the semiconductor devices, the smaller the difference in the characteristics characterizing the semiconductor devices. The embodiment of the disclosure sorts the weighted sums corresponding to the semiconductor devices, and the difference between the sorted weighted sum and the weighted sum adjacent to the sorted weighted sum is smaller than the difference between the weighted sum and the weighted sum not adjacent to the other weighted sum, so that the embodiment of the disclosure sorts the semiconductor devices with the odd-numbered sorting number into one group, and the semiconductor devices with the even-numbered sorting number into another group, thereby reducing the characteristic difference between the grouped semiconductor devices among the groups, and further improving the accuracy of verifying the reliability of the second test facility based on the result difference after the grouped semiconductor devices are subjected to the aging test.

In some embodiments, the method further comprises:

In the embodiment of the present disclosure, before performing weighting processing on a result corresponding to a target test item by using a weight corresponding to the target test item, the verification device performs data processing on the result corresponding to the target test item by using a preset data processing rule; the preset data processing rules comprise data filtering rules and data normalization rules.

In the embodiment of the disclosure, the verification device performs filtering processing on the data according to the data filtering rule, and may filter a result that does not fall within a preset parameter range according to a preset parameter range, such as a range of a target test item; wherein the result that does not fall within the preset parameter range is an abnormal voltage value. It can be understood that, by performing data filtering processing on the result corresponding to the target test item in the embodiments of the present disclosure, the influence of abnormal data exceeding the range of the target test item on the weighting result can be reduced, so as to improve the accuracy of grouping the semiconductor devices and verifying the reliability of the second test facility according to the result of the grouped burn-in test.

In the embodiment of the present disclosure, the verification device normalizes the data according to the data normalization rule, which may be to normalize a result corresponding to the target test item according to a preset normalization function, where the preset normalization function may be represented by the following formula (3):

where M (i, j) represents the normalized result, max { M (i, j) } represents the maximum value in the results corresponding to the target test item, and min { M (i, j) } represents the minimum value in the results corresponding to the target test item.

It can be understood that, since the magnitude of the result of each target test item may be different, the result with a larger magnitude has a larger influence on the weighting result, and the embodiment of the present disclosure performs data normalization processing on the result corresponding to the target test item, so that the influence of different magnitudes on the weighting result can be reduced, and further, the accuracy of determining the weighting result corresponding to the target test item according to the result after data processing, grouping the semiconductor devices according to the weighting result, and verifying the reliability of the second test facility according to the result of the burn-in test after grouping is improved.

In some embodiments, the result that does not fall within the preset parameter range may also be assigned as the minimum value of the results corresponding to the target test item, and the result corresponding to the assigned target test item may be represented by the following formula (4):

M(i,j)＝min{M(i,j)} (4)；

wherein, M (i, j) represents the result corresponding to the assigned target test item. In the embodiment of the present disclosure, under the condition that the result corresponding to the target test item does not fall within the preset parameter range, the result may be assigned as the minimum value in the results corresponding to the target test item by using the formula (4), and the result corresponding to the normalized target test item is changed into zero by using the preset normalization function of the formula (3), so that the filtering processing of the result corresponding to the target test item that does not fall within the preset range is realized by normalization.

It can be understood that, after the verification device processes the result corresponding to the target test item according to the preset data processing rule, the result corresponding to the target test item after data processing is weighted to obtain the weighted result corresponding to the target test item, so that the accuracy of subsequently grouping the semiconductor devices according to the weighted result is higher.

In the embodiment of the present disclosure, since the second test facility performing the test may increase or decrease the test items, after determining the target test item, the verification device in the embodiment of the present disclosure determines whether the target test item meets the preset test requirement; wherein the predetermined test requirements include test items executable by the second test facility.

And if the target test item belongs to the test items executable by the second test facility, the verification equipment groups the plurality of semiconductor devices according to the result corresponding to the target test item. If the target test item does not belong to the test item executable by the second test facility, the second test facility does not execute the test item, thereby filtering the test item, and reselecting the target test item according to the correlation between each test item except the test item and the first test item. For example, if 5 target test items need to be selected, in the ranking of the relevance from high to low, the 5 th test item in the 6 test items ranked at the top does not meet the preset test requirement, so that the test items ranked in 1-4 and 6 can be determined as the target test items.

It can be understood that, when determining the target test item, the embodiment of the present disclosure filters the test item that is not executed by the second test facility according to the preset test requirement, so as to improve the purpose of the selected target test item, and analyzes the semiconductor device according to the result corresponding to the target test item, so as to reduce the influence of the test item that is not executed by the second test facility on the grouping, thereby improving the purpose of the grouping, and further improving the accuracy of verifying the reliability of the second test facility based on the target test item related to the second test facility.

determining a target test item according to the correlation between each second test item and the first test item, including:

for each second test item, summing the correlation coefficients between the second test item and the first test items; wherein the correlation coefficient is used for characterizing the correlation, and the correlation coefficient is positively correlated with the degree of correlation;

and determining the target test item according to the summed correlation coefficient corresponding to each second test item.

In the embodiment of the disclosure, the first result set includes results of at least two first test items, that is, the first result set includes results corresponding to at least two aging test items, and each first test item includes a different aging test parameter group. The verification equipment of the embodiment of the disclosure determines the correlation coefficient between each second test item and each first test item for each second test item, and adds the correlation coefficients to obtain the added correlation coefficient corresponding to the second test item; and determining the target test item according to the summed correlation coefficient corresponding to each second test item.

Illustratively, the first result set includes N4 columns of test results corresponding to N4 burn-in test items, and the second result set includes N1 columns of test results corresponding to N1 DC test items, N2 columns of test results corresponding to N2 AC test items, and N3 columns of test results corresponding to N3 functional test items; the verification device determines, for each second test item, correlation coefficients of 1 column of results corresponding to the second test item and 1 column of results corresponding to N4 first test items, respectively, by using, for example, a correlation function, determines a sum of the correlation coefficients corresponding to the second test item as a weighted correlation coefficient corresponding to the second test item, and determines a test item corresponding to a weighted correlation coefficient greater than a preset correlation coefficient threshold (e.g., 1.5) as a target test item; and then the verification equipment groups the semiconductor devices according to the result corresponding to the target test item, and verifies the reliability of the probe test of the second test facility by using the grouped semiconductor devices.

If the first result set includes at least two first test items, when determining the weight corresponding to each target test item according to the correlation between each target test item and the first test item, for example, when determining the weight based on the foregoing formula (1), b (i) is the sum of the correlation coefficients corresponding to each target test item and each first test item.

It can be understood that, in the embodiment of the present disclosure, when the first result set includes results of at least two first test items, that is, when the semiconductor device is tested by using at least two sets of burn-in test parameters, the semiconductor device burn-in test is performed with high sufficiency, so that the verification apparatus sums, for each second test item, correlation coefficients between the second test item and each first test item, and determines the target test item according to the summed correlation coefficient corresponding to each second test item, which may improve accuracy of grouping the semiconductor device based on the results of the target test item, thereby improving accuracy of verifying the second test facility.

the verifying the reliability of the probe test by the second test facility by using the grouped semiconductor devices comprises the following steps:

obtaining a second test result after the probe test is carried out on the grouped group of semiconductor devices by using the first test facility;

obtaining a third test result after the probe test is carried out on the other group of grouped semiconductor devices by using the second test facility;

determining a difference between the second test result and the third test result;

determining that the second test facility is reliable under the condition that the difference meets a preset difference condition;

determining that the second test facility is unreliable if the difference does not satisfy the preset difference condition.

In the embodiment of the present disclosure, it can be seen from the foregoing that the verification apparatus may divide the plurality of semiconductor devices into two groups, where the characteristic difference of the semiconductor devices between the two groups is within a preset difference range, and the processes of the semiconductor devices between the two groups are similar.

In the verification apparatus of the embodiment of the present disclosure, in the same manner as the aforementioned first test result, a second test result obtained by performing a probe test on one group of grouped semiconductor devices by using the first test facility, and a third test result obtained by performing a probe test on another group of grouped semiconductor devices by using the second test facility are obtained, and a difference between the second test result and the first test result is determined. If the difference between the second test result and the third test result meets the preset difference condition, determining that the second test facility is reliable; and if the difference does not meet the preset difference condition, determining that the second test facility is unreliable. Wherein the difference may be a difference between a proportion of the semiconductor devices in the second test result whose electrical signals satisfy the requirements corresponding to the test items and a proportion of the semiconductor devices in the third test result whose electrical signals satisfy the requirements corresponding to the test items; or the difference between the mean value of the electrical signals in the second test result and the mean value of the electrical signals in the third test result.

The preset difference condition in the embodiment of the present disclosure may include the preset difference threshold, and may further include a preset difference range. Taking a preset difference condition as a preset difference threshold value as an example, determining that the second test facility is reliable under the condition that the difference is smaller than the preset difference threshold value; and determining that the second test facility is unreliable if the difference is greater than or equal to a preset difference threshold.

It can be understood that, because the processes of the semiconductor devices are similar between the groups divided into two groups, the results of testing the two groups of semiconductor devices with similar processes based on the testing facility with higher reliability should also be similar. Therefore, the verification equipment disclosed by the embodiment of the disclosure can verify whether the second test facility is reliable or not by using the difference between the second test result obtained by performing the probe test on one group of semiconductor devices by using the first test facility and the third test result obtained by performing the probe test on the other group of semiconductor devices by using the second test facility, and can improve the efficiency and convenience for obtaining the verification result by comparing two test results in the groups compared with the case that the semiconductor devices are divided into multiple groups.

Fig. 2 shows a second flowchart of a verification method for probe test according to an embodiment of the present disclosure, and as shown in fig. 2, the method includes:

s21, analyzing a large amount of data, extracting N columns of test items, and calculating weights corresponding to the N columns of test items;

in an embodiment of the disclosure, the mass data corresponds to a first test result of the probe testing of the plurality of semiconductor devices on the one or more wafers using the first test facility; the first test result comprises a first result set after the burn-in test is carried out on each semiconductor device and a second result set after the test except the burn-in test is carried out on each semiconductor device; the N columns of test items correspond to the aforementioned target test items.

The verification equipment analyzes the mass data, namely determines the correlation between a first test item and each test item (including the first test item and a second test item) according to the result corresponding to the first test item and the results corresponding to at least two second test items in the mass data, and determines N columns of test items according to the correlation between each test item and the first test item; and the degree of correlation between any one test item in the N columns of test items and the first test item is greater than the degree of correlation between the test items except the N columns of test items and the first test item.

S22, determining whether the N rows of test items are suitable for the experiment;

in the embodiment of the present disclosure, it is determined whether N columns of test items are applicable to the experiment, that is, it is determined whether N columns of test items satisfy the aforementioned preset test requirement, and in the case where N columns of test items are applicable to the experiment, step S23 is performed, and in the case where any N columns of test items are not applicable to the experiment, step S21 is performed.

S23, selecting a wafer to be tested, and extracting test results of N rows of test items and coordinates of each bare chip;

in the embodiment of the present disclosure, the wafer to be tested is the one or more wafers, the bare chip corresponds to the semiconductor device, and the coordinates of the bare chip correspond to the position identifier of the semiconductor device. The position identifier may be coordinates of the semiconductor device on the wafer, or serial numbers of the semiconductor devices arranged on the wafer determined according to a preset sequence.

After the verification equipment determines the N rows of test items, the test results of the N rows of test items of the wafer to be tested are selected from the first test results, and each test result is associated with the coordinate of the bare chip.

S24, eliminating abnormal data of the N rows of test items, and performing normalization processing;

in the embodiment of the present disclosure, the verification device processes the test results of the N columns of test items according to a preset data processing rule, for example, performs data filtering processing on the N columns of test items, thereby removing abnormal data, and performing normalization processing on the data.

S25, carrying out weighted summation and sequencing on the normalized data, and dividing the bare chips into two groups according to a sequencing result;

in the embodiment of the disclosure, the verification device determines the weight corresponding to each N columns of test items according to the correlation between the N columns of test items and the first test item; the weight corresponding to the N columns of test items is positively correlated with the correlation degree of the N columns of test items and the first test item.

The verification equipment weights the results after normalization processing corresponding to the N columns of test items by using the weights corresponding to the N columns of test items to obtain weighted results corresponding to the N columns of test items; and adding the weighting results corresponding to the N columns of test items of the bare chips aiming at each bare chip to obtain the weighting sum corresponding to the bare chips.

After determining the weighted sum corresponding to each bare chip, the verification device of the embodiment sorts the weighted sum corresponding to each bare chip, puts the bare chips indicated by the weighted sum and the associated position identifier with odd sorting serial numbers into one group, and puts the bare chips indicated by the weighted sum and the associated position identifier with even sorting serial numbers into another group.

And S26, verifying and analyzing the aging test items by utilizing the two groups of bare chips.

In the embodiment of the disclosure, after dividing a plurality of bare chips into two groups of bare chips, the verification device obtains a second test result obtained after testing one group of bare chips grouped by using a first test facility and a third test result obtained after testing the other group of bare chips grouped by using a second test facility;

determining the difference between the second test result and the third test result, and determining that the second test facility is reliable under the condition that the difference meets the preset difference condition; and determining that the second test facility is unreliable under the condition that the difference does not meet the preset difference condition.

It can be understood that the verification device divides the semiconductor device into a plurality of groups with similar processes according to the first test result, so that the reliability of the second test facility is verified based on the difference between the test results of testing the groups with similar processes, and the instantaneity of verification can be improved on the basis of considering the accuracy of verification. In addition, the abnormal data in the results of the N columns of test items are removed, and normalization processing is performed, so that the verification accuracy can be further improved.

Fig. 3 shows a block diagram of a verification apparatus for probe test according to an embodiment of the present disclosure, and as can be seen from fig. 3, the apparatus includes:

an obtaining module 301, configured to obtain a first test result of performing a probe test on a plurality of semiconductor devices on a wafer by using a first test facility;

a grouping module 302 for grouping the plurality of semiconductor devices according to the first test result; wherein, the characteristic difference of the semiconductor devices among the groups after grouping is within the preset difference range;

and the verification module 303 is configured to verify the reliability of the probe test performed by the second test facility by using the grouped semiconductor devices.

the grouping module 302 is configured to group the plurality of semiconductor devices according to the first result set and the second result set;

the verification module 303 is configured to verify reliability of the burn-in test performed by using a second test facility, using the grouped semiconductor devices.

the grouping module 302 is configured to determine a correlation between the first test item and each of the second test items according to a result corresponding to the first test item and a result corresponding to the at least two second test items; determining a target test item according to the correlation between each second test item and the first test item; wherein the degree of relevance of the target test item to the first test item is greater than the degree of relevance of test items other than the target test item to the first test item; and grouping the plurality of semiconductor devices according to the result corresponding to the target test item.

a determining module 304, configured to determine a weight corresponding to each target test item according to a correlation between each target test item and the first test item; wherein the weight corresponding to the target test item is positively correlated with the degree of correlation between the target test item and the first test item;

the grouping module 302 is configured to weight a result corresponding to the target test item by using the weight corresponding to the target test item to obtain a weighted result corresponding to the target test item; and grouping the plurality of semiconductor devices according to the weighting result corresponding to each target test item of each semiconductor device.

In some embodiments, the grouping module 302 is configured to, for each semiconductor device, add the weighting results corresponding to the target test items of the semiconductor device to obtain a weighted sum corresponding to the semiconductor device; and grouping the plurality of semiconductor devices according to the weighted sum corresponding to each semiconductor device.

the grouping module 302 is configured to sort the weighted sums corresponding to the semiconductor devices, group the semiconductor devices indicated by the weighted sum associated with the odd-numbered sorting serial number into one group, and group the semiconductor devices indicated by the weighted sum associated with the even-numbered sorting serial number into another group.

In some embodiments, the apparatus further comprises:

a processing module 305, configured to perform data processing on the result corresponding to the target test item in the second result set according to a preset data processing rule, so as to obtain a result after data processing; wherein the preset data processing rule comprises at least one of the following: data filtering rules and data normalization rules;

the grouping module 302 is configured to weight a result after data processing corresponding to the target test item by using the weight corresponding to the target test item, so as to obtain a weighted result corresponding to the target test item.

In some embodiments, the grouping module 302 is configured to, when the target test item meets a preset test requirement, group the plurality of semiconductor devices according to a result corresponding to the target test item; wherein the preset test requirement comprises a test item included by the second test facility.

the grouping module 302 is configured to sum, for each second test item, correlation coefficients between the second test item and the first test items; wherein the correlation coefficient is used for characterizing the correlation, and the correlation coefficient is positively correlated with the degree of correlation; and determining the target test item according to the summed correlation coefficient corresponding to each second test item.

the verification module 303 is configured to obtain a second test result obtained after the probe test is performed on the grouped group of semiconductor devices by using the first test facility; obtaining a third test result after the probe test is carried out on the other group of grouped semiconductor devices by using the second test facility; determining a difference between the second test result and the third test result; determining that the second test facility is reliable under the condition that the difference meets a preset difference condition; determining that the second test facility is unreliable if the difference does not satisfy the preset difference condition.

Fig. 4 shows a schematic physical structure diagram of an electronic device according to an embodiment of the present disclosure, as shown in fig. 4, including: a processor 01, a memory 02 in which instructions executable by the processor 01 are stored, a communication interface 03, and a bus 04 for connecting the processor 01, the memory 02 and the communication interface 03. The processor 01 is used for executing the verification method program of the probe test stored in the memory.

In an embodiment of the present invention, the Processor 01 may be at least one of an Application Specific Integrated Circuit (ASIC), a Digital Signal Processor (DSP), a Digital Signal Processing Device (DSPD), a Programmable Logic Device (PLD), a Field Programmable Gate Array (FPGA), a Central Processing Unit (CPU), a controller, a microcontroller, and a microprocessor. It will be appreciated that the electronic devices used to implement the processor functions described above may be other devices, and embodiments of the present invention are not limited in particular. The terminal may further comprise a memory 02, which memory 02 may be connected to the processor 01, wherein the memory 02 is for storing semantic analysis program code, which program code comprises computer operating instructions, and the memory 02 may comprise a high speed RAM memory, and may further comprise a non-volatile memory, such as at least two disk memories.

In practical applications, the Memory 02 may be a volatile Memory (volatile Memory), such as a Random-Access Memory (RAM); or a non-volatile Memory (non-volatile Memory), such as a Read-Only Memory (ROM), a flash Memory (flash Memory), a Hard Disk (Hard Disk Drive, HDD) or a Solid-State Drive (SSD); or a combination of the above types of memories and provides instructions and data to the processor 01.

In addition, each functional module in this embodiment may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware or a form of a software functional module.

Based on the understanding that the technical solutions of the present embodiment substantially or partially contribute to the prior art, or all or part of the technical solutions may be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for enabling a computer device (which may be a personal computer, a server, or a network device, etc.) or a processor (processor) to execute all or part of the steps of the method of the present embodiment. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, an optical disk, or other various media capable of storing program codes.

The disclosed embodiments provide a storage medium having stored thereon computer-executable instructions; the computer executable instructions, when executed by a processor, can implement at least one of the methods provided by one or more of the foregoing aspects, for example, the verification method of the probe test shown in fig. 1.

In the several embodiments provided in the present disclosure, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described device embodiments are merely illustrative, for example, the division of the modules is only one logical functional division, and other division manners may be available in actual implementation, such as: multiple modules or components may be combined, or may be integrated into another system, or some features may be omitted, or not implemented. In addition, the coupling, direct coupling or communication connection between the components shown or discussed may be through some interfaces, and the indirect coupling or communication connection between the devices or units may be electrical, mechanical or other forms.

The modules described as separate parts may or may not be physically separate, and parts displayed as modules may or may not be physical modules, may be located in one place, or may be distributed on a plurality of network modules; some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, all functional modules in the embodiments of the present disclosure may be integrated into one processing module, or each module may be separately used as one module, or two or more modules may be integrated into one module; the integrated module can be realized in a hardware form, and can also be realized in a form of hardware and a software functional module. Those of ordinary skill in the art will understand that: all or part of the steps for implementing the method embodiments may be implemented by hardware related to program instructions, and the program may be stored in a computer readable storage medium, and when executed, the program performs the steps including the method embodiments; and the aforementioned storage medium includes: various media capable of storing program codes, such as a removable Memory device, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.

The methods disclosed in the several method embodiments provided in this disclosure may be combined arbitrarily without conflict to arrive at new method embodiments.

The features disclosed in several of the apparatus embodiments provided in this disclosure may be combined in any combination to yield new apparatus embodiments without conflict.

The features disclosed in the several method or apparatus embodiments provided in this disclosure may be combined in any combination to arrive at a new method or apparatus embodiment without conflict.

The above description is only for the specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present disclosure, and all the changes or substitutions should be covered within the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A method of validating a probe test, the method comprising:

acquiring a first test result of performing probe test on a plurality of semiconductor devices on a wafer by using a first test facility;

grouping the plurality of semiconductor devices according to the first test result; wherein, the characteristic difference of the semiconductor devices among the groups is within the range of the preset difference;

and verifying the reliability of the probe test performed by the second test facility by using the grouped semiconductor devices.

2. The method of claim 1, wherein the first test results comprise a first set of results after performing a burn-in test on each of the semiconductor devices and a second set of results after performing a test other than the burn-in test on each of the semiconductor devices;

the grouping the plurality of semiconductor devices according to the first test result includes:

3. The method of claim 2, wherein the first set of results comprises results for a first test item, and wherein the second set of results comprises results for at least two second test items;

said grouping said plurality of semiconductor devices according to said first result set and said second result set comprises:

4. The method of claim 3, wherein the target test item comprises a plurality, the method further comprising:

determining the weight corresponding to each target test item according to the correlation between each target test item and the first test item; wherein the weight corresponding to the target test item is positively correlated with the degree of correlation between the target test item and the first test item;

the grouping the plurality of semiconductor devices according to the result corresponding to the target test item includes:

5. The method of claim 4, wherein grouping the plurality of semiconductor devices according to the weighting result corresponding to each of the target test items of each semiconductor device comprises:

6. The method of claim 4, wherein the semiconductor device corresponds to a location identifier;

7. The method of claim 4, further comprising:

8. The method of claim 3, wherein grouping the plurality of semiconductor devices according to the result corresponding to the target test item comprises:

9. The method of claim 3, wherein the first set of results includes results for at least two first test items;

10. The method of claim 1, wherein the grouped semiconductor devices comprise two groups of semiconductor devices;

acquiring a third test result after the probe test is carried out on the other group of grouped semiconductor devices by using the second test facility;

determining that the second test facility is reliable when the difference meets a preset difference condition;

11. An apparatus for validating a probe test, the apparatus comprising:

the system comprises an acquisition module, a test module and a control module, wherein the acquisition module is used for acquiring a first test result of probe testing of a plurality of semiconductor devices on a wafer by using a first test facility;

a grouping module for grouping the plurality of semiconductor devices according to the first test result; wherein, the characteristic difference of the semiconductor devices among the groups after grouping is within the preset difference range;

and the verification module is used for verifying the reliability of the probe test performed by the second test facility by using the grouped semiconductor devices.

12. An electronic device, comprising:

a memory for storing computer executable instructions;

a processor, coupled to the memory, for implementing the method of any one of claims 1 to 10 by executing the computer-executable instructions.

13. A computer storage medium having stored thereon computer-executable instructions; the computer executable instructions, when executed by a processor, are capable of implementing the method of any one of claims 1 to 10.