CN115575718B - Capacitor detection method and capacitor detection circuit based on delay phase-locked loop - Google Patents
Capacitor detection method and capacitor detection circuit based on delay phase-locked loop Download PDFInfo
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Abstract
The embodiment of the invention provides a capacitance detection method and a capacitance detection circuit based on a delay phase-locked loop, wherein the method comprises the following steps: the reference clock signal is sequentially subjected to delay processing through a first capacitor and a first voltage comparator, so that a first delay signal is obtained; the reference clock signal and the output signal of the main channel in the last time step sequentially pass through a second capacitor and a second voltage comparator to be subjected to delay processing, so that a second delay signal is obtained; inputting the first delay signal and the second delay signal into the main channel to obtain an output signal of the main channel at the current time step; when the output signal of the main channel at the current time step is stable, the value of the first capacitor is calculated according to the output signal of the current time step. The invention can make the first voltage comparator and the second voltage comparator work at the turning point with higher signal quantity, thereby improving the signal quantity of delay time, locking range and further improving the accuracy of capacitance detection.
Description
Technical Field
The present invention relates to the field of electronic devices, and in particular, to a capacitance detection method and a capacitance detection circuit based on a delay locked loop.
Background
The delay phase-locked loop is used for eliminating clock delay, realizing zero transmission delay, minimizing deviation between an input clock signal and an overall clock network inside the whole chip, and mainly comprises a phase discriminator, a charge pump and a sampler, wherein an elimination path is formed through the output of the sampler and the phase discriminator, and the clock signal of the overall clock network is synchronized with the input clock signal through a feedback signal. In the conventional capacitance detection circuit, since the input clock signal is delayed by the delay capacitance in the signal path and the delay signal is determined by the capacitance in the cancellation path, it is necessary to detect and adjust the delay capacitance of the signal path and the capacitance in the feedback loop, so that the input clock signal is synchronized with the output clock signal after delay, and when the output clock signal is stable, the value of the delay capacitance in the signal path is calculated. However, the existing delay phase-locked loop performs signal feedback through an input clock signal, so that the signal quantity of delay time is low, the locking range is narrow, and the accuracy of capacitance detection is low.
Disclosure of Invention
The embodiment of the invention provides a capacitor detection method based on a delay phase-locked loop, which is characterized in that a first voltage comparator and a second voltage comparator are arranged in a signal path and an elimination path, and the turning points of the first voltage comparator and the second voltage comparator are adjusted, so that the first voltage comparator and the second voltage comparator can work at higher turning points, the signal quantity of delay time can be improved, the locking range is improved, and the accuracy of capacitor detection is further improved.
In a first aspect, an embodiment of the present invention provides a capacitance detection method based on a delay locked loop, which is applied to a capacitance detection circuit, where the capacitance detection circuit includes: the method comprises the following steps of:
Sequentially passing the reference clock signal through the first capacitor and the first voltage comparator to perform delay processing to obtain a first delay signal;
the input signal of the elimination path and the output signal of the main path at the last time step sequentially pass through the second capacitor and the second voltage comparator to be subjected to delay processing, so as to obtain a second delay signal;
Inputting the first delay signal and the second delay signal into a main channel to obtain an output signal of the main channel at the current time step;
and when the output signal of the main channel in the current time step is stable, calculating the value of the first capacitor according to the output signal of the current time step.
Optionally, the step of sequentially passing the reference clock signal through the first capacitor and the first voltage comparator to perform delay processing to obtain a first delay signal includes:
delay processing is carried out on the reference clock signal through the first capacitor, and a first signal to be turned over is obtained;
and when the first signal to be flipped reaches the flipping point of the first voltage comparator, flipping the first signal to be flipped to obtain a first delay signal.
Optionally, the step of sequentially passing the input signal of the cancellation path and the output signal of the main path at the previous time step through the second capacitor and the second voltage comparator to perform delay processing to obtain a second delay signal includes:
Loading the output signal of the main channel in the last time step to the second capacitor, and carrying out delay processing on the input signal of the elimination channel through the second capacitor loaded with the output signal of the main channel in the last time step to obtain a second signal to be overturned;
And when the second signal to be overturned reaches the overturned point of the second voltage comparator, the second signal to be overturned is overturned, and a second delay signal is obtained.
Optionally, before the step of sequentially passing the reference clock signal through the first capacitor and the first voltage comparator to perform delay processing to obtain a first delay signal, the method further includes:
Determining a target turning point of the first voltage comparator by taking a rising edge end point of the first capacitor or a falling edge end point of the first capacitor or a voltage value of a power supply as a nearby point;
and adjusting the turning point of the first voltage comparator to the target turning point of the first voltage comparator by controlling the threshold voltage of the first voltage comparator.
Optionally, before the step of determining the target turning point of the first voltage comparator with the rising edge end point of the first capacitor or the falling edge end point of the first capacitor or the power supply voltage as the approach point, the method further includes:
determining the phase difference detection type of the main path;
And determining the type of the approach point according to the phase difference detection type of the main path, wherein the type of the approach point comprises a rising edge end point of the first capacitor, a falling edge end point of the first capacitor and a voltage value of the power supply.
Optionally, the main path includes a phase frequency detector, and the step of determining the type of the approach point according to the phase difference detection type of the main path includes:
when the phase frequency detector detects the phase difference of the rising edge, determining the type of the approach point as the rising edge end point of the first capacitor;
When the phase frequency detector detects a phase difference of a falling edge, determining the type of the approach point as a falling edge end point of the first capacitor;
when the rising edge of the first voltage comparator corresponds to the rising edge of the reference clock signal and the phase difference of the rising edge is detected by the phase frequency detector, the type of the approaching point is determined to be the voltage value of the power supply.
Optionally, the step of determining the target turning point of the first voltage comparator with the rising edge end point of the first capacitor or the falling edge end point of the first capacitor or the power supply voltage as the approach point includes:
determining a semaphore for the delay time;
According to the signal quantity of the delay time, adjusting the distance value between the turning point of the first voltage comparator and the approaching point;
and determining a target turning point of the first voltage comparator according to the distance value between the turning point of the first voltage comparator and the approaching point.
Optionally, the step of determining the target turning point of the first voltage comparator with the rising edge end point of the first capacitor or the falling edge end point of the first capacitor or the power supply voltage as the approach point includes:
determining a semaphore for the delay time;
According to the signal quantity of the delay time, adjusting the proportion value of the turning point of the first voltage comparator to the approaching point;
And determining a target turning point of the first voltage comparator according to the ratio value of the turning point of the first voltage comparator to the approaching point.
Optionally, the inversion point of the first voltage comparator is the same as the inversion point of the second voltage comparator, and the threshold voltage of the first voltage comparator and the threshold voltage of the second voltage comparator are adjusted by the same adjusting signal.
In a second aspect, an embodiment of the present invention provides a capacitance detection circuit, including: the circuit comprises a main path, a signal path and a cancellation path, wherein the output end of the signal path is electrically connected with the input end of the main path, the output end of the cancellation path is electrically connected with the output end of the main path so that the main path and the cancellation path form a delay phase-locked loop, the signal path comprises a first capacitor and a first voltage comparator, the cancellation path comprises a second capacitor and a second voltage comparator, the turning point of the first voltage comparator is adjusted according to the threshold voltage of the first voltage comparator, the turning point of the second voltage comparator is adjusted according to the threshold voltage of the second voltage comparator, and the capacitor detection circuit is used for realizing the steps in the capacitor detection method based on the delay phase-locked loop.
In the embodiment of the invention, a reference clock signal sequentially passes through the first capacitor and the first voltage comparator to be subjected to delay processing, so as to obtain a first delay signal; the reference clock signal and the output signal of the main channel at the last time step sequentially pass through the second capacitor and the second voltage comparator to be subjected to delay processing, so that a second delay signal is obtained; inputting the first delay signal and the second delay signal into a main channel to obtain an output signal of the main channel at the current time step; and when the output signal of the main channel in the current time step is stable, calculating the value of the first capacitor according to the output signal of the current time step. The first voltage comparator and the second voltage comparator are arranged in the signal path and the elimination path, and the turning points of the first voltage comparator and the second voltage comparator are adjusted, so that the first voltage comparator and the second voltage comparator can work at the turning point with higher signal quantity, the signal quantity of delay time can be improved, the locking range is improved, and the accuracy of capacitance detection is further improved.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a block diagram of a capacitance detection circuit according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a delay of a reference clock signal provided by an embodiment of the present invention;
fig. 3 is an equivalent circuit diagram of a process of charging a capacitor by an inverter according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a response process of an RC network to a step signal according to an embodiment of the present invention;
fig. 5 is a flowchart of a capacitance detection method based on a delay locked loop according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to fig. 1, fig. 1 is a block diagram of a capacitance detection circuit according to an embodiment of the present invention, as shown in fig. 1, the capacitance detection circuit includes: main path, signal path and cancel path.
In the embodiment of the invention, the output end of the signal path is electrically connected with the input end of the main path, the output end of the elimination path is electrically connected with the input end of the main path, and the output end of the elimination path is electrically connected with the output end of the main path, wherein the signal path comprises a first capacitor and a first voltage comparator, and the elimination path comprises a second capacitor and a second voltage comparator. The main path and the cancellation path form a delay phase-locked loop, and the first capacitor can also be called a capacitor to be detected.
The input of the signal path is a reference clock signal Vosc, and the first capacitor Cx in the signal path delays the reference clock signal Vosc to obtain a first delayed signal Vosc_Cx output by the signal path.
In the embodiment of the present invention, the input of the cancellation path is the reference clock signal Vosc, the output signal Dout of the main path in the last time step is loaded in the second capacitor Cc in the cancellation path, and the second capacitor Cc in the cancellation path delays the reference clock signal Vosc to obtain the second delayed signal vosc_cc output by the cancellation path. At the current time step, the first delay signal vosc_cx and the second delay signal vosc_cc are input into the main channel, so as to obtain the output signal Dout of the main channel at the current time step. It can be seen that since the charging of the first capacitor Cx takes time, the reference clock signal Vosc is delayed to obtain the first delayed signal vosc_cx, and when the magnitude of the first capacitor Cx is changed, the charging time also changes, and thus the delay time also changes. The first delay signal vosc_cx and the second delay signal vosc_cc are coupled together to form a corresponding output signal Dout. The output signal Dout is fed back to control the magnitude of the second capacitor Cc on the cancellation path. When the loop lock is stable, the phase of the first delay signal vosc_cx is the same as the phase of the second delay signal vosc_cc, and the output of the main channel is stable to a certain value. When the output of the main path is stable, the value of the second capacitance Cc of the current time step can be deduced from the output signal Dout of the main path. And the delay time of the cancellation channel is positively correlated with the delay time of the signal path. Therefore, by analyzing the output signal Dout of the main path, a specific variation of the first capacitance Cx can be obtained, thus realizing the detection of the first capacitance Cx.
The change in the magnitude of the first capacitance Cx may be a change in the magnitude generated by a biological touch.
Specifically, referring to fig. 2, fig. 2 is a schematic diagram of delaying a reference clock signal according to an embodiment of the present invention, and as shown in fig. 2, a signal path includes a first inverter and a first voltage comparator, and a first capacitance Cx is coupled between the first inverter and the first voltage comparator. The main path includes a phase frequency detector PFD, a charge pump CP (chargepump), and an ADC sampler. The cancellation path includes a second inverter and a second voltage comparator coupled between the second inverter and the second voltage comparator with a second capacitance Cc. Since the first capacitor Cx requires time for charging, the reference clock signal Vosc is delayed to obtain the first delayed signal vosc_cx, and when the magnitude of the first capacitor Cx is changed, the charging time also changes, and thus the delay time also changes.
Further, in the embodiment of the present invention, the process of charging the capacitor by the inverter may be equivalent to the process of responding to the Step signal by the RC network, please refer to fig. 3 and fig. 4, fig. 3 is an equivalent circuit diagram of the process of charging the capacitor by the inverter provided in the embodiment of the present invention, fig. 4 is a schematic diagram of the process of responding to the Step signal by the RC network provided in the embodiment of the present invention, as shown in fig. 4, step Input is a signal source of a reference clock signal, signal strength is a voltage value VDD of a power supply, R is an equivalent output impedance of the inverter, C is a load capacitor, and Vout is an output signal of an equivalent circuit. Referring to fig. 5, taking a step from 0 as an example, the process of establishing the voltage value VDD from 0 to the power supply output by the inverter is equivalent. When the output voltage exceeds the first level switching point, a point in time Tp can be found at which the voltage on the capacitor C reaches the second level switching point. It can be assumed that the second level inversion point is VDD/2, tp satisfies the following equation:
In the equation, τ=rc=time constant (time comstant).
When Vout is equal to VDD/2, the time is 'Tp', VDD/2= (1-) VDD, in turn, can give tp=ln (2) τ=0.69 τ, and since τ=rc=time constant, tp=0.69 RC can be obtained.
It can further be seen that when a small change in capacitance occurs, the resulting delay time changes to:
Further, when the inversion point is aVDD, the delay time can be changed to:
The above-mentioned a may represent a coefficient of the inversion point with respect to the voltage value VDD of the power supply, and the closer a is to 1, the larger the delay time variation amount is, so that the larger the delay time variation signal amount is. It can be further understood that the closer the inversion point aVDD is to the voltage value VDD of the power supply, the larger the delay time variation amount is, so that the larger the delay time variation signal amount is. Similarly, it can be seen that the amount of delay time varying signal is positively correlated with the equivalent resistance, and the equivalent resistance R of the inverter is increased in order to increase the amount of delay time varying signal. But the equivalent resistance cannot be increased indefinitely because the inverter needs to be essentially set up to operate. If R is too large, the signal establishment time is too long, the signal path and the elimination path formed by the whole reverser are not overturned, and the work is not normal. In addition, since the input signals of the signal path and the cancellation path are both clock reference signals, when the output of the delay locked loop is stable, the delay time of the cancellation path is required to be equal to the delay time of the signal path: . While the value of the second capacitance Cc in the cancellation path is typically less than the value of the first capacitance Cx in the signal path, this requires the equivalent resistance of the cancellation path To be greater than the equivalent resistance of the signal path. The value of the second capacitor Cc in the elimination path can be dynamically adjusted to ensure that the equivalent resistance of the elimination pathAnd fixing.
In practical applications, the range of the first capacitance Cx in the signal path may be very large, for example, to support the situation that the first capacitance Cx in the signal path is close to 0 pF. Thus, when the first capacitance Cx in the signal path is small, the second capacitance Cc in the cancellation path is small, and the signal path is satisfiedGreater thanUnder the condition of (a), the delays of the signal path and the cancellation path may never be equal, resulting in inaccurate clock synchronization. So thatThe amount of signal for the delay time is reduced by not being set too large.
In the embodiment of the invention, since the voltage comparator is used for replacing the inverter to perform voltage inversion, the inversion point of the voltage comparator can be controlled by the threshold voltage Vref. Compared with the existing inverter, the first voltage comparator comprises two inputs, wherein one input is a threshold voltage Vref and the other input is a reference clock signal after passing through the first capacitor. Compared with the prior inverter, the second voltage comparator comprises two inputs, wherein one input is a threshold voltage Vref and the other input is a reference clock signal after passing through a second capacitor.
The switching point of the first voltage comparator and the switching point of the second voltage comparator may be the same size, and further, the threshold voltage of the first voltage comparator may be equal to the threshold voltage of the second voltage comparator.
In one possible embodiment, the third delayed signal vosc_delay is input to the cancellation path, and the second capacitor Cc in the cancellation path delays the third delayed signal vosc_delay to obtain the second delayed signal vosc_cc output by the cancellation path. The third delay signal vosc_delay is a signal delayed from the signal path, and the third delay signal may be a preset adjustable signal. Compared with the prior art, the second voltage comparator comprises two inputs, one input is a threshold voltage Vref, and the other input is a third delay signal Vosc_delay after passing through the second capacitor. Since the third delay signal is used as the input signal of the cancellation path, unlike the input signal of the signal path, the delay time of the cancellation path is not required to be equal to the delay time of the signal path when the output of the delay locked loop is stable. Therefore, when the output of the delay phase locked loop is stable, the equivalent resistance of the cancellation path is not requiredTo be greater than the equivalent resistance of the signal pathWhen the first capacitance Cx in the signal path is smaller, the second capacitance Cc in the elimination path is even smaller, the situation that the delay of the signal path and the delay of the elimination path cannot be equal can not occur, and the clock synchronization accuracy is improved. Equivalent resistance of the path to be eliminatedEquivalent resistance to signal pathDecoupling and equivalent resistance of signal pathThe delay time signal quantity is enhanced without considering the loop locking range when setting. In addition, the equivalent resistance of the path will be eliminatedEquivalent resistance to signal pathThe decoupling of the first capacitor Cx in the signal path and the second capacitor Cc in the cancellation path may also be performed without covering the range of the value of the first capacitor Cx in the signal path. The second capacitor Cc in the cancellation path, which is formed by the on-chip capacitor, can be reduced, and the size of the second capacitor Cc in the cancellation path is positively related to the chip area. The size of the second capacitor Cc in the elimination path is reduced, so that the area of the chip is reduced, and the cost of the chip is reduced.
Referring to fig. 5, fig. 5 is a flowchart of a method for detecting capacitance based on a delay locked loop according to an embodiment of the present invention, as shown in fig. 5, the method for detecting capacitance based on a delay locked loop includes the following steps:
501. And sequentially carrying out delay processing on the reference clock signal through the first capacitor and the first voltage comparator to obtain a first delay signal.
In an embodiment of the present invention, a delay locked loop-based capacitance detection is applied to a capacitance detection circuit, where the capacitance detection circuit includes: the circuit comprises a main path, a signal path and a cancellation path, wherein the output end of the signal path is electrically connected with the input end of the main path, the output end of the cancellation path is electrically connected with the output end of the main path, the signal path comprises a first capacitor, and the cancellation path comprises a second capacitor. Wherein the main path and the cancellation path form a delay locked loop.
The reference clock signal may be a clock signal generated by a slave clock signal source, and in a clock network, the reference clock signal may include a master clock device and a slave clock device, where the master clock device may send its own system clock as the reference clock signal to the slave clock device, so that the slave clock device and the master clock device have synchronous clocks. The master clock device may be used as a clock signal source. The delay locked loop in the embodiment of the invention can calculate the value of the first capacitor by using the clock synchronization of the slave clock device and the master clock device, and the first capacitor can be a capacitor control device applied to a capacitor control device, such as a capacitor touch screen or a capacitor signal generator.
The delay processing is a process of charging the first capacitor, and since the first capacitor requires time to charge, the reference clock signal generates delay to obtain a first delay signal, and when the size of the first capacitor changes, the charging time also changes, so that the delay time also changes.
Specifically, the signal path includes a first inverter and a first voltage comparator, and a first capacitor is coupled between the first inverter and the first voltage comparator. The reference clock signal is input to the first capacitor through the first inverter, delayed through charging of the first capacitor, and turned over through the first voltage comparator to obtain a first delay signal.
The inversion point of the first voltage comparator is adjusted according to the threshold voltage of the first voltage comparator, and the threshold voltage of the first voltage comparator can be set near the voltage value VDD of the power supply.
Optionally, in the step of sequentially delaying the reference clock signal by the first capacitor and the first voltage comparator to obtain a first delayed signal, the reference clock signal may be delayed by the first capacitor to obtain a first signal to be flipped; when the first signal to be flipped reaches the flipping point of the first voltage comparator, the first signal to be flipped is flipped to obtain a first delay signal.
The first signal to be turned over is an input signal of the first voltage comparator, and when the first signal to be turned over reaches the turning point of the first voltage comparator, the first signal to be turned over is turned over by the first voltage comparator, so that a first delay time is obtained. Since the inversion point of the first voltage comparator can be controlled by the threshold voltage of the first voltage comparator, the threshold voltage of the first voltage comparator can be adjusted to be close to the rising edge end point or the falling edge end point of the first signal to be inverted, and the signal quantity of the delay time can be increased.
Optionally, before the step of sequentially passing the reference clock signal through the first capacitor and the first voltage comparator to perform delay processing to obtain the first delay signal, a rising edge end point of the first capacitor or a falling edge end point of the first capacitor or a voltage value of the power supply source may be used as a point of approach to determine a target turning point of the first voltage comparator; the switching point of the first voltage comparator is adjusted to the target switching point of the first voltage comparator by controlling the threshold voltage of the first voltage comparator.
Specifically, before the capacitance detection is performed on the first capacitor, the threshold voltage of the first voltage comparator can be controlled to adjust the turning point of the first voltage comparator, so that the first voltage comparator works on a better turning point. The rising edge end point of the first capacitor may be understood as a rising edge end point of the first signal to be flipped, where the first signal to be flipped is no longer changed at the rising edge, and the falling edge end point of the first voltage may be understood as a falling edge end point of the first signal to be flipped, where the first signal to be flipped is no longer changed at the falling edge.
The approach point is a signal point at which the turning point is adjusted to approach from the rising edge or the falling edge during the adjustment of the turning point of the first voltage comparator. In the principle of the operation of the inverter, the approach point is set to VDD/2, and in the practical application of the inverter, the inversion point is generally set near VDD/2.
Optionally, before the step of determining the target turning point of the first voltage comparator by using the rising edge end point of the first capacitor or the falling edge end point of the first capacitor or the power supply voltage as the approach point, determining the type of the approach point according to the type of the phase difference detection of the main path, where the type of the approach point includes the rising edge end point of the first capacitor, the falling edge end point of the first capacitor, and the voltage value of the power supply.
Specifically, when the phase difference detection type of the main path is the phase difference of the detected rising edge, the type of the approach point can be the rising edge end point of the first capacitor; when the phase difference detection type of the main path is the phase difference of the detection falling edge, the type of the approach point can be the falling edge end point of the first capacitor; when the rising edge of the first comparator corresponds to the rising edge of the first signal to be flipped, and the phase difference detection type of the main path is to detect the phase difference of the rising edges of the two signals, the type of the approach point may be the voltage value of the power supply.
Optionally, the main path includes a phase frequency detector PFD, a charge pump CP, and an ADC sampler. In the step of determining the type of the approach point according to the phase difference detection type of the main path, when the phase difference of the rising edge is detected by the phase frequency detector PFD, the type of the approach point may be determined as the rising edge end point of the first capacitor; when the phase difference of the falling edge is detected by the phase frequency detector PFD, determining the type of the approach point as the falling edge end point of the first capacitor; when the rising edge of the first voltage comparator corresponds to the rising edge of the reference clock signal and the phase difference of the rising edge is detected by the phase frequency detector PFD, the type of the approach point is determined as the voltage value of the power supply.
In the embodiment of the invention, the type of the approach point is determined according to the phase difference detection type of the main path, and the turning point of the first voltage comparator can be more accurately adjusted, so that the turning point of the first voltage comparator is arranged near the approach point, and the signal quantity of the delay time is improved.
Optionally, in the step of determining the target turning point of the first voltage comparator with the rising edge end point of the first capacitor or the falling edge end point of the first capacitor or the voltage value of the power supply as the approach point, the signal amount of the delay time may be determined; according to the signal quantity of the delay time, adjusting the distance value between the turning point and the approaching point of the first voltage comparator; and determining a target turning point of the first voltage comparator according to the distance value between the turning point and the approaching point of the first voltage comparator.
Specifically, the signal amount of the delay time may be determined according to a specific use environment, for example, the signal amount of the delay time may be set to be larger for a use environment with a high accuracy requirement, and the signal amount of the delay time may be set to be smaller for a use environment with a low accuracy requirement. The threshold voltage corresponding to the turning point can be calculated according to the signal quantity of the delay time, so that the turning point of the first voltage comparator can be adjusted by adjusting the threshold voltage of the first voltage comparator.
In one possible embodiment, the threshold voltage of the first voltage comparator may be manually adjusted by a user, or may be automatically adjusted according to an accuracy gear selected by the user.
Optionally, in the step of determining the target turning point of the first voltage comparator with the rising edge end point of the first capacitor or the falling edge end point of the first capacitor or the voltage value of the power supply as the approach point, the signal amount of the delay time may be determined; according to the signal quantity of the delay time, adjusting the proportion value of the turning point and the approaching point of the first voltage comparator; and determining a target turning point of the first voltage comparator according to the proportional value of the turning point and the approaching point of the first voltage comparator.
Specifically, when the inversion point is aVDD, the above a may represent a ratio value of the inversion point to the voltage value VDD of the power supply, and under a condition that the equivalent resistance is constant, the closer a is to 1, the larger the delay time variation amount is, so that the larger the signal amount of the delay time variation is. It can be further understood that the closer the inversion point aVDD is to the voltage value VDD of the power supply, the larger the delay time variation amount is, so that the larger the delay time variation signal amount is. The signal amount of the delay time may be determined according to a specific use environment or a user use requirement, for example, the signal amount of the delay time may be set to be larger for a use environment or a user use requirement with higher accuracy, and the signal amount of the delay time may be set to be smaller for a use environment or a user use requirement with lower accuracy. The ratio of the turning point to the approach point of the first voltage comparator can be calculated according to the signal quantity of the delay time, so that the threshold voltage corresponding to the turning point is calculated, and the turning point of the first voltage comparator is adjusted by adjusting the threshold voltage of the first voltage comparator.
502. And sequentially passing the input signal of the elimination path and the output signal of the main path at the previous time step through a second capacitor and a second voltage comparator to perform delay processing to obtain a second delay signal.
In the embodiment of the present invention, the input signal of the cancellation path may be a reference clock signal, that is, the input signal of the cancellation path is the same as the input signal of the signal path.
Optionally, the turning point of the second voltage comparator is the same as the turning point of the first voltage comparison, which may be specifically understood that the threshold voltage of the second voltage comparator is equal to the threshold voltage of the first voltage comparator, and the first voltage comparator and the second voltage comparator may be adjusted by the same threshold voltage control signal, so that the first voltage comparator and the second voltage comparator work at the same turning point.
In one possible embodiment, the input signal of the cancellation path may be a third delay signal, where the third delay signal is a delay signal relative to the reference clock signal when the loop is locked in the calibration loop.
The calibration link is a link for performing automatic calibration and delay time calibration before detecting the first capacitor and the second capacitor in the delay locked loop.
The third delay signal is obtained through the calibration link to replace the reference clock signal in the prior art to be used as the input signal of the cancellation path, so that the delay time of the cancellation path is not required to be equal to the delay time of the signal path when the output of the delay phase-locked loop is stable. Therefore, when the output of the delay phase-locked loop is stable, the equivalent resistance of the cancellation path is not required to be larger than that of the signal path, and when the first capacitance in the signal path is smaller, the second capacitance in the cancellation path is even smaller, and the situation that the delay of the signal path and the delay of the cancellation path cannot be equal forever can not occur, so that the accuracy of clock synchronization is improved.
The previous time step refers to the time step corresponding to the previous detection of the first capacitor and the second capacitor, for example, when the first capacitor and the second capacitor are detected at the time t, the output signal of the main channel in the previous time step is the output signal of the main channel at the time t-1.
Specifically, the cancellation path includes a second inverter and a second voltage comparator, and a second capacitor is coupled between the second inverter and the second voltage comparator.
In the process of carrying out delay processing on the input signal of the elimination path and the output signal of the main path in the previous time step through the second capacitor, the output signal of the main path in the previous time step is directly loaded on the second capacitor, the input signal of the elimination path is input to the second capacitor through the second inverter, and the input signal of the elimination path is charged and delayed through the second capacitor loaded with the output signal of the main path in the previous time step, so as to obtain a second delay signal.
The first delay signal corresponding to the previous time step and the second delay signal of the previous time step are simultaneously input to a phase frequency detector PFD of the main channel, input to a charge pump CP after passing through the phase frequency detector PFD, and output signals of the previous time step are sampled and output through an ADC (analog to digital converter) sampler after passing through the charge pump CP.
503. And inputting the first delay signal and the second delay signal into the main channel to obtain an output signal of the main channel at the current time step.
In the embodiment of the invention, the main path includes a phase frequency detector PFD, a charge pump CP, and an ADC sampler. In the current time step, the first delay signal and the second delay signal are input into a main channel, and are input into a phase frequency detector PFD of the main channel at the same time, and are input into a charge pump CP after passing through the phase frequency detector PFD, and are sampled and output through an ADC sampler after passing through the charge pump CP. The output signal of the ADC sampler may be digitally processed and then loaded onto the second capacitor for changing the size of the second capacitor.
504. When the output signal of the main channel at the current time step is stable, the value of the first capacitor is calculated according to the output signal of the current time step.
In the embodiment of the invention, in the phase frequency detector PFD, when the phases of the first delay signal and the second delay signal are the same, the output of the charge pump CP is stable and unchanged, and the output of the ADC sampler is also stable at a certain value, at this time, the delay phase-locked loop is controlled to lock, and the values of the first capacitor and the second capacitor are locked and no longer change, so that the phases of the first delay signal and the second delay signal are no longer changed, and still keep the same phase, thereby completing the synchronization of the clock signals. When the first capacitor is influenced by the outside to change, the specific change amount of the first capacitor can be obtained by analyzing the output signal of the main channel of the current time step, so that the detection of the first capacitor is realized.
Specifically, in the current time step, the first delay signal and the second delay signal are input into the main channel, so as to obtain an output signal of the main channel in the current time step. Since the first capacitor requires time to charge, the reference clock signal is delayed to obtain a first delayed signal, and when the size of the first capacitor is changed, the charging time also changes, and thus the delay time also changes. The first delay signal and the second delay signal pass through the main channel and then output corresponding output signals. The output signal is fed back to control the magnitude of the second capacitance on the cancellation path. When the loop lock stabilizes, the phase of the first delay signal is the same as that of the second delay signal, and the output stability of the main path stabilizes to a certain value. When the output of the main path is stable, the value of the second capacitance of the current time step can be deduced from the output signal of the main path. And the delay time of the cancellation channel is positively correlated with the delay time of the signal path. Therefore, by analyzing the output signal of the main channel, the specific variation of the first capacitor can be obtained, and the detection of the first capacitor is realized.
In the embodiment of the invention, a reference clock signal sequentially passes through the first capacitor and the first voltage comparator to be subjected to delay processing, so as to obtain a first delay signal; the reference clock signal and the output signal of the main channel at the last time step sequentially pass through the second capacitor and the second voltage comparator to be subjected to delay processing, so that a second delay signal is obtained; inputting the first delay signal and the second delay signal into a main channel to obtain an output signal of the main channel at the current time step; and when the output signal of the main channel in the current time step is stable, calculating the value of the first capacitor according to the output signal of the current time step. The first voltage comparator and the second voltage comparator are arranged in the signal path and the elimination path, and the turning points of the first voltage comparator and the second voltage comparator are adjusted, so that the first voltage comparator and the second voltage comparator can work at higher turning points, the signal quantity of delay time can be improved, the locking range is improved, and the accuracy of capacitance detection is further improved.
Meanwhile, in the calibration link, a delay signal relative to a reference clock signal is used as a third delay signal, delay processing is carried out through a second capacitor on the basis of the third delay signal and an output signal of the previous time step, the second delay signal is obtained, the second delay signal and the first delay signal are input into a main channel together to obtain a current time step output signal, the change value of the first capacitor and the change value of the second capacitor are calculated according to the output signal of the current time step, the first capacitor and the second capacitor can be adjusted according to the change value of the first capacitor and the change value of the second capacitor, and compared with the prior art, the delay processing is carried out by using the third delay signal to replace the output signal of the reference clock signal and the output signal of the previous time step, so that inaccurate clock synchronization caused by using the reference clock signal is avoided, and the clock synchronization accuracy of the delay phase-locked loop is improved.
Optionally, before the step of delaying the third delay signal and the output signal of the main channel in the previous time step by using the second capacitor to obtain the second delay signal, the delay phase-locked loop may be calibrated, and in the calibration link, when the loop is locked, the delay signal of the reference clock signal is obtained as the third delay signal.
In the embodiment of the invention, before the first capacitor and the second capacitor in the delay locked loop are formally detected, the delay locked loop can be automatically calibrated and the delay time is calibrated to determine the delay time of the third delay signal relative to the reference clock signal when the loop is locked.
The third delay signal is a delay time obtained by adding the automatic calibration and the delay time calibration to the reference clock signal. In the embodiment of the invention, the delay phase-locked loop can be helped by a proper third delay signal, so that the output signal of the main channel can reach a stable state rapidly when the first capacitor and the second capacitor are formally detected, and the locking speed of the loop is improved.
Optionally, in the step of acquiring the delay signal of the reference clock signal as the third delay signal in the calibration step when the loop is locked, a target operating point of the loop locking may be set; when the loop is locked at the target operating point, the delayed signal of the reference clock signal is acquired as the second delayed signal.
In the embodiment of the invention, the target operating point of loop locking refers to an operating point when the delay locked loop is stable, specifically, in the phase frequency detector PFD, when the phases of the first delay signal and the second delay signal are the same, the output of the charge pump CP is stable and unchanged, and the output of the ADC sampler is also stable at a certain value, where the certain value is the operating point when the delay locked loop is stable, at this time, the delay locked loop is controlled to lock, the values of the first capacitor and the second capacitor are locked and are not changed any more, and then the phases of the first delay signal and the second delay signal are not changed any more, and the same phase is still maintained, so that the synchronization of the clock signal at the operating point is completed.
In the calibration link, the delay phase-locked loop can be automatically calibrated and delay time calibrated to determine the working point of the delay phase-locked loop when the loop is locked as a target working point, and at the moment, the acquired delay time is added with the reference clock signal to obtain the delay signal of the reference clock signal as a third delay signal. When the capacitor detection is performed on the delay locked loop formally, the delay locked loop can be locked at a target working point rapidly through the third delay signal delay locked loop, so that the locking speed of the delay locked loop is improved.
Optionally, in the step of setting the target operating point of loop locking, the target operating point of loop locking may be determined by a preset search method.
In the embodiment of the invention, the preset searching method can be a binary searching method or a traversal searching method, preferably a binary searching method, specifically, an ordered list of delay time can be preset, and the proper delay time is searched in the ordered list by the binary searching method, so that the delay phase-locked loop performs loop locking on a better working point. The delay time searching is carried out on the ordered list of delay time by the binary searching method, and the method has the advantages of less comparison times, high searching speed, good average performance and less occupied system memory.
In the embodiment of the invention, the delay time in the above-mentioned ordered list can be arranged according to ascending order, the delay time recorded in the middle position of the list is used for the calibration link, if the delay phase-locked loop performs loop locking on the same working point, the search is successful; otherwise, dividing the table into a front sub-table and a rear sub-table by using the intermediate position record, if the working point of the delay time recorded by the intermediate position record is larger than the working point of the delay phase-locked loop in the calibration link, searching the front sub-table further, otherwise, searching the rear sub-table further. The above process is repeated until a delay time satisfying the condition is found, so that the search is successful, or until the sub-table does not exist, at which time the search is unsuccessful. When the search is unsuccessful, the delay time closest to the working point of the delay phase-locked loop in the calibration link can be selected to be added with the reference clock signal, a third delay signal is obtained, and then the target working point locked by the loop in the calibration link is determined through the third delay signal.
In the embodiment of the invention, the voltage value VDD of the power supply, in the calibration link, delays the operating point of the phase-locked loop by a target operating point when the loop is locked and the voltage value of the third capacitor is close to VDD. And calculating the delay time of the delay phase-locked loop under the target working point, and adding the delay time and the reference clock signal to obtain a third delay signal. When the first capacitor and the second capacitor in the delay phase-locked loop are detected, the delay time obtained by the calibration link is added with the reference clock signal, so that the delay phase-locked loop can be helped to be quickly stabilized.
Optionally, the main path includes a third capacitor, and in the step of setting the target operating point of the loop locking, the voltage value of the third capacitor may be analyzed according to the voltage value of the power supply, with the signal quantity being improved as a target; and determining a target working point of loop locking according to the voltage value of the third capacitor.
In the embodiment of the invention, the signal quantity is the signal quantity of the delay time, and the data of the delay phase-locked loop with the same structure can be used for carrying out big data analysis to analyze the relationship among the voltage value of the third capacitor, the voltage value of the power supply and the signal quantity of the delay time, so as to find the optimal voltage value of the third capacitor with the maximum signal quantity of the delay time, and the voltage value of the third capacitor is at the optimal voltage value when the delay phase-locked loop is locked in the loop in the calibration link. The delay time obtained by the calibration link is added with the reference clock signal, so that the delay phase-locked loop can be helped to quickly stabilize.
Optionally, in the step of acquiring the delay signal of the reference clock signal as the third delay signal when the loop is locked at the target operating point, a plurality of candidate delay times may be obtained by adjusting the value of the first capacitor and the value of the second capacitor; determining a target candidate delay time from a plurality of candidate delay times according to the loop locking at the target operating point; a third delay signal is determined based on the target candidate delay time and the reference clock signal.
In the embodiment of the invention, when the value of the first capacitor changes, the value of the second capacitor can be adjusted through the change of the output signal of the main channel, so that the loop is locked. In the calibration link, after the target working point is determined, the delay phase-locked loop can be locked at different working points by adjusting the value of the first capacitor and the value of the second capacitor, and at the moment, a plurality of candidate delay times can be obtained. When the delay phase-locked loop performs loop locking at a target working point, determining the delay time as target candidate delay time. The target candidate delay time and the reference clock signal may be added to obtain a second delay signal. The delay time obtained by the calibration link is added with the reference clock signal, so that the delay phase-locked loop can be helped to quickly stabilize.
Optionally, in the step of obtaining a plurality of candidate delay times by adjusting the value of the second capacitor, a current usage environment parameter in the target delay locked loop may be obtained; according to the current use environment parameters, the change value of the historical first capacitor and the change value of the historical second capacitor of the reference delay phase-locked loop are obtained, and the reference delay phase-locked loop and the target delay phase-locked loop have the same circuit structure and the same use environment parameters; predicting the initial value of the first capacitor and the initial value of the second capacitor of the target delay phase-locked loop according to the change value of the historical first capacitor and the change value of the historical second capacitor; and obtaining a plurality of candidate delay times by adjusting the initial value of the first capacitor and the initial value of the second capacitor.
In the embodiment of the present invention, the current usage environment parameter may be a working condition to which the delay locked loop is applied, such as a working frequency, a working temperature, a master clock device parameter, a slave clock device parameter, and the like.
After the change value of the historical first capacitor and the change value of the historical second capacitor of the reference delay phase-locked loop are obtained, the initial value of the first capacitor and the initial value of the second capacitor of the target delay phase-locked loop can be predicted through the change value of the historical first capacitor and the change value of the historical second capacitor. Specifically, the change value of the historical first capacitor and the change value of the historical second capacitor can be input into a pre-trained first timing network prediction, and an initial value of the first capacitor and an initial value of the second capacitor of the target delay phase-locked loop are preset.
Because the reference delay phase-locked loop and the target delay phase-locked loop have the same circuit structure and the same use environment parameters, the reference delay phase-locked loop and the target delay phase-locked loop have similar working parameters, the initial value of the first capacitor and the initial value of the second capacitor of the target delay phase-locked loop are predicted by the change value of the historical first capacitor and the change value of the historical second capacitor, and the delay phase-locked loop can be helped to be fast and stable in a calibration link by adjusting the initial value of the first capacitor and the initial value of the second capacitor, so that the delay phase-locked loop is helped to be fast locked.
Optionally, in the step of acquiring the delay signal of the reference clock signal as the third delay signal when the loop is locked at the target operating point, a current usage environment parameter in the target delay locked loop may be acquired; according to the current use environment parameters, acquiring the historical delay time of a reference delay phase-locked loop, wherein the reference delay phase-locked loop and the target delay phase-locked loop have the same circuit structure and the same use environment parameters; according to the historical delay time, predicting the delay time of the target delay phase-locked loop through a pre-trained prediction network to obtain a predicted delay time; the predicted delay time is taken as the initial delay time, and the value of the second capacitor is adjusted to obtain a plurality of candidate delay times; determining target candidate delay time from a plurality of candidate delay times or initial delay time according to the condition that the loop is locked at the target working point; a third delay signal is determined based on the target candidate delay time and the reference clock signal.
In the embodiment of the present invention, the current usage environment parameter may be a working condition to which the delay locked loop is applied, such as a working frequency, a working temperature, a master clock device parameter, a slave clock device parameter, and the like.
After the historical delay time of the reference delay locked loop is obtained, the predicted delay time of the target delay locked loop can be predicted through the historical delay time. Specifically, the change value of the historical first capacitor and the change value of the historical second capacitor can be input into a pre-trained second time sequence network prediction, and the predicted delay time of the target delay phase-locked loop is preset.
Because the reference delay phase-locked loop and the target delay phase-locked loop have the same circuit structure and the same use environment parameters, the reference delay phase-locked loop and the target delay phase-locked loop have similar working parameters, the predicted delay time of the target delay phase-locked loop is predicted by historical delay time, the predicted delay time is added with the reference signal to obtain a predicted third delay signal, and the delay phase-locked loop can be helped to be fast and stable in a calibration link through the predicted third delay signal, so that the delay phase-locked loop is helped to be fast locked.
After the calibration link is finished, when the changes of the first capacitor and the second capacitor in the delay phase-locked loop are formally detected, the change value of the first capacitor and the change value of the second capacitor can be calculated according to the output signal of the current time step, and the first capacitor and the second capacitor can be adjusted according to the change value of the first capacitor and the change value of the second capacitor, so that the delay phase-locked loop performs loop locking. In the embodiment of the invention, the delay time obtained during automatic calibration is added with the reference clock signal to obtain the third delay signal, which can help the delay phase-locked loop to be fast and stable, thereby helping the delay phase-locked loop to be fast locked. When the first capacitor is detected to change, the output signal of the main channel also changes, and the second capacitor is adjusted according to the change of the output signal of the main channel, so that the output of the delay phase-locked loop is stabilized again, and the delay phase-locked loop is locked.
In the embodiment of the present invention, it should be noted that, the input signal of the cancellation channel has a delay with respect to the input signal of the signal channel, that is, there is a delay time between the third delay signal and the reference clock signal, and the delay time is determined in a calibration link before the formal capacitance detection.
The embodiment of the invention also provides a computer storage medium, wherein the computer storage medium stores a computer program for electronic data exchange, and the computer program makes a computer execute part or all of the steps of any one of the capacitance detection optimization methods based on delay locked loops described in the embodiment of the method.
The embodiment of the present invention also provides an electronic device, which includes a non-transitory computer-readable storage medium storing a computer program, where the computer program is operable to cause a computer to perform part or all of the steps of any one of the delay locked loop-based capacitance detection methods described in the above method embodiments.
It should be noted that, for simplicity of description, the foregoing method embodiments are all described as a series of acts, but it should be understood by those skilled in the art that the present invention is not limited by the order of acts described, as some steps may be performed in other orders or concurrently in accordance with the present invention. Further, those skilled in the art will also appreciate that the embodiments described in the specification are alternative embodiments, and that the acts and modules referred to are not necessarily required for the present invention.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and for parts of one embodiment that are not described in detail, reference may be made to related descriptions of other embodiments.
In the several embodiments provided by the present application, it should be understood that the disclosed apparatus may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, such as the division of the units, merely a logical function division, and there may be additional manners of dividing the actual implementation, such as multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, or may be in electrical or other forms.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in the embodiments of the present invention may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units described above may be implemented either in hardware or in software program modules.
The integrated units, if implemented in the form of software program modules, may be stored in a computer-readable memory for sale or use as a stand-alone product. Based on such understanding, the technical solution of the present invention may be embodied essentially or partly in the form of a software product or all or part of the technical solution, which is stored in a memory, and includes several instructions for causing a computer device (which may be a single-chip microcomputer, a personal computer, a server or a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned memory includes: a usb disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a removable hard disk, a magnetic disk, or an optical disk, or other various media capable of storing program codes.
The foregoing has outlined rather broadly the more detailed description of embodiments of the invention, wherein the principles and embodiments of the invention are explained in detail using specific examples, the above examples being provided solely to facilitate the understanding of the method and core concepts of the invention; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in accordance with the ideas of the present invention, the present description should not be construed as limiting the present invention in view of the above.
Claims (10)
1. A capacitance detection method based on a delay locked loop, which is characterized by being applied to a capacitance detection circuit, wherein the capacitance detection circuit comprises: the signal path comprises a first capacitor and a first voltage comparator, the cancellation path comprises a second capacitor and a second voltage comparator, the turning point of the first voltage comparator is adjusted according to the threshold voltage of the first voltage comparator, and the turning point of the second voltage comparator is adjusted according to the threshold voltage of the second voltage comparator, and the method comprises the following steps:
Sequentially passing the reference clock signal through the first capacitor and the first voltage comparator to perform delay processing to obtain a first delay signal;
the input signal of the elimination path and the output signal of the main path at the last time step sequentially pass through the second capacitor and the second voltage comparator to be subjected to delay processing, so as to obtain a second delay signal;
Inputting the first delay signal and the second delay signal into a main channel to obtain an output signal of the main channel at the current time step;
and when the output signal of the main channel in the current time step is stable, calculating the value of the first capacitor according to the output signal of the current time step.
2. The delay locked loop-based capacitance detection method as claimed in claim 1, wherein said step of sequentially passing the reference clock signal through the first capacitor and the first voltage comparator to perform delay processing to obtain a first delay signal comprises:
delay processing is carried out on the reference clock signal through the first capacitor, and a first signal to be turned over is obtained;
and when the first signal to be flipped reaches the flipping point of the first voltage comparator, flipping the first signal to be flipped to obtain a first delay signal.
3. The delay locked loop-based capacitance detection method as claimed in claim 1, wherein said step of sequentially passing said input signal of said cancellation path and said output signal of said main path at a previous time step through said second capacitor and said second voltage comparator to perform delay processing to obtain a second delay signal comprises:
Loading the output signal of the main channel in the last time step to the second capacitor, and carrying out delay processing on the input signal of the elimination channel through the second capacitor loaded with the output signal of the main channel in the last time step to obtain a second signal to be overturned;
And when the second signal to be overturned reaches the overturned point of the second voltage comparator, the second signal to be overturned is overturned, and a second delay signal is obtained.
4. The delay locked loop-based capacitance detection method according to claim 1, wherein before the step of sequentially passing the reference clock signal through the first capacitor and the first voltage comparator to perform delay processing to obtain a first delay signal, the method further comprises:
Determining a target turning point of the first voltage comparator by taking a rising edge end point of the first capacitor or a falling edge end point of the first capacitor or a voltage value of a power supply as a nearby point;
and adjusting the turning point of the first voltage comparator to the target turning point of the first voltage comparator by controlling the threshold voltage of the first voltage comparator.
5. The delay locked loop-based capacitance detection method of claim 4, wherein before the step of determining the target flip point of the first voltage comparator with the rising edge end of the first capacitance or the falling edge end of the first capacitance or the power supply voltage as a point of approach, the method further comprises:
determining the phase difference detection type of the main path;
And determining the type of the approach point according to the phase difference detection type of the main path, wherein the type of the approach point comprises a rising edge end point of the first capacitor, a falling edge end point of the first capacitor and a voltage value of the power supply.
6. The delay locked loop-based capacitance detection method of claim 5, wherein the main path comprises a phase frequency detector, and wherein the step of determining the type of the approach point based on the phase difference detection type of the main path comprises:
when the phase frequency detector detects the phase difference of the rising edge, determining the type of the approach point as the rising edge end point of the first capacitor;
When the phase frequency detector detects a phase difference of a falling edge, determining the type of the approach point as a falling edge end point of the first capacitor;
when the rising edge of the first voltage comparator corresponds to the rising edge of the reference clock signal and the phase difference of the rising edge is detected by the phase frequency detector, the type of the approaching point is determined to be the voltage value of the power supply.
7. The delay locked loop-based capacitance detection method of claim 6, wherein determining the target flip point of the first voltage comparator with a rising edge end of the first capacitance or a falling edge end of the first capacitance or a power supply voltage as a close point comprises: determining a semaphore for the delay time;
According to the signal quantity of the delay time, adjusting the distance value between the turning point of the first voltage comparator and the approaching point;
and determining a target turning point of the first voltage comparator according to the distance value between the turning point of the first voltage comparator and the approaching point.
8. The delay locked loop-based capacitance detection method of claim 6, wherein determining the target flip point of the first voltage comparator with a rising edge end of the first capacitance or a falling edge end of the first capacitance or a power supply voltage as a close point comprises:
determining a semaphore for the delay time;
According to the signal quantity of the delay time, adjusting the proportion value of the turning point of the first voltage comparator to the approaching point;
And determining a target turning point of the first voltage comparator according to the ratio value of the turning point of the first voltage comparator to the approaching point.
9. The delay locked loop-based capacitance detection method as claimed in any one of claims 1 to 8, wherein a flip point of the first voltage comparator is the same as a flip point of the second voltage comparator, and a threshold voltage of the first voltage comparator and a threshold voltage of the second voltage comparator are adjusted by the same adjustment signal.
10. A capacitance detection circuit, the capacitance detection circuit comprising: a main path, a signal path, and a cancellation path, the output end of the signal path is electrically connected with the first input end of the main path, the output end of the cancellation path is electrically connected with the second input end of the main path, the input end of the cancellation path is electrically connected with the output end of the main path so that the main path and the cancellation path form a delay locked loop, wherein the signal path comprises a first capacitor and a first voltage comparator, the cancellation path comprises a second capacitor and a second voltage comparator, the inversion point of the first voltage comparator is adjusted according to the threshold voltage of the first voltage comparator, the inversion point of the second voltage comparator is adjusted according to the threshold voltage of the second voltage comparator, and the capacitance detection circuit is used for realizing the steps in the delay locked loop-based capacitance detection method as claimed in any one of claims 1 to 8.
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| PCT/CN2023/121579 WO2024067590A1 (en) | 2022-09-28 | 2023-09-26 | Capacitance measurement method based on delay phase-locked loop and capacitance measurement circuit |
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| CN115575719B (en) * | 2022-09-28 | 2024-05-28 | 深圳曦华科技有限公司 | Capacitor detection method and capacitor detection circuit based on delay phase-locked loop |
| CN115616294B (en) * | 2022-09-28 | 2024-05-28 | 深圳曦华科技有限公司 | Capacitor detection method and capacitor detection circuit based on delay phase-locked loop |
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