CN115567014A

CN115567014A - Multi-input low-noise amplifier architecture circuit

Info

Publication number: CN115567014A
Application number: CN202210605648.6A
Authority: CN
Inventors: 王靖
Original assignee: Individual
Current assignee: Individual
Priority date: 2022-05-31
Filing date: 2022-05-31
Publication date: 2023-01-03

Abstract

The invention discloses a multi-input low-noise amplifier architecture circuit, which comprises a low-noise amplifier; a power management module; the input matching circuit comprises a plurality of first switches connected in parallel, a plurality of inductors connected in series and second switches respectively connected in parallel to the inductors, wherein an inductor L0 is an input end inductor, an inductor Ln is an output end inductor, the input side of the input end inductor L0 is connected with a variable capacitor array C0array, and the output side of the output end inductor Ln is connected with the variable capacitor array C1array and then connected to the input end of the low noise amplifier; the output resonant network is connected with the output end of the low-noise amplifier and the input end of the power management module; the input matching circuit greatly reduces the number of matching elements, saves cost and pcb area, and is more effective in writing under the condition of area constraint.

Description

Multi-input low-noise amplifier architecture circuit

Technical Field

The invention belongs to the technical field of wireless communication, and particularly relates to a multi-input low-noise amplifier architecture circuit.

Background

With the development of communication technology, various communication modes appear to improve data transmission rate, different countries and regions divide a large number of different carrier frequency bands, and in order to meet these situations, a wireless system often needs to integrate an amplifier unit capable of processing many frequency bands on one chip, and finally select one or more frequency bands for output at an output end. The processing unit meeting the requirements is complicated, input and output matching is complicated, matching components become very many, a large amount of space is occupied, system cost is increased, signal paths are reasonably planned, a part of circuits are shared, and complexity of circuit design can be reduced.

As shown in fig. 1 to fig. 6, in order to implement multi-mode communication, a large number of components and circuits are provided, the system is complex, and there are limitations in terms of gain and bandwidth, and the fusion of various communication modes such as 2g,3g,4g, and 5g also greatly broadens the signal bandwidth processed by the communication system circuit, and if each frequency band is independently matched for input and output, the circuit system is very complex. It is important to extend the bandwidth of the amplifier so that it can amplify a wider bandwidth signal.

Along with the reduction of the characteristic size, on one hand, the intrinsic gain of a transistor is reduced, so that the gain of an LNA is reduced, on the other hand, the input and output isolation is also reduced, so that the input and output are influenced mutually, when one-stage LNA cannot meet the gain requirement, a plurality of stages of LNAs are needed to improve the gain, but because the input matching requirement, the noise coefficient requirement and the output high-power linearity are required to be met, generally, the output load of the two stages of LNAs is realized by adopting an RLC parallel structure, at the moment, the two stages of LNAs are equivalent to two-stage filters, so that the effective bandwidth of the two stages of LNAs is greatly reduced, under the condition, the multi-stage LNA framework which can meet the requirements of the gain, the linearity, the noise coefficient and the matching performance and does not reduce the effective bandwidth is particularly important, and the gain attenuation range of the multi-stage LNA can be better planned.

Disclosure of Invention

The invention aims to provide a multi-input low-noise amplifier architecture circuit to solve the problems that in the prior art, a matching circuit is multiple in components, large in occupied space and high in system cost.

In order to achieve the purpose, the invention adopts the technical scheme that: a multiple input low noise amplifier architecture circuit includes a low noise amplifier; a power management module; the input matching circuit comprises a plurality of first switches connected in parallel, a plurality of inductors connected in series and second switches respectively connected in parallel on the inductors, wherein an inductor L0 is an input end inductor, an inductor Ln is an output end inductor, the input side of the input end inductor L0 is connected with a variable capacitor whole column C0array, and the output side of the output end inductor Ln is connected with the input end of the low noise amplifier after being connected with a variable capacitor whole column C1 array; and the output resonant network is connected between the output end of the low-noise amplifier and the input end of the power management module.

Further, the input matching circuit further comprises a third switch incorporated at the second switch node, or a combination of a fourth switch and a third inductor incorporated, or a third capacitance incorporated.

Further, the low noise amplifier comprises a stacked transistor formed by sequentially and parallelly stacking a plurality of transistors and a diode array connected to the stacked transistor, wherein the diode array is an array of one diode or an array formed by serially connecting a plurality of diodes and connected to two ends of a collector and an emitter of each transistor in the stacked transistor in parallel.

Further, the low noise amplifiers are at least two and are connected in series.

Further, the diode connection of the diode array parallel to the emitter of each transistor in the stacked transistors is node 1, 2, \8230, n-1, and a current source is arranged at one or more of the nodes 1, 2, \8230, and n-1.

Further, the output resonant network comprises;

the inductor Ld1 is connected with the input end of the power management module and the output end of the low-noise amplifier;

a capacitor Cd1 connected in parallel to the inductor Ld1;

a resistor Rd1 connected in parallel to the inductor Ld1;

further, the output resonant network includes: the first transistor Qp11 and the second transistor Qp22 are connected between the input end of the power management module and the output end of each low noise amplifier;

a first inductor Ld11 connected in parallel to the first transistor Qp11;

a first capacitor Cd11 connected in parallel to the first transistor Qp11;

a first resistor Rd11 connected in parallel to the first transistor Qp11;

a second inductor Ld22 connected in parallel to the second transistor Qp22;

a second capacitor Cd22 connected in parallel to the second transistor Qp22;

a second resistor Rd22 connected in parallel to the second transistor Qp22;

further, the power management module PMU is a linear low dropout regulator LDO or a pass switch SW or a BOOST DC converter BOOST DC-DC or a BUCK DC converter BUCK DC-DC.

The invention has the beneficial effects that:

1. the input matching circuit greatly reduces the number of matching elements, saves cost and pcb area, and is more effective in writing under the condition of area constraint.

2. By improving the output network, the bandwidth of the frequency selection network is expanded, the equivalent output impedance of the frequency selection network is increased, and the signal bandwidth is expanded and the LNA gain is improved.

3. The different injection currents at the diode connections of the diode array with which the emitter of each transistor is in parallel in the stacked transistors can improve circuit gain without affecting the noise figure.

4. The LNA power supply scheme is planned, and a new power supply management module is provided to meet the special requirements of different characteristics on the power supply, so that the characteristics of the LNA power supply scheme reach the optimal value.

Drawings

FIG. 1 is a conventional single input LNA array and matching;

FIG. 2 is a conventional single input LNA architecture;

FIG. 3 is a schematic diagram of a conventional input matching and input signal planning circuit for a low noise amplifier architecture;

FIG. 4 is a schematic diagram of an alternative input matching and input signal planning circuit for a conventional LNA circuit;

FIG. 5 is a schematic diagram of a transconductance stage of the LNA circuit of FIG. 4;

FIG. 6 is an inventive block diagram of a common output circuit of the low noise amplifier block circuit of FIG. 4;

FIG. 7 is a circuit diagram of a multiple-input low noise amplifier architecture according to the present invention;

FIG. 8 is a diagram illustrating matching inductor topology for optimal band selection according to the present invention in FIG. 7;

FIG. 9 is a circuit schematic of a low noise amplifier;

FIG. 10 is a circuit schematic of a low noise amplifier implementing a bandwidth extended secondary amplifier;

fig. 11 is a schematic diagram of a circuit for implementing gain enhancement by a low noise amplifier.

Detailed Description

The present invention is described in further detail below with reference to the attached drawing figures.

As shown in fig. 7, a multiple input low noise amplifier architecture circuit includes a low noise amplifier; the input matching circuit comprises a plurality of first switches K11-K1n connected in parallel, a plurality of inductors L0-Ln connected in series and second switches K21-K2n respectively connected in parallel to the inductors L1-Ln, wherein the inductor L0 is an input end inductor, the inductor Ln is an output end inductor, the input side of the input end inductor L0 is connected with a variable capacitor array C0array, and the output side of the output end inductor Ln is connected with the input end of a low noise amplifier after being connected with the variable capacitor array C1 array; the input signal N1/IN 2/\ 8230, INn respectively passes through the selection of a first switch K11/K12/. Once/K1N and then passes through a matching network L0-C0 and L1-K21, L2-K22, \ 8230, the Ln-K2N is matched and then enters an LNA, according to the frequency range of the input signal, the number of L1-K21, L2-K22, \ 8230, ln-K2N and the on-off number of the switches K21/K22/. Once/K2N can be flexibly selected, so that the number of components is minimum, and if all the input signal frequencies are the same, only two components L0-C0 are needed; if the frequency range of the input signal is 2 frequency ranges, only L1-K21 needs to be added; if the frequency range of the input signal is 3 frequency ranges, only L2-K22 is needed to be added; and so on. In general applications, the frequency bands of the input signals of each LNA are substantially the same or the number of the frequency bands is much smaller than the number of the input signal paths, so that the number of matching elements can be greatly reduced by the matching method.

Fig. 8 is a matching inductance collocation topology framework of fig. 7 when optimizing band selection, which improves circuit characteristics, and when the LNA input frequency band is more, there are more switches that need to be simultaneously closed or opened in fig. 8, so as to affect matching and noise characteristics, at this time, we determine a suitable position at the second switch K21-K2n node according to the specific actual requirements of the circuit and incorporate the corresponding third switch Kqp, or incorporate the combination of the fourth switch Kxy and the third inductance Lxy, or incorporate the third capacitance Cs at the node to improve the above characteristics.

As shown in fig. 9, the low noise amplifier includes a plurality of transistors Q1 to Qn, bias voltages Vb1 to Vbn, a bias resistor R1n, an input blocking capacitor C1n, an inductor Ls, a transistor array D1A to dnas connected in parallel to both collector and emitter ends of two adjacent transistors of the plurality of transistors Q1 to Qn stacked in parallel, a base of each transistor of the plurality of transistors Q1 to Qn stacked in parallel is connected to the bias voltage Vb1 to Vbn, the transistor Q1 of the plurality of transistors Q1 to Qn stacked in parallel is an output transistor, the transistor Qn is an input transistor, an emitter and a collector between two adjacent stacked transistors between the input transistor and the output transistor are connected, an input signal is connected to one end of the input blocking capacitor C1n, the other end of the input blocking capacitor C1n is connected to one end of the bias resistor R1n and then connected to a base of the transistor Qn, an emitter of the transistor Qn is connected to one end of the inductor Ls, the other end of the inductor Vin, a collector of the transistor Qn is connected to one end of the adjacent transistor Q1, a collector of the transistor Q1 is connected to an output network transistor Q1, a collector of the transistor Q1 n is connected to an emitter of the adjacent transistor Q1 is connected to one end of the inductor Ls, a collector of the transistor array is connected to a single resonant diode array, and a diode array of the plurality of the resonant diode array are connected in series.

As shown in fig. 10, two low noise amplifiers are connected in series, the bandwidth of the circuit can be expanded through a series of circuit changes, two transistors Qp11 and Qp22 are added to the circuit of the low noise amplifier shown in fig. 8 to provide dc bias current, and an inductor with a high Q value in a conventional circuit is replaced by an inductor Ld11 or Ld22 with a low or very low Q value, so that the bandwidth of two stages of LNAs can be greatly expanded, and one or two sets of the inductors Ld11/Cd11 and Ld22/Cd22 can be removed without consuming too much to the voltage margin of the collector of Q11 and Q21 due to the inductor with a low Q value, thereby further greatly expanding the bandwidth of the circuit, and the LC resonant network formed by the high Q value L has to be used as a load because no two transistors Qp11 and Qp22 provide dc bias current in the conventional LNA circuit, thereby reducing the bandwidth.

As shown in FIG. 11, the circuit gain can be improved without affecting the noise figure by injecting current at different nodes, the junction of the emitter of each transistor and the diode of the diode array connected in parallel in the stacked transistors is node 1, 2, \8230;, n-1, and one or more nodes of node 1, 2, \8230;, n-1 are provided with current sources, so that under the condition that the total current of the amplifier is not changed, the current flowing through Q1, Q2, \8230;, qn-1 is reduced, so that the intrinsic gain of the devices is increased, the gain of the whole LNA is increased, meanwhile, the Rd1 value can be further increased due to the reduction of the current flowing through Q1 without affecting the output voltage margin, the total gain is further increased, and the transconductance of the Qn-1 tube is not changed due to the unchanged, so that the noise and the input matching characteristics are not affected.

In fig. 9 and 10, a power management module PMU is a power plan required by an LNA, and is configured to provide power to an amplifier and an output resonant network in a reasonable power management module form according to the lamination condition and efficiency requirement of the amplifier, so that the LNA module is not limited to a specific system voltage value, and can flexibly configure and select a voltage value according to the requirement of the LNA module to make the characteristic of the LNA module reach an optimal value, so that the characteristic of the LNA module reaches the optimal value, and the system power supply module can select a through switch SW mode when the voltage value of the system is appropriate, and can select a linear low dropout regulator to step down or select a BUCK DC converter to step down the BUCK DC-DC converter to not affect the efficiency when the voltage value of the system is too large, and can use a BOOST DC-DC converter to BOOST when the voltage value of the system is too low, and these modules can use common circuit modules.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A multiple-input low noise amplifier architecture circuit, characterized by: comprises that

A low noise amplifier; a power management module;

the input matching circuit comprises a plurality of first switches (K11-K1 n) connected in parallel, a plurality of inductors (L0-Ln) connected in series and second switches (K21-K2 n) respectively connected in parallel to the inductors (L1-Ln), wherein the inductor (L0) is an input end inductor, the inductor (Ln) is an output end inductor, the input side of the input end inductor (L0) is connected with a variable capacitor array (C0 array), and the output side of the output end inductor (Ln) is connected with the input end of a low noise amplifier after being connected with the variable capacitor array (C1 array);

and the output resonant network is connected between the output end of the low-noise amplifier and the input end of the power management module.

2. A multiple-input low noise amplifier architecture circuit according to claim 1, wherein: the input matching circuit further comprises a third switch (Kqp) incorporated at the node of the second switch (K21-K2 n), or a combination of a fourth switch (Kxy) and a third inductance (Lxy) incorporated, or a third capacitance (Cs) switched in.

3. A multiple-input low noise amplifier architecture circuit according to claim 1 or 2, wherein: the low-noise amplifier comprises stacked transistors and a diode array, wherein the stacked transistors are sequentially overlapped in parallel through a plurality of transistors, the diode array is connected onto the stacked transistors, and the diode array is an array of a diode or an array formed by connecting a plurality of diodes in series, and the diode array is connected to two ends of a collector and an emitter of each transistor in the stacked transistors in parallel.

4. A multiple-input low noise amplifier architecture circuit according to claim 3, wherein: the low noise amplifiers are at least two and are connected in series.

5. A multiple-input low noise amplifier architecture circuit according to claim 3, wherein: the diode junction of the diode array of each transistor in the stacked transistors, with the emitter of the transistor in parallel with the transistor, is node 1, 2, \\ 8230, n-1, with a current source at one or more of nodes 1, 2, \ 8230, n-1.

6. A multiple-input low noise amplifier circuit according to claim 3, wherein: the output resonant network comprises;

the inductor (Ld 1) is connected with the input end of the power management module and the output end of the low noise amplifier;

a capacitor (Cd 1) connected in parallel to the inductor (Ld 1);

and a resistor (Rd 1) connected in parallel to the inductor (Ld 1).

7. A multiple-input low noise amplifier architecture circuit according to claim 4, wherein: the output resonant network includes:

the circuit comprises a first transistor (Qp 11), a second transistor (Qp 22), a first inductor (Ld 11), a second inductor (Ld 22), a first capacitor (Cd 11), a second capacitor (Cd 22), a first resistor (Rd 11) and a second resistor (Rd 22);

the first transistor (Qp 11) and the second transistor (Qp 22) are connected between the input end of the power management module and the output end of each low noise amplifier;

a first inductor (Ld 11) connected in parallel to the first transistor (Qp 11);

a first capacitor (Cd 11) connected in parallel to the first transistor (Qp 11);

a first resistor (Rd 11) connected in parallel to the first transistor (Qp 11);

a second inductor (Ld 22) connected in parallel to the second transistor (Qp 22);

a second capacitor (Cd 22) connected in parallel to the second transistor (Qp 22);

and a second resistor (Rd 22) connected in parallel to the second transistor (Qp 22).

8. A multiple-input low noise amplifier architecture circuit according to claim 1, wherein: the power management module (PMU) is a linear low dropout regulator (LDO), a through Switch (SW), a BOOST direct current converter (BOOST DC-DC) or a BUCK direct current converter (BUCK DC-DC).