CN115566069A

CN115566069A - Semiconductor structure

Info

Publication number: CN115566069A
Application number: CN202210945046.5A
Authority: CN
Inventors: 朱家宏; 梁顺鑫; 张旭凯; 陈姿蓓; 林侃儒; 张阡; 黄鸿仪; 王菘豊
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2021-08-27
Filing date: 2022-08-08
Publication date: 2023-01-03
Also published as: TW202312498A; US12002867B2; US20230068965A1

Abstract

The present disclosure describes a semiconductor structure. The semiconductor structure may include a substrate, a gate structure on the substrate, a dielectric material layer on the gate structure, a source/drain (S/D) contact layer formed through and adjacent to the gate structure, and a trench conductive layer on and in contact with the source/drain (S/D) contact layer. The source/drain (S/D) contact layer may comprise a platinum group metal material layer and a silicide layer formed between the substrate and the platinum group metal material layer. A top width of the top of the platinum group metal material layer may be greater than or substantially equal to a bottom width of the bottom of the platinum group metal material layer.

Description

Semiconductor structure

Technical Field

Embodiments of the present invention relate to semiconductor technology, and more particularly, to a semiconductor structure and a method for forming the same.

Background

Advances in semiconductor technology have increased the demand for semiconductor devices with higher storage capacity, faster processing systems, higher performance, and lower cost. To meet these demands, the semiconductor industry continues to shrink the size of semiconductor devices. Such scaling increases the complexity of semiconductor device fabrication.

Disclosure of Invention

In some embodiments, a semiconductor structure is provided, comprising: a substrate, a gate structure on the substrate, a dielectric material layer on the gate structure, a source/drain (S/D) contact layer through and adjacent to the gate structure, and a trench conductive layer on and in contact with the source/drain (S/D) contact layer. The source/drain (S/D) contact layer may include a platinum group metal material layer and a silicide layer formed between the substrate and the platinum group metal material layer. The top width of the top of the platinum group metal material layer can be greater than or substantially equal to the bottom width of the bottom of the platinum group metal material layer.

In some embodiments, a semiconductor structure is provided, comprising: forming a source/drain (S/D) region on a substrate; forming a dielectric material layer on the source/drain (S/D) region; forming a recess structure in the dielectric material layer to expose a source/drain (S/D) region; depositing a first metal material layer in the groove structure at a first deposition rate, and depositing the first metal material layer on the dielectric material layer at a second deposition rate which is less than the first deposition rate; and forming a second metal material layer on and in contact with the first metal material layer.

In some embodiments, a method of forming a semiconductor structure is provided, comprising: forming first and second gate structures on a substrate; forming a dielectric material layer on the first and second gate structures; forming a recess structure in the dielectric material layer and between the first and second gate structures; forming a first metal material layer to fill and seal the groove structure; forming a second metal material layer on and in contact with the first metal material layer, wherein the first and second metal material layers may comprise the same platinum group metal material; and forming an interconnect structure on and in contact with the second metal material layer.

Drawings

Fig. 1 illustrates an isometric view of a semiconductor device according to some embodiments.

Fig. 2A-2C and 3 illustrate cross-sectional schematic views of semiconductor devices according to some embodiments.

Fig. 4 illustrates a flow chart of a method of manufacturing a semiconductor device according to some embodiments.

Fig. 5-16 illustrate cross-sectional schematic views of a semiconductor device at various stages of its fabrication process, in accordance with some embodiments.

The reference numbers are as follows:

100 semiconductor device

102 Field Effect Transistor (FET)

106 base

108 fin structure

108A buffer layer

108CH channel layer

110 source/drain (S/D) region

112,112A,112B,112C,112D, a gate structure

114 gate spacer

116,122A Contact Etch Stop Layer (CESL)

118 interlayer dielectric (ILD) layer

120 contact structure

122 interlayer dielectric (ILD) layer

122B,124,126 dielectric material layer

128,136,162 Trench conductive layer

128L,128R,130L,130R,701L,701R lateral surface

130,834 layer of metallic material

130B lower surface

130G1,130G2 bare chip structure

130T upper surface

132 silicide layer

134 oxidation liner

138 Shallow Trench Isolation (STI) region

140 inner connection structure

144,148 insulating material layer

146 layer of conductive material

400 method

405,410,415,420,425 Process step

701,1401 groove structure

H ₁₃₆ Height of

S ₁₁₂ Distance between

W ₁₃₆ Width (L)

Detailed Description

It should be noted that references in the specification to "one embodiment," "an example embodiment," etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, the above phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.

It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the teachings herein.

Spatially relative terms, such as "below," "lower," "above," "upper," and the like, are used herein to readily convey the relationship of an element or feature to another element or feature in the figures illustrated in this specification. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be oriented differently (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The term "nominally" herein refers to a desired value or target value of a characteristic or parameter of a component or process operation, as set at the design stage of the product or process operation, and a range of values above and/or below this desired value. This range of values is typically due to slight variations or tolerances in the manufacturing process.

In some embodiments, the terms "about" and "substantially" may represent a given number of values varying within 5% of the above-described values (e.g., ± 1%, ± 2%, ± 3%, ± 4%, ± 5% of the above-described values). These values are exemplary only and are not meant to be limiting. The terms "about" and "substantially" may refer to percentages of numerical values that are interpreted by one of ordinary skill in the art in light of the teachings herein.

The term "perpendicular" as used herein refers to a surface that is nominally perpendicular to the substrate.

Fins associated with fin field effect transistors (finfets) or gate-all-around (GAA) field effect transistors may be patterned by any suitable method. For example, the fin may use one or more photolithography processes, including a double patterning process or a multiple patterning process. Double patterning and multiple patterning processes may combine lithographic and self-aligned processes, allowing patterns to be formed with smaller pitches than can be obtained directly using a single lithographic process. For example, a sacrificial layer is formed on a substrate and patterned using a photolithography process. And forming a spacer layer beside the patterned sacrificial layer by using a self-alignment process. The sacrificial layer is then removed and the remaining spacer layer may be used to pattern the fins.

Technological advances in the semiconductor industry have driven the pursuit of Integrated Circuits (ICs) with higher device density, higher performance, and lower cost. In the development of integrated circuits, transistor structures have been scaled down along with contact structures, such as source/drain (S/D) contact structures, to achieve integrated circuits with higher transistor densities. As the contact structure is scaled down, the resistance of the contact structure increases. Thus, cobalt has been employed as a conductive material to provide reduced resistivity for contact structures. However, the cobalt contact structure requires a liner structure to promote adhesion and/or act as a diffusion barrier to ensure the structural integrity of the contact structure. The liner structure reduces the effective contact area of the contact structure, thereby increasing contact resistance and reducing Integrated Circuit (IC) performance. Furthermore, in back-end-of-line (BEOL) processes for forming interconnect structures, cobalt tends to diffuse away from the contact structures toward vertically adjacent contact structures. This diffusion of cobalt creates voids in the contact structure, thereby reducing the yield and performance of the integrated circuit.

To address the above challenges, the present disclosure provides a fabrication method and a transistor structure with a contact structure. The transistor structure may include a gate structure and a source/drain (S/D) region adjacent to the gate structure. The horizontal dimension of the contact structure may be less than about 30nm, such as less than about 20nm, to meet the technology node requirements of the contact structure (e.g., beyond the 14nm technology node, such as the 7nm, 5nm, and 3nm nodes). The contact structure may be cobalt-free to avoid the formation of voids in the contact structure. For example, the contact structure may be made of a platinum group metal material, such as ruthenium, as the platinum group metal material may have a lower diffusivity than cobalt to inhibit void formation as described in the challenges above. Furthermore, the diffusivity of the platinum group metal material is reduced, such that there is no barrier layer or liner in the contact structure, since the platinum group metal material can have sufficient adhesion to the sidewalls of the dielectric layer formed by the contact structure. The contact structure may reduce the resistance value by omitting the barrier layer in the contact structure. Accordingly, one benefit of the present invention is to provide reliable structural integrity (e.g., to avoid void formation) and reduced resistance (e.g., to increase the effective contact area by omitting the barrier layer or liner) for the contact structure, thereby improving the yield and reliability of Integrated Circuits (ICs).

Fig. 1, 2A-2C illustrate a semiconductor device 100 having a plurality of Field Effect Transistors (FETs) 102, a contact structure 120 disposed on the FETs 102, and an interconnect structure 140 disposed on the contact structure 120, according to some embodiments. Fig. 1 illustrates an isometric view of a semiconductor device 100 according to some embodiments. Fig. 2A and 3 illustrate schematic cross-sectional views along linebase:Sub>A-base:Sub>A of the semiconductor device 100 of fig. 1, in accordance with some embodiments. Fig. 2B illustrates a cross-sectional schematic view along line B-B of the semiconductor device 100 of fig. 1, in accordance with some embodiments. Fig. 2C shows a schematic cross-sectional view along the line C-C of the semiconductor device 100 of fig. 1. Unless otherwise noted, the descriptions of components having the same reference numbers in fig. 1, 2A-2C, and 3 apply to each other. The semiconductor device 100 may be included in a microprocessor, memory unit, or other integrated circuit. Although the Field Effect Transistors (FETs) 102 shown in fig. 1, 2A-2C, and 3 are gate all-around (GAA) Field Effect Transistors (FETs), according to some embodiments, each Field Effect Transistor (FET) 102 may be a fin field effect transistor (finFET).

Referring to fig. 1 and 2A-2C, a Field Effect Transistor (FET) 102 may include a fin structure 108 extending in an X-direction, a gate structure 112 (e.g., gate structures 112A-112D) traversing the fin structure 108 in a Y-direction, and a source/drain (S/D) region 110 formed on portions of the fin structure 108. In some embodiments, the Field Effect Transistor (FET) 102 may include a plurality of fin structures 108 (not shown in fig. 1 and 2A-2C), wherein each of the plurality of fin structures 108 may extend in the X-direction and be traversed by a common gate structure 112. A Field Effect Transistor (FET) 102 may be formed on a substrate 106. The substrate 106 may be a semiconductor material, such as silicon (Si). In some embodiments, the substrate 106 may include: (ii) (i) elemental semiconductors such as silicon and germanium (Ge); (ii) Compound semiconductors including silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and indium antimonide (InSb); or (iii) combinations thereof. In some embodiments, the substrate 106 may be doped with a P-type dopant (e.g., boron (B), indium (In), aluminum (Al), or gallium (Ga)) or an n-type dopant (e.g., phosphorus (P) or arsenic (As)).

Referring to fig. 2B, a fin structure 108 may be formed on the substrate 106. The fin structures 108 may extend in the X-direction and be traversed by one or more gate structures 112 (e.g., gate structures 112A-112D) in the Y-direction. The fin structure 108 may include a buffer layer 108A disposed on the substrate 106. The buffer layer 108A may be made of a material similar to that of the substrate 106 to ensure that the channel region of the Field Effect Transistor (FET) 102 is free of crystalline defects. In some embodiments, the buffer layer 108A may be made of a semiconductor material having a lattice mismatch of less than about 0.5% compared to the substrate 106. In some embodiments, the buffer layer 108A and the substrate 106 may be made of the same material, such as Si. The fin structure 108 may further include one or more channel layers 108CH disposed on the buffer layer 108A. The gate structure 112 may cross and/or surround each channel layer 108CH to form a channel region of the Field Effect Transistor (FET) 102. Each channel layer 108CH may be made of silicon or silicon germanium (SiGe). In some embodiments, channel layer 108CH may have a higher concentration of germanium atoms than buffer layer 108A and substrate 106.

Referring to fig. 2C, source/drain (S/D) regions 110 may be formed on the fin structure 108. The source/drain (S/D) regions 110 may comprise an epitaxially grown semiconductor material. In some embodiments, the epitaxially grown semiconductor material may be the same material as the substrate 106. For example, the lattice constant of the epitaxially grown semiconductor material may be substantially similar to the lattice constant of the substrate 106 (e.g., lattice mismatch within 5%). In some embodiments, the epitaxially grown semiconductor material may include: (i) semiconductor materials such as Ge and Si; (ii) compound semiconductor materials such as GaAs and AlGaAs; or (iii) semiconductor alloys such as SiGe and GaAsP. The source/drain (S/D) regions 110 may be doped with p-type dopants or doped with n-type dopants. The p-type dopant may include B, in, al, or Ga. The n-type dopant may include P or As.

Referring to fig. 2A-2C, the gate structure 112 (e.g., the gate structures 112A-112D) may be a multi-layer structure that surrounds a portion of the fin structure 108. For example, as shown in fig. 2B, the gate structure 112 may surround the channel layer 108CH of the Field Effect Transistor (FET) 102 to adjust the conductivity of the channel region of the Field Effect Transistor (FET) 102. The gate structures 112 may be spaced apart from each other in a horizontal direction (e.g., in the X direction) by a spacing S ₁₁₂ (as shown in fig. 2A), from about 35nm to about 75nm. If the spacing S ₁₁₂ Below the lower limit, the source/drain (S/D) regions 110 may not have sufficient volume for useTo reduce the parasitic resistance of the Field Effect Transistor (FET) 102. If the spacing S ₁₁₂ Beyond the above upper limit, the semiconductor device 100 may not meet the gate pitch requirements of the related art node. In some embodiments, one set of gate structures 112 (e.g.,

gate structures

112A and 112B) may surround the fin structure 108, while another set of gate structures (e.g., gate structure 112D) may be formed over and in contact with a Shallow Trench Isolation (STI) region 138 (described below) and spaced apart from the gate structure 108. In some embodiments, the gate structure 112 (e.g., the gate structure 112C) may surround the fin structure 108 and be formed over and in contact with a Shallow Trench Isolation (STI) region 138.

The gate structure 112 may include a gate dielectric layer (not shown in fig. 1 and 2A-2C), a gate electrode (not shown in fig. 1 and 2A-2C) disposed on the gate dielectric layer, and gate spacers 114 (shown in fig. 2A and 2C) disposed on sidewalls of the gate electrode. A gate dielectric layer may surround the fin structure 108, electrically isolating the fin structure 108 from the gate electrode. A gate dielectric layer may be disposed between the gate electrode and the source/drain (S/D) region 110 to prevent electrical shorting therebetween.

The gate dielectric layer may comprise any suitable dielectric material separating the gate electrode from the fin structure 108, such as: (i) Silicon oxide, silicon nitride, and silicon oxynitride layers, (ii) high k dielectric materials having a dielectric constant greater than silicon dioxide (e.g., greater than about 3.9), such as hafnium oxide (HfO) ₂ ) Titanium oxide (TiO) ₂ ) Hafnium zirconium oxide (HfZrO), tantalum oxide (Ta) ₂ O ₃ ) Hafnium silicate (HfSiO) ₄ ) Zirconium oxide (ZrO) ₂ ) And zirconium silicate (ZrSiO) ₂ ) (ii) a And (iii) combinations thereof. In some embodiments, the gate dielectric layer may comprise a single layer or a stack of layers of insulating material. The thickness of the gate dielectric layer may be from about 1nm to about 5nm. Other materials and thicknesses for the gate dielectric layer are also within the spirit and scope of the present disclosure.

The gate electrode may be the gate terminal of a Field Effect Transistor (FET) 102. The gate electrode may include a metal stack surrounding the fin structure 108. In some embodiments, the gate electrode may include a gate blocking layer (not shown in fig. 1 and 2A-2C), a gate work function layer (not shown in fig. 1 and 2A-2C), and a gate metal fill layer (not shown in fig. 1 and 2A-2C). The gate blocking layer may serve as a nucleation layer for the subsequent formation of a gate work function layer. The gate barrier layer may comprise titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), or other suitable diffusion barrier material. The gate work function layer may comprise a single metal layer or a stack of metal layers. In some embodiments, the gate work function layer may include aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), nickel silicide (NiSi), cobalt silicide (CoSi), silver (Ag), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), tantalum carbon nitride (TaCN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tungsten nitride (WN), a metal alloy, or a combination thereof. The gate metal fill layer may comprise a single metal layer or a stack of metal layers. In some embodiments, the gate metal fill layer may comprise a suitable conductive material, such as Ti, silver (Ag), al, titanium aluminum nitride (TiAlN), tantalum carbide (TaC), tantalum carbide nitride (TaCN), tantalum silicon nitride (TaSiN), manganese (Mn), zirconium (Zr), titanium nitride (TiN), tantalum nitride (TaN), ruthenium (Ru), molybdenum (Mo), tungsten nitride (WN), copper (Cu), tungsten (W), cobalt (Co), nickel (Ni), titanium carbide (TiC), titanium aluminum carbide (TiAlC), tantalum aluminum carbide (TaAlC), metal alloys, and combinations thereof. Other materials for the gate blocking layer, the gate work function layer, and the gate metal fill layer are within the spirit and scope of the present disclosure.

The gate spacers 114 (as shown in figure 2C) may be in physical contact with the gate dielectric layer. In some embodiments, the gate spacers 114 may be formed on the side surfaces of the fin structure 108, as shown in fig. 2C. The gate spacer 114 may comprise a low-k material having a dielectric constant less than about 3.9. For example, the gate spacer 114 may comprise an insulating material, such as silicon oxide, silicon nitride, low-k materials, and combinations thereof. In some embodiments, the thickness of the gate spacer 114 may be from about 2nm to about 10nm. Other materials and thicknesses for the gate spacer 114 are within the spirit and scope of the present disclosure.

Referring to fig. 1, 2A, and 2C, the semiconductor device 100 may further include a Shallow Trench Isolation (STI) region 138 that provides electrical isolation for the fin structure 108. For example, a Shallow Trench Isolation (STI) region 138 may electrically isolate the fin structure 108 from another fin structure 108 (not shown in fig. 1) formed within the semiconductor device 100. In addition, shallow Trench Isolation (STI) regions 138 may provide electrical isolation between Field Effect Transistors (FETs) 102 and adjacent active and passive components (not shown in fig. 1) that are integrated with the substrate 106 or deposited on the substrate 106. Shallow Trench Isolation (STI) regions 138 may include one or more layers of dielectric material, such as a nitride layer, an oxide layer disposed on the nitride layer, and an insulating layer disposed on the nitride layer. In some embodiments, an insulating layer may be referred to as an electrically insulating layer (e.g., a dielectric layer). In some embodiments, the insulating layer may comprise silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric material, or other suitable insulating material. Other materials and thicknesses for the Shallow Trench Isolation (STI) regions 138 are within the spirit and scope of the present disclosure.

The semiconductor device 100 may further include a Contact Etch Stop Layer (CESL) 116 and an interlayer dielectric (ILD) layer 118 to provide electrical insulation between adjacent fin structures 108. A Contact Etch Stop Layer (CESL) 116 may be formed on the gate spacers 114 and the source/drain (S/D) regions 110 to protect the gate gap 104 and the source/drain (S/D) regions 110 during the formation of an inter-layer dielectric (ILD) layer 118. The Contact Etch Stop Layer (CESL) 116 may be made of any suitable dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, siCN, siOC, siOCN, boron nitride, silicon nitride, and silicon boron carbon nitride. The Contact Etch Stop Layer (CESL) 116 may have any suitable thickness, such as from about 1nm to about 10nm. Other materials and thicknesses of the Contact Etch Stop Layer (CESL) 116 are within the scope and spirit of the present disclosure.

An inter-layer dielectric (ILD) layer 118 may be formed on the Contact Etch Stop Layer (CESL) 116. An inter-layer dielectric (ILD) layer 118 may be formed on the fin structures 108 to provide electrical insulation between adjacent fin structures 108. In some embodiments, an interlayer dielectric (ILD) layer 118 may provide electrical insulation between the source/drain (S/D) regions 110 and the contact structure 120. By way of example and not limitation, the inter-layer dielectric (ILD) layer 118 may comprise a dielectric material deposited using a deposition method suitable for a flowable dielectric material (e.g., flowable silicon oxide, flowable silicon nitride, flowable silicon oxynitride, flowable silicon carbide, or flowable silicon oxycarbide). In some embodiments, the dielectric material may be silicon oxide or silicon nitride. In some embodiments, the interlayer dielectric (ILD) layer 118 may have a thickness from about 50nm to about 200nm. Other materials, thicknesses, and methods of forming the interlayer dielectric (ILD) layer 118 are within the spirit and scope of the present disclosure. In some embodiments, the upper surfaces of the Contact Etch Stop Layer (CESL) 116, the interlayer dielectric (ILD) layer 118, and the gate spacer 114 may be substantially coplanar with one another.

Referring to fig. 1 and 2A, the contact structure 120 may be sandwiched between the Field Effect Transistor (FET) 102 and the dielectric material layer 124 to electrically connect the Field Effect Transistor (FET) 102 and the dielectric material layer 124. The contact structure 120 may include an inter-layer dielectric (ILD) layer 122 disposed on the ILD layer 118 and on the gate structure 112. In some embodiments, the interlayer dielectric (ILD) layer 122 may include an Etch Stop Layer (ESL) 122A and a layer of dielectric material 122B (which may have a different etch selectivity than the ESL 122A). In some embodiments, the term "etch selectivity ratio" may refer to the ratio of the etch rates of two materials under the same etch conditions. Each of the Etch Stop Layer (ESL) 122A and the dielectric material layer 122B may be made of any suitable insulating material, such as silicon nitride, silicon oxynitride, and silicon oxide. Each of the Etch Stop Layer (ESL) 122A and the dielectric material layer 122B may have any suitable thickness, such as from about 50nm to about 200nm. Other materials and thicknesses of the interlayer dielectric (ILD) layer 122, such as the Etch Stop Layer (ESL) 122A and the dielectric material layer 122B, are within the spirit and scope of the present disclosure.

The contact structure 120 may further include a trench conductive layer 136 extending vertically (e.g., in the Z-direction) through the inter-layer dielectric (ILD) layer 122 and beyond the inter-layer dielectric (ILD) layer 118 to contact the source/drain (S/D) regions 110. In some embodiments, the trench conductive layer 136 may represent a source of a Field Effect Transistor (FET) 102A/drain (S/D) contact structure that contacts a source/drain (S/D) region 110 of a Field Effect Transistor (FET) 102. The trench conductive layer 136 may have a width W of a horizontal (e.g., in the X direction) ₁₃₆ Is less than or substantially equal to the spacing S ₁₁₂ . In some embodiments, the width W ₁₃₆ May represent the horizontal (e.g., in the X direction) width of the upper portion (e.g., near the upper surface of inter-layer dielectric (ILD) layer 122) and/or the bottom (e.g., near source/drain (S/D) regions 110) of trench conductive layer 136. In some embodiments, the width W ₁₃₆ And may be from about 13nm to about 20nm. If width W ₁₃₆ Below the above-mentioned lower limit, the resistance of the trench conductive layer 136 may increase, resulting in a decrease in the performance of the semiconductor device 100. If width W ₁₃₆ Beyond the upper limit, the semiconductor device 100 may not meet the gate pitch requirements of the related art node (e.g., the gate pitch should be less than 75nm for 7nm, 5nm, 3nm nodes). Trench conductive layer 136 may have a suitable vertical (e.g., in the Z-direction) height H ₁₃₆ Wherein the height H ₁₃₆ And width W ₁₃₆ May be from about 3 to about 6. If the height H ₁₃₆ And width W ₁₃₆ A ratio of (D) less than the lower limit may cause higher parasitic capacitance between the dielectric material layer 124 and the source/drain (S/D) regions 110, which may slow down the speed of the Field Effect Transistor (FET) 102. If the height H ₁₃₆ And width W ₁₃₆ If the ratio of (a) is greater than the above upper limit, the trench conductive layer 136 may incorporate a void structure therein, which may reduce the reliability of the semiconductor device 100.

The trench conductive layer 136 may include a silicide layer 132 protruding into the source/drain (S/D) regions 110. The silicide layer 132 may provide a low resistance interface between the metal material layer 130 (described below) and the source/drain (S/D) regions 110. The silicide layer 132 may be a metal silicide including titanium, cobalt, nickel, platinum, palladium, tungsten, molybdenum, tantalum, vanadium, chromium, silicon, or germanium. The silicide layer 132 may have any suitable thickness, for example, from about 1nm to about 20nm. Other materials for the silicide layer 132 are also within the scope and spirit of the present disclosure.

The trench conductive layer 136 may further include a metal material layer 130 formed on the silicide layer 132. Gold (Au)The layer of metal material 130 may have an upper surface 130T that is substantially coplanar with the interlayer dielectric (ILD) layer 122. The metal material layer 130 also has a lower surface 130B (shown in fig. 2A) that is located on and in contact with the silicide layer 132. The metal material layer 130 may be a non-liner (e.g., non-undercut-free) structure, such that the upper surface 130T (shown in fig. 2A) and the lower surface 130B of the metal material layer 130 may be connected to the two opposite side surfaces 130L and 130R of the metal material layer 130 (e.g., the metal material layer 130 does not have a liner structure). Since the metal material layer 130 has no liner structure, most of the width W of the trench conductive layer 136 ₁₃₆ Can contribute to the effective contact area (e.g., width W) of the contact structure ₁₃₆ Unoccupied liner structure is consumed) while minimizing the resistance of trench conductive layer 136. In some embodiments, the metal material layer 130 may be a liner-free structure, and the upper surface 130T and the lower surface 130B of the metal material layer 130 may each have a width W corresponding to the width of the trench conductive layer 136 ₁₃₆ Substantially equal widths (e.g., the entire trench conductive layer 136 may be a liner-free structure). In some embodiments, the metal material layer 130 may be a liner-free structure having inclined side surfaces 130L and 130R, such that the upper surface 130T of the metal material layer 130 may have a width (e.g., a width W near the upper surface 130T) ₁₃₆ ) Is greater than another width of the lower surface 130B of the underlying metallic material layer 130 (e.g., width W near the lower surface 130B) ₁₃₆ ). In some embodiments, as shown in fig. 2A, two opposing side surfaces 130L and 130R of the metal material layer 130 may be in contact with an interlayer dielectric (ILD) layer 122 and a Contact Etch Stop Layer (CESL) 116. In some embodiments, as shown in fig. 2A, two opposing side surfaces 130L and 130R of the metal material layer 130 may contact the interlayer dielectric (ILD) layer 122 and a portion of the interlayer dielectric (ILD) layer 118 (e.g., a portion of the interlayer dielectric (ILD) layer 118 is between the metal material layer 130 and the Contact Etch Stop Layer (CESL) 116, which is not shown in fig. 2A).

In some embodiments, as shown in fig. 3, the semiconductor device 100 may further include a liner oxide layer 134 sandwiched between the metal material layer 130 and the interlayer dielectric (ILD) layer 122, or between the metal material layer 130 and the contact etchBetween stop layers (CESL) 116. The oxide liner 134 may be formed during the process of forming the silicide layer 132 (illustrated in the method 400). Thus, the oxide liner layer 134 may comprise the same metal element as the silicide layer 132, such as titanium. The oxide liner layer 134 may have a thickness (e.g., dimension in the X direction), for example, from about 0.5nm to about 2nm, which is less than the width W of the trench conductive layer 136 ₁₃₆ . In some embodiments, the thickness of the oxide liner layer 134 and the width W of the trench conductive layer 136 ₁₃₆ May be about 0.01 to about 0.1. If the thickness of the oxide liner layer 134 and the width W of the trench conductive layer 136 are equal ₁₃₆ With a ratio of (a) below the lower limit, the silicide layer 132 may not have a sufficient thickness to reduce the contact resistance between the source/drain (S/D) regions 110 and the trench conductive layer 136. If the thickness of the oxide liner layer 134 and the width W of the trench conductive layer 136 are equal ₁₃₆ If the ratio of (d) is greater than the above upper limit, the trench conductive layer 136 may increase the resistance value due to the loss of the effective contact area of the trench conductive layer 136.

Returning to fig. 1 and 2A, the metal material layer 130 may be made of a metal material having a reduced diffusivity toward adjacent contact structures, e.g., toward the trench conductive layer 128 (described below), and toward adjacent dielectric layers, e.g., toward the interlayer dielectric (ILD) layer 122 and the Contact Etch Stop Layer (CESL) 116. Therefore, the metal material layer 130 becomes a void-free structure after the process of forming the dielectric material layer 124. The metal material layer 130 may be made of a metal material that also has enhanced adhesion to adjacent dielectric layers (e.g., enhanced adhesion of the inter-layer dielectric (ILD) layer 122 and/or the Contact Etch Stop Layer (CESL) 116). Accordingly, the metal material layer 130 and the entire trench conductive layer 136 can be a barrier-free and liner-free structure. That is, neither the metal material layer 130 nor the trench conductive layer 136 has a barrier layer (e.g., a TaN layer or a TiN layer) that acts as an adhesion promoting and/or diffusion barrier. The metal material layer 130 may be made of a metal material without Co and/or a metal material without Cu to satisfy the above requirements of reduced diffusivity and enhanced adhesion. In some embodiments, the metallic material layer 130 may be made of a platinum group metal material, such as Ru, rhodium (Rh), and iridium (Ir). In some embodiments, the metallic material layer 130 may be made of Mo. In some embodiments, the metallic material layer 130 may be made of a single layer of metallic material, such as a single layer of platinum group metallic material and a single layer of molybdenum. For example, the metal material layer 130 may be a single layer of Ru, such that various portions of the metal material layer 130 (e.g., portions near the upper surface 130T, the side surfaces 130L and 130R, and the lower surface 130B) are made of Ru. In some embodiments, the metallic material layer 130 may be made of multiple layers of metallic materials (not shown in fig. 2A), wherein each of the multiple layers may be a linerless (e.g., no recession) structure made of a platinum group metal material or Mo.

In some embodiments, as shown in fig. 2C, the metal material layer 130 may include a plurality of die structures, such as die structures 130G1 and 130G2. Die structure 130G1 may be proximate to upper surface 130T. In some embodiments, the die structure 130G1 may be proximate to a metal layer of the metal material layer 130, such as proximate to the trench conductive layer 128 (explained below). The die structure 130G2 may be adjacent to a dielectric layer of the metal material layer 130, such as adjacent to the inter-layer dielectric (ILD) layer 118 and the inter-layer dielectric (ILD) layer 122. The average die size of the die structure 130G1 (e.g., the average size of the die structure 130G1 in the X-direction, the Y-direction, and/or the Z-direction) may be greater than the average die size of the die structure 130G2 (e.g., the average size of the die structure 130G2 in the X-direction, the Y-direction, and/or the Z-direction) because adjacent dielectric layers (e.g., the inter-layer dielectric (ILD) layer 118 and the inter-layer dielectric (ILD) layer 122) may reduce the die growth rate of the metal material layer 130 in the process of forming the metal material layer 130 (illustrated in the method 400). In some embodiments, the average size of die structure 130G1 may be at least 2 times greater than the average size of die structure 130G2.

The contact structure 120 may further include a dielectric material layer 124 disposed on the trench conductive layer 136 and the inter-layer dielectric (ILD) layer 122. The dielectric material layer 124 may comprise any suitable insulating material, such as silicon nitride, silicon oxynitride, silicon oxide, metal-based oxide materials (e.g., aluminum oxide), and carbide materials (e.g., silicon oxycarbonitride). The layer of dielectric material 124 may have any suitable thickness, for example, from about 2nm to about 30nm. Other materials, thicknesses, and methods of forming the dielectric material layer 124 are within the spirit and scope of the present disclosure.

The contact structure 120 may further include a dielectric material layer 126 disposed on the dielectric material layer 124. The dielectric material layer 126 and the dielectric material layer 124 may separate the trench conductive layer 136 from the interconnect structure 140. The dielectric material layer 126 may be made of any suitable insulating material, such as silicon nitride, silicon oxynitride, silicon oxide, and metal-based oxide materials (e.g., aluminum oxide). In some embodiments, the dielectric material layer 126 and the dielectric material layer 124 may be made of different materials having different etching selectivity ratios from each other. The layer of dielectric material 126 may have any suitable thickness, such as from about 50nm to about 200nm. Other materials and thicknesses for the dielectric material layer 126 are within the spirit and scope of the present disclosure.

The contact structure 120 may further include a trench conductive layer 128 extending vertically (e.g., in the Z-direction) through the dielectric material layers 126 and 124 to contact the underlying trench conductive layer 136 and/or the gate structure 112. The trench conductive layer 128 may further electrically connect the interconnect structure 140 with the underlying trench conductive layer 136 and/or the gate structure 112. Accordingly, the trench conductive layer 128 and the trench conductive layer 136 may electrically bridge the interconnection structure 140 and the source/drain (S/D) region 110 and/or the gate structure 112. The upper surface of trench conductive layer 128 (e.g., the surface in contact with interconnect structure 140) may have any suitable horizontal dimension (e.g., width in the X-direction), such as from about 15nm to about 50nm, and any suitable vertical dimension (e.g., height in the Z-direction), such as from about 100nm to about 600nm. In some embodiments, as shown in fig. 2A, a lower surface of the trench conductive layer 128 (which is in contact with the upper surface 130T of the metal material layer 130) may be less than or substantially equal to the width W of the trench conductive layer 136 ₁₃₆ 。

The trench conductive layer 128 may be made of any suitable conductive material, such as platinum group metal materials, mo, W, al, cu, co, ta, silicide materials, and conductive nitride materials. In some embodiments, the trench conductive layer 128 may be a liner-free (e.g., no recess) structure for reducing the resistance of the trench conductive layer 128. Therefore, the upper surface and the lower surface of the trench conductive layer 128 may be connected to two opposite side surfaces 128L and 128R of the trench conductive layer 128. In some embodiments, two opposing side surfaces 128L and 128R of the trench conductive layer 128 may be in contact with the

dielectric layers

124 and 126. In some embodiments, the trench conductive layer 128 may be made of a platinum group metal material or Mo, such that the trench conductive layer 128 may be an unobstructed and unlined contact structure. In some embodiments, trench conductive layer 128 may be made of a single layer of metallic material. For example, the trench conductive layer 128 may be a single layer of Ru, such that various portions of the trench conductive layer 128 (e.g., portions near the top, sides, and bottom) are made of Ru. In some embodiments, the trench conductive layer 128 may be made of the same material as the metallic material layer 130 to exclude an interface resistance between the trench conductive layer 128 and the trench conductive layer 136. For example, a portion of the bottom of the trench conductive layer 128 in contact with the metal material layer 130 may be made of the same material, such as Ru, to exclude an interface resistance between the trench conductive layer 128 and the trench conductive layer 136. In some embodiments, the trench conductive layer 128 may be made of multiple layers of metallic materials, where each layer of metallic material may be a liner-free structure made of platinum group metallic materials or Mo.

The interconnect structures 140 may provide routing of metal lines for the underlying Field Effect Transistors (FETs) 102. The interconnect structure 140 may include a layer of insulating material 144, a layer of conductive material 146 embedded in the layer of insulating material 144, a layer of insulating material 148 disposed on the layer of conductive material 146, and a trench conductive layer 162 passing through the layer of insulating material 148 and contacting the layer of conductive material 146. The conductive material layer 146 may be a lateral (e.g., in the x-y plane) routing of the interconnect structure 140. Conversely, each of trench

conductive layers

128 and 136 may be a vertical (e.g., in the z-direction) wire routing of contact structure 120, and trench conductive layer 162 may be a vertical (e.g., in the z-direction) wire routing of interconnect structure 140. Accordingly, in some embodiments, the aspect ratio (e.g., height to width ratio) of the conductive material layer 146 may be less than the aspect ratio of each of the trench conductive layers 128,136 and 162. In some embodiments, the ratio of the aspect ratio of the conductive material layer 146 to the aspect ratio of each of the trench conductive layers 128,136 and 162 may be less than about 1, less than about 0.8, less than about 0.6, less than about 0.4, less than about 0.2, or less than about 0.1. If the aspect ratio of the conductive material 146 and the respective aspect ratios of the trench conductive layers 128,136 and 162 exceed the above-mentioned upper limits, the interconnect structure 140 may not meet the fin pitch requirements of the related art node and thus the product requirements of the Integrated Circuit (IC). A conductive material layer 146 may be disposed over one or more of the trench conductive layer 128 and the trench conductive layer 136 to electrically connect the underlying gate structure 112 and the source/drain (S/D) region 110. The trench conductive layer 162 may electrically connect the conductive material layer 146 vertically (e.g., in the Z-direction) to another one (not shown in fig. 1-3) above the conductive material layer 146 of the interconnect structure 140. The conductive material layer 146 and the trench conductive layer 162 may be made of any suitable conductive material, such as W, al, cu, co, ti, ta, ru, mo, silicide material and conductive nitride material. The insulating material layer 148 and the insulating material layer 144 may be made of a suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric material, and high-k dielectric material. Other materials for the conductive material layer 146, the trench conductive layer 162, the insulating material layer 144, and the insulating material layer 148 are also within the spirit and scope of the present invention.

Fig. 4 is a flow chart of an exemplary method 400 of fabricating the semiconductor device 100 according to some embodiments. For illustrative purposes, the operational steps described in fig. 4 will be described with reference to fig. 5-16. Fig. 5-16 illustrate cross-sectional views along linebase:Sub>A-base:Sub>A of fig. 1 at various stages of fabrication to formbase:Sub>A semiconductor device 100, according to some embodiments. The operational steps may be performed in a different order or not performed depending on the particular application. The method 400 may not result in a completed semiconductor device 100. Accordingly, it is understood that additional processes may be provided before, during, and after the method 400, and that some other processes may only be briefly described herein. Also, the descriptions of components having the same reference numbers in fig. 1, 2A-2C, 3, and 5-16 apply to each other, unless otherwise noted.

Referring to fig. 4, in operation 405, a dielectric layer is formed over source/drain (S/D) regions of the transistor structure. For example, fig. 6 illustrates the formation of an interlayer dielectric (ILD) layer 122 on the source/drain (S/D) regions 110 of Field Effect Transistors (FETs) 102, as illustrated in fig. 5 and 6. The process of forming the dielectric material layer 122 may include: (i) Forming the semiconductor device 100 of fig. 5 and (ii) depositing an Etch Stop Layer (ESL) 122A and a layer of dielectric material 122B on the semiconductor device 100 of fig. 5. Any suitable deposition process is used, such as a Chemical Vapor Deposition (CVD) process, an Atomic Layer Deposition (ALD) process, a Physical Vapor Deposition (PVD) process, a Plasma Enhanced CVD (PECVD) process, and a spin-on process. In some embodiments, the process of forming the semiconductor device 100 of fig. 5 may include providing a substrate 106, forming a fin structure 108 on the substrate 106, forming a Shallow Trench Isolation (STI) region 138 adjacent to the fin structure 108, forming a gate structure 112 through the fin structure 108, forming a source/drain (S/D) region 110, and forming a Contact Etch Stop Layer (CESL) 116 and an inter-layer dielectric (ILD) layer 118 on a portion of the fin structure 108 (not covered by the gate structure 112). In some embodiments, the Contact Etch Stop Layer (CESL) 116 and the interlayer dielectric (ILD) layer 118 may be substantially coplanar with the gate structure 112. Other methods of forming the semiconductor device 100 of fig. 5 are also within the spirit and scope of the present disclosure.

Referring to fig. 4, in operation 410, a silicide layer is formed on the source/drain (S/D) regions. For example, as shown in fig. 9. Referring to fig. 7-9, a silicide layer 132 may be formed on the source/drain (S/D) regions 110. Referring to fig. 7, the process of forming the silicide layer 132 may include forming a trench structure 701 through an interlayer dielectric (ILD) layer 122 having a horizontal (e.g., in the X-direction) width W using a photolithography process and an etching process ₁₃₆ And a depth in a vertical direction (e.g., in the Z-direction) substantially equal to the height H of the trench conductive layer 136 ₁₃₆ ). Accordingly, the recess structure 701 may expose side surfaces of the underlying source/drain (S/D) regions 110 and the interlayer dielectric (ILD) layer 122. In some embodiments, the recessed structure 701 further exposes a side surface of the Contact Etch Stop Layer (CESL) 116 such that the recessed junction is formedThe two opposing side surfaces 701L and 701R of the structure 701 may include a side surface contacting the etch stop layer (CESL) 116 and a side surface of the interlayer dielectric (ILD) layer 122. In some embodiments, the recess structure 701 may expose a side surface of the inter-layer dielectric (ILD) layer 118 (the Contact Etch Stop Layer (CESL) 116 is covered by the inter-layer dielectric (ILD) layer 118; not shown in fig. 7), such that two opposing side surfaces 701L and 701R of the recess structure 701 may include a side surface of the inter-layer dielectric (ILD) layer 118 and a side surface of the inter-layer dielectric (ILD) layer 122. In some embodiments, the two opposing side surfaces 701L and 701R of the recess structure 701 may be substantially coplanar with the side surfaces 130L and 130R of the metal material layer 130 after the method 400 is performed. The etch process for forming the recess structure 701 may include using a suitable dry etchant (e.g., carbon tetrafluoride (CF)) ₄ ) Chlorine (Cl) ₂ ) And hydrogen bromide (HBr)), or a wet etch process using a suitable wet etchant, such as hydrofluoric acid (HF), ammonium Peroxide Mixture (APM), and tetramethylammonium hydroxide (TMAH).

Referring to fig. 8 and 9, the process of forming the silicide layer 132 may further include: (i) Using deposition processes, such as Atomic Layer Deposition (ALD) processes and Chemical Vapor Deposition (CVD) processes, a metal material layer 834, such as titanium, cobalt, nickel, tungsten, and any other suitable metal materials, is deposited on the interlayer dielectric (ILD) layer 122 and within the groove structure 701 (shown in fig. 8) to contact the side surfaces 701L and 701R of the source/drain (S/D) regions 110 and the groove structure 701; (ii) An annealing process is performed on the structure of fig. 8 to react a portion of the deposited metal material 834 with the source/drain (S/D) regions 110 to form a silicide layer 132 (shown in fig. 9); and (iii) selectively etching unreacted portions of the metal material layer 834 deposited over the silicide layer 132 and/or the oxide liner layer 134 using an etching process (not shown in fig. 9). In some embodiments, the anneal process for forming the silicide layer 132 may further react the deposited metal material layer 834 with the inter-layer dielectric (ILD) layer 122, the inter-layer dielectric (ILD) layer 118, and/or the Contact Etch Stop Layer (CESL) 116 (e.g., react the deposited metal material layer 834 with the side surfaces 701L and 701R of the recess structure 701 to form the oxide layer 134 of fig. 9. In some embodiments, the structure of fig. 9 may form the semiconductor device 100 of fig. 2A after performing the processes of operation steps 415-425 (described below).

In some embodiments, referring to fig. 10, the process for forming the silicide layer 132 may further include selectively etching the oxide layer 134 of fig. 9 on the silicide layer 132 using a selective etching process to expose the interlayer dielectric (ILD) layer 122 and the side surfaces 701L and 701R of the recess structure 701. The selective etch process may be a plasma-free etch process that provides a substantially uniform etch rate to etch the oxide layer 134 on the top surface of the inter-layer dielectric (ILD) layer 122 and the side surfaces 701L and 701R of the recessed feature 701. In some embodiments, the plasma-free etching process may be a Chemical Vapor Etching (CVE) process, where a mixture of first and second dry etchants is applied at an appropriate temperature (e.g., about 250 ℃). The first dry etchant of the Chemical Vapor Etching (CVE) process may include a chlorine-based gas, such as trichloroboron (BCl) ₃ ) Which may react with the metallic material layer 834 to form byproducts (not shown in fig. 10), and the second dry etchant of the Chemical Vapor Etching (CVE) process may include a fluorine-based gas, such as HF gas, which may remove the byproducts. In some embodiments, the plasma-free etch process may be a cyclic Atomic Layer Etching (ALE) process, operating at an appropriate temperature (e.g., from about 100 ℃ to about 250 ℃), and may include alternately flowing first and second precursors in each cycle of the cyclic Atomic Layer Etching (ALE) process (e.g., flowing the first and second precursors separately at different times). The cyclic Atomic Layer Etching (ALE) process also includes a purging process (e.g., flowing an ambient gas, such as nitrogen, without flowing the first and second precursors) in each cycle of the cyclic Atomic Layer Etching (ALE) process. In some embodiments, the first precursor for each cycle period of a cyclic Atomic Layer Etch (ALE) process may include a fluorine-based precursor, such as tungsten hexafluoride (WF) ₆ ) To alter the surface energy of the metal material layer 834 (not shown in FIG. 10), a second precursor for each cyclic Atomic Layer Etch (ALE) process may be includedIncluding chlorine-based precursors, e.g. trichloroboron (BCl) ₃ ) To react with the metallic material layer 834 to form a byproduct. The purging of each cycle of the cyclic Atomic Layer Etch (ALE) process may be performed between or after the steps of flowing the first and second precursors to remove the byproducts and the excess first and second precursors attached to the structures of fig. 9 and 10. In some embodiments, the structure of fig. 10 may form the semiconductor device 100 of fig. 3 after performing the process of operation steps 415-425 (described below).

Referring to fig. 4, in operation 415, a metal material layer is formed through the dielectric layer to contact the silicide layer. For example, as shown in fig. 13, a metal material layer 130 may be formed through an interlayer dielectric (ILD) layer 122 to contact an underlying silicide layer 132 (see fig. 11-13). Referring to fig. 11, the process of forming the metal material layer 130 may include performing a non-conformal deposition process on the structure of fig. 9 or 10 to deposit the metal material layer 130 in the recess structure 701 in contact with the underlying silicide layer 132. The non-conformal deposition process for forming the metal material layer 130 may have a higher deposition rate on the upper surface of the silicide layer 132 than on the upper surface of the inter-layer dielectric (ILD) layer 122. Accordingly, the non-compliant deposition process may alleviate the gap filling challenge (due to the opening width W of the trench structure 701) ₁₃₆ Smaller) to avoid forming void structures in the metal material layer 130 after performing operation 415. Furthermore, the non-conformal deposition process may prevent formation of a liner structure in the recess structure 701, and the metal material layer 130 may be formed without a liner structure after the operation 415 is performed. In some embodiments, the non-compliant deposition process for forming the metal material layer 130 has a higher deposition rate on the upper surface of the silicide layer 132 than on the side surfaces 701L and 701R of the recess structure 701. In some embodiments, a non-conformal deposition process for forming the metal material layer 130 may selectively deposit the metal material layer 130 on the upper surface of the silicide layer 132 to expose the upper surface of the interlayer dielectric (ILD) layer 122 and/or the side surfaces 701L and 701R of the recess structure 701. In some embodiments, the non-compliant deposition process may include including a metal precursorSubstance (e.g., dodecacarbonyltriruthenium (Ru) ₃ (CO) ₁₂ (ii) a DCR), ruthenium oxide (RuO) ₄ ) Bis (ethylcyclopentadiene) ruthenium (II) (Ru (EtCp) ₂ ) Ethylphenethyl-1,4-cyclohexadieneruthenium (EBECHRu), bis (isopropylcyclopentadiene) ruthenium (II) (C) ₁₆ H ₂₂ Ru) and carbonyl diene precursor [ Ru (CO) ₃ C ₆ H ₈ ]) An Atomic Layer Deposition (ALD) process or a Chemical Vapor Deposition (CVD) process. In some embodiments, as shown in fig. 11, in the non-compliant deposition process, the metal material layer 130 may have a curved upper surface in the groove structure 701.

Referring to fig. 12, the non-compliant deposition for forming the metal material layer 130 may be continued until the metal material layer 130 seals the recess structure 701. Such that: (i) The metal material layer 130 covers the side surfaces 701L and 701R of the groove structure 701; and (ii) the metal material layer 130 located on the upper portion of the silicide layer 132 protrudes vertically (e.g., in the Z-direction) above the upper surface of the adjacent inter-layer dielectric (ILD) layer 122. Since the growth rate of the non-conformal deposition process for forming the metal material layer 130 in the recess structure 701 may be higher than the growth rate on the upper surface of the inter-layer dielectric (ILD) layer 122, the metal material layer 130 formed after performing operation 415 may have a vertical dimension H above the upper surface of the inter-layer dielectric (ILD) layer 122 ₁₂₃₀ (e.g., in the z-direction) that is less than the depth H of the recess structure 701 ₁₃₆ (e.g., after performing operation 415, it later becomes the height H of trench conductive layer 136 ₁₃₆ ). In some embodiments, the vertical dimension H ₁₂₃₀ And the depth H of the groove structure 701 ₁₃₆ The ratio of (a) may be from about 0.01 to about 0.1. If the vertical dimension H ₁₂₃₀ And the depth H of the groove structure 701 ₁₃₆ If the ratio of (b) is less than the lower limit, the interlayer dielectric (ILD) layer 122 may be damaged during the subsequent polishing process in operation 415. If the vertical dimension H ₁₂₃₀ And the depth H of the groove structure 701 ₁₃₆ If the ratio of (a) is greater than the above upper limit, the non-compliant deposition process for forming the metal material layer 130 may be susceptible to gap filling, and a void structure may be formed in the metal material layer 130.

In some embodiments, the process for forming the metallic material layer 130 may further include performing an annealing process (e.g., after performing a non-compliant deposition process) on the structure of fig. 12 to form or grow a crystalline die within the metallic material layer 130 to reduce the resistivity of the metallic material layer 130. The above-described annealing process may be performed at a temperature range of about 300 ℃ to about 500 ℃ under a suitable atmosphere (e.g., nitrogen). If the temperature of the annealing process is less than the lower limit, the metal material layer 130 may exhibit a higher resistivity. If the temperature of the anneal process is greater than the upper limit, the underlying silicide layer 132 may decompose due to the thermal budget of the silicide layer 132. In some embodiments, the annealing process may form die structures 130G1 and 130G2 within the metal material layer 130 (shown in fig. 2C). Since the adjacent dielectric layers (e.g., inter-layer dielectric (ILD) layer 118 and/or inter-layer dielectric (ILD) layer 122) may reduce the mobility of the metal element of the metal material layer 130 (e.g., reduce the mobility of the Ru element), the die structure 130G2 (near the inter-layer dielectric (ILD) layer 118/122) may be smaller in size than the die structure 130G1 (near the upper surface of the structure of fig. 12 and/or far from the inter-layer dielectric (ILD) layer 118/122).

Referring to fig. 13, the process for forming the metal material layer 130 may further include planarizing the structure of fig. 12, for example, by a Chemical Mechanical Polishing (CMP) process, so that the metal material layer 130 and the interlayer dielectric (ILD) layer 122 are co-planarized to define the metal material layer 130 and the trench conductive layer 136. Thus, operation 415 may form unlined metal material layer 130 having: (i) The upper surface 130T is substantially coplanar with the interlayer dielectric (ILD) layer 122; (ii) the lower surface 130B is in contact with the silicide layer 132; and (iii) the side surfaces 130L and 130R are substantially coplanar with the side surfaces 701L and 701R of the groove structure 701.

In some embodiments, the process of forming the metallic material layer 130 may further include performing an annealing process (e.g., after a near planarization process) on the structure of fig. 13 to form or grow a crystalline die within the metallic material layer 130 to reduce the resistivity of the metallic material layer 130. The anneal process may be performed in a suitable atmosphere (e.g., nitrogen) at a temperature in the range of about 300 c to about 500 c. If the temperature of the annealing process is less than the lower limit, the metal material layer 130 may exhibit a higher resistivity. If the temperature of the anneal process is greater than the upper limit, the underlying silicide layer 132 may decompose due to the thermal budget of the silicide layer 132.

Referring to fig. 4, in operation 420, a trench conductive layer is formed on the metal material layer. For example, as shown in fig. 15. Referring to fig. 14 and 15, a trench conductive layer 128 may be formed on the metal material layer 130. As shown in fig. 14, the process of forming the trench conductive layer 128 may include depositing the dielectric material layer 124 and the dielectric material layer 126 on the structure of fig. 13 using any suitable deposition process, such as a Chemical Vapor Deposition (CVD) process, an Atomic Layer Deposition (ALD) process, a Physical Vapor Deposition (PVD) process, a Plasma Enhanced Chemical Vapor Deposition (PECVD) process, and a spin-on process. The process of forming the trench conductive layer 128 may further include forming a recess structure 1401 through the layers of

dielectric material

126 and 128 to expose the underlying trench conductive layer 136. For example, the underlying metal material layer 130 is exposed using a photolithography process and an etching process. In some embodiments, the recess structure 1401 may further expose the gate structure 112 located below.

Referring to fig. 15, the process for forming the trench conductive layer 128 may further include filling a conductive material in the recess structure 1401 by using a deposition process and a Chemical Mechanical Polishing (CMP) process to define the trench conductive layer 128, which is substantially coplanar with the dielectric material layer 126 and contacts the trench conductive layer 136 and/or the gate structure 112. The filled conductive material may be the same as the material of the trench conductive layer 128. In some embodiments, the filled conductive material may be a single layer of a platinum group metal material or a single layer of Mo. In some embodiments, the filled conductive material may be a multi-layer platinum group metal material or Mo. In some embodiments, the filled conductive material may be the same metal material (e.g., ru) as the metal material layer 130. The deposition process to form trench conductive layer 128 may include a deposition (CVD) process, an Atomic Layer Deposition (ALD) process, or a Physical Vapor Deposition (PVD) process. In some embodiments, the deposition process to form the trench conductive layer 128 may be a non-compliant deposition process with a higher deposition rate on the upper surface 130T of the metallic material layer 130 than on the upper surface of the dielectric material layer 126.

Referring to fig. 4, in operation 425, an interconnect structure is formed on the trench conductive layer. For example, as shown in fig. 1-3. As described with reference to fig. 16 and 1-3, an interconnect structure 140 may be formed on the trench conductive layer 128. Referring to fig. 16, the process of forming the interconnection structure 140 may include: (i) Using a deposition process and an etching process, a patterned insulating material layer 144 is formed on the structure of fig. 15 to expose the trench conductive layer 128; (ii) Blanket depositing a conductive material over the patterned insulating material layer 144 using a deposition process; (iii) The deposited conductive material is polished using a Chemical Mechanical Polishing (CMP) process to form a layer of conductive material 146 that is substantially coplanar with the layer of insulating material 144. The process of forming the interconnection structure 140 may further include: (i) Blanket depositing a layer of insulating material 148 (shown in fig. 2A and 3) over the structure of fig. 16 using a deposition process (e.g., a deposition (CVD) process, a plasma-enhanced chemical vapor deposition (PECVD) process, a Physical Vapor Deposition (PVD), an Atomic Layer Deposition (ALD) process); (ii) Forming one or more recess structures (not shown in fig. 16), through the layer of insulating material 148, using a photolithography process and an etching process; and (iii) filling the one or more recess structures with a conductive material using a deposition process (e.g., a (CVD) process, an Atomic Layer Deposition (ALD) process, a Physical Vapor Deposition (PVD) process, or e-beam evaporation) and a polishing process (e.g., a Chemical Mechanical Polishing (CMP) process) to form a trench conductive layer 162 (shown in fig. 2A and 3). Since the metallic material layer 130 may be made of a platinum group metal material or Mo, the deposition process in operation 425 does not cause the metallic material to diffuse outward from the metallic material layer 130, and thus no void may be formed in the trench conductive layer 136 after operation 425 is performed.

The present disclosure provides a contact structure and a method of forming the same. The contact structure may be a source/drain (S/D) contact structure formed on a source/drain (S/D) region of the transistor structure. The contact structure may be made of one or more layers of a metallic material having reduced diffusivity. Accordingly, the contact structure may be free of voids during or after the process of forming the interconnect structure. Furthermore, the contact structure may be an unobstructed structure (e.g., a liner-free structure) because the metal material of the contact structure may have sufficient adhesion to the adjacent dielectric sidewalls of the contact structure. The metallic material of the contact structure may include a platinum group metal material (e.g., ru). Accordingly, the contact structure of the present disclosure may have a reduced resistance value compared to another contact structure made of cobalt or copper. Accordingly, one benefit of the present disclosure is to provide contact structures with enhanced structural integrity (e.g., no voids) and reduced resistance, thereby improving the reliability and performance of integrated circuits.

In some embodiments, a semiconductor structure may include: a substrate, a gate structure on the substrate, a dielectric material layer on the gate structure, a source/drain (S/D) contact layer through and adjacent to the gate structure, and a trench conductive layer on and in contact with the source/drain (S/D) contact layer. The source/drain (S/D) contact layer may include a platinum group metal material layer and a silicide layer formed between the substrate and the platinum group metal material layer. The top width of the platinum group metal material layer can be greater than or substantially equal to the bottom width of the bottom of the platinum group metal material layer.

In some embodiments, the platinum group metal material layer comprises a ruthenium layer, with side surfaces of the ruthenium layer in contact with the dielectric material layer. Further, the top width of the top of the platinum group metal material layer is from about 5nm to about 20nm. Additionally, the ratio of the height of the source/drain contact layer to the top width of the source/drain contact layer is from about 2 to about 5. In some embodiments, the trench conductive layer comprises a platinum group metal material in contact with the source/drain contact layer. Furthermore, the trench conductive layer is located on and in contact with the gate structure. In some embodiments, the semiconductor structure further comprises an oxide liner layer formed between the source/drain contact layer and the dielectric material layer.

In some embodiments, a method of forming a semiconductor structure may include: forming a source/drain (S/D) region on a substrate; forming a dielectric material layer on the source/drain (S/D) region; forming a recess structure in the dielectric material layer to expose a source/drain (S/D) region; depositing a first metal material layer in the groove structure at a first deposition rate, and depositing the first metal material layer on the dielectric material layer at a second deposition rate which is less than the first deposition rate; and forming a second metal material layer on and in contact with the first metal material layer.

In some embodiments, forming the groove structure includes forming the groove structure to have a width from about 5nm to about 20nm. In some embodiments, depositing the first metallic material layer includes depositing a platinum group metallic material within the recess structure to seal the recess structure. In some embodiments, depositing the first metallic material layer includes annealing the substrate with the deposited first metallic material layer prior to forming the second metallic material layer. In some embodiments, the method further comprises forming a silicide layer between the first metal material layer and the source/drain region, wherein forming the silicide layer comprises forming a metal oxide layer on a side surface of the recess structure. Furthermore, the method further comprises an atomic layer etching process to selectively etch the metal oxide layer on the silicide layer. In some embodiments, the method further comprises forming a gate structure adjacent to the source/drain region, wherein forming the second metal material layer comprises forming the second metal material layer over and in contact with the gate structure.

In some embodiments, a method of forming a semiconductor structure may include: forming first and second gate structures on a substrate; forming a dielectric material layer on the first and second gate structures; forming a recess structure in the dielectric material layer and between the first and second gate structures; forming a first metal material layer to fill and seal the groove structure; forming a second metal material layer on and in contact with the first metal material layer; and forming an interconnect structure on and in contact with the second metal material layer. The first and second metallic material layers may comprise the same platinum group metal material.

In some embodiments, forming the first and second gate structures includes forming the first and second gate structures with a spacing of from about 30nm to about 60 nm. Further, forming the trench structure includes forming the trench structure to have a width from about 5nm to about 20nm. In some embodiments, forming the first metallic material layer includes growing a platinum group metal material within the recess structure at a first growth rate and growing the platinum group metal material on the dielectric material layer at a second growth rate that is less than the first growth rate. In some embodiments, forming the second layer of metallic material includes forming the second layer of metallic material in contact with the first gate structure. In some embodiments, forming the first gate structure and the second gate structure comprises: forming a first gate structure on a fin structure, and forming a second gate structure separated from the fin structure on a shallow trench isolation region.

The foregoing has outlined rather broadly the features of several embodiments of the present invention so that those skilled in the art may better understand the aspects of the present disclosure. It should be appreciated by those skilled in the art that the present disclosure may be readily utilized as a basis for modifying or designing other processes or structures for carrying out the same purposes and/or obtaining the same advantages of the embodiments described herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor structure, comprising:

a substrate;

a gate structure on the substrate;

a dielectric material layer on the gate structure;

a source/drain contact layer through and adjacent to the gate structure, wherein the source/drain contact layer comprises a platinum group metal material layer and a silicide layer formed between the substrate and the platinum group metal material layer, wherein a top width of a top of the platinum group metal material layer is greater than or equal to a bottom width of a bottom of the platinum group metal material layer; and

a trench conductive layer overlying and in contact with the source/drain contact layer.