CN115563927A - Chip wiring method for accelerating construction of minimum right-angle Steiner tree by GPU - Google Patents
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Abstract
The invention discloses a chip wiring method for accelerating construction of a minimum right-angle Steiner tree by a GPU (graphics processing Unit), belongs to the technical field of integrated circuit design automation, relates to the integrated circuit chip wiring technology, designs a minimum right-angle Steiner tree construction method for accelerating calculation of the GPU applied to chip wiring, accelerates the Steiner tree search process of a plurality of wire nets by using the GPU in a large-scale parallel manner, and comprises the following steps: initializing a lookup table, acquiring a flattened Steiner tree branch list and a branch lookup table index, and copying from a CPU memory to a GPU memory; initializing the net data, obtaining a pin list and a pin initial position index of the net, and copying the pin list and the pin initial position index from a CPU memory to a GPU memory; parallel division of the wire mesh, and establishment of a layered wire mesh division forest; parallel solving and merging of wire nets; the technical scheme provided by the invention improves the calculation efficiency of the wiring of the integrated circuit chip.
Description
Technical Field
The invention belongs to the technical field of integrated circuit design automation, relates to a Steiner tree construction technology in an integrated circuit chip wiring technology, and particularly relates to a minimum right-angle Steiner tree construction method for GPU accelerated calculation, which is used for chip wiring.
Background
Routing is a core step in chip design, in which the chip design automation system calculates the routing scheme for each net in the chip. A net in a chip is a collection of chip pins, each pin being a two-dimensional coordinate representing its location on the chip. The task of chip routing is to use metal wires to connect pins inside each net. In early steps of chip design, the scheme of routing is typically approximated using a Minimum orthogonal Steiner Minimum Tree (RSMT). For a given net, all pins of the net are connected by using only horizontal lines and vertical lines, and a right-angle Steiner tree can be obtained through any transit point. The minimum rectangular steiner tree is defined as the rectangular steiner tree with the shortest bus length.
Because the minimum rectangular steiner tree construction problem is difficult to solve accurately, the existing method pursues balance in time and solving accuracy. Among them, fast Look-Up Table Estimation (FLUTE) is the most typical method, and can achieve higher calculation efficiency while maintaining better solution accuracy. However, as the scale of chip design continues to increase, one wire routing requires solving the minimum orthogonal steiner tree for millions of nets, which takes a lot of time. The existing method including FLUTE only supports running on a CPU, is limited by the parallel capability and the memory scheduling capability of a multi-core CPU, can only utilize the parallel computing resources of 16 threads at most, and is difficult to efficiently finish the rapid wiring estimation of a large-scale circuit.
Disclosure of Invention
The invention aims to provide a minimum right-angle Steiner tree construction method for GPU accelerated computation, which can efficiently finish the quick wiring estimation of a large-scale circuit so as to overcome the defects of the conventional minimum right-angle Steiner tree construction method.
The invention designs the Steiner tree searching process into a GPU-friendly breadth-first computing process, and simultaneously processes the minimum right-angle Steiner tree construction task of a large number of nets by utilizing the large-scale data parallel computing capability of the GPU. On the premise of not reducing the solving precision, the construction efficiency of the minimum right-angle Steiner tree is improved, and the calculation efficiency of the wiring of the integrated circuit chip is improved.
The technical scheme of the invention is as follows:
a chip wiring method for building a minimum right-angle Steiner tree by GPU accelerated calculation comprises the following steps: initializing a lookup table, initializing net data, parallelly dividing nets, and parallelly solving and merging nets. In the initialization process of the lookup table, a minimum right-angle Steiner tree lookup table is constructed for all the nets with the number of the net degrees smaller than the threshold value of the lookup table by using a fast lookup table estimation method (FLUTE); flattening the minimum right-angle Steiner tree lookup table to obtain a flattened Steiner tree branch list and a branch lookup table index; and copying the flattened Steiner tree branch list and the branch lookup table index from the CPU memory to the GPU video memory. In the process of initializing the online network data, flattening the input wire network to obtain a pin list and a pin initial position index of the wire network, and copying the pin list and the initial position index from a CPU memory to a GPU memory. In the step of net parallel segmentation, performing iterative segmentation on a pin list and a pin initial position index of a net on a GPU to establish a layered net segmentation forest; and repeating the segmentation operation on the obtained pin list and the pin initial position index of the next-layer wire mesh until the number of the pins of all the wire meshes is smaller than the threshold value of the lookup table. In the process of parallel solving and merging of the wire nets, the divided wire nets are solved on a GPU, if the degree is smaller than the threshold value of a lookup table, the minimum right-angle Steiner tree of the wire net is obtained through a flattened Steiner tree branch list and a branch lookup table index, and if the degree is greater than the threshold value of the lookup table, the minimum right-angle Steiner tree of the wire net is obtained through merging of the solving results of the lower-layer wire net; the sequence of solving the net is from the lower layer to the upper layer on the layered net segmentation forest; and obtaining a combination result of the top-layer wire network, namely a solving result of the minimum right-angle Steiner tree of the input wire network. The method specifically comprises the following steps:
A. initializing a lookup table;
and constructing a minimum right-angle Steiner tree lookup table for all the wire nets of which the wire net degree number is smaller than a lookup table threshold value in the chip by using FLUTE, wherein the minimum right-angle Steiner tree lookup table comprises mapping from the relative position codes of the wire net pins to the potential minimum right-angle Steiner tree, the wire net degree number is defined as the pin number in the wire nets, the potential minimum right-angle Steiner tree is obtained by using a FLUTE method, and the lookup table threshold value is a constant.
Flattening the minimum rectangular Steiner tree lookup table to obtain a flattened Steiner tree branch list and a branch lookup table index. Storing all branches of the potential minimum right-angle Steiner tree in an array according to the relative position coding sequence of pins, so that the last branch of the last Steiner tree is adjacent to the first branch of the next Steiner tree, and the obtained branch array is a flattened Steiner tree branch list; and calculating the subscript of the first branch of each potential minimum rectangular Steiner tree in the array to obtain a branch lookup table index.
And copying the flattened Steiner tree branch list and the branch lookup table index from the CPU memory to the GPU memory.
B. Net data initialization
Flattening all the nets (namely input nets) in the chip to obtain a pin list and a pin initial position index of the nets, wherein the pin list of the nets comprises an abscissa list and an ordinate list. The specific process is that all pins in the input wire mesh are expressed as an abscissa and an ordinate, the abscissa and the ordinate are respectively stored in two arrays according to the wire mesh number sequence, and an abscissa list and an ordinate list are obtained, namely the pin list of the wire mesh; and calculating subscripts of the first pin of each wire mesh in the abscissa list and the ordinate list to obtain a pin initial position index.
And copying the pin list and the initial position index from the CPU memory to the GPU video memory.
C. Wire mesh parallel partitioning
And iteratively segmenting a pin list and a pin initial position index of the wire mesh on the GPU, and establishing a layered wire mesh segmentation forest, wherein the wire mesh segmentation forest is composed of a plurality of wire mesh segmentation trees, a node of each wire mesh segmentation tree is the wire mesh, a tree edge connecting a father node and a child node represents a child node wire mesh obtained by segmenting the father node wire mesh, a root node is an input wire mesh, and a leaf node is the wire mesh which does not need to be segmented continuously, namely the number of pins is less than the threshold value of the lookup table.
The specific process of iterative division is to perform division operation from the input net, which constitutes the first layer of nets. And for each wire mesh in the layer, obtaining the interval where the pin of the wire mesh is located in the wire mesh pin list through the pin initial position index. For the line network of which the degree is less than the threshold value of the lookup table, no operation is performed; and selecting one pin as a dividing point for the line nets with the degrees larger than or equal to the threshold value of the lookup table, and dividing the line net into two line nets with smaller degrees, namely the sub-nodes of the current line net on the line net dividing tree. The specific way of dividing is to divide the original net into upper and lower parts or left and right parts, try a plurality of division schemes, select the pins and the directions of the division points to make the divided nets as uniform as possible, enumerate all the pins and the directions of the division points, calculate the difference between the degrees of the two nets obtained by the division, and select the division scheme which can minimize the difference between the degrees. And (4) segmenting each original net to obtain a plurality of groups of child nodes. And connecting each wire mesh obtained by division to the original wire mesh by using the tree edge of the wire mesh division tree to obtain a pin list of the next wire mesh. And repeating the segmentation operation on the obtained pin list and the pin initial position index of the next-layer wire mesh until the number of the pins of all the wire meshes is smaller than the threshold value of the lookup table.
D. Wire mesh parallel solution merging
The split nets are solved on the GPU. The concrete way of solving is:
1. if the degree of the wire network is smaller than the threshold value of the lookup table, the minimum right-angle Steiner tree of the wire network is obtained through the flattened Steiner tree branch list and the branch lookup table index.
2. If the degree is greater than the threshold value of the lookup table, the minimum right-angle Steiner tree of the lower-layer wire network is obtained by combining the solving results of the lower-layer wire network, and the specific method is to connect the minimum right-angle Steiner trees of the lower-layer wire network at the dividing points. And taking the scheme with the minimum straight angle Steiner tree bus length as the division scheme of the local wire network for a plurality of division schemes.
The order in which nets are solved is from bottom to top on a layered net splitting forest. And obtaining a merging result of the top-layer wire network, namely a solving result of the minimum right-angle Steiner tree of the input wire network.
Compared with the prior art, the invention has the beneficial effects that:
according to the invention, through flattening the Steiner tree lookup table and the wire network data (namely steps A and B), the minimum rectangular Steiner tree searching process is reconstructed into a GPU-friendly breadth-first computing process (namely steps C and D), and the large-scale data parallel computing capacity of the GPU is utilized to simultaneously process the minimum rectangular Steiner tree construction tasks of a large number of wire networks. On the premise of not reducing the solving precision, the construction efficiency of the minimum right-angle Steiner tree is improved, and the wiring estimation of the integrated circuit chip is efficiently realized.
Drawings
Fig. 1 is a flowchart of a chip routing method for building a minimum right-angle steiner tree by using GPU accelerated computation according to the present invention.
FIG. 2 is a schematic diagram of a minimum orthogonal Steiner tree. Where the solid dots represent the four pins of the wire mesh and the solid lines represent the metal wires on the Steiner tree.
FIG. 3 is a schematic diagram of wire mesh pin coordinates and relative position coding. Wherein, pin 0 to Pin 3 represent four pins of the wire net, xs0 to xs3 represent the result of the sequence of the horizontal coordinates of the four pins from small to large, ys0 to ys3 represent the result of the sequence of the vertical coordinates of the four pins from small to large, and s0 to s3 represent the relative position code of the pins of the wire net.
FIG. 4 is a schematic diagram of a forest segmented with layered nets. Layer represents the level of the node, m represents the number of the last Layer, the number starts from 0, and Layer 0 is the first Layer. Net0 to Net n represent 0 th to nth nets, subletXX represents a sub-node Net with the number XX, and an arrow represents a tree edge of a Net partition tree.
FIG. 5 is a process diagram of net parallel partitioning and net parallel solution merging. The meanings of net and subnet are the same as the definitions of fig. 4, the right-side word sample is divided to mark the position of the wire mesh parallel division step, the right-side word sample is combined to mark the position of the wire mesh parallel solving combination step, the axis marked with time on the left side is the time axis of the processing process of the method, and RSMTXX represents the minimum right-angle Steiner tree of the XX wire mesh obtained through calculation.
Detailed Description
The invention will be further illustrated by way of example, without in any way limiting its scope, with reference to the accompanying drawings.
The invention provides a method for constructing a minimum right-angle Steiner tree for chip wiring by GPU accelerated calculation, which can efficiently construct the minimum right-angle Steiner tree shown in figure 2 and realize chip wiring. The method comprises the following steps: initializing a lookup table, initializing net data, partitioning nets in parallel, and solving and merging nets in parallel (such as figure 1). The method specifically comprises the following steps:
A. look-up table initialization
A minimum orthogonal Steiner tree lookup table is constructed using FLUTE for all nets having a number of net degrees less than a lookup table threshold, the lookup table containing a mapping from the pin relative position codes of the nets to the potential minimum orthogonal Steiner tree. The coding mode of the pin relative position coding of the wire net is shown in fig. 3, firstly, respectively sequencing the horizontal and vertical coordinates of all pins to obtain xs and ys arrays which represent the sequenced horizontal and vertical coordinates; then, an s array is calculated, the kth position of the array represents the ordinate ranking of the kth small pin of the abscissa ranking, and the s array is the relative position code of the pins of the wire mesh. The specific construction process of the minimum right-angle Steiner tree lookup table adopts a FLUTE method. The lookup table threshold is a constant, and in this embodiment, the default setting of FLUTE is adopted, and 9 is taken.
And flattening the minimum rectangular Steiner tree lookup table to obtain a flattened Steiner tree branch list and a branch lookup table index. Storing all branches of the potential minimum right-angle Steiner tree in an array according to the relative position coding sequence of pins, so that the last branch of the last Steiner tree is adjacent to the first branch of the next Steiner tree, and the obtained branch array is a flattened Steiner tree branch list; and calculating the subscript of the first branch of each potential minimum rectangular Steiner tree in the array to obtain a branch lookup table index. Pseudo code for computing the flattened Steiner Tree Branch List and Branch lookup Table indices is as follows:
TableOffset[0] <- 0
For i=1 To L
TableOffset[i] <- TableOffset[i-1] + TreeSize[i]
Memcopy(FlattenedBranch[TableOffset[i]], Branch[i], TreeSize[i])
End For
where i represents a loop variable, L represents the size of the minimum Cartesian Tree lookup table, brackets [ ] represent array addressing, treeSiz [ i ] represents the size of the ith potential minimum Cartesian Tree, the tableOffset array represents the Branch lookup Table index, memcopy represents the memory copy operation, the FlattinedBranch array represents the flattened Steiner Tree Branch list, and Branch [ i ] represents the Branch list of the ith potential minimum Steiner Tree.
And copying the flattened Steiner tree branch list and the branch lookup table index from the CPU memory to the GPU memory by calling a cudamememcpyAsync function at the CUDA platform.
B. Net data initialization
Flattening the input wire mesh to obtain a pin list and a pin initial position index of the wire mesh, wherein the pin list of the wire mesh comprises an abscissa list and an ordinate list. The specific process is that all pins in an input wire mesh are expressed as an abscissa and an ordinate, the abscissa and the ordinate are respectively stored in two arrays according to the serial number sequence of the wire mesh to obtain an abscissa list and an ordinate list, and the abscissa list and the ordinate list are the pin list of the wire mesh; and calculating subscripts of the first pin of each wire mesh in the abscissa list and the ordinate list to obtain a pin initial position index. The pseudo code for calculating the abscissa list, the ordinate list and the pin start position index is as follows:
NetOffset[0] <- 0
For i=1 To N
NetOffset[i] <- NetOffset[i-1] + NetDegree[i]
Memcopy(FlattenedX[NetOffset[i]], X[i], NetDegree[i])
Memcopy(FlattenedY[NetOffset[i]], Y[i], NetDegree[i])
End For
wherein NetDegreee [ i ] represents the degree of the ith net, netOffset represents the index of the initial position of the pin, X [ i ] and Y [ i ] respectively represent the abscissa and the ordinate of all pins of the current ith net, and FlattenedX and FlattenedY respectively represent an abscissa list and an ordinate list.
The pin list and the starting position index are copied from the CPU memory to the GPU memory by calling the cudaMemcpyAsync function at the CUDA platform.
C. Wire mesh parallel partitioning
And iteratively segmenting a pin list and a pin initial position index of the net on the GPU, and establishing a layered net segmentation forest. As shown in fig. 4, the net segmentation forest is composed of a plurality of net segmentation trees, a node of each net segmentation tree is a net, a tree edge connecting a father node and a child node represents a child node net obtained by segmenting the father node net, a root node is an input net, and a leaf node is a net which does not need to be segmented continuously, that is, a net with pins less than a threshold of a lookup table. As in fig. 4, net0 is a root node and is the first net of inputs; subnet00 is a net with pins less than the threshold of the lookup table, and has no need of continuous division and no child nodes; subnet01 is a net with pins greater than or equal to the threshold of the lookup table, and has child nodes.
The specific process of iterative division is to perform the division operation starting from the input net, which constitutes the first layer net, i.e., layer 0 in fig. 4. And for each net in the layer, obtaining the section of the pin of the net in the net pin list through the initial pin position index. Defining the degree of the net as the number of pins in the net, and not performing any operation on the net with the degree smaller than the threshold value of the lookup table, such as subnet00 in fig. 4; for a net with the degree greater than or equal to the threshold of the lookup table, such as subnet01 in fig. 4, one of the pins is selected as a dividing point to divide the net into two nets with smaller degrees, i.e., two sub-nodes. The specific way of selecting the dividing point is to select pins and dividing directions that make the divided wire net as uniform as possible, and to divide the wire net into upper and lower parts or left and right parts. The smaller net obtained by division is connected to the original net by using the tree edge of the net division tree, and the pin list of the next-layer net is obtained, such as layer 1 from layer 0 in fig. 4. And repeating the division operation on the obtained pin list and the pin starting position index of the next-layer net, and obtaining layer 2 from layer 1 until the pin number of all nets is less than the threshold value of the lookup table.
In this embodiment, we record which net each child node comes from the previous layer, as shown in the Break stage of FIG. 5, so that the subsequent net parallel solution merge step can merge the results of the child node nets at the correct original net.
D. Wire mesh parallel solution merging
The split nets are solved on the GPU. The concrete way of solving is:
1. if the degree of the wire network is smaller than the threshold value of the lookup table, the minimum right-angle steiner tree of the wire network is obtained through the flattened branch list of the steiner tree and the index of the branch lookup table, for example, the sub net03 in fig. 5 is solved in the first step of Merge to obtain RSMT011. The specific method is to calculate the relative position code of the pin according to the method described in fig. 3, and obtain the section of all branches of the minimum right-angle steiner tree in the branch list through the branch lookup table index. The specific implementation method is to use the tableOffset array in step A, and if the pin relative position code corresponds to the ith position of the minimum rectangular Steiner tree lookup table, the interval in the branch list is TableOffset [ i ] to TableOffset [ i +1] -1. These branches constitute the smallest orthogonal steiner tree of the present net.
2. If the degree is greater than the threshold value of the lookup table, the minimum right-angle Steiner tree of the lower-layer wire network is obtained by combining the solving results of the lower-layer wire network, and the specific method is to connect the minimum right-angle Steiner trees of the lower-layer wire network at the dividing points. For a plurality of division schemes, the scheme with the minimum straight angle Steiner tree bus length is taken as the division scheme of the local wire network. RSMT000 and RSMT011 are combined to obtain RSMT00 in fig. 4.
The order of solving the net is from the lower layer to the upper layer on the layered net segmentation forest, which is opposite to the order of parallel net segmentation, and is represented as the Break part and the Merge part in mirror symmetry in FIG. 4. In fig. 4, after RSMT000 and RSMT011 are combined to obtain RSMT00, RSMT01 is continuously combined, RSMT02 and RSMT03 are combined to obtain two right-angle steiner trees of net0, and RSMT0 is obtained by taking the minimum bus length. And obtaining the merging results RSMT0 and RSMT1 of the top-layer net, namely the solving result of the minimum right-angle Steiner tree of the input net.
It is noted that the disclosed embodiments are intended to aid in further understanding of the invention, but those skilled in the art will appreciate that: various alternatives and modifications are possible without departing from the invention and scope of the appended claims. Therefore, the invention should not be limited to the embodiments disclosed, but the scope of the invention is defined by the appended claims.
Claims (6)
1. A chip wiring method for accelerating construction of a minimum right-angle Steiner tree by a GPU is characterized by comprising the following steps:
A. initializing a lookup table, acquiring a flattened Steiner tree branch list and a branch lookup table index, and copying the flattened Steiner tree branch list and the branch lookup table index from a CPU memory to a GPU memory; the method comprises the following steps:
A1. constructing a minimum right-angle Steiner tree lookup table for all the nets of which the number of the net degrees is smaller than the threshold value of the lookup table in the chip; the minimum rectangular Steiner tree lookup table contains a mapping from net pin relative position codes to potential minimum rectangular Steiner trees; the lookup table threshold is a constant;
A2. flattening the minimum right-angle Steiner tree lookup table to obtain a flattened Steiner tree branch list and a branch lookup table index; storing all branches of the potential minimum right-angle Steiner tree in an array according to a pin relative position coding sequence, enabling the last branch of the last Steiner tree to be adjacent to the first branch of the next Steiner tree, and obtaining a branch array which is a flattened Steiner tree branch list; calculating subscripts of the first branches of each potential minimum rectangular Steiner tree in the array to obtain branch lookup table indexes;
A3. copying a flattened Steiner tree branch list and a branch lookup table index from a CPU memory to a GPU memory;
B. initializing the net data, obtaining a pin list and a pin initial position index of the net, and copying the pin list and the pin initial position index from a CPU memory to a GPU memory;
B1. flattening the input wire nets to obtain pin lists and pin initial position indexes of the wire nets, wherein the pin lists of the wire nets comprise abscissa lists and ordinate lists;
B2. copying the pin list and the initial position index from the CPU memory to the GPU video memory;
C. parallel division of the wire mesh, and establishment of a layered wire mesh division forest;
iteratively dividing a pin list and a pin initial position index of a wire mesh on a GPU, and establishing a layered wire mesh division forest, wherein the wire mesh division forest is composed of a plurality of wire mesh division trees, a node of each wire mesh division tree is a wire mesh, a tree edge connecting a father node and a child node represents a child node wire mesh obtained by division of the father node wire mesh, a root node is an input wire mesh, and a leaf node is a wire mesh which does not need to be continuously divided, namely the number of pins is less than a lookup table threshold value;
the specific process of iterative segmentation comprises the following steps:
C1. performing a dividing operation from an input net, wherein the input net forms a first layer of net;
C2. for each wire mesh in the layer, obtaining the interval of the pin of the wire mesh in the wire mesh pin list through the pin initial position index;
C3. defining the number of pins of the net as the number of the pins in the net, and not performing any operation on the net with the number of pins smaller than the threshold value of the lookup table; selecting one pin of the net with the degree greater than or equal to the threshold value of the lookup table as a dividing point, and dividing the net into two nets, namely sub-nodes of the current net on the net dividing tree;
D. and (3) parallel solving and merging of the nets: solving the segmented net on the GPU in a specific mode that:
D1. if the degree of the wire network is smaller than the threshold value of the lookup table, the minimum right-angle Steiner tree of the wire network is obtained through the flattened Steiner tree branch list and the branch lookup table index, the specific method is to calculate the relative position code of the pins, and the section of all branches of the minimum right-angle Steiner tree in the branch list is obtained through the branch lookup table index, and the branches form the minimum right-angle Steiner tree of the wire network;
D2. if the degree of the net is greater than the threshold value of the lookup table, combining the solution results of the lower-layer net to obtain the minimum right-angle Steiner tree of the net, and specifically connecting the minimum right-angle Steiner trees of the lower-layer net at the division points; for a plurality of division schemes, taking the scheme with the minimum straight angle Steiner tree bus length as the division scheme of the local wire network;
D3. the sequence of solving the net is that the combined result of the top net is obtained from the lower layer to the upper layer on the layered net segmentation forest, namely the minimum right-angle Steiner tree solving result of the input net;
E. and according to the obtained minimum right-angle Steiner tree solving result of the input net, realizing the accelerated construction of the chip wiring of the minimum right-angle Steiner tree by the GPU.
2. The method for accelerating the chip wiring for constructing the minimum orthogonal Steiner tree by the GPU as claimed in claim 1, wherein in the step A3, the flattened Steiner tree branch list and the branch lookup table index are copied from the CPU memory to the GPU video memory by calling the cudamemcpyAsync function on the CUDA platform.
3. The method for the chip routing by the GPU for the accelerated construction of the minimum orthorhombic steiner tree as claimed in claim 1, wherein in step B1, the input net is flattened by representing all pins in the input net as abscissa and ordinate, and storing the abscissa and ordinate in two arrays respectively according to the net numbering sequence to obtain an abscissa list and an ordinate list, which are the pin lists of the net; and calculating subscripts of the first pin of each wire mesh in the abscissa list and the ordinate list to obtain a pin initial position index.
4. The method for accelerating the chip wiring for building the minimum orthogonal steiner tree by the GPU as claimed in claim 1, wherein in step B2, the pin list and the start position index are copied from the CPU memory to the GPU memory, specifically by calling a cudaMemcpyAsync function in the CUDA platform.
5. The method for accelerating the construction of the chip wiring of the minimum rectangular Steiner tree by the GPU as claimed in claim 1, wherein in the step C3, the specific mode of segmentation is as follows:
dividing an original wire net into an upper part, a lower part or a left part and a right part, trying a plurality of division schemes, and selecting a pin of a division point and a division direction to enable the divided wire net to be uniform;
each original net is segmented to obtain a plurality of groups of sub-nodes;
connecting each wire mesh obtained by segmentation to a corresponding original wire mesh by using the tree edge of the wire mesh segmentation tree to obtain a next wire mesh pin list;
and repeating the segmentation operation on the obtained pin list and the pin initial position index of the next layer of wire mesh until the number of the pins of all the wire meshes is less than the threshold value of the lookup table.
6. The method for accelerating the chip wiring for constructing the minimum orthogonal Steiner tree by the GPU as claimed in claim 5, wherein the method for making the divided nets uniform is specifically as follows: enumerating all the pin and the dividing direction of the dividing points, calculating the difference of degrees of the two wire nets obtained by dividing, and selecting the dividing scheme with the minimum difference of degrees.
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| CN116402006A (en) * | 2023-06-07 | 2023-07-07 | 南京集成电路设计服务产业创新中心有限公司 | Method for constructing complete optimal Steiner tree lookup table based on edge movement |
| CN116402010A (en) * | 2023-05-10 | 2023-07-07 | 南京邮电大学 | Multi-instantiation block top-level wiring method based on Steiner tree algorithm |
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| CN116402010A (en) * | 2023-05-10 | 2023-07-07 | 南京邮电大学 | Multi-instantiation block top-level wiring method based on Steiner tree algorithm |
| CN116402010B (en) * | 2023-05-10 | 2023-11-21 | 南京邮电大学 | Multi-instantiation block top-level wiring method based on Steiner tree algorithm |
| CN116402006A (en) * | 2023-06-07 | 2023-07-07 | 南京集成电路设计服务产业创新中心有限公司 | Method for constructing complete optimal Steiner tree lookup table based on edge movement |
| CN116402006B (en) * | 2023-06-07 | 2023-08-22 | 南京集成电路设计服务产业创新中心有限公司 | Method for constructing complete optimal Steiner tree lookup table based on edge movement |
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