CN115562579A

CN115562579A - Data storage method, chip and electronic equipment

Info

Publication number: CN115562579A
Application number: CN202211194218.6A
Authority: CN
Inventors: 雷超; 许智宁
Original assignee: Guangzhou Sirui Core Semiconductor Co ltd
Current assignee: Guangzhou Sirui Core Semiconductor Co ltd
Priority date: 2022-09-28
Filing date: 2022-09-28
Publication date: 2023-01-03

Abstract

The invention relates to the technical field of computers, and provides a data storage method, a chip and electronic equipment. The chip comprises a processor, a storage controller and a memory, wherein the processor sends a data writing instruction to the storage controller, and the data writing instruction comprises data to be written and a writing address; then the memory controller encrypts data to be written and a write address to obtain a first stored value, and sends the first stored value and the write address to the memory; finally, the memory stores the first stored value according to the write address. The data and the address are encrypted to obtain the stored value to be stored in the memory, and each data only needs one storage unit, so that the safety of the data is improved, the utilization rate of the storage space is improved, and the storage cost is reduced.

Description

Data storage method, chip and electronic equipment

Technical Field

The invention relates to the technical field of computers, in particular to a data storage method, a chip and electronic equipment.

Background

With the increasingly wide application of chips in the fields of industrial control, communication, internet of things and the like and the increasing development cost of product manufacturers, the importance of manufacturers on data protection is increasing, and chip designers also begin to take great care in the aspects of anti-reversal and anti-plagiarism.

At present, a mode of performing error check on read-write data is generally adopted to prevent data abnormality of a memory caused by attack means such as laser. However, when laser is irradiated on the control block address decoding area of the memory, address errors are easily caused, and such errors cannot be detected only by verifying read and write data, so that the problems of poor prevention effect and low reliability exist.

Disclosure of Invention

In view of the above, the present invention provides a data storage method, a chip and an electronic device.

In order to achieve the above purpose, the embodiment of the present invention adopts the following technical solutions:

in a first aspect, the present invention provides a data storage method applied to a chip, where the chip includes a processor, a storage controller, and a memory, and the method includes:

the processor sends a data writing instruction to the storage controller, wherein the data writing instruction comprises data to be written and a writing address;

the storage controller encrypts the data to be written and the write address to obtain a first stored value, and sends the first stored value and the write address to the memory;

the memory stores the first stored value according to the write address.

In an optional implementation manner, the step of encrypting, by the storage controller, the data to be written and the write address to obtain a first storage value includes:

the storage controller receives the data to be written and the write address, and calculates an address check value of the write address to obtain a first address check value;

and the storage controller encrypts the first address check value and the data to be written to obtain the first storage value.

In an alternative embodiment, the memory controller has a pre-stored address range;

after the step of the processor sending a data write instruction to the storage controller, the method further comprises:

when the storage controller judges that the write address does not belong to the address range, sending a write address error message to the processor;

and when the storage controller judges that the write address belongs to the address range, executing the step that the storage controller encrypts the data to be written and the write address to obtain a first storage value.

In an alternative embodiment, the method further comprises:

the processor sends a data reading instruction to the storage controller, wherein the data reading instruction comprises a reading address;

the memory controller reads a second storage value from the memory according to the read address, decrypts the second storage value to obtain target data and a second address check value, and then verifies the read address according to the second address check value;

if the verification is successful, the target data is sent to the processor;

and if the verification fails, sending a data reading failure message to the processor.

In an optional embodiment, the step of verifying the read address according to the second address check value includes:

the storage controller calculates an address check value of the read address to obtain a third address check value, and compares the third address check value with the second address check value to verify the read address;

if the third address check value is consistent with the second address check value, the verification is successful;

and if the third address check value is inconsistent with the second address check value, the verification fails.

after the step of the processor sending a data read instruction to the storage controller, the method further comprises:

when the memory controller determines that the read address does not belong to the address range, sending a read address error message to the processor;

and when the memory controller judges that the read address belongs to the address range, executing the step that the memory controller reads a second storage value from the memory according to the read address.

In a second aspect, the present invention provides a chip comprising a processor, a memory controller, and a memory;

the processor is used for sending a data writing instruction to the storage controller, wherein the data writing instruction comprises data to be written and a writing address;

the memory controller is used for encrypting the data to be written and the write address to obtain a first stored value and sending the first stored value and the write address to the memory;

the memory is configured to store the first stored value according to the write address.

In an alternative embodiment, the storage controller is further configured to:

receiving the data to be written and the write address, and calculating an address check value of the write address to obtain a first address check value; and encrypting the first address check value and the data to be written to obtain the first storage value.

In an alternative embodiment, the processor is further configured to: sending a data reading instruction to the storage controller, wherein the data reading instruction comprises a reading address;

the storage controller is further configured to: reading a second storage value from the memory according to the read address, decrypting the second storage value to obtain target data and a second address check value, and verifying the read address according to the second address check value; if the verification is successful, the target data is sent to the processor; and if the verification fails, sending a data reading failure message to the processor.

In a third aspect, the invention provides an electronic device comprising the chip as described in any of the previous embodiments.

The chip comprises a processor, a storage controller and a memory, wherein the processor sends a data writing instruction to the storage controller, and the data writing instruction comprises data to be written and a writing address; then the memory controller encrypts data to be written and a write address to obtain a first stored value, and sends the first stored value and the write address to the memory; finally, the memory stores the first stored value according to the write address. The data and the address are encrypted to obtain the stored value to be stored in the memory, and each data only needs one storage unit, so that the safety of the data is improved, the utilization rate of the storage space is improved, and the storage cost is reduced.

In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.

FIG. 1 is a block diagram of a chip provided by an embodiment of the invention;

FIG. 2 is a flow chart illustrating a data storage method according to an embodiment of the present invention;

FIG. 3 is a schematic flow chart illustrating a data storage method according to an embodiment of the present invention;

FIG. 4 is a diagram illustrating an example of a data storage method provided by an embodiment of the invention;

FIG. 5 is a schematic flow chart illustrating a data storage method according to an embodiment of the present invention;

FIG. 6 is a schematic flow chart illustrating a data storage method according to an embodiment of the present invention;

fig. 7 is a diagram illustrating a further example of a data storage method according to an embodiment of the present invention.

Icon: 100-chip; 110-a bus; 120-a processor; 130-a memory controller; 140-memory.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.

Thus, the following detailed description of the embodiments of the present invention, as presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without making any creative effort, shall fall within the protection scope of the present invention.

It is noted that relational terms such as "first" and "second," and the like, may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising a … …" does not exclude the presence of another identical element in a process, method, article, or apparatus that comprises the element.

At present, a mode of performing error check on read-write data is generally adopted to prevent data abnormality of a memory caused by attack means such as laser. However, when laser is irradiated on the control block address decoding area of the memory, address errors are easily caused, and such errors cannot be detected only by verifying read and write data, so that the problems of poor prevention effect and low reliability exist. Further, an embodiment of the present invention provides a data storage method to solve the above problem.

Fig. 1 is a block diagram of a chip according to an embodiment of the invention. Chip 100 includes bus 110, processor 120, memory controller 130, and memory 140.

Bus 110 may be a circuit that interconnects the above-described elements and passes information between the above-described elements. The information transferred by the bus may include addresses, data, address check values, stored values, comparison results, etc. The information transmitted each time is checked through the bus, so that errors are prevented from occurring when the information is transmitted in the bus, and the accuracy of information transmission is ensured.

Processor 120 may send instructions to write data or read data to memory controller 130 or memory 140 over bus 110.

The processor 120 may be an integrated circuit chip having signal processing capabilities. The Processor 120 may be a general-purpose Processor including a Central Processing Unit (CPU), a Network Processor (NP), and the like; but may also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), an off-the-shelf programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components.

Memory controller 130 may receive instructions from processor 120 or memory 140 to control the writing or reading of data.

Memory 140 may receive instructions from processor 120 or memory controller 130 to store data. The memory 140 includes a plurality of memory cells, each having a corresponding address.

The Memory 140 may be, but is not limited to, a Random Access Memory (RAM), a Read Only Memory (ROM), a Programmable Read-Only Memory (PROM), an Erasable Read-Only Memory (EPROM), and an electrically Erasable Read-Only Memory (EEPROM).

It is understood that the structure shown in fig. 1 is merely a schematic diagram of the structure of the chip 100, and the chip 100 may include more or less components than those shown in fig. 1, or have a different configuration than that shown in fig. 1. The components shown in fig. 1 may be implemented in hardware, software, or a combination thereof.

Optionally, the chip may be further externally connected with a storage device, and the data storage method provided in the embodiment of the present invention may also be used in a storage system including the chip and the storage device.

The chip is taken as an execution subject, and each step in each method provided by the embodiment of the invention is executed, and the corresponding technical effect is achieved.

Referring to fig. 2, fig. 2 is a schematic flowchart illustrating a data storage method according to an embodiment of the present invention.

Step S202, the processor sends a data writing instruction to the storage controller, wherein the data writing instruction comprises data to be written and a writing address;

step S204, the memory controller encrypts data to be written and a write address to obtain a first stored value, and sends the first stored value and the write address to the memory;

in step S206, the memory stores the first storage value according to the write address.

In this embodiment, when data needs to be stored, the processor acquires data to be stored, that is, data to be written, and an address corresponding to a storage unit for storing the data to be written, that is, a write address, and then the processor generates a data write instruction based on the data to be written and the write address, and sends the data write instruction to the storage controller.

The storage controller obtains data to be written and a write address from the received data write instruction, then encrypts the data to be written and the write address by adopting a preset encryption algorithm to obtain a first stored value, and sends the first stored value and the write address to the storage.

The memory acquires a target memory cell corresponding to the write address from all memory cells according to the received first storage value and the write address, and stores the first storage value in the target memory cell.

Based on the steps, the processor sends a data writing instruction to the storage controller, wherein the data writing instruction comprises data to be written and a writing address; then the memory controller encrypts data to be written and a write address to obtain a first stored value, and sends the first stored value and the write address to the memory; finally, the memory stores the first stored value according to the write address. The data and the address are encrypted to obtain the stored value to be stored in the memory, and each data only needs one storage unit, so that the safety of the data is improved, the utilization rate of the storage space is improved, and the storage cost is reduced.

Optionally, as for the step in which the storage controller encrypts the data to be written and the write address in step S204 to obtain the first storage value, a possible implementation manner is provided in the embodiment of the present invention, please refer to fig. 3.

Step S204-1, the storage controller receives data to be written and a written address, and calculates an address check value of the written address to obtain a first address check value;

and S204-3, the storage controller encrypts the first address check value and the data to be written to obtain a first storage value.

In this embodiment, after receiving a data write instruction sent by a processor, a storage controller obtains data to be written and a write address from the data write instruction, and then calculates an address check value of the write address by using a preset check algorithm to obtain a first address check value.

Alternatively, the check algorithm may be a parity check algorithm, an error correction code ECC check algorithm, a hamming check algorithm, a CRC check algorithm, and the like. It should be understood that the verification algorithm may be set according to practical situations, and the embodiment of the present invention is not limited thereto.

After the storage controller obtains the first address check value, the first address check value and the data to be written are encrypted to obtain a first storage value. Alternatively, the encryption algorithm in the present embodiment may be a plurality of encryption algorithms combined by simple arithmetic logic. Different combination sequences and calculation parameters can obtain different encryption results, certain randomness is achieved, and the difficulty of cracking is increased.

For example, the first is an additive encryption algorithm: y = x + a; the second is an exclusive-or encryption algorithm: y = x ^ b; the third is a displacement encryption algorithm: y = x < < c; wherein; y represents encrypted information; x represents information to be encrypted; a. b and c each represent an encrypted random number. It should be understood that the encryption algorithm may be set according to practical situations, and the embodiment of the present invention is not limited thereto.

To facilitate understanding, an exemplary diagram is provided in an embodiment of the present invention, please refer to fig. 4. The process of writing data will be described below with reference to fig. 4, in which the memory controller can be divided into a control unit and a write operation unit according to functions.

First, the processor sends a data write command to the memory controller, where the data write command includes data D1 to be written and a write address A1. Then, the control unit receives the data D1 to be written and the write address A1, calculates an address check value of the write address A1 to obtain a first address check value C1, and transmits the data D1 to be written and the first address check value C1 to the write operation unit; the write operation unit encrypts data D1 to be written and a first address check value C1 to obtain a first stored value S1; the control unit sends a write address A1 to the memory, and the write operation unit sends a first stored value S1 to the memory; finally, the memory stores the first stored value S1 according to the write address A1.

Optionally, the storage controller prestores an address range, that is, after the storage controller communicates with the memory, the address range of the memory can be obtained, and after the step S202, the storage controller may further determine whether the write address belongs to the address range; if not, go to step S208A; if so, go to step S208B.

Step S208A, when the storage controller judges that the write address does not belong to the address range, sending a write address error message to the processor;

and step S208B, when the storage controller judges that the writing address belongs to the address range, the storage controller encrypts the data to be written and the writing address to obtain a first storage value.

In this embodiment, in order to further improve the data security, after receiving a data write command sent by the processor, the memory controller may determine, based on the address range, a write address in the data write command, that is, determine whether the write address belongs to the address range.

If the write address does not fall within the address range, the memory controller sends a write address error message, such as an address error code, to the processor to notify the processor that the write address is out of range, i.e., the write address exceeds the address range or the write address is not present.

If the write-in address belongs to the address range, the storage controller calculates the address check value of the write-in address to obtain a first address check value, encrypts the first address check value and the data to be written to obtain a first stored value, and then sends the first stored value and the write-in address to the storage, so that the storage stores the first stored value according to the write-in address.

Optionally, based on the above manner of storing data, an embodiment of the present invention further provides a manner of reading data, please refer to fig. 5.

Step S212, the processor sends a data reading instruction to the storage controller, wherein the data reading instruction comprises a reading address;

step S214, the memory controller reads a second storage value from the memory according to the read address, and after decrypting the second storage value to obtain target data and a second address check value, verifies the read address according to the second address check value;

step S216A, if the verification is successful, target data are sent to the processor;

in step S216B, if the verification fails, a data reading failure message is sent to the processor.

In this embodiment, when data needs to be read, the processor acquires an address corresponding to a storage unit where the data to be read is located, that is, a read address, and then generates a data read instruction based on the read address, and sends the data read instruction to the storage controller.

The storage controller acquires a reading address from the received data reading instruction and reads a second storage value from the storage according to the reading address; then, carrying out decryption processing on the second stored value by adopting a preset decryption algorithm to obtain target data and a second address check value; and verifying the read address according to the second address check value.

Optionally, for the encryption algorithm provided above, the embodiment of the present invention also provides a corresponding decryption algorithm. For example, the decryption algorithm corresponding to the first addition encryption algorithm is a subtraction decryption algorithm, that is: x = y-a; the decryption algorithm corresponding to the second xor encryption algorithm is an xor decryption algorithm, that is: x = y ^ b; the decryption algorithm corresponding to the third displacement encryption algorithm is a displacement decryption algorithm, that is: x = y > > c; wherein; y represents information to be decrypted; x represents the decrypted information; a. b and c both represent encrypted random numbers. It should be understood that the decryption algorithm may be set according to practical situations, and the embodiment of the present invention is not limited thereto.

The storage controller verifies the read address according to the second address check value, and if the verification is successful, the storage controller sends target data to the processor; if the verification fails, the storage controller sends a data read failure message, such as a check error code, to the processor to inform the processor that the read address verification failed.

Optionally, as to the step of verifying the read address according to the second address check value in the step S214, a possible implementation manner is provided in the embodiment of the present invention, please refer to fig. 6.

Step S214-1, the storage controller calculates an address check value of the read address to obtain a third address check value, and compares the third address check value with the second address check value to verify the read address;

step S214-3a, if the third address check value is consistent with the second address check value, the verification is successful;

in step S214-3b, if the third address check value is inconsistent with the second address check value, the verification fails.

In this embodiment, after receiving a data read instruction sent by a processor, a storage controller obtains a read address from a data write instruction, and then calculates an address check value of the read address by using a preset check algorithm to obtain a third address check value.

And after obtaining the second address check value and the third address check value, the storage controller compares the third address check value with the second address check value so as to verify the read address. If the comparison result is that the third address check value is consistent with the second address check value, the verification is judged to be successful; and if the comparison result is that the third address check value is inconsistent with the second address check value, judging that the verification fails.

To facilitate understanding, an example diagram is provided in an embodiment of the present invention, please refer to fig. 7. The process of reading data will be described with reference to fig. 7, in which the memory controller may be divided into a control unit and a read operation unit according to functions.

First, the processor sends a data read instruction to the memory controller, the data read instruction including a read address A2. Then, the control unit receives the reading address A2 and sends the reading address A2 to the memory, and the memory acquires a second stored value S2 according to the reading address A2 and sends the second stored value S2 to the reading operation unit; the control unit calculates an address check value of the read address A2 to obtain a third address check value C2, and sends the read address A2 and the third address check value C2 to the read operation unit.

The read operation unit decrypts the second stored value S2 according to the read address A2 to obtain the target data D2 and the second address verification value C2', and compares the third address verification value C2 with the second address verification value C2'.

If the third address check value C2 is identical to the second address check value C2', that is, C2= C2', the read operation unit transmits the comparison result, that is, the verification is successful, to the control unit, and the control unit sends the target data D2 to the processor; if the third address check value C2 is not consistent with the second address check value C2', i.e. C2 ≠ C2', the read operation unit transmits the comparison result, i.e. the verification failure, to the control unit, and the control unit sends a data reading failure message to the processor.

Optionally, the storage controller prestores an address range, that is, after the storage controller communicates with the memory, the address range of the memory can be obtained, and after the step S212, the storage controller may further determine whether the read address belongs to the address range; if not, go to step S218A; if yes, go to step S218B.

Step S218A, when the storage controller judges that the read address does not belong to the address range, a read address error message is sent to the processor;

in step S218B, when the memory controller determines that the read address belongs to the address range, the memory controller performs a step of reading the second stored value from the memory according to the read address.

In this embodiment, in order to further improve the data security, after receiving a data read command sent by the processor, the memory controller may determine, based on the address range, a read address in the data read command, that is, determine whether the read address belongs to the address range.

If the read address does not fall within the address range, the memory controller sends a read address error message, such as an address error code, to the processor to notify the processor that the read address is out of range, i.e., the read address exceeds the address range or the read address is not present.

If the read address belongs to the address range, the memory controller calculates the address check value of the read address to obtain a third address check value, reads a second stored value from the memory according to the read address, then decrypts the second stored value to obtain target data and the second address check value, and then compares the third address check value with the second address check value.

If the third address check value is consistent with the second address check value and indicates that the verification is successful, the storage controller sends target data to the processor; and if the third address check value is inconsistent with the second address check value and indicates that the verification fails, the storage controller sends a data reading failure message to the processor.

In order to perform the corresponding steps in the above embodiments and various possible manners, an implementation manner of the chip is given below. It should be noted that the basic principle and the generated technical effect of the chip provided by the embodiment are the same as those of the above embodiment, and for the sake of brief description, no part of the present embodiment is mentioned, and corresponding contents in the above embodiment may be referred to. The chip includes a processor, a memory controller, and a memory.

The processor is used for sending a data writing instruction to the storage controller, and the data writing instruction comprises data to be written and a writing address;

the memory is used for storing a first storage value according to the write address.

Optionally, the storage controller is further configured to: receiving data to be written and a write address, and calculating an address check value of the write address to obtain a first address check value; and encrypting the first address check value and the data to be written to obtain a first storage value.

Optionally, the storage controller is further configured to: when the write address is judged not to belong to the address range, sending a write address error message to the processor; and when the write address is judged to belong to the address range, executing the step of encrypting the data to be written and the write address to obtain a first storage value.

Optionally, the processor is further configured to: sending a data reading instruction to a storage controller, wherein the data reading instruction comprises a reading address;

the storage controller is further configured to: reading a second storage value from the memory according to the reading address, decrypting the second storage value to obtain target data and a second address check value, and verifying the reading address according to the second address check value; if the verification is successful, sending target data to the processor; and if the verification fails, sending a data reading failure message to the processor.

Optionally, the storage controller is further configured to: calculating an address check value of the read address to obtain a third address check value, and comparing the third address check value with the second address check value to verify the read address; if the third address check value is consistent with the second address check value, the verification is successful; if the third address check value is not consistent with the second address check value, the verification fails.

Optionally, the storage controller is further configured to: when the read address is judged not to belong to the address range, sending a read address error message to the processor; when it is determined that the read address belongs to the address range, a step of reading the second stored value from the memory in accordance with the read address is performed.

The invention also provides electronic equipment which comprises the chip provided by the embodiment of the invention, and the chip can be used for realizing the data storage method disclosed by the embodiment. Alternatively, the electronic device may be a smart phone, a Personal Computer, a tablet Computer, a wearable device, a notebook Computer, an Ultra-mobile Personal Computer (UMPC), a netbook, a Personal Digital Assistant (PDA), and the like, which are not limited in this respect.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A data storage method applied to a chip, the chip comprising a processor, a storage controller and a memory, the method comprising:

the memory controller encrypts the data to be written and the write address to obtain a first stored value, and sends the first stored value and the write address to the memory;

the memory stores the first stored value according to the write address.

2. The method according to claim 1, wherein the step of encrypting, by the memory controller, the data to be written and the write address to obtain a first stored value comprises:

the storage controller receives the data to be written and the written address, and calculates an address check value of the written address to obtain a first address check value;

3. The method of claim 1, wherein the memory controller has a pre-stored address range;

4. The method of claim 1, further comprising:

if the verification is successful, the target data is sent to the processor;

5. The method of claim 4, wherein the step of verifying the read address according to the second address check value comprises:

6. The method of claim 4, wherein the memory controller has a pre-stored address range;

7. A chip, wherein the chip comprises a processor, a memory controller, and a memory;

8. The chip of claim 7, wherein the memory controller is further configured to:

9. The chip of claim 7, wherein the processor is further configured to: sending a data reading instruction to the storage controller, wherein the data reading instruction comprises a reading address;

10. An electronic device comprising a chip as claimed in any one of claims 7 to 9.