CN115562465B - Resetting method and system for soft core processor in FPGA system - Google Patents
Resetting method and system for soft core processor in FPGA system Download PDFInfo
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Abstract
The invention discloses a resetting method and a resetting system for a soft core processor in an FPGA (field programmable gate array) system, and relates to the technical field of FPGAs. The method comprises the following steps: resetting a preset soft core processor in the FPGA system through a preset reset signal, and executing a reset flow of the soft core processor; the control target soft core processor is kept in a reset state; acquiring an original value in a preset address of a memory where a program running environment of a target soft core processor of the FPGA system is located and a preset length of specific data; covering the original value of the specific data in a preset address of the memory and covering the original value of the specific data as a preset length; releasing the preset reset signal, suspending reset and ending the reset. When the soft-core processor is reset, the invention ensures that the execution environment is restored to the initial state, and the specific data in the memory is restored to the initial value, thereby helping the normal reset of the soft-core processor system.
Description
Technical Field
The invention relates to the technical field of FPGA (field programmable gate array), in particular to a method and a system for resetting a soft core processor in an FPGA system.
Background
An FPGA (Field Programmable Gate Array field programmable gate array) is a semiconductor device that can be programmed to perform logic functions desired by a user. FPGAs can provide both powerful computing power and sufficient flexibility, allowing custom solutions to be developed for complex tasks; the processing performance of the computationally intensive tasks can be improved through parallelization; the flexibility is high, the instantaneity is strong, and the development period is short. The FPGA is widely applied to a plurality of fields such as medical treatment, military industry, aerospace, communication, image processing, artificial intelligence and the like.
The soft-core processor (Softcore Microprocessor) is a processor implemented by FPGA logic. By embedding a soft core processor in the FPGA system, the execution capability of the FPGA system software can be endowed. On one hand, the task flexibility of the FPGA system can be obviously improved, and on the other hand, the requirements of an external system processor can be reduced, so that the number of system chips is reduced, the area of a circuit board is reduced, and the system has great advantages in various aspects such as volume, weight, power consumption, cost and the like. Therefore, the soft-core embedded processor has important application prospect.
The FPGA realizes environment initialization and function configuration through configuration operation. When the FPGA executes the configuration operation, a configuration file is firstly obtained, and the configuration file describes the logic structure of the FPGA and the initial value of the memory data. The FPGA realizes the establishment of internal logic functions and the initialization of memory data by writing configuration files into an internal configuration memory.
According to the configuration process, the FPGA logic structure and the memory data initialization are performed simultaneously, and the memory data cannot be independently initialized; however, the soft-core processor reset requires that specific data (such as a data segment) in the memory should be restored to an initial value, so that the soft-core processor cannot be reliably reset directly in the FPGA system.
Disclosure of Invention
The invention aims to solve the technical problem of overcoming the defects of the prior art and provides a method and a system for resetting a soft core processor in an FPGA system.
The technical scheme for solving the technical problems is as follows:
a reset method of a soft core processor in an FPGA system comprises the following steps:
resetting a preset soft core processor in the FPGA system through a preset reset signal, and executing a reset flow of the soft core processor;
the control target soft core processor is kept in a reset state;
acquiring an original value in a preset address of a memory where a program running environment of a target soft core processor of the FPGA system is located and a preset length of specific data;
covering the original value of the specific data in a preset address of the memory and covering the original value of the specific data as a preset length;
releasing the preset reset signal, suspending reset and ending the reset.
The beneficial effects of the invention are as follows: in the prior art, when the soft core processor is reset, in order to ensure that the execution environment is restored to the initial state, specific data in the memory is required to be restored to the initial value. However, since the FPGA system is not reconfigured at this time, the above requirements cannot be met, resulting in a soft-core processor system reset exception. When the soft-core processor is reset, the invention ensures that the execution environment is restored to the initial state, and the specific data in the memory is restored to the initial value, thereby helping the normal reset of the soft-core processor system.
Further, the method comprises the steps of: one or more target soft-core processors, each corresponding to a preset reset signal;
resetting a preset soft core processor in an FPGA system through a preset reset signal, and executing a reset process of the soft core processor, wherein the reset process comprises the following steps of:
resetting a corresponding preset soft core processor in the FPGA system through each preset reset signal, and executing a reset flow of the soft core processor.
The beneficial effects of adopting the further scheme are as follows: separate or simultaneous resets supporting one or more soft-core processors may be implemented.
Further, the original value is the original value of the program data section, the preset address is the starting address of the program data section, and the preset length is the data length of the data section. Further, the method further comprises the following steps: and obtaining the original value by analyzing the FPGA configuration file.
Further, the method further comprises the following steps: and obtaining the original value through backup of specific data in a preset address and a preset length in the starting process of the soft core processor.
Further, the method further comprises the following steps: the original value is obtained by an external system input.
Further, the overlaying the original value of the specific data in the preset address of the memory and overlaying the original value of the specific data as a preset length specifically includes:
and covering the original value of the specific data with the data formed by the preset address of the memory due to the execution of the pre-program, and covering the preset length of the specific data.
The other technical scheme for solving the technical problems is as follows:
a reset system for a soft-core processor in an FPGA system, comprising: the system comprises a reset flow management module, an original information acquisition module, a data coverage module and a reset signal control module;
the reset flow management module is used for resetting a preset soft core processor in the FPGA system through a preset reset signal and executing a reset flow of the soft core processor;
the reset signal control module is used for controlling the target soft core processor to be kept in a reset state;
the original information acquisition module is used for acquiring an original value in a preset address of a memory where a program running environment of the target soft core processor of the FPGA system is located and a preset length of specific data;
the data coverage module is used for covering the original value of the specific data in a preset address of the memory and covering the original value of the specific data as a preset length;
the reset signal control module is used for releasing the preset reset signal, suspending the reset and ending the reset.
The beneficial effects of the invention are as follows: in the prior art, when the soft core processor is reset, in order to ensure that the execution environment is restored to the initial state, specific data in the memory is required to be restored to the initial value. However, since the FPGA system is not reconfigured at this time, the above requirements cannot be met, resulting in a soft-core processor system reset exception. When the soft-core processor is reset, the invention ensures that the execution environment is restored to the initial state, and the specific data in the memory is restored to the initial value, thereby helping the normal reset of the soft-core processor system.
Further, the method comprises the steps of: one or more target soft-core processors, each corresponding to a preset reset signal;
the reset flow management module is specifically configured to reset a corresponding preset soft core processor in the FPGA system by using each preset reset signal, and execute a reset flow of the soft core processor.
Further, the original value is the original value of the program data section, the preset address is the starting address of the program data section, and the preset length is the data length of the data section.
Further, the method further comprises the following steps: the original value obtaining module is used for obtaining the original value by analyzing the FPGA configuration file.
Further, the original value obtaining module is further configured to obtain the original value through backup of specific data in a preset address and a preset length in a starting process of the soft core processor.
Further, the original value obtaining module is further configured to obtain the original value through an external system input.
Further, the data coverage module is specifically configured to cover the original value of the specific data with the data formed by the preset address of the memory due to the execution of the program in advance, and cover the preset length of the specific data.
Additional aspects of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
Fig. 1 is a schematic flow chart of a method for resetting a soft core processor in an FPGA system according to an embodiment of the present invention;
FIG. 2 is a block diagram of a reset system of a soft core processor in an FPGA system according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of an exemplary system for FPGA containing a soft-core processor provided in accordance with other embodiments of the present invention;
FIG. 4 is a schematic diagram of a reset operation flow of a reset management module of a soft core processor according to another embodiment of the present invention;
FIG. 5 is a diagram of an embodiment of a system including a soft-core processor reset management module according to another embodiment of the present invention;
FIG. 6 is a schematic diagram of a reset management module supporting multiple soft-core processors according to other embodiments of the present invention;
fig. 7 is a flowchart of a process for obtaining an original value of initialization data from a processor according to another embodiment of the present invention.
Detailed Description
The principles and features of the present invention are described below with reference to the drawings, the illustrated embodiments are provided for illustration only and are not intended to limit the scope of the present invention.
As shown in fig. 1, a method for resetting a soft core processor in an FPGA system according to an embodiment of the present invention includes:
s1, resetting a preset soft core processor in an FPGA system through a preset reset signal, and executing a reset flow of the soft core processor;
s2, controlling the target soft core processor to be kept in a reset state;
s3, acquiring a preset address of a memory where a program running environment of a target soft core processor of the FPGA system is located and an original value in a preset length of specific data;
s4, covering the original value of the specific data in a preset address of the memory and covering the original value of the specific data as a preset length;
s5, releasing the preset reset signal, suspending reset and ending reset.
In the prior art, when the soft core processor is reset, in order to ensure that the execution environment is restored to the initial state, specific data in the memory is required to be restored to the initial value. However, since the FPGA system is not reconfigured at this time, the above requirements cannot be met, resulting in a soft-core processor system reset exception. When the soft-core processor is reset, the invention ensures that the execution environment is restored to the initial state, and the specific data in the memory is restored to the initial value, thereby helping the normal reset of the soft-core processor system.
It should be noted that, in another embodiment, the reset signal resets the preset soft-core processor in the FPGA system, and the reset process of the soft-core processor shown in fig. 1 is executed;
in one embodiment, a typical FPGA system containing a soft-core processor includes components such as the soft-core processor, program memory, interconnect bus, and other FPGA logic. The soft core processor program and the running environment are located in the memory, and the program and the initial data are specified by the configuration file when the FPGA is configured. During the operation of the soft-core processor, memory data may change as the program executes. When the soft-core processor is reset, specific data in the memory is required to be restored to an initial value in order to ensure that the execution environment is restored to an initial state. However, since the FPGA system is not reconfigured at this time, the above requirements cannot be met, resulting in a soft-core processor system reset exception.
The reconfiguration can be performed by the method of the present invention to restore the specific data (initial data required by the program) in the memory to the initial value.
In one embodiment, the method of the present invention may include, as shown in fig. 4:
step 11, stopping the instruction processing of the target soft core processor in the FPGA system by activating a reset signal of the target soft core processor, and starting to execute the reset flow;
step 12, controlling the target soft-core processor to be kept in a reset state by continuously keeping a soft-core processor reset signal;
step 13, acquiring an appointed address of a memory where a program running environment of a target soft core processor of the FPGA system is located and an original value of data in an appointed length;
step 14, the original value of the data is covered in the appointed address of the memory, and the covering length is the appointed length;
and 15, releasing a reset signal, and ending the reset process.
By the method, when the soft core processor is reset, the execution environment is ensured to be restored to the initial state, the specific data in the memory is restored to the initial value, and the normal reset of the soft core processor system is facilitated.
In one embodiment, an apparatus for reliably resetting a soft core processor in an FPGA system, as shown in fig. 5, includes: the system comprises a reset flow management module, an original information acquisition module, a data coverage module and a reset signal control module;
the reset flow management module controls the original information acquisition module, the data coverage module and the reset signal control module to execute a complete reset flow; in one embodiment, as shown in FIG. 7, the raw data acquisition process includes: powering up and configuring the FPGA;
the soft core processor reset management module defaults to enable and maintain a reset signal to the soft core processor;
reading data in a preset address and a preset length of a memory where a program running environment of a target soft core processor in the FPGA system is located, and storing the data as an original value of specific data;
releasing a reset signal of the target soft core processor, and starting normal booting of the processor;
the acquisition of the original data is ended.
The reset signal control module is used for activating a reset signal of the target soft core processor and stopping instruction processing of the target soft core processor in the FPGA system;
the reset signal control module is used for continuously keeping the reset signal of the soft core processor and controlling the target soft core processor to be kept in a reset state;
the method comprises the steps that an original information acquisition module acquires an original value of data in a designated address and a designated length of a memory where a program running environment of a target soft core processor of an FPGA system is located;
the data coverage module is used for covering the original value of the data in the appointed address of the memory, and the coverage length is the appointed length;
the reset signal control module is used for releasing the reset signal, and the reset process is finished.
Through the steps, the specific data needing to be initialized in the memory is restored to the original value in the resetting process, and the correct resetting of the soft core processor is completed.
Optionally, the device for reliably resetting the soft core processors in the FPGA system may support single or simultaneous resetting of one or more soft core processors, and an embodiment is shown in fig. 6, where the module supports resetting of multiple sets of soft core processors, and stores and manages the original value and corresponding address and length information of specific data required to be initialized in the resetting process of multiple sets of processors.
When the reset process is executed, the reset module selects corresponding reset signals, original data and corresponding address and length information according to the target soft core processor. And performs the reset procedure described in fig. 4.
In any of the above embodiments, the soft-core processor reset management module may be located inside the FPGA, implemented by FPGA logic, or located outside the FPGA, implemented by a processor, DSP, or other device.
In any of the above embodiments, the original value of the specific data to be initialized is the program data section original value, the memory designation address is the program data section start address, and the designated length is the data section data length.
In all the above embodiments, the original value of the specific data to be initialized and the corresponding address and length information can be obtained by the following ways: obtained by analyzing the FPGA configuration file or derived from the backup of the data in the appointed address and the appointed length in the starting process of the soft core processor.
In one embodiment, as shown in fig. 2, a reset system of a soft core processor in an FPGA system includes: a reset flow management module 1101, a reset signal control module 1102, an original information acquisition module 1103, and a data coverage module 1104;
the reset flow management module 1101 is configured to reset a preset soft core processor in the FPGA system by using a preset reset signal, and execute a reset flow of the soft core processor;
the reset signal control module 1102 is used for controlling the target soft-core processor to be kept in a reset state;
the original information obtaining module 1103 is configured to obtain an original value in a preset address of a memory where a program running environment of the target soft core processor of the FPGA system is located and a preset length of specific data;
the data overlay module 1104 is configured to overlay an original value of the specific data in a preset address of the memory and to overlay the original value to a preset length;
the reset signal control module 1103 is configured to release the preset reset signal, suspend the reset, and end the reset.
In the prior art, when the soft core processor is reset, in order to ensure that the execution environment is restored to the initial state, specific data in the memory is required to be restored to the initial value. However, since the FPGA system is not reconfigured at this time, the above requirements cannot be met, resulting in a soft-core processor system reset exception. When the soft-core processor is reset, the invention ensures that the execution environment is restored to the initial state, and the specific data in the memory is restored to the initial value, thereby helping the normal reset of the soft-core processor system.
Optionally, in any embodiment above, the method includes: one or more target soft-core processors, each corresponding to a preset reset signal;
the reset flow management module is specifically configured to reset a corresponding preset soft core processor in the FPGA system by using each preset reset signal, and execute a reset flow of the soft core processor.
Optionally, in any embodiment above, the original value is a program data section original value, the preset address is a program data section start address, and the preset length is a data section data length.
Optionally, in any embodiment above, the method further includes: the original value obtaining module is used for obtaining the original value by analyzing the FPGA configuration file. Wherein the original value is stored in an external memory.
Optionally, in any embodiment of the foregoing, the original value obtaining module is further configured to obtain the original value by backing up specific data in a preset address and a preset length during a startup process of the soft core processor. The original value is stored in an internal memory.
Optionally, in any embodiment of the foregoing, the original value obtaining module is further configured to obtain the original value through an external system input. And constructing corresponding external connection aiming at different external systems so as to acquire the original value.
Optionally, in any embodiment of the foregoing, the data overwriting module is specifically configured to overwrite an original value of the specific data with data formed by a pre-program execution of a preset address of the memory, and overwrite a preset length of the specific data.
It is to be understood that in some embodiments, some or all of the alternatives described in the various embodiments above may be included.
It should be noted that, the foregoing embodiments are product embodiments corresponding to the previous method embodiments, and the description of each optional implementation manner in the product embodiments may refer to the corresponding description in the foregoing method embodiments, which is not repeated herein.
The reader will appreciate that in the description of this specification, a description of terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.
In the several embodiments provided in this application, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the method embodiments described above are merely illustrative, e.g., the division of steps is merely a logical function division, and there may be additional divisions of actual implementation, e.g., multiple steps may be combined or integrated into another step, or some features may be omitted or not performed.
The above-described method, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer-readable storage medium. Based on such understanding, the technical solution of the present invention is essentially or a part contributing to the prior art, or all or part of the technical solution may be embodied in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods of the embodiments of the present invention. And the aforementioned storage medium includes: a usb disk, a removable hard disk, a Read-only memory (ROM), a random access memory (RAM, randomAccessMemory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
The present invention is not limited to the above embodiments, and various equivalent modifications and substitutions can be easily made by those skilled in the art within the technical scope of the present invention, and these modifications and substitutions are intended to be included in the scope of the present invention. Therefore, the protection scope of the invention is subject to the protection scope of the claims.
Claims (10)
1. The resetting method of the soft core processor in the FPGA system is characterized by comprising the following steps of:
resetting a preset soft core processor in the FPGA system through a preset reset signal, and executing a reset flow of the soft core processor;
the control target soft core processor is kept in a reset state;
acquiring an original value in a preset address of a memory where a program running environment of a target soft core processor of the FPGA system is located and a preset length of specific data;
covering the original value of the specific data in a preset address of the memory and covering the original value of the specific data as a preset length;
releasing the preset reset signal, suspending reset and ending reset;
the original value is the original value of the program data section, the preset address is the initial address of the program data section, and the preset length is the data length of the data section.
2. The method for resetting a soft-core processor in an FPGA system of claim 1, comprising: one or more target soft-core processors, each corresponding to a preset reset signal;
resetting a preset soft core processor in an FPGA system through a preset reset signal, and executing a reset process of the soft core processor, wherein the reset process comprises the following steps of:
resetting a corresponding preset soft core processor in the FPGA system through each preset reset signal, and executing a reset flow of the soft core processor.
3. The method for resetting a soft core processor in an FPGA system according to claim 1, wherein the original value is a program data section original value, the preset address is a program data section start address, and the preset length is a data section data length.
4. The method for resetting a soft-core processor in an FPGA system of claim 1, further comprising: and obtaining the original value by analyzing the FPGA configuration file.
5. The method for resetting a soft-core processor in an FPGA system of claim 1, further comprising: and obtaining the original value through backup of specific data in a preset address and a preset length in the starting process of the soft core processor.
6. The method for resetting a soft-core processor in an FPGA system of claim 1, further comprising: the original value is obtained by an external system input.
7. The method for resetting a soft-core processor in an FPGA system according to any one of claims 1-6, wherein the overlaying the original value of the specific data in the preset address of the memory and the preset length comprises:
and covering the original value of the specific data with the data formed by the preset address of the memory due to the execution of the pre-program, and covering the preset length of the specific data.
8. A reset system for a soft-core processor in an FPGA system, comprising: the system comprises a reset flow management module, an original information acquisition module, a data coverage module and a reset signal control module;
the reset flow management module is used for resetting a preset soft core processor in the FPGA system through a preset reset signal and executing a reset flow of the soft core processor;
the reset signal control module is used for controlling the target soft core processor to be kept in a reset state;
the original information acquisition module is used for acquiring an original value in a preset address of a memory where a program running environment of the target soft core processor of the FPGA system is located and a preset length of specific data;
the data coverage module is used for covering the original value of the specific data in a preset address of the memory and covering the original value of the specific data as a preset length;
the reset signal control module is used for releasing the preset reset signal, suspending reset and ending reset;
the original value is the original value of the program data section, the preset address is the initial address of the program data section, and the preset length is the data length of the data section.
9. The reset system of a soft-core processor in an FPGA system of claim 8, comprising: one or more target soft-core processors, each corresponding to a preset reset signal;
the reset flow management module is specifically configured to reset a corresponding preset soft core processor in the FPGA system by using each preset reset signal, and execute a reset flow of the soft core processor.
10. The reset system of a soft-core processor in an FPGA system of claim 8, wherein the original value is a program data section original value, the preset address is a program data section start address, and the preset length is a data section data length.
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| CN105573789B (en) * | 2015-09-07 | 2017-08-08 | 武汉精测电子技术股份有限公司 | The many image upgrade loading methods of FPGA and device based on soft-core processor |
| CN105653384A (en) * | 2015-12-30 | 2016-06-08 | 惠州市伟乐科技股份有限公司 | Soft-core CPU resetting method and master-slave type system |
| CN112347030A (en) * | 2020-09-24 | 2021-02-09 | 深圳市紫光同创电子有限公司 | Data processing method and system based on FPGA |
| CN113270137A (en) * | 2021-04-29 | 2021-08-17 | 北京航天飞腾装备技术有限责任公司 | DDR2 test method based on FPGA embedded soft core |
| CN114327660B (en) * | 2021-12-30 | 2024-01-30 | 浙江大立科技股份有限公司 | Initialization method of external memory based on FPGA |
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