CN115562465A - Resetting method and system for soft-core processor in FPGA system - Google Patents
Resetting method and system for soft-core processor in FPGA system Download PDFInfo
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- CN115562465A CN115562465A CN202211115890.1A CN202211115890A CN115562465A CN 115562465 A CN115562465 A CN 115562465A CN 202211115890 A CN202211115890 A CN 202211115890A CN 115562465 A CN115562465 A CN 115562465A
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/24—Resetting means
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention discloses a method and a system for resetting a soft core processor in an FPGA system, and relates to the technical field of FPGA. The method comprises the following steps: resetting a preset soft-core processor in the FPGA system through a preset reset signal, and executing a reset process of the soft-core processor; controlling the target soft-core processor to be kept in a reset state; acquiring a preset address of a memory where a target soft core processor program operation environment of an FPGA system is located and an original value in a preset length of specific data; covering the original value of the specific data in a preset address of the memory and covering the original value of the specific data to be a preset length; and releasing the preset reset signal, suspending reset and finishing reset. When the soft-core processor is reset, the invention ensures that the execution environment is restored to the initial state, restores the specific data in the memory to the initial value and helps the soft-core processor system to be normally reset.
Description
Technical Field
The invention relates to the technical field of FPGA (field programmable gate array), in particular to a method and a system for resetting a soft-core processor in an FPGA system.
Background
An FPGA (Field Programmable Gate Array) is a semiconductor device, and can be programmed to implement logic functions required by a user. The FPGA can provide strong computing power and enough flexibility at the same time, and a customized solution is allowed to be developed aiming at complex tasks; the processing performance of the calculation intensive tasks can be improved through parallelization; high flexibility, strong real-time performance and short development period. The FPGA is widely applied to a plurality of fields such as medical treatment, military industry, space navigation, communication, image processing, artificial intelligence and the like.
A soft core processor (Softcore Microprocessor) is a processor implemented by FPGA logic. By embedding the soft core processor in the FPGA system, the FPGA system can be endowed with software execution capacity. On one hand, the task flexibility of the FPGA system can be remarkably improved, and on the other hand, the requirement of an external system processor can be reduced, so that the number of system chips is reduced, the area of a circuit board is reduced, and the system has great advantages in aspects of size, weight, power consumption, cost and the like. Therefore, the soft core embedded processor has an important application prospect.
The FPGA realizes environment initialization and function configuration through configuration operation. When the FPGA executes configuration operation, a configuration file is firstly obtained, and the configuration file describes the logic structure of the FPGA and the initial value of the data of the memory. The FPGA realizes the establishment of internal logic functions and the data initialization of the memory by writing the configuration file into the internal configuration memory.
According to the configuration process, the FPGA logic structure and the memory data initialization are carried out simultaneously, and the memory data cannot be initialized independently; and the soft-core processor reset requires that specific data (such as a data field) in the memory is restored to an initial value, so that the FPGA system cannot directly and reliably reset the soft-core processor.
Disclosure of Invention
The invention aims to solve the technical problem of the prior art and provides a method and a system for resetting a soft-core processor in an FPGA system.
The technical scheme for solving the technical problems is as follows:
a reset method of a soft core processor in an FPGA system comprises the following steps:
resetting a preset soft-core processor in the FPGA system through a preset reset signal, and executing a reset process of the soft-core processor;
controlling the target soft-core processor to be kept in a reset state;
acquiring a preset address of a memory where a target soft-core processor program operating environment of the FPGA system is located and an original value in a preset length of specific data;
covering the original value of the specific data in a preset address of the memory and covering the original value of the specific data to be a preset length;
and releasing the preset reset signal, suspending reset and finishing reset.
The invention has the beneficial effects that: in the existing scheme, when the soft-core processor is reset, in order to ensure that the execution environment is restored to the initial state, specific data in a memory is required to be restored to the initial value. However, at this time, the FPGA system is not reconfigured, so that the above requirements cannot be met, and the soft core processor system is abnormal in reset. When the soft core processor is reset, the invention ensures that the execution environment is restored to the initial state, restores the specific data in the memory to the initial value and helps the soft core processor system to be normally reset.
Further, comprising: each target soft-core processor corresponds to a preset reset signal;
the method comprises the following steps of resetting a preset soft-core processor in the FPGA system through a preset reset signal, and executing a reset flow of the soft-core processor, and specifically comprises the following steps:
and resetting the corresponding preset soft-core processor in the FPGA system through each preset reset signal, and executing the reset flow of the soft-core processor.
The beneficial effect of adopting the further scheme is that: support for individual or simultaneous reset of one or more soft-core processors may be implemented.
Further, the original value is an original value of the program data section, the preset address is a starting address of the program data section, and the preset length is a data section data length. Further, still include: and analyzing the FPGA configuration file to obtain the original value.
Further, still include: and obtaining the original value through the backup of the specific data in the preset address and the preset length in the starting process of the soft-core processor.
Further, the method also comprises the following steps: the original value is obtained by an external system input.
Further, the overwriting the original value of the specific data in a preset address of the memory and with a preset length specifically includes:
and covering the original value of the specific data with data formed by a preset address of the memory due to the execution of a pre-program, and covering the preset length of the specific data.
Another technical solution of the present invention for solving the above technical problems is as follows:
a reset system of a soft core processor in an FPGA system comprises: the system comprises a reset flow management module, an original information acquisition module, a data coverage module and a reset signal control module;
the reset flow management module is used for resetting a preset soft-core processor in the FPGA system through a preset reset signal and executing a reset flow of the soft-core processor;
the reset signal control module is used for controlling the target soft-core processor to be kept in a reset state;
the original information acquisition module is used for acquiring the original value in the preset address of the memory where the FPGA system target soft-core processor program operating environment is located and the preset length of the specific data;
the data coverage module is used for covering the original value of the specific data in a preset address of the memory and covering the original value of the specific data to be a preset length;
the reset signal control module is used for releasing the preset reset signal, suspending reset and ending reset.
The beneficial effects of the invention are: in the existing scheme, when the soft-core processor is reset, in order to ensure that the execution environment is restored to the initial state, specific data in a memory is required to be restored to the initial value. However, at this time, the FPGA system is not reconfigured, so that the above requirements cannot be met, and the soft core processor system is abnormal in reset. When the soft core processor is reset, the invention ensures that the execution environment is restored to the initial state, restores the specific data in the memory to the initial value and helps the soft core processor system to be normally reset.
Further, comprising: each target soft-core processor corresponds to a preset reset signal;
the reset flow management module is specifically configured to reset a corresponding preset soft-core processor in the FPGA system through each preset reset signal, and execute a reset flow of the soft-core processor.
Further, the original value is an original value of the program data section, the preset address is a starting address of the program data section, and the preset length is a data section data length.
Further, still include: and the original value acquisition module is used for acquiring the original value by analyzing the FPGA configuration file.
Further, the module for obtaining an original value is further configured to obtain the original value by backing up specific data in a preset address and a preset length in a starting process of the soft-core processor.
Further, the original value obtaining module is further configured to obtain the original value through an external system input.
Further, the data overwriting module is specifically configured to overwrite an original value of the specific data with data formed by a preset address of the memory due to pre-program execution, and overwrite a preset length of the specific data.
Advantages of additional aspects of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.
Drawings
Fig. 1 is a schematic flowchart of a reset method for a soft-core processor in an FPGA system according to an embodiment of the present invention;
fig. 2 is a structural framework diagram of a reset system of a soft core processor in an FPGA system according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of an example FPGA system including a soft-core processor according to another embodiment of the present invention;
fig. 4 is a schematic diagram of a reset operation flow of a reset management module of a soft-core processor according to another embodiment of the present invention;
FIG. 5 is a diagram of an example system including a soft-core processor reset management module according to another embodiment of the present invention;
FIG. 6 is a schematic diagram of a reset management module supporting multiple soft-core processors according to another embodiment of the present invention;
fig. 7 is a schematic diagram of a process for obtaining an original value of initialization data from a processor according to another embodiment of the present invention.
Detailed Description
The principles and features of this invention are described below in conjunction with the following drawings, which are set forth to illustrate, but are not to be construed to limit the scope of the invention.
As shown in fig. 1, a method for resetting a soft core processor in an FPGA system according to an embodiment of the present invention includes:
s1, resetting a preset soft-core processor in an FPGA system through a preset reset signal, and executing a reset process of the soft-core processor;
s2, controlling the target soft-core processor to be kept in a reset state;
s3, acquiring a preset address of a memory where a target soft-core processor program operation environment of the FPGA system is located and an original value in a preset length of specific data;
s4, covering the original value of the specific data in a preset address of the memory, and covering the original value of the specific data to be a preset length;
and S5, releasing the preset reset signal, suspending reset and finishing reset.
In the existing scheme, when the soft-core processor is reset, in order to ensure that the execution environment is restored to the initial state, specific data in the memory is required to be restored to the initial value. However, at this time, the FPGA system is not reconfigured, so that the above requirements cannot be met, and the system of the soft core processor is reset abnormally. When the soft-core processor is reset, the invention ensures that the execution environment is restored to the initial state, restores the specific data in the memory to the initial value and helps the soft-core processor system to be normally reset.
It should be noted that, in another embodiment, a preset soft-core processor in the FPGA system is reset by a preset reset signal, and the soft-core processor reset flow illustrated in fig. 1 is executed;
in one embodiment, a typical FPGA system including a soft core processor includes the soft core processor, a program memory, an interconnection bus, and other FPGA logic. The soft-core processor program and the operating environment are located in the memory, and the program and the initial data are specified by the configuration file during FPGA configuration. During the operation of the soft-core processor, the memory data can change along with the execution of the program. When the soft core processor is reset, in order to ensure that the execution environment is restored to the initial state, the specific data in the memory is required to be restored to the initial value. However, at this time, the FPGA system is not reconfigured, so that the above requirements cannot be met, and the system of the soft core processor is reset abnormally.
The reconfiguration can be carried out by the method of the invention, and the specific data (initial data required by the program) in the memory is restored to the initial value.
In one embodiment, the method of the present invention may comprise, as shown in fig. 4:
step 11, by activating a reset signal of a target soft-core processor, stopping the instruction processing of the target soft-core processor in the FPGA system and starting to execute the reset flow;
step 12, controlling the target soft-core processor to be kept in a reset state by continuously keeping the soft-core processor reset signal;
step 13, acquiring the original values of data in the specified address and the specified length of a memory where the FPGA system target soft-core processor program operating environment is located;
step 14, covering the original value of the data in the designated address of the memory, wherein the covering length is the designated length;
and step 15, releasing the reset signal, and ending the reset process.
By the method, when the soft core processor is reset, the execution environment is guaranteed to be restored to the initial state, the specific data in the memory is restored to the initial value, and the normal reset of the soft core processor system is facilitated.
In one embodiment, an apparatus for reliably resetting a soft-core processor in an FPGA system, as shown in fig. 5, includes: the system comprises a reset flow management module, an original information acquisition module, a data coverage module and a reset signal control module;
the reset flow management module controls the original information acquisition module, the data coverage module and the reset signal control module to execute a complete reset flow; in one embodiment, as shown in fig. 7, the raw data acquisition process includes: the FPGA is electrified and configured;
the soft-core processor reset management module enables and keeps a reset signal of the soft-core processor by default;
reading data in a preset address and a preset length of a memory where a target soft-core processor program operating environment in the FPGA system is located, and storing the data as an original value of specific data;
releasing a reset signal of the target soft-core processor, and starting normal booting of the processor;
and finishing acquiring the original data.
The reset signal control module is used for activating a reset signal of the target soft-core processor and stopping instruction processing of the target soft-core processor in the FPGA system;
the reset signal control module is used for continuously keeping the reset signal of the soft-core processor and controlling the target soft-core processor to be kept in a reset state;
the method comprises the following steps that an original information acquisition module acquires an original value of data in a specified address and a specified length of a memory where an FPGA system target soft-core processor program operating environment is located;
the data covering module is used for covering the original value of the data in the designated address of the memory, and the covering length is the designated length;
the reset signal control module is used for releasing the reset signal, and the reset process is finished.
Through the steps, the specific data needing to be initialized in the memory in the resetting process is restored to the original value, and the correct resetting of the soft-core processor is completed.
Optionally, the device for reliably resetting the soft-core processors in the FPGA system may support individual or simultaneous resetting of one or more soft-core processors, and the implementation example is as shown in fig. 6, where the module supports resetting of multiple groups of soft-core processors, and stores and manages original values of specific data, corresponding addresses, and length information of the specific data that needs to be initialized in the resetting process of the multiple groups of processors.
When the reset process is executed, the reset module selects the corresponding reset signal, the original data and the corresponding address and length information according to the target soft-core processor. And performs the reset procedure described in fig. 4.
In any of the above embodiments, the soft-core processor reset management module may be located inside the FPGA and implemented by FPGA logic, or may be located outside the FPGA and implemented by a processor, a DSP, or other devices.
In any of the above embodiments, the original value of the specific data to be initialized is the original value of the program data segment, the memory specified address is the start address of the program data segment, and the specified length is the data segment data length.
In all the above embodiments, the original value of the specific data to be initialized and the corresponding address and length information may be obtained as follows: the method is obtained by analyzing the FPGA configuration file or is from backup of data in a specified address and a specified length in the starting process of the soft-core processor.
In one embodiment, as shown in fig. 2, a reset system for a soft-core processor in an FPGA system includes: a reset process management module 1101, a reset signal control module 1102, an original information acquisition module 1103 and a data coverage module 1104;
the reset flow management module 1101 is configured to reset a preset soft core processor in the FPGA system by a preset reset signal, and execute a reset flow of the soft core processor;
the reset signal control module 1102 is configured to control the target soft-core processor to be kept in a reset state;
the original information acquiring module 1103 is configured to acquire an original value in a preset length of a preset address and specific data of a memory where an FPGA system target soft-core processor program operating environment is located;
the data overwriting module 1104 is configured to overwrite an original value of the specific data in a preset address of the memory, and overwrite the original value of the specific data to a preset length;
the reset signal control module 1103 is configured to release the preset reset signal, suspend reset, and terminate reset.
In the existing scheme, when the soft-core processor is reset, in order to ensure that the execution environment is restored to the initial state, specific data in the memory is required to be restored to the initial value. However, at this time, the FPGA system is not reconfigured, so that the above requirements cannot be met, and the system of the soft core processor is reset abnormally. When the soft core processor is reset, the invention ensures that the execution environment is restored to the initial state, restores the specific data in the memory to the initial value and helps the soft core processor system to be normally reset.
Optionally, in any of the above embodiments, the method includes: each target soft-core processor corresponds to a preset reset signal;
the reset flow management module is specifically used for resetting the corresponding preset soft-core processor in the FPGA system through each preset reset signal and executing the reset flow of the soft-core processor.
Optionally, in any embodiment described above, the original value is an original value of a program data segment, the preset address is a start address of the program data segment, and the preset length is a data segment data length.
Optionally, in any embodiment above, the method further includes: and the original value acquisition module is used for acquiring the original value by analyzing the FPGA configuration file. Wherein the original value is stored with an external memory.
Optionally, in any embodiment described above, the module for obtaining an original value is further configured to obtain the original value by backing up specific data in a preset address and a preset length in a starting process of the soft-core processor. The original value is stored in an internal memory.
Optionally, in any embodiment above, the obtain original value module is further configured to obtain the original value through an external system input. For different external systems, corresponding external connections are constructed to obtain the original values.
Optionally, in any embodiment described above, the data overwriting module is specifically configured to overwrite an original value of the specific data with data, which is formed by pre-program execution at a preset address of the memory, and overwrite a preset length of the specific data.
It is understood that some or all of the alternative embodiments described above may be included in some embodiments.
It should be noted that the foregoing embodiments are product embodiments corresponding to the foregoing method embodiments, and for the description of each optional implementation in the product embodiments, reference may be made to the corresponding description in each method embodiment, which is not described herein again.
The reader should understand that in the description of this specification, reference to the description of the terms "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Moreover, various embodiments or examples and features of various embodiments or examples described in this specification can be combined and combined by one skilled in the art without being mutually inconsistent.
In the several embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described method embodiments are merely illustrative, and for example, the division of steps into only one type of logical functional division may be implemented in practice in other ways, for example, multiple steps may be combined or integrated into another step, or some features may be omitted, or not implemented.
The above method, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention essentially or partially contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product stored in a storage medium and including instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-only memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.
While the invention has been described with reference to specific embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (10)
1. A reset method of a soft core processor in an FPGA system is characterized by comprising the following steps:
resetting a preset soft-core processor in the FPGA system through a preset reset signal, and executing a reset flow of the soft-core processor;
controlling the target soft-core processor to be kept in a reset state;
acquiring a preset address of a memory where a target soft-core processor program operating environment of the FPGA system is located and an original value in a preset length of specific data;
covering the original value of the specific data in a preset address of the memory and covering the original value of the specific data to be a preset length;
and releasing the preset reset signal, suspending reset and finishing reset.
2. The method for resetting the soft-core processor in the FPGA system according to claim 1, comprising the following steps: each target soft-core processor corresponds to a preset reset signal;
the method comprises the following steps of resetting a preset soft-core processor in the FPGA system through a preset reset signal, and executing a reset flow of the soft-core processor, and specifically comprises the following steps:
and resetting the corresponding preset soft-core processor in the FPGA system through each preset reset signal, and executing the reset flow of the soft-core processor.
3. The method according to claim 1, wherein the original value is an original value of a program data segment, the preset address is a start address of the program data segment, and the preset length is a data segment data length.
4. The method according to claim 1, further comprising: and obtaining the original value by analyzing the FPGA configuration file.
5. The method for resetting the soft-core processor in the FPGA system according to claim 1, further comprising: and obtaining the original value through the backup of the specific data in the preset address and the preset length in the starting process of the soft-core processor.
6. The method for resetting the soft-core processor in the FPGA system according to claim 1, further comprising: the original value is obtained by an external system input.
7. The method according to any one of claims 1 to 6, wherein the overwriting an original value of the specific data in a preset address of the memory and with a preset length specifically comprises:
and covering the original value of the specific data with data formed by a preset address of the memory due to the execution of a pre-program, and covering the preset length of the specific data.
8. A reset system of a soft core processor in an FPGA system is characterized by comprising: the system comprises a reset flow management module, an original information acquisition module, a data coverage module and a reset signal control module;
the reset flow management module is used for resetting a preset soft-core processor in the FPGA system through a preset reset signal and executing a reset flow of the soft-core processor;
the reset signal control module is used for controlling the target soft-core processor to be kept in a reset state;
the original information acquisition module is used for acquiring a preset address of a memory where a target soft core processor program operation environment of the FPGA system is located and an original value in a preset length of specific data;
the data covering module is used for covering the original value of the specific data in a preset address of the memory and covering the original value of the specific data to be a preset length;
the reset signal control module is used for releasing the preset reset signal, suspending reset and ending reset.
9. The system of claim 8, wherein the reset system comprises: each target soft-core processor corresponds to a preset reset signal;
the reset flow management module is specifically used for resetting the corresponding preset soft-core processor in the FPGA system through each preset reset signal and executing the reset flow of the soft-core processor.
10. The reset system of the soft-core processor in the FPGA system of claim 8, wherein the original value is an original value of a program data segment, the preset address is a start address of the program data segment, and the preset length is a data segment data length.
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