CN115552385A

CN115552385A - Bidirectional interface configuration for memory

Info

Publication number: CN115552385A
Application number: CN202180032839.1A
Authority: CN
Inventors: G·E·胡申; R·C·墨菲; H·孙
Original assignee: Micron Technology Inc
Current assignee: Micron Technology Inc
Priority date: 2020-05-05
Filing date: 2021-04-28
Publication date: 2022-12-30
Also published as: KR20230003188A; US20220012193A1; US11144482B1; US11657009B2; DE112021002620T5; WO2021225838A1

Abstract

Apparatus and methods may be related to configuring an interface protocol for a memory. The interface protocol may define commands that are received by the memory device utilizing a transceiver, receiver, and/or transmitter of an interface of the memory device. The interface protocol used by the memory device may be implemented with a decoder of signals provided via multiple transceivers of the memory device. The decoder utilized by a memory device may be selected by setting a mode register of the memory device.

Description

Bidirectional interface configuration for memory

Technical Field

The present disclosure relates generally to memory, and more particularly, to apparatus and methods associated with configuring a bidirectional interface of memory.

Background

Memory devices are typically provided as internal semiconductor integrated circuits in computers or other electronic devices. There are many different types of memory, including volatile and non-volatile memory. Volatile memory may require power to maintain its data and includes, among other things, random Access Memory (RAM), dynamic Random Access Memory (DRAM), and Synchronous Dynamic Random Access Memory (SDRAM). Non-volatile memory can provide persistent data by retaining stored data when not powered, and can include NAND flash memory, NOR flash memory, read Only Memory (ROM), electrically Erasable Programmable ROM (EEPROM), erasable Programmable ROM (EPROM), and resistance variable memory such as Phase Change Random Access Memory (PCRAM), resistive Random Access Memory (RRAM), and Magnetoresistive Random Access Memory (MRAM), among others.

Memory is also used as volatile and non-volatile data storage for a wide range of electronic applications including, but not limited to, personal computers, portable memory sticks, digital cameras, cellular telephones, portable music players (e.g., MP3 players), movie players, and other electronic devices. The memory cells may be arranged in an array, where the array is used in a memory device.

The interface protocol may be utilized to provide commands to the memory. The commands provided to the memory may be predefined and may be used to control the functions of the memory.

Drawings

Fig. 1 is a block diagram of an apparatus in the form of a computing system including a memory device, according to a number of embodiments of the present disclosure.

Fig. 2 is a block diagram of an apparatus in the form of a computing system including an interface in accordance with several embodiments of the present disclosure.

Fig. 3A is a block diagram of a memory device including a transmitter, receiver, and transceiver, in accordance with a number of embodiments of the present disclosure.

Fig. 3B is a block diagram of a memory device including multiple transceivers, in accordance with a number of embodiments of the present disclosure.

Fig. 4 illustrates an example flow diagram of a method for performing operations in a memory in accordance with several embodiments of the present disclosure.

FIG. 5 illustrates an example machine of a computer system within which a set of instructions for causing the machine to perform the various methodologies discussed herein may be executed.

Detailed Description

The present disclosure includes apparatus and methods related to configuring a bidirectional interface of a memory. The memory device may include multiple transceivers, transmitters, and/or receivers. The memory device may receive a plurality of signals through a plurality of pins. For example, a memory device may receive commands, addresses, and/or data, among other signals, over multiple pins. As used herein, a plurality of pins physically couple a memory device to a computing system. The pins of the memory device are the physical interface that enables communication between the memory device and the computing system. The transceiver, transmitter, and/or receiver may be coupled to a physical interface (e.g., a pin of a memory device) such that the transceiver, transmitter, and/or receiver receives or transmits signals over the physical interface.

In various examples, a protocol may define the use of a transceiver, transmitter, and/or receiver. This protocol is described herein as an interface protocol. The interface protocol may define how and/or what type of data is received by the transceiver, transmitter, and/or receiver. For example, an interface protocol may define a first transceiver for commands, a second transceiver for addresses, and/or a third transceiver for data, among other uses of the transceivers. The interface protocol may also define whether the transceiver is used for directional data transfer or bi-directional data transfer.

The interface protocol defines communication between the memory device and devices external to the memory device. If the devices communicate as defined by the interface protocol, they may conform to the interface protocol. The interface protocol may be defined such that the memory device may receive signals from a plurality of devices external to the memory device and process the signals, where the plurality of devices are manufactured by a plurality of different vendors. Examples of interface protocols are the double data rate (DDR 5) standard and other standards such as DDR4 or any other DDR standard. In various examples, the interface protocol may be generated by an organization such as JEDEC that enables any devices compatible with the interface protocol to communicate with each other without increasing the expense of defining a new interface protocol for the plurality of devices.

The interface protocol may be limited in its ability to define communications between devices due to limitations on the number of pins that the memory device may have and/or hardware coupled to the number of pins, such as a transceiver, transmitter, and/or receiver of the memory device. Hardware coupled to the pins, such as transceivers, transmitters, and/or receivers, may also define the directionality of the pins. In various examples, some pins may be configured to receive signals without transmitting signals or may be configured to transmit signals without receiving signals. Hardware coupled to the pins may be configured to function as defined by an interface protocol. For example, a pin configured to receive a signal may be coupled to a receiver without being coupled to a transmitter and/or transceiver.

In a number of examples, directionality of an interface of a memory device can be overcome by implementing multiple interface protocols and by implementing hardware to enable the multiple interface protocols. As used herein, an interface may include a bus, pins, and transceivers, transmitters, and/or receivers that couple a device to a different device. For example, the interface may include a transceiver, transmitter, and/or receiver of a host, a bus coupling the host to the memory device, pins of the memory device, and a transceiver, transmitter, and/or receiver of the memory device. Multiple interface protocols may be implemented in a single device utilizing the same decoder and multiple multiplexers to reroute signals to different portions of a memory device.

Fig. 1 is a block diagram of an apparatus in the form of a computing system 100 including a memory device 103, according to several embodiments of the present disclosure. As used herein, memory device 103, memory array 110, and/or host 102 may also be considered an "apparatus" individually, for example.

In this example, the computing system 100 includes a host 102 coupled to a memory device 103 via an interface 104. Computing system 100 may be a personal laptop computer, desktop computer, digital camera, mobile phone, memory card reader, or internet of things (IoT) enabled device, among other types of systems. The host 102 may include a number of processing resources (e.g., one or more processors, microprocessors, or some other type of control circuitry) capable of accessing the memory 103. The computing system 100 may include separate integrated circuits, or both the host 102 and the memory device 103 may be on the same integrated circuit. For example, the host 102 may be a system controller of a memory system comprising a plurality of memory devices 103, wherein the system controller 102 provides access to the respective memory devices 103 through another processing resource, such as a Central Processing Unit (CPU).

In the example shown in fig. 1, host 102 is responsible for executing an Operating System (OS) and/or various applications that may be loaded thereto (e.g., from memory device 103 via control circuitry 105). The OS and/or various applications may be loaded from memory device 103 by providing access commands from host 102 to access data comprising the OS and/or various applications to memory device 103. The host 102 may also access data utilized by the OS and/or various applications by providing access commands to the memory device 103 to retrieve the data for execution of the OS and/or various applications.

For clarity, the computing system 100 has been simplified to focus on features that are particularly relevant to the present disclosure. The memory array 110 may be, for example, a DRAM array, an SRAM array, an STT RAM array, a PCRAM array, a TRAM array, an RRAM array, a NAND flash array, and/or a NOR flash array. Array 110 can include memory cells arranged in rows coupled by access lines (which can be referred to herein as word lines or select lines) and columns coupled by sense lines (which can be referred to herein as digit lines or data lines). Although a single array 110 is shown in fig. 1, embodiments are not so limited. For example, memory device 103 may include several arrays 110 (e.g., several banks of DRAM cells).

The memory device 103 includes address circuitry 106 for latching address signals provided via the interface 104. The interface may comprise, for example, a physical interface employing a suitable protocol (e.g., a data bus, an address bus, and a command bus, or a combined data/address/command bus). The data bus, address bus, and command bus are shown as interfaces 204 and 304 in fig. 2, 3A, and 3B, respectively. This protocol may be custom or proprietary, or the interface 104 may employ a first interface protocol, which may be a standardized interface protocol such as peripheral component interconnect express (PCIe), gen-Z interconnect, cache coherent interconnect of accelerators (CCIX), or the like. In various examples, a standardized interface protocol may refer to an interface protocol defined in a standard. A non-standardized interface protocol (e.g., a second interface protocol) may refer to an interface protocol that is defined by a different standard or that is not defined by a standard. Address signals are received and decoded by a row decoder 108 and a column decoder 112 to access the memory array 110. Data can be read from the memory array 110 by sensing voltage and/or current changes on sense lines using sensing circuitry 111. The sensing circuitry 111 can include, for example, sense amplifiers that can read and latch a page (e.g., a row) of data from the memory array 110. The I/O circuitry 107 may be used for bi-directional data communication with the host 102 via the interface 104. Read/write circuitry 113 is used to write data to memory array 110 or read data from memory array 110. As an example, circuitry 113 may include various drivers, latching circuitry, and so forth.

Control circuitry 105 decodes signals provided by host 102. The signal may be a command provided by the host 102. These signals may include a chip enable signal, a write enable signal, and an address latch signal used to control operations performed on the memory array 110, including data read operations, data write operations, and data erase operations. In various embodiments, control circuitry 105 is responsible for executing instructions from host 102. Control circuitry 105 may include a state machine, a sequencer, and/or some other type of control circuitry, which may be implemented in hardware, firmware, or software, or any combination of the three. In some examples, host 102 can be a controller external to memory device 103. For example, the host 102 may be a memory controller coupled to the processing resources of a computing device. Data may be provided to the memory array 110 via data lines 116 and/or from the memory array via data lines 116.

In various examples, control circuitry 105 may include command circuitry and/or address circuitry. The command circuitry and/or the address circuitry may include one or more decoders configured to decode command signals and/or address signals. The command signals may include commands provided to the memory device 103. The address signals may include an address of the memory array 110. The control circuitry 105 may also include response circuitry, which may include an encoder to encode the response signal. In various examples, the control circuitry 105 may further include I/O circuitry 107 shown in fig. 1 as being external to the control circuitry 105. The I/O circuitry 107 may include encoders and decoders to encode and decode data signals provided to the memory device 103 and/or data signals provided by the memory device 103.

In various examples, the functionality of the memory device 103 may be controlled by the host 102. For example, the host 102 may provide commands to the memory device 103 through the interface 104 to read from and/or write to the memory array 110, as well as other functionality of the memory array 110. However, the implemented interface protocol may not define commands to control the functionality of the sensing circuitry 111 to perform operations.

Fig. 2 is a block diagram of an apparatus in the form of a computing system 200 including an interface in accordance with several embodiments of the present disclosure. Interfaces 204-1, 204-2, 204-3, 204-4, and 204-5, referred to as interfaces 204, may include hardware configured to facilitate the transfer of signals between devices, such as memory controller 224 and memory device 203. The memory controller 224 may be incorporated in a host, such as the host 102 of FIG. 1.

The interface 204 may include a first portion 204-1, a second portion 204-2, a third portion 204-3, a fourth portion 204-4, and a fifth portion 204-5. The first portion 204-1 and the second portion 204-1 of the interface 204 may comprise a first bus. The third portion 204-3 and the fourth portion 204-4 of the interface 204 may include a second bus. The fifth portion 204-5 of the interface may include a third bus. The first bus may be configured to communicate signals including command signals and/or address signals to the memory device 203. Thus, the first bus may comprise a command bus and/or an address bus. The second bus may be configured to communicate an error signal (e.g., a response signal). The third bus may be configured to transfer data stored by the memory device 203 or data to be stored by the memory device 203. Thus, the third bus may comprise a data bus. The data transferred over the third bus may be stored in a memory array of the memory device 203. The bus may comprise a physical connection between a memory controller 224 incorporated in the host and the memory device 203.

An interface protocol (the implementation of which is not shown in fig. 2) may be used to configure the first and second buses as unidirectional. The first bus may provide signals from the memory controller 224 to the memory device 203. The second bus may provide signals from the memory device 203 to the memory controller 224. The third bus may be bidirectional. Bidirectionality may be implemented by implementing software/firmware and hardware capable of transmitting and receiving signals in the memory device 203 and the memory controller 224.

Different interface protocols, the implementation of which is shown in fig. 2, may be used to configure the first, second, and third buses. The first bus may be configured such that a first portion of interface 204-1 is unidirectional and a second portion of interface 204-2 is bidirectional. The second bus may be configured such that a third portion of interface 204-3 is unidirectional and a fourth portion of interface 204-4 is bidirectional. The fifth portion of the interface 204-5 may remain bidirectional, as configured by a different interface protocol and as specified by the implementation of the interface protocol.

A first portion of the interface 204-1 may be used to communicate command signals and/or address signals to the memory device 203. The second portion of the interface 204-2 may be used to transfer command signals, address signals and/or data signals to and from the memory controller 224 and the memory device 203. The third portion of the interface 204-3 may be used to transfer response signals from the memory controller 224 to the memory device 203. A fourth portion of the interface 204-4 may be used to transfer response signals and/or data signals to and from the memory controller and memory device 203. As used herein, a response signal may include a signal including a response to a command and/or address signal provided by the first bus or a data signal provided by the third bus. As used herein, the response signals may include error signals that describe errors encountered by the memory device 203, as well as other types of response signals. The response signal may also include a signal to represent completion of an operation performed by the memory device 203. For example, the response signal may signal completion of a write operation that stores data to a memory array of the memory device 203. The fifth portion of the interface 204-5 may transfer data signals to and from the memory controller 224 and the memory device 203.

The interface 204 may include a plurality of pins that couple the memory device 203 to the memory controller 224. The pins of the interface 204 may be comprised of a metal, such as copper, nickel, and/or gold, among other types of metals. The pins of the interface 204 may include a top pin and a bottom pin. The top and bottom pins may include pins formed on either side of the circuit board and are not intended to limit the orientation of the pins on the memory device 203.

The pins of the interface 204 may include a power supply (PWR) pin, a Ground (GND) pin, and a signal pin, among other possible types of pins. The PWR pin may provide power to the memory device 203, the gnd pin may provide a ground connection to the memory device 203, and the signal pin may provide signals to and from the memory device 203.

The command signals, address signals, response signals, and/or data signals may be referred to as commands, addresses, responses, and/or data. Memory device 203 may receive commands, addresses, responses, and/or data via interface 204. Although the example provided in FIG. 2 describes two different implementations of two different interface protocols, multiple interface protocols may be implemented by updating the software/firmware and hardware of the memory controller 224 and/or the memory device 203. For example, three different interface protocols may be implemented to configure the interface 204.

Each of the interface protocols may be incompatible with any of the other interface protocols. For example, the first interface protocol may not be compatible with the second interface protocol. For example, a first interface protocol may not be used to configure the memory controller 224 and the memory device 203 to provide data signals through the second portion of the interface 204-2, while a second interface protocol may be used to configure the memory controller 224 and the memory device 203 to provide data signals through the second portion of the interface 204-2. Although the memory device 203 may be configured with a second interface protocol that is incompatible with the first interface protocol, the memory device 203 may operate in compliance with the first interface protocol by avoiding transmission of signals over the second portion of the interface 204-2.

As used herein, a first interface protocol and a second interface protocol may be compatible with each other if the pins as configured by either of the first interface protocol and the second interface protocol have the same directionality. The first interface protocol and the second interface protocol may be incompatible with each other if the pins as configured by the first interface protocol and the second interface protocol have different directivities (e.g., directional versus bidirectional). The first interface protocol and the second interface protocol are also compatible with each other if the pins are configured to communicate the same type of signal. For example, the first interface protocol and the second interface protocol may be incompatible if the pins communicate control signals under the first interface protocol and the pins communicate control signals and data signals under the second interface protocol.

Fig. 3A is a block diagram of a memory device 303A including a transmitter 344, a receiver 345, and a transceiver 346, according to several embodiments of the present disclosure. FIG. 3A includes an interface 304 that includes a first portion 304-1, a second portion 304-2, a third portion 304-3, a fourth portion 304-4, and a fifth portion 304-5. The interface 304 may couple the memory device 303A to a host or memory controller 324A. The memory device 303A may be configured using a first interface protocol.

Portions of interfaces 304-1 and 304-2 may be unidirectional such that portions of interfaces 304-1 and 304-2 receive signals but cannot transmit signals. Portions of interfaces 304-1 and 304-2 are coupled to a receiver 341 configured to receive command/address signals. Receiver 341 may provide the received signal to command/address circuitry 338 of control circuitry 305. The command/address circuitry 338 may be configured to decode signals (e.g., command signals and/or address signals). The control circuitry 305 may also include response circuitry 339, which may be configured to encode a response signal. Fig. 3A and 3B identify command and/or address circuitry 338 and response circuitry 339 as being incorporated in control circuitry 305. However, command and/or address circuitry 338 and response circuitry 339 may be implemented external to control circuitry 305.

The response signal may be transmitted by the transmitter 342. Portions of interfaces 304-3 and 304-4 may be unidirectional. Portions of interface 304-5 may be bi-directional such that transceiver 343 may transmit data signals and may receive data signals. The transceiver 343 may be coupled to the I/O circuitry 307 and may receive signals from the data lines of the memory device 303A. In various examples, command and/or address circuitry 338, response circuitry 228, and/or I/O circuitry 307 may comprise encoders and/or decoders to encode and/or decode signals provided by interface 304. In at least one embodiment, interface 304 can include a command receiver 341, a response transmitter 342, and a data transceiver 343. For example, the interface 304 may be described as including a command receiver 341, a response transmitter 342, and/or a data transceiver 343. The interface 304 may also be described as including a command transmitter 344, a response receiver 345, and/or a data transceiver 346.

The interface 304 may couple the memory device 303A to the memory controller 324A. For example, portions of interfaces 304-1 and 304-2 may couple transmitter 344 of memory controller 324A to receiver 341 of memory device 303A. Portions of interfaces 304-3 and 304-4 may couple a receiver 345 of memory controller 324A to a transmitter 342 of memory device 303A. Portions of interface 304-5 may couple transceiver 346 of memory controller 324A to transceiver 343 of memory device 303A.

FIG. 3B is a block diagram of a memory device 303B including a plurality of

transceivers

333, 334, 335, 347, 348, and 349, according to a number of embodiments of the present disclosure. FIG. 3B includes an interface 304 that includes a sixth portion 304-6, a seventh portion 304-7, an eighth portion 304-8, a ninth portion 304-9, and a tenth portion 304-10. The interface 304 may couple the memory device 303B to a host or memory controller 324B.

Memory device 303B may differ from memory device 303A of fig. 3A in that: memory device 303B implements the second interface protocol while memory device 303A implements the first interface protocol. Memory device 303A may also differ from memory device 303B in that: memory device 303B implements

command transceivers

333 and 334 in place of command receiver 341 and response transmitter 342 shown in fig. 3A, respectively.

Memory devices

303A and 303B also differ from each other in that: the receiver 341 and transmitter 342 of fig. 3A are coupled to the command and address circuitry 338 and response circuitry 339 in a different manner than the

transceivers

333 and 334 of fig. 3B are coupled to the command and address circuitry 338, response circuitry 339, and I/O circuitry 307.

Configuring memory device 303B with the second interface protocol may configure the portion of interface 304 that is configured to be unidirectional with the first interface protocol to be bidirectional. For example, portions of interfaces 304-7 and 304-9 are configured to be bi-directional with respect to memory device 303B, as opposed to the corresponding portions of interfaces 304-2 and 304-4 of FIG. 3A that are configured to be unidirectional with respect to memory device 303A. To enable a bi-directional configuration, memory device 303B may include transceivers 333 and 334 (in place of receiver 341 and transmitter 342 as shown for memory device 303A). Similarly, memory controller 324B may be enabled to achieve bi-directionality for portions of interfaces 304-7 and 304-9 by implementing

transceivers

347 and 348 of memory controller 324B instead of transmitter 344 and receiver 345 of memory controller 324A.

The interface 304 corresponding to memory device 303B may be configured such that the portion of the interface 304 is unchanged from the interface 304 corresponding to memory device 303A. For example, the portions of interfaces 304-6 and 304-8 corresponding to the first portion of the command bus and the second portion of the response bus may remain unidirectional corresponding to the portions of interfaces 304-1 and 304-3. As such, various implementations may implement a combination of a receiver and a transceiver to couple memory device 303B to portions of interfaces 304-6 and 304-7 instead of transceiver 333, as shown in association with memory device 303B. Interface 304 may also be described as including command transceiver 347, response transceiver 348, data transceiver 349, command transceiver 333, response transceiver 334, and/or data transceiver 335.

Transceivers

333 and 334 may be coupled to

MUXs

336 and 337, respectively. MUX336 may couple transceiver 333 to command/address circuitry 338 and I/O circuitry 307.MUX 337 may couple transceiver 334 to response circuitry 339 and I/O circuitry 307.

For example, portions of interface 304-6 may be coupled to command/address circuitry 338 using MUX336, as configured by the interface protocol. Portions of interface 304-7 may be coupled to command/address circuitry 338 and/or I/O circuitry 307 using MUX336, as configured by the interface protocol. Although not shown, different interface protocols may be used to configure the MUX336 to couple portions of interface 304-6 to command/address circuitry 338 and/or I/O circuitry 307 and portions of interface 304-7 to command/address circuitry 338.

Coupling portions of interface 304-7 to I/O circuitry 307 provides the ability to communicate bi-directionally, given that I/O circuitry 307 may provide data for transfer. Transmitting data using pins corresponding to portions of interfaces 304-7, 304-9, and 304-10 may result in greater data throughput than transmitting data using pins corresponding to portions of interfaces 304-10.

The particular configuration of

MUXs

336 and 337 may be controlled using mode register 331. The particular configuration of

transceivers

333 and 334 may also be controlled by mode register 331 such that command transceiver 333, response transceiver 334, MUX336, and MUX 337 are coupled to mode register 331. As used herein, the mode register 331 can include a register (e.g., memory) that can be accessed externally to the memory device 303B. The mode register 331 may be set or reset using a command provided through an open pin of the interface protocol. For example, the interface protocol may define pins as open so that commands that are not defined by the interface protocol may be provided through the open pins. A read or write command provided to the memory device 303B may be used to set or reset the mode register 331.

In some examples, the set mode register 331 may be associated with selecting a first interface protocol, while the reset mode register 331 may be associated with selecting a second interface protocol. Although the mode register 331 is labeled, a single mode register 331 may be implemented. Implementing multiple mode registers 331 provides the ability to implement more than two interface protocols. Mode register 331 may be configured to select an interface protocol that may be used to configure

MUXs

336 and 337 and

transceivers

333 and 334. For example, responsive to the set mode register 331,

muxs

336 and 337 may couple

particular transceivers

333, 334 and/or 335 of interface 304 to command/address circuitry 338, response circuitry 339 and/or I/O circuitry 307. In response to setting or resetting the mode register 331, the

transceivers

333 and 334 may be configured to transmit or receive signals to accommodate a variety of interface protocols.

The mode register 331 may be set by a host including the memory controller 324B. For example, memory device 303B may receive, via portions of interface 304-6, a command signal to set mode register 331 to configure memory device 303B with an interface protocol. The memory controller 324B may also include a memory configured to select an interface protocol. For example, the memory controller 324B may also include a separate mode register (e.g., not shown) to select an interface protocol. The interface protocol selected by memory controller 324B may conform to the interface protocol selected for memory device 303B. For example, in response to providing a command to set or reset the mode register 331 to select an interface protocol, the memory controller 324B may set or reset the mode register 324B or memory internal to the host to select the corresponding interface protocol. Thus, memory internal to memory controller 324B may also be used to control

transceivers

347, 348, and 349.

Fig. 4 illustrates an example flow diagram of a method for performing operations in a memory in accordance with several embodiments of the present disclosure. At 460, a first signal to set a mode register of a memory device to configure the transceiver to be unidirectional using a first interface protocol may be received via the transceiver. The first signal may be received from a host. For example, the first signal may be received via a command bus. At 462, a second signal can be received at the memory device, wherein the transceiver is configured to be bi-directional using a second interface protocol selected in response to receipt of the second signal, and wherein the first interface protocol is different from the second interface protocol. In various examples, the second signal may be an access command, for example. The access command may be processed by the memory device. The second signal may be processed using the second interface protocol in response to the mode register being set.

At 464, a third signal may be transmitted via a transceiver of the memory device in response to setting the mode register and the reception of the second signal. The third signal may be a response signal indicating that the second signal has been processed using the second interface protocol. For example, the third signal may indicate completion of the command identified by the second signal.

The method may further include refraining from configuring a different transceiver in response to the receiving of the first signal. That is, different transceivers may be used as unidirectional or bidirectional using the first interface protocol and the second interface protocol. The different transceiver may also be configured in response to receipt of the first signal, where the different transceiver is configured to be unidirectional using the second interface protocol and the first interface protocol. With respect to the configuration of the various transceivers, receivers, and transmitters, the transceivers, receivers, and transmitters may remain unchanged regardless of whether the first interface protocol or the second interface protocol is implemented.

The different transceivers may be configured to receive and/or transmit signals including command, address, data, and/or error signals in response to implementing the second interface protocol. The different transceivers may be limited to receiving or transmitting command, address, data, or error signals in response to implementing the first interface protocol.

In various examples, the configuration of the transceiver is performed independently of the configuration of different transceivers utilizing the first interface protocol and the second interface protocol. For example, the memory device may refrain from configuring a different transceiver in response to receipt of the first signal, wherein the different transceiver is configured to be bidirectional regardless of whether the transceiver is configured to be unidirectional or bidirectional.

In various examples, a mode register coupled to the memory device is configured to implement the set command and to cause the memory device to operate according to the first interface protocol in the first mode in response to implementing the first set command. The mode register may also be configured to cause the memory device to operate according to the second interface protocol in the second mode in response to implementing the second set command. A particular one of the transceivers may operate unidirectionally in accordance with a first interface protocol. The particular transceiver may operate bi-directionally in accordance with the second interface protocol.

A particular transceiver may be coupled to the command bus and may be configured to receive signals according to a first interface protocol and to receive and transmit signals according to a second interface protocol. Signals may be received and transmitted over a command bus. A particular transceiver may be configured to receive and transmit data over a data bus. A particular transceiver may be configured to receive and transmit commands over a command bus. A particular transceiver may be configured to receive and transmit addresses over an address bus. A particular transceiver may be configured to receive and transmit signals representing errors via pins of a memory device.

The memory device may also include a MUX coupled to the particular transceiver and configured to couple the particular transceiver to the particular decoder. For example, the multiplexer may be further configured to provide a signal received from the first decoder to a particular transceiver in response to implementation of the first set command.

The multiplexer may also be coupled to the mode register. The multiplexer may also be configured to provide a signal received via a particular transceiver to a first decoder in response to implementation of a first set command, wherein the signal is provided without providing the signal to a second decoder. The multiplexer may also be configured to provide signals received from a particular transceiver to the second decoder and signals received from the second decoder to the particular transceiver in response to implementation of the second set command. The first setup command may be used to select a first interface protocol and the second setup command may be used to select a second interface protocol.

The multiplexer may provide signals received from the particular transceiver to the first decoder and signals received from the particular transceiver to the second decoder in response to implementation of the second set command. The multiplexer may also provide a signal received from the second decoder to a particular transceiver in response to implementation of a second set command. The first interface protocol may conform to a standard and the second interface protocol may not conform to the standard. Thus, the first interface protocol may be referred to as a conforming interface protocol, and the second interface protocol may be referred to as a non-conforming interface protocol.

In various examples, a host can include a first transceiver and a device coupled to the first transceiver. The device may be configured to cause a first signal to set a mode register of the memory device to configure a second transceiver of the memory device with a second interface protocol to be transmitted via the first transceiver. That is, the host may control which interface protocol is implemented in the memory device and the host. The same interface protocol may be selected in the host and the memory device to allow the host and the interface protocol to correctly decode and encode signals utilizing the first interface protocol or the second interface protocol.

The host may cause a first transceiver configured using a first interface protocol to be configured with a second interface protocol. The first transceiver may already be unidirectional before being configured and may be bidirectional after being configured. The first interface protocol is incompatible with the second interface protocol. The host may also cause the second signal to be transmitted to the memory device utilizing the first transceiver and the second transceiver. The host may also cause a third signal to be received via the first transceiver in response to transmitting the second signal, the first signal, and in response to configuring the first transceiver. The first transceiver and the second transceiver may be coupled to a memory device of a host.

Fig. 5 illustrates an example machine of a computer system 540 within which a set of instructions for causing the machine to perform the various methodologies discussed herein may be implemented. In various embodiments, computer system 540 may correspond to a system (e.g., computing system 100 of fig. 1) that includes, is coupled to, or utilizes a memory subsystem (e.g., memory device 103 of fig. 1) or may be used to perform the operations of a controller (e.g., control circuitry 105 of fig. 1). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, an intranet, an extranet, and/or the internet. The machine may operate in the capacity of a server or a client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

The machine may be a Personal Computer (PC), a tablet PC, a set-top box (STB), a Personal Digital Assistant (PDA), a cellular telephone, a web appliance, a server, a network router, switch or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Further, while a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

An example computer system 540 includes a processing device 502, a main memory 504 (e.g., read Only Memory (ROM), flash memory, dynamic Random Access Memory (DRAM) such as Synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 506 (e.g., flash memory, static Random Access Memory (SRAM)), etc.), and a data storage system 518, which communicate with each other via a bus 530.

The processing device 502 represents one or more general-purpose processing devices such as a microprocessor, central processing unit, or the like. More particularly, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, reduced Instruction Set Computing (RISC) microprocessor, very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets or processors implementing a combination of instruction sets. The processing device 502 may also be one or more special-purpose processing devices such as an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), a Digital Signal Processor (DSP), a network processor, or the like. The processing device 502 is configured to execute instructions 526 for performing the operations and steps discussed herein. The computer system 540 may further include a network interface device 508 to communicate over the network 520.

The data storage system 518 may include a machine-readable storage medium 524 (also referred to as a computer-readable medium) on which is stored one or more sets of instructions 526 or software embodying any one or more of the methodologies or functions described herein. The instructions 526 may also reside, completely or at least partially, within the main memory 504 and/or within the processing device 502 during execution thereof by the computer system 540, the main memory 504 and the processing device 502 also constituting machine-readable storage media.

In one embodiment, the instructions 526 include instructions to implement the functionality corresponding to the host 102 and/or the memory device 103 of FIG. 1. While the machine-readable storage medium 524 is shown in an example embodiment to be a single medium, the term "machine-readable storage medium" should be taken to include a single medium or multiple media that store the one or more sets of instructions. The term "machine-readable storage medium" shall also be taken to include any medium that is capable of storing or encoding a set of instructions for execution by the machine and that cause the machine to perform any one or more of the methodologies of the present disclosure. The term "machine-readable storage medium" shall accordingly be taken to include, but not be limited to, solid-state memories, optical media, and magnetic media.

As used herein, "a number of something may refer to one or more of such things. For example, a number of memory devices may refer to one or more memory devices. The "plurality" of something is desirably two or more. Additionally, as used herein, an indicator such as "N" (particularly with respect to reference designators in the drawings) indicates that a number of the particular feature so indicated may be included in a number of embodiments of the present disclosure.

The figures herein follow a numbering convention in which the first digit or digits correspond to the drawing figure number and the remaining digits identify an element or component in the drawing. Similar elements or components between different figures may be identified by the use of similar digits. As will be appreciated, elements shown in the various embodiments herein can be added, exchanged, and/or eliminated so as to provide a number of additional embodiments of the present disclosure. Additionally, the proportion and the relative scale of the elements provided in the figures are intended to illustrate the various embodiments of the present disclosure, and are not to be used in a limiting sense.

Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that an arrangement that achieves the same result calculation may be substituted for the specific embodiments shown. This disclosure is intended to cover adaptations or variations of various embodiments of the disclosure. It is to be understood that the above description has been made in an illustrative fashion, and not a restrictive one. Combinations of the above embodiments, and other embodiments not specifically described herein, will be apparent to those of skill in the art upon reviewing the above description. The scope of the various embodiments of the present disclosure includes other applications in which the above structures and methods are used. The scope of various embodiments of the disclosure should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

In the foregoing detailed description, various features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the disclosed embodiments of the disclosure have to use more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Thus, the following claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment.

Claims

1. An apparatus, comprising:

a memory device including a plurality of transceivers; and

a mode register coupled to the memory device, wherein the mode register is configured to:

implementing a set command;

cause the memory device to operate in accordance with a first interface protocol in a first mode in response to implementing a first set command; and

cause the memory device to operate in accordance with a second interface protocol in a second mode in response to implementing a second set command;

wherein a particular one of the transceivers operates unidirectionally in accordance with the first interface protocol; and is

Wherein the particular transceiver operates bi-directionally in accordance with the second interface protocol.

2. The apparatus of claim 1, wherein the particular transceiver is coupled to a command bus and configured to:

receiving a signal according to the first interface protocol; and

receiving and transmitting signals according to the second interface protocol, wherein the signals are received and transmitted over the command bus.

3. The apparatus of claim 2, wherein the particular transceiver is configured to receive and transmit data over a data bus.

4. The apparatus of claim 2, wherein the particular transceiver is configured to receive and transmit commands via the command bus.

5. The apparatus of claim 2, wherein the particular transceiver is configured to receive and transmit addresses over an address bus.

6. The apparatus of claim 2, wherein the particular transceiver is configured to receive and transmit a signal representative of an error via a pin of the memory device.

7. The apparatus of any of claims 1-6, further comprising a Multiplexer (MUX) coupled to the particular transceiver and configured to couple the particular transceiver to a particular decoder.

8. The apparatus of claim 7, wherein the multiplexer is further configured to provide a signal received from the first decoder to the particular transceiver in response to the implementation of the first set command.

9. The apparatus of claim 7, wherein the multiplexer is further coupled to the mode register and is further configured to provide a signal received via the particular transceiver to the first decoder in response to the implementation of the first set command, wherein the signal is provided without providing the signal to the second decoder.

10. The apparatus of claim 9, wherein the multiplexer is further configured to provide a signal received from the particular transceiver to a second decoder and to provide a signal received from the second decoder to the particular transceiver in response to the implementation of the second set command.

11. The apparatus of claim 9, wherein the multiplexer is further configured to:

providing a signal received from the particular transceiver to the first decoder;

providing a signal received from the particular transceiver to the second decoder in response to the implementation of the second set command; and

providing a signal received from the second decoder to the particular transceiver in response to the implementation of the second set command.

12. The apparatus of any of claims 1-6, wherein the first interface protocol conforms to a standard and the second interface protocol does not conform to the standard.

13. A method, comprising:

receiving, via a transceiver, a first signal to set a mode register of a memory device to configure the transceiver as unidirectional using a first interface protocol;

receiving a second signal at the memory device, wherein the transceiver is configured to be bidirectional using a second interface protocol selected in response to receipt of the second signal, and wherein the first interface protocol is different from the second interface protocol; and

transmitting a third signal via the transceiver of the memory device in response to setting the mode register and receipt of the second signal.

14. The method of claim 13, further comprising refraining from configuring a different transceiver in response to receipt of the first signal.

15. The method of claim 13, further comprising configuring a different transceiver in response to receipt of the first signal, wherein the different transceiver is configured to be unidirectional using the second interface protocol and the first interface protocol.

16. The method of claim 15, further comprising configuring the different transceiver to receive a signal comprising a command, address, or error signal in response to implementing the second interface protocol.

17. The method of any of claims 13-16, further comprising refraining from configuring a different transceiver in response to receipt of the first signal, wherein the different transceiver is configured to be bidirectional regardless of whether the transceiver is configured to be unidirectional or bidirectional.

18. The method of any of claims 13-16, wherein the second signal is received via the transceiver, and wherein the third signal indicates completion of a command identified by the second signal.

19. An apparatus, comprising:

a first transceiver;

a device coupled to the first transceiver and configured to:

cause a first signal to be transmitted through the first transceiver to set a mode register of a memory device to configure a second transceiver of the memory device with a second interface protocol;

causing the first transceiver configured using a first interface protocol to be configured with the second interface protocol such that the first transceiver is unidirectional before being configured and bidirectional after being configured, and wherein the first interface protocol is different from the second interface protocol;

causing a second signal to be transmitted to the memory device utilizing the first transceiver and the second transceiver; and

causing a third signal to be received via the first transceiver in response to transmitting the second signal, the first signal, and configuring the first transceiver.

20. The apparatus of claim 19, wherein the first transceiver and the second transceiver couple the memory device to the apparatus.