CN115549505B - Midpoint potential and common-mode voltage cooperative control method of three-level NPC inverter - Google Patents

Midpoint potential and common-mode voltage cooperative control method of three-level NPC inverter Download PDF

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CN115549505B
CN115549505B CN202211517679.2A CN202211517679A CN115549505B CN 115549505 B CN115549505 B CN 115549505B CN 202211517679 A CN202211517679 A CN 202211517679A CN 115549505 B CN115549505 B CN 115549505B
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CN115549505A (en
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张树林
康劲松
张正松
宋玉明
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CHENGDU HOPE ELECTRONIC INST C
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CHENGDU HOPE ELECTRONIC INST C
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/483—Converters with outputs that each can have more than two voltages levels
    • H02M7/487—Neutral point clamped inverters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/12—Arrangements for reducing harmonics from ac input or output
    • H02M1/123—Suppression of common mode voltage or current
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/483—Converters with outputs that each can have more than two voltages levels
    • H02M7/4833—Capacitor voltage balancing

Abstract

The invention discloses a cooperative control method for a midpoint potential and a common-mode voltage of a three-level NPC inverter, which belongs to the field of power electronics and power transmission
Figure DEST_PATH_IMAGE001
And
Figure 941235DEST_PATH_IMAGE002
to limit the common-mode voltage amplitude to
Figure DEST_PATH_IMAGE003
The following; secondly, constructing a virtual voltage vector set with the midpoint current of 0 by using the rest basic voltage vectors to realize midpoint potential balance; and finally, based on the virtual voltage vector set, realizing the output current control of the three-level NPC inverter through a prediction model. The algorithm realizes the midpoint potential balance and the common-mode voltage cooperative inhibition, and has the advantages of no need of parameter setting, low harmonic content of output current and the like.

Description

Midpoint potential and common-mode voltage cooperative control method of three-level NPC inverter
Technical Field
The invention relates to the field of power electronics and power transmission, in particular to a cooperative control method for a midpoint potential and a common-mode voltage of a three-level NPC inverter.
Background
The traditional two-level inverter has a simple modulation algorithm, is limited by the voltage withstanding capability of a switching tube, and is generally used in low-voltage occasions. When the medium-high voltage is applied, the direct current bus voltage is higher, so that dv/dt in the output voltage is higher, and the harmonic performance of the output voltage is poor. In order to solve the problem, a cascade topology structure is provided, which can expand the range of voltage class and power class, but has the defects of more switching tubes, low reliability, higher cost and the like; the appearance of the three-level NPC inverter provides a new technical route for medium-high voltage application. The three-level inverter can bear high voltage, effectively reduces the voltage stress of a switching device, and can generate more levels compared with the traditional two-level inverter under the condition of the same switching frequency, so that the harmonic content of an output waveform is reduced, the torque ripple is low, and the three-level inverter is widely applied to the field of medium-high voltage high-power alternating current speed regulation. Firstly, due to the existence of ground distributed capacitance, common-mode voltage can cause the generation of common-mode current to influence the service life of a motor, and in addition, high-frequency common-mode voltage generates high-frequency electromagnetic interference to influence the normal operation of surrounding equipment; secondly, due to the characteristics of the topological structure, the midpoint potential fluctuation is too large or even seriously biased during working, so that the output voltage is distorted, and the harmonic content of the output current is increased.
Disclosure of Invention
Aiming at the problems, the invention provides a midpoint potential and common mode voltage cooperative control method of a three-level NPC inverter, which has the advantages of simultaneously inhibiting midpoint potential and common mode voltage, effectively inhibiting third harmonic of current and the like.
In order to achieve the purpose, the invention adopts the technical scheme that:
the method for cooperatively controlling the midpoint potential and the common-mode voltage of the three-level NPC inverter is realized by the following steps and principles:
s1, for 27 basic voltage vectors of the three-level NPC inverter, the common mode voltage amplitude is rounded off
Figure 646165DEST_PATH_IMAGE001
And
Figure 210001DEST_PATH_IMAGE002
the remaining 19 basic voltage vectors constitute the control set.
S2, taking each medium vector in the control set and a small vector which leads the medium vector by 90 degrees, and constructing 6 virtual medium vectors which are respectively
Figure 190595DEST_PATH_IMAGE003
Taking the 6 virtual medium vectors
Figure 294818DEST_PATH_IMAGE003
Reconstructing 6 virtual small vectors by two adjacent vectors
Figure 793537DEST_PATH_IMAGE004
。
S3, taking three adjacent basic medium vectors and two adjacent basic large vectors in the control set, and constructing 6 virtual large vectors which are respectively
Figure 59433DEST_PATH_IMAGE005
。
And S4, forming a virtual voltage vector set based on the zero vector, the 6 virtual small vectors and the 6 virtual large vectors, and realizing the control of the output current of the three-level NPC inverter through a prediction model.
Further, in the step S1, the common mode voltage has a magnitude of
Figure 261745DEST_PATH_IMAGE001
The basic voltage vector comprises on, ppo, non, opp, nno and pop, and the common-mode voltage has the amplitude of
Figure 169658DEST_PATH_IMAGE002
The basic voltage vectors of (a) include ppp, nnn; the remaining 19 fundamental voltage vectors are ooo, poo, opo, oop, oon, noo, ono, pon, opn, npo, nop, onp, pno, pnn, npn, nnp, ppn, npp, pnp;
wherein, the first and the second end of the pipe are connected with each other,
Figure 914760DEST_PATH_IMAGE006
is a dc bus voltage; p represents a switching tube
Figure 476191DEST_PATH_IMAGE007
And
Figure 306744DEST_PATH_IMAGE008
the power-on state is carried out,
Figure 487190DEST_PATH_IMAGE009
and
Figure 211432DEST_PATH_IMAGE010
off, o denotes onPipe closing device
Figure 819131DEST_PATH_IMAGE008
And
Figure 136980DEST_PATH_IMAGE009
the power-on state is carried out,
Figure 980171DEST_PATH_IMAGE007
and
Figure 699865DEST_PATH_IMAGE010
off, n denotes a switching tube
Figure 603099DEST_PATH_IMAGE009
And
Figure 408244DEST_PATH_IMAGE010
the power-on state is carried out,
Figure 930492DEST_PATH_IMAGE007
and
Figure 629327DEST_PATH_IMAGE008
turning off;x= a, b, c respectively for the three-phase legs of a three-level NPC inverter,
Figure 844407DEST_PATH_IMAGE011
in turn representx4 switching tubes from top to bottom of the bridge arm; for each phase of bridge arm, any one combination of any three of p, o and n corresponds to a basic voltage vector, and 3 bridge arms in total form
Figure 605690DEST_PATH_IMAGE012
A vector of elementary voltages.
Further, in step S2, the 6 virtual medium vectors have the following calculation formula:
Figure 321842DEST_PATH_IMAGE013
Figure 484970DEST_PATH_IMAGE014
Figure 870952DEST_PATH_IMAGE015
Figure 512674DEST_PATH_IMAGE016
Figure 642304DEST_PATH_IMAGE017
Figure 784572DEST_PATH_IMAGE018
wherein, the middle vector is opn, npo, nop, onp, pno and pon; the small vectors are poo, oon, opo, noo, oop and ono; virtual medium vector is
Figure 607035DEST_PATH_IMAGE019
(ii) a Virtual medium vector
Figure 342909DEST_PATH_IMAGE020
Synthesized by oon and pno according to equal proportion, which respectively account for 1/2; virtual medium vector
Figure 400864DEST_PATH_IMAGE021
The OPO and the pon are synthesized according to the equal proportion of 1/2; virtual medium vector
Figure 538584DEST_PATH_IMAGE022
Synthesized by the noo and the opn according to the equal proportion of 1/2 respectively; virtual medium vector
Figure 266369DEST_PATH_IMAGE023
Synthesized by oop and npo according to equal proportion of 1/2 respectively; virtual medium vector
Figure 614174DEST_PATH_IMAGE024
The ono and the nop are synthesized according to equal proportion and respectively account for 1/2; virtual medium vector
Figure 85606DEST_PATH_IMAGE025
The synthesis is carried out by po and onp according to the proportion of 1/2.
Further, in step S2, the 6 virtual small vectors are calculated as follows:
Figure 343412DEST_PATH_IMAGE026
Figure 366732DEST_PATH_IMAGE027
Figure 77199DEST_PATH_IMAGE028
Figure 211377DEST_PATH_IMAGE029
Figure 589269DEST_PATH_IMAGE030
Figure 393277DEST_PATH_IMAGE031
wherein the large vectors are pnn, ppn, npn, npp, nnp, pnp; virtual small vector is
Figure 981253DEST_PATH_IMAGE032
(ii) a Virtual small vector
Figure 528909DEST_PATH_IMAGE033
Synthesized by oon, pno, opo and pon according to equal proportion, wherein the oon, pno, opo and pon respectively account for 1/4; virtual small vector
Figure 761307DEST_PATH_IMAGE034
Is synthesized by opo, pon, noo and opn according to equal proportion which respectively account for 1/4; virtual small vector
Figure 126429DEST_PATH_IMAGE035
Synthesized by nono, opn, oop and npo which respectively account for 1/4 of the total weight of the materials according to equal proportion; virtual small vector
Figure 811489DEST_PATH_IMAGE036
Synthesized by oop, npo, ono and nop according to equal proportion, wherein the ratio of each oop, npo, ono and nop is 1/4; virtual small vector
Figure 290399DEST_PATH_IMAGE037
The materials are synthesized by ono, nop, poo and onp according to equal proportion, wherein the ratio of the materials is 1/4; virtual small vector
Figure 111725DEST_PATH_IMAGE038
The synthesis is carried out by po, onp, oon and pno according to the proportion of 1/4.
Further, in step S3, the 6 virtual large vectors are calculated as follows:
Figure 788694DEST_PATH_IMAGE039
Figure 85683DEST_PATH_IMAGE040
Figure 975141DEST_PATH_IMAGE041
Figure 182132DEST_PATH_IMAGE042
Figure 623477DEST_PATH_IMAGE043
Figure 283129DEST_PATH_IMAGE044
wherein the virtual large vector is
Figure 100912DEST_PATH_IMAGE045
(ii) a Virtual large vector
Figure 162409DEST_PATH_IMAGE046
Ppn and pnn respectively account for 1/4 according to equal proportion and pno, pon and opn respectively account for 1/6 according to equal proportion; virtual large vector
Figure 915601DEST_PATH_IMAGE047
Synthesized by 1/4 of ppn and npn in equal proportion and 1/6 of pon, opn and npo in equal proportion; virtual large vector
Figure 187183DEST_PATH_IMAGE048
The synthesis is carried out by npn and npp respectively accounting for 1/4 of the equal proportion and opn, npo and nop respectively accounting for 1/6 of the equal proportion; virtual large vector
Figure 684023DEST_PATH_IMAGE049
The synthesis is carried out by npp and nnp which are respectively 1/4 of the equal proportion and npo, nop and onp which are respectively 1/6 of the equal proportion; virtual large vector
Figure 334447DEST_PATH_IMAGE050
The synthesis is carried out by nnp and pnp which are respectively 1/4 of the equal proportion and nop, onp and pno which are respectively 1/6 of the equal proportion; virtual large vector
Figure 648754DEST_PATH_IMAGE051
Synthesized from pnp and pnn in equal proportion of 1/4 each and on, pno and pon in equal proportion of 1/6 each.
Compared with the prior art, the invention has the beneficial effects that: the invention realizes the midpoint potential balance and the common-mode voltage cooperative inhibition, can effectively inhibit the common-mode voltage, reduces the amplitude of the common-mode voltage, simultaneously keeps the midpoint potential stable, can effectively reduce the current harmonic wave, and has the advantages of no need of parameter setting, low output current harmonic wave content and the like.
Drawings
The invention is described in further detail below with reference to the following figures and detailed description:
FIG. 1 is a three-level inverter topology provided by the present invention;
FIG. 2 shows that the basic voltage vector provided by the present invention is static in two phases
Figure 17418DEST_PATH_IMAGE052
A profile in a coordinate system;
FIG. 3 is a diagram of a virtual medium vector provided by the present invention
Figure 317950DEST_PATH_IMAGE053
And virtual small vector
Figure 947514DEST_PATH_IMAGE054
A schematic construction diagram;
FIG. 4 is a diagram of a virtual large vector provided by the present invention
Figure 308088DEST_PATH_IMAGE055
A schematic construction diagram;
FIG. 5 is a graph of experimental results of a conventional algorithm, where a is the output phase voltage of the conventional algorithm, b is the output common mode voltage of the conventional algorithm, and c is the output current of the conventional algorithm;
FIG. 6 is a graph of experimental results of an algorithm of the present invention, wherein d is an output phase voltage of the present invention, e is an output common mode voltage of the present invention, and f is an output current of the present invention;
FIG. 7 is a harmonic analysis of the output current of a conventional algorithm;
FIG. 8 is a harmonic analysis of the output current of the algorithm of the present invention.
Detailed Description
The following are merely preferred embodiments of the present invention. The invention is further described in detail in connection with the drawings and the detailed description below for the understanding of the present invention by those skilled in the art, and it should be noted that all the inventions utilizing the inventive concept are protected by the protection of the present invention without departing from the principle of the present invention as long as the various changes are within the spirit and scope of the present invention defined and defined by the appended claims.
The specific implementation steps are as follows:
a method for cooperatively controlling a midpoint potential and a common-mode voltage of a three-level NPC inverter comprises the following steps:
step 1: fig. 1 shows a three-level inverter topology provided by the present invention. According to the three-level inverter topology, 27 groups of switch combinations coexist and are static in two phases
Figure 288683DEST_PATH_IMAGE052
27 basic voltage vectors are corresponded under the coordinate system;
wherein the content of the first and second substances,
Figure 127326DEST_PATH_IMAGE056
is a voltage of the direct-current bus,
Figure 752342DEST_PATH_IMAGE057
the potential is the midpoint potential of the side of the direct current bus, and N is the midpoint potential of the side of the motor; p represents a switching tube
Figure 411381DEST_PATH_IMAGE007
And
Figure 489059DEST_PATH_IMAGE008
the power-on state is carried out,
Figure 396972DEST_PATH_IMAGE058
and
Figure 266708DEST_PATH_IMAGE010
off, o denotes switching tube
Figure 703505DEST_PATH_IMAGE008
And
Figure 534058DEST_PATH_IMAGE059
the power-on state is realized,
Figure 573558DEST_PATH_IMAGE007
and
Figure 438746DEST_PATH_IMAGE010
off, n represents a switching tube
Figure 171079DEST_PATH_IMAGE059
And
Figure 488927DEST_PATH_IMAGE010
the power-on state is carried out,
Figure 207485DEST_PATH_IMAGE007
and
Figure 51813DEST_PATH_IMAGE008
turning off;x= a, b, c respectively for the three-phase legs of a three-level NPC inverter,
Figure 830413DEST_PATH_IMAGE011
in turn representx4 switching tubes from top to bottom of the bridge arm; for each phase of bridge arm, any one combination of any three of p, o and n corresponds to a basic voltage vector, and 3 bridge arms in total form
Figure 635558DEST_PATH_IMAGE060
A vector of elementary voltages.
FIG. 2 shows that the basic voltage vector provided by the present invention is static in two phases
Figure 548019DEST_PATH_IMAGE052
Distribution map in coordinate system. As shown in fig. 2, the basic voltage vectors with the common mode voltage amplitude of 0 are ooo, pon, opn, npo, nop, onp, pno; common mode voltage amplitude of
Figure 856641DEST_PATH_IMAGE061
The basic voltage vector of (1) is poo, opo, oop, oon, noo, ono, pnn, npn, nnp, ppn, npp, pnp; common modeA voltage amplitude of
Figure 71721DEST_PATH_IMAGE001
The basic voltage vector of (1) is on, non, nno, ppo, opp, pop; common mode voltage amplitude of
Figure 957638DEST_PATH_IMAGE002
The basic voltage vectors of (1) are ppp, nnn. Discarding the common-mode voltage amplitude of
Figure 549156DEST_PATH_IMAGE002
And
Figure 571339DEST_PATH_IMAGE001
the total number of basic voltage vectors of 8 is ppp, nnn, on, non, nno, ppo, opp, pop, and the remaining 19 basic voltage vectors ooo, pon, opn, npo, nop, onp, pno, poo, opo, oop, oon, noo, ono, pnn, npn, nnp, ppn, npp, pnp constitute a control set.
Step 2: FIG. 3 shows a virtual medium vector provided by the present invention
Figure 957321DEST_PATH_IMAGE053
And virtual small vector
Figure 587323DEST_PATH_IMAGE054
Constructing a schematic diagram, taking the vector in each control set and a small vector which leads the medium vector by 90 degrees, and constructing 6 virtual medium vectors as
Figure 716954DEST_PATH_IMAGE019
The 6 virtual medium vectors are calculated as follows:
Figure 734588DEST_PATH_IMAGE013
Figure 681684DEST_PATH_IMAGE014
Figure 417559DEST_PATH_IMAGE015
Figure 85301DEST_PATH_IMAGE016
Figure 347655DEST_PATH_IMAGE017
Figure 341019DEST_PATH_IMAGE018
wherein, the middle vector is opn, npo, nop, onp, pno and pon; the small vectors are poo, oon, opo, noo, oop and ono; virtual medium vector is
Figure 423244DEST_PATH_IMAGE019
(ii) a Virtual medium vector
Figure 160256DEST_PATH_IMAGE062
Synthesized by oon and pno according to equal proportion, which respectively account for 1/2; virtual medium vector
Figure 152483DEST_PATH_IMAGE063
The OPO and the pon are synthesized according to the equal proportion of 1/2; virtual medium vector
Figure 175803DEST_PATH_IMAGE064
Is synthesized by noo and opn which respectively account for 1/2 of the total weight of the mixture according to equal proportion; virtual medium vector
Figure 886270DEST_PATH_IMAGE065
Synthesized by oop and npo according to equal proportion of 1/2; virtual medium vector
Figure 161393DEST_PATH_IMAGE066
Is synthesized by ono and nop according to the equal proportion of 1/2 respectively; virtual medium vector
Figure 132760DEST_PATH_IMAGE067
The synthesis is carried out by po and onp according to the proportion of 1/2.
And step 3: FIG. 3 shows a virtual medium vector provided by the present invention
Figure 467927DEST_PATH_IMAGE053
And virtual small vector
Figure 524744DEST_PATH_IMAGE054
A schematic diagram of the structure, taking the above 6 virtual medium vectors
Figure 603559DEST_PATH_IMAGE019
Two adjacent vectors in the set reconstruct 6 virtual small vectors
Figure 570378DEST_PATH_IMAGE004
The 6 virtual small vectors are calculated as follows:
Figure 935500DEST_PATH_IMAGE068
Figure 620559DEST_PATH_IMAGE027
Figure 237485DEST_PATH_IMAGE069
Figure 186374DEST_PATH_IMAGE029
Figure 597764DEST_PATH_IMAGE070
Figure 629174DEST_PATH_IMAGE071
the 6 virtual small vector switching sequences are as follows:
Figure 49791DEST_PATH_IMAGE072
Figure 991202DEST_PATH_IMAGE073
Figure 698127DEST_PATH_IMAGE074
Figure 357779DEST_PATH_IMAGE075
Figure 50928DEST_PATH_IMAGE076
Figure 971480DEST_PATH_IMAGE077
wherein the large vectors are pnn, ppn, npn, npp, nnp, pnp; virtual small vector is
Figure 990251DEST_PATH_IMAGE004
(ii) a Virtual small vector
Figure 871620DEST_PATH_IMAGE033
Synthesized by oon, pno, opo and pon according to equal proportion, wherein the oon, pno, opo and pon respectively account for 1/4; virtual small vector
Figure 493094DEST_PATH_IMAGE034
Is synthesized by opo, pon, noo and opn according to equal proportion which respectively account for 1/4; virtual small vector
Figure 409097DEST_PATH_IMAGE035
Is composed of noo, opn, oop,npo is synthesized according to the equal proportion of 1/4; virtual small vector
Figure 457825DEST_PATH_IMAGE078
Synthesized by oop, npo, ono and nop according to equal proportion, wherein the ratio of each oop, npo, ono and nop is 1/4; virtual small vector
Figure 92068DEST_PATH_IMAGE037
The materials are synthesized by ono, nop, poo and onp according to equal proportion, wherein the ratio of the materials is 1/4; virtual small vector
Figure 127020DEST_PATH_IMAGE079
The synthetic method is characterized in that the synthetic method is synthesized by poo, onp, oon and pno according to the equal proportion of 1/4.
And 4, step 4: FIG. 4 shows a virtual large vector provided by the present invention
Figure 22164DEST_PATH_IMAGE055
Constructing a schematic diagram, taking three adjacent basic medium vectors and two adjacent basic large vectors in the control set, and constructing 6 virtual large vectors respectively
Figure 117159DEST_PATH_IMAGE005
The 6 virtual large vectors are calculated as follows:
Figure 973120DEST_PATH_IMAGE080
Figure 936396DEST_PATH_IMAGE040
Figure 826992DEST_PATH_IMAGE081
Figure 358467DEST_PATH_IMAGE042
Figure 563708DEST_PATH_IMAGE043
Figure 206042DEST_PATH_IMAGE044
the 6 virtual large vector switching sequences are as follows:
Figure 810199DEST_PATH_IMAGE082
Figure 512576DEST_PATH_IMAGE083
Figure 77549DEST_PATH_IMAGE084
Figure 648208DEST_PATH_IMAGE085
Figure 247817DEST_PATH_IMAGE086
Figure 121095DEST_PATH_IMAGE087
wherein the virtual large vector is
Figure 32419DEST_PATH_IMAGE045
(ii) a Virtual large vector
Figure 282135DEST_PATH_IMAGE046
Ppn and pnn respectively account for 1/4 according to equal proportion and pno, pon and opn respectively account for 1/6 according to equal proportion; virtual large vector
Figure 860883DEST_PATH_IMAGE047
Synthesized by 1/4 of ppn and npn in equal proportion and 1/6 of pon, opn and npo in equal proportion; virtual large vector
Figure 905063DEST_PATH_IMAGE048
The synthesis is carried out by npn and npp respectively accounting for 1/4 of the equal proportion and opn, npo and nop respectively accounting for 1/6 of the equal proportion; virtual large vector
Figure 179049DEST_PATH_IMAGE049
The synthesis is carried out by npp and nnp which are respectively 1/4 of the equal proportion and npo, nop and onp which are respectively 1/6 of the equal proportion; virtual large vector
Figure 91511DEST_PATH_IMAGE050
The synthesis is carried out by nnp and pnp which are respectively 1/4 of the equal proportion and nop, onp and pno which are respectively 1/6 of the equal proportion; virtual large vector
Figure 400132DEST_PATH_IMAGE051
Synthesized from pnp and pnn in equal proportion of 1/4 each and on, pno and pon in equal proportion of 1/6 each.
And 5: and forming a virtual voltage vector set based on the zero vector, the 6 virtual small vectors and the 6 virtual large vectors, and realizing the control of the output current of the three-level NPC inverter through a prediction model.
FIG. 5 is a graph of experimental results of a conventional algorithm, where a is the output phase voltage of the conventional algorithm, b is the output common mode voltage of the conventional algorithm, and c is the output current of the conventional algorithm; FIG. 6 is a graph of experimental results of an algorithm of the present invention, wherein d is an output phase voltage of the present invention, e is an output common mode voltage of the present invention, and f is an output current of the present invention; comparing fig. 5 and fig. 6, it can be found that the cooperative control method of the midpoint potential and the common mode voltage of the three-level NPC inverter provided by the invention can effectively suppress the common mode voltage, so that the amplitude of the common mode voltage is reduced, and the midpoint potential is kept stable.
FIG. 7 is a harmonic analysis of the output current of the conventional algorithm, and FIG. 8 is a harmonic analysis of the output current of the algorithm of the present invention; comparing fig. 7 and fig. 8, it can be found that the cooperative control method of the midpoint potential and the common mode voltage of the three-level NPC inverter provided by the invention can effectively reduce the current harmonics.
While the embodiments of the invention have been described in detail in connection with the accompanying drawings, it is not intended to limit the scope of the invention. Various modifications and changes may be made by those skilled in the art without inventive step within the scope of the appended claims.

Claims (2)

1. A method for cooperatively controlling a midpoint potential and a common-mode voltage of a three-level NPC inverter is characterized by comprising the following steps of:
s1, for 27 basic voltage vectors of the three-level NPC inverter, the common mode voltage amplitude is cut offU dc /3 andU dc 8 basic voltage vectors of/2, and the rest 19 basic voltage vectors form a control set;
s2, taking each medium vector in the control set and a small vector which leads the medium vector by 90 degrees, and constructing 6 virtual medium vectors which are respectivelyV M1 、V M2 、V M3 、V M4 、V M5 、V M6 The 6 virtual medium vectors are calculated as follows:
Figure QLYQS_1
，
Figure QLYQS_2
，
Figure QLYQS_3
，
Figure QLYQS_4
，
Figure QLYQS_5
，
Figure QLYQS_6
，
wherein, the middle vector is opn, npo, nop, onp, pno and pon; the small vectors are poo, oon, opo, noo, oop and ono; virtual medium vector isV M1 、V M2 、V M3 、V M4 、V M5 、V M6 (ii) a Virtual medium vectorV M1 Synthesized by oon and pno according to equal proportion, which respectively account for 1/2; virtual medium vectorV M2 The OPO and the pon are synthesized according to the equal proportion of 1/2; virtual medium vectorV M3 Synthesized by the noo and the opn according to the equal proportion of 1/2 respectively; virtual medium vectorV M4 Synthesized by oop and npo according to equal proportion of 1/2; virtual medium vectorV M5 Is synthesized by ono and nop according to the equal proportion of 1/2 respectively; virtual medium vectorV M6 The POO and the onp are synthesized according to the equal proportion of 1/2 respectively;
taking the 6 virtual medium vectorsV M1 、V M2 、V M3 、V M4 、V M5 、V M6 Reconstructing 6 virtual small vectors by two adjacent vectorsV SS1 、V SS2 、V SS3 、V SS4 、V SS5 、V SS6 The 6 virtual small vectors are calculated as follows:
Figure QLYQS_7
，
Figure QLYQS_8
，
Figure QLYQS_9
，
Figure QLYQS_10
，
Figure QLYQS_11
，
Figure QLYQS_12
，
wherein the large vector is pnn, ppn, npn, npp, nnp, pnp; virtual small vector isV SS1 、V SS2 、V SS3 、V SS4 、V SS5 、V SS6 (ii) a Virtual small vectorV SS1 Synthesized by oon, pno, opo and pon according to equal proportion, wherein the oon, pno, opo and pon respectively account for 1/4; virtual small vectorV SS2 Is synthesized by opo, pon, noo and opn according to equal proportion which respectively account for 1/4; virtual small vectorV SS3 Synthesized by nono, opn, oop and npo which respectively account for 1/4 of the total weight of the materials according to equal proportion; virtual small vectorV SS4 Synthesized by oop, npo, ono and nop according to equal proportion, wherein the ratio of each oop, npo, ono and nop is 1/4; virtual small vectorV SS5 The materials are synthesized by ono, nop, poo and onp according to equal proportion, wherein the ratio of the materials is 1/4; virtual small vectorV SS6 The synthetic method is characterized in that the synthetic method is synthesized by poo, onp, oon and pno according to equal proportion, wherein the proportion of the poo, the onp, the oon and the pno is 1/4;
s3, taking three adjacent basic medium vectors and two adjacent basic large vectors in the control set, and constructing 6 virtual large vectors which are respectivelyV LL1 、V LL2 、V LL3 、V LL4 、V LL5 、V LL6 The 6 virtual large vectors are calculated as follows:
Figure QLYQS_13
，
Figure QLYQS_14
，
Figure QLYQS_15
，
Figure QLYQS_16
，
Figure QLYQS_17
，
Figure QLYQS_18
，
wherein the virtual large vector isV LL1 、V LL2 、V LL3 、V LL4 、V LL5 、V LL6 (ii) a Virtual large vectorV LL1 Ppn and pnn respectively account for 1/4 according to equal proportion and pno, pon and opn respectively account for 1/6 according to equal proportion; virtual large vectorV LL2 Synthesized by 1/4 of ppn and npn in equal proportion and 1/6 of pon, opn and npo in equal proportion; virtual large vectorV LL3 The synthesis is carried out by npn and npp respectively accounting for 1/4 of the equal proportion and opn, npo and nop respectively accounting for 1/6 of the equal proportion; virtual large vectorV LL4 The synthesis is carried out by npp and nnp which are respectively 1/4 of the equal proportion and npo, nop and onp which are respectively 1/6 of the equal proportion; virtual large vectorV LL5 The synthesis is carried out by nnp and pnp which are respectively 1/4 of the equal proportion and nop, onp and pno which are respectively 1/6 of the equal proportion; virtual large vectorV LL6 The synthesis is carried out by pnp and pnn which are respectively 1/4 of the equal proportion and onp, pno and pon which are respectively 1/6 of the equal proportion;
and S4, forming a virtual voltage vector set based on the zero vector, the 6 virtual small vectors and the 6 virtual large vectors, and realizing the control of the output current of the three-level NPC inverter through a prediction model.
2. The cooperative control method for the midpoint potential and the common-mode voltage of the three-level NPC inverter as recited in claim 1, whereinIn the step S1, the common mode voltage amplitude isU dc The basic voltage vector of/3 comprises on, ppo, non, opp, nno and pop, and the common-mode voltage amplitude isU dc The basic voltage vector of/2 includes ppp, nnn; the remaining 19 fundamental voltage vectors are ooo, poo, opo, oop, oon, noo, ono, pon, opn, npo, nop, onp, pno, pnn, npn, nnp, ppn, npp, pnp;
wherein the content of the first and second substances,U dc is a dc bus voltage; p represents a switching tube T x1 And T x2 Conduction, T x3 And T x4 Off, o denotes the switching tube T x2 And T x3 Conduction, T x1 And T x4 Off, n denotes the switching tube T x3 And T x4 Conduction, T x1 And T x2 Turning off;x= a, b, c for the three-phase leg of the three-level NPC inverter, T respectively x1 、T x2 、T x3 、T x4 In turn representx4 switching tubes from top to bottom of the bridge arm; for each phase of bridge arm, any one combination of three of p, o and n corresponds to a basic voltage vector, and 3 bridge arms in total form 3 3 =27 basis voltage vectors.
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