CN115549433A

CN115549433A - Filtering module and electronic equipment

Info

Publication number: CN115549433A
Application number: CN202110738263.2A
Authority: CN
Inventors: 白昕昊; 眭克涵; 周宴; 蔡远彬
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2021-06-30
Filing date: 2021-06-30
Publication date: 2022-12-30
Also published as: WO2023273635A1

Abstract

The application relates to the technical field of circuits, and discloses a filtering module and electronic equipment. The filtering module comprises a printed circuit board, and a chip packaging structure is arranged on the upper surface of the printed circuit board; the upper surface of the printed circuit board comprises a chip power contact area, the chip power contact area comprises a chip power contact, and the power module supplies power to the chip packaging structure through the power contact; the lower surface of the printed circuit board comprises a first area, and the first area is arranged opposite to the power supply contact area of the chip; the capacitors are arranged in the first area in parallel, and the capacitors are arranged between a connecting line for supplying power to the chip packaging structure by the power supply module and a ground wire in parallel; the lower surface of the printed circuit board comprises a second area which is arranged corresponding to the non-chip power supply contact area; the expansion board is arranged in the second area; at least one additional capacitor connected in parallel with the plurality of capacitors is disposed on the expansion board. Therefore, the performance of voltage reduction, voltage stabilization and the like in the filtering module is improved to a certain extent.

Description

Filtering module and electronic equipment

Technical Field

The application relates to the technical field of circuits, in particular to a filtering module and electronic equipment.

Background

With the increase of the chip capability and the advance of the computing capability, the power supply requirement of the chip is also increased, for example, at present, the steady-state current of some chips exceeds 1000A, and the transient current jump exceeds 2000A/uS.

For example, taking a chip in a base station as an example, in a process that a power supply circuit of the base station outputs a power supply current to the chip of the base station, a large current and a current need to rapidly jump in a transient state to suppress voltage drop through rapid discharge of the power supply circuit in the power supply circuit, and improving the layout density of capacitors is called as a key technology for successful products.

However, in the prior art, because the spatial position of the circuit board where the chip is located is limited, the filter capacitor in the power supply circuit arranged on the circuit board is less, and there is a contradiction between the dynamic performance of the load current and the insufficient capacity of the capacitor, that is, the power supply circuit cannot effectively suppress the drop of the output voltage of the power supply circuit to the chip.

Disclosure of Invention

In order to overcome the technical problem, a first aspect of the embodiments of the present application provides a filtering module, where the module includes a printed circuit board, a chip package structure, a power module, a plurality of capacitors, an expansion board, and at least one additional capacitor;

the printed circuit board has an upper surface and a lower surface opposite to the upper surface;

the chip packaging structure is arranged on the upper surface of the printed circuit board;

the upper surface of the printed circuit board comprises a chip power contact area, the chip power contact area comprises a chip power contact, and the power module supplies power to the chip packaging structure through the power contact;

the lower surface of the printed circuit board comprises a first area, and the first area is arranged opposite to the chip power supply contact area;

the capacitors are arranged in the first area in parallel, and the capacitors are arranged between a connecting line for supplying power to the chip packaging structure by the power supply module and a ground wire in parallel;

the lower surface of the printed circuit board comprises a second area which is arranged corresponding to the non-chip power supply contact area;

the expansion plate is arranged in the second area;

the at least one additional capacitor is connected with the plurality of capacitors in parallel and arranged on the expansion board.

It is understood that the filter module can also be called a chip module, and the non-chip power contact area can be any one or more of a storage contact area and a high-speed input/output contact area adjacent to the chip power contact area. The second region may be any one or more of a memory pin region and an input/output pin region, but is not limited thereto. The expansion board, also called a pinch plate, is a carrier for electrical interconnection of electronic components, such as a printed circuit board. The chip packaging structure can be arranged in the chip arrangement area.

Referring to the embodiment shown in fig. 11, the PCB120 is provided with a conductive channel 126 serving as a power line, the conductive channel 126 extends along the thickness (z axis) direction of the PCB120 from the upper surface 121 of the PCB120, extends along the extension length direction (y axis), extends along the thickness (z axis) direction of the PCB120, and reaches the bending channel on the upper surface 121 of the PCB120, and the inner wall of the bending channel is provided with a conductive medium, such as copper, but not limited thereto. As shown in fig. 9, the conductive via 127a serves as a ground line.

Compared with the structure without the additional capacitor in the prior art, the additional capacitor can store more capacitors, and the instant voltage drop can be reduced by using the electric energy stored by the additional capacitor under the condition that the instant voltage drop is generated in the power supply process of the power module for the chip packaging structure.

In a possible implementation of the first aspect, at least one conductive via and at least one ground via are disposed on the expansion board;

a conductive hole is formed in the printed circuit board, and one end of the conductive hole is electrically connected with a connecting wire for supplying power to the chip packaging structure by the power supply module;

the other end of the conductive hole is electrically connected with one end of each additional capacitor in the at least one additional capacitor, and the other end of each additional capacitor in the at least one additional capacitor is electrically connected with a grounding wire in the printed circuit board through the grounding via hole.

In a possible implementation of the first aspect, the filter module further includes a first conductive channel, where the first conductive channel does not penetrate through the printed circuit board in a thickness direction of the printed circuit board;

the conductive via is located between the first conductive channel and the lower surface.

The first conductive channel does not penetrate through the printed circuit board in the thickness direction, and the conductive via hole is positioned between the first conductive channel and the lower surface and is provided with a larger space (in the X-axis direction, the Y-axis direction and the Z-axis direction) position in which the conductive channel connected with a power line can be arranged.

In one possible implementation of the first aspect, the at least one additional capacitor is disposed on a lower surface of the expansion board.

In one possible implementation of the first aspect, a part of the at least one additional capacitor is disposed on a lower surface of the expansion board, the rest of the additional capacitors are arranged inside the expansion board.

In one possible implementation of the first aspect, the at least one additional capacitor is disposed inside the expansion board.

In a possible implementation of the first aspect, the printed circuit board has a multi-layer structure, and the conductive vias are sequentially electrically connected to a part of the multi-layer structure in the printed circuit board.

In one possible implementation of the first aspect, the non-chip power contact region is a contact region adjacent to the chip power contact region.

It will be appreciated that the non-chip power contact area may be any one or more of a storage contact area, a high speed input output contact area adjacent to the chip power contact area.

In a possible implementation of the first aspect, the chip package structure is an integrated structure of any one or more of an application processor, a modem processor, a graphics processor, an image signal processor, a controller, a video codec, a digital signal processor, a baseband processor, and a neural network processor.

In a possible implementation of the first aspect, the filter module further includes a power device, and the power device is disposed on the expansion board.

It will be appreciated that more additional capacitors may be provided in parallel with the expansion board, and thus the above-mentioned voltage drop and transient voltage drop problems may be better reduced. In addition, other power devices than capacitors, such as resistors and inductors, may be disposed on the expansion board. Other power devices than capacitors may be connected in series or in parallel with the additional capacitors, etc.

In a second aspect, an embodiment of the present application further provides an electronic device, where the electronic device includes the filter module of any one of the first aspects.

Drawings

Fig. 1 is a schematic diagram illustrating an application scenario of a chip module according to some embodiments of the present application;

fig. 2 shows a schematic structural diagram of a base station 1 according to an embodiment of the present application;

FIG. 3 illustrates a schematic structural diagram of a generic chip module, according to some embodiments of the present application;

fig. 4 is an exploded view of the chip module 100 in fig. 3 along the Y-axis direction;

fig. 5 is a schematic diagram illustrating the distribution of different types of pins on the lower surface 111 of the chip package structure 110 and the upper surface 121 of the PCB120 according to different connecting devices of the pins based on the chip module structure of fig. 3;

FIG. 6 is a schematic diagram showing a distribution of additional expansion plates and additional capacitors on the lower surface 124 of the printed circuit board 120;

FIG. 7 illustratesbase:Sub>A cross-sectional view of the chip module 100 taken along the A-A direction shown in FIG. 3 in some embodiments;

FIG. 8 is a schematic diagram showing a distribution of additional expansion plates and additional capacitors on the lower surface 124 of the printed circuit board 120;

fig. 9 showsbase:Sub>A cross-sectional view of the chip module taken alongbase:Sub>A-base:Sub>A direction in fig. 3;

fig. 10 isbase:Sub>A cross-sectional view of still another chip module taken alongbase:Sub>A-base:Sub>A direction in fig. 3;

fig. 11 is a schematic cross-sectional view of the chip module 100 taken along the direction B-B shown in fig. 3;

fig. 12 shows a cross-sectional view of a chip module in the YZ plane;

FIG. 13 illustrates a partial cross-sectional view in a YZ plane of an extension board with additional capacitors disposed therein;

FIG. 14 is a partial cross-sectional view in a YZ plane of an extension board with additional capacitors disposed therein;

FIG. 15 is a schematic diagram showing a distribution of additional expansion plates and additional capacitors on the lower surface 124 of the printed circuit board 120;

FIG. 16 showsbase:Sub>A cross-sectional view of the universal chip module taken along the A-A direction in FIG. 3;

FIG. 17 is a schematic diagram showing a distribution of additional expansion plates and additional capacitors on the lower surface 124 of the printed circuit board 120;

FIG. 18 showsbase:Sub>A cross-sectional view of the generic chip module taken along the direction A-A in FIG. 3;

FIG. 19 isbase:Sub>A cross-sectional view ofbase:Sub>A chip module taken along the line A-A in FIG. 3, corresponding to FIG. 8, according to an embodiment of the present application;

fig. 20 is a circuit diagram illustrating a simplified structure among the power module 140, the chip package structure 110, the capacitor 160, the capacitor 180, and the capacitor 190 according to an embodiment of the present disclosure;

fig. 21 is a schematic diagram of a Power Delivery Network (PDN) diagram of the chip module 100 without the expansion board 170;

fig. 22 is a diagram illustrating a PDN curve of the chip module 100 after an expansion board 170 is attached to the PCB 120.

Description of reference numerals:

1-a base station; 2-a terminal; 3-a terminal;

101-a signal receiver; 102-a signal transmitter; 103-video monitoring instrument; 100-chip module; 110-central processing unit (chip package); 120-a printed circuit board; 130-a memory; 140-a power supply module; 150-video monitoring instrument control chip;

111-the lower surface of the chip package structure; 121-the upper surface of the chip package structure, 122-the chip placement area; 123-non-chip setting area;

1112-chip power pin area; 1212-chip power contact area;

1113-store pin area; 1213-a storage contact area;

1114 — input output pin area; 1214-input output contact area;

1111-power pin area; 1211-the power contact area;

124-lower surface;

127 a-a conductive via; 127 b-a conductive channel; 127 c-a conductive channel; 129-conductive channels;

f-additional capacitance; f2-capacitor body; f1-a first electrode end; f3-a second electrode terminal;

170-an expansion board; 171-conductive vias; 172-lower surface of expansion plate; 173-the upper surface of the expansion board; 200-solder ball.

Detailed Description

The following description of the embodiments of the present application is provided by way of specific examples, and other advantages and effects of the present application will be readily apparent to those skilled in the art from the disclosure herein. While the description of the present application will be presented in conjunction with certain examples, this is not intended to limit the features of this application to that embodiment. On the contrary, the application of the present disclosure with reference to the embodiments is intended to cover alternatives or modifications as may be extended based on the claims of the present disclosure. In the following description, numerous specific details are included to provide a thorough understanding of the present application. The present application may be practiced without these particulars. Moreover, some of the specific details have been omitted from the description in order to avoid obscuring or obscuring the focus of the present application. It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict.

It should be noted that in this specification, like reference numerals and letters refer to like items in the following drawings, and thus, once an item is defined in one drawing, it need not be further defined and explained in subsequent drawings.

In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "electrically connected" are to be construed broadly, e.g., as meaning either a fixed electrical connection, a removable electrical connection, or an integral electrical connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.

The illustrative embodiments of the present application include, but are not limited to, a chip module and a base station. For convenience of understanding, the technical solution of the present application is described with a base station as an application scenario, but it can be understood that the chip module mentioned in the technical solution of the present application may also be used in other electronic devices, for example, a server, a satellite system, and the like.

Fig. 1 is a schematic diagram illustrating an application scenario of a chip module according to some embodiments of the present application.

As shown in fig. 1, in the application scenario, the base station 1, the terminal 2, and the terminal 3 are provided with a chip module inside. It can be understood that the base station 1, i.e. the public mobile communication base station, is an interface device for the terminals 2 and 3 to access the internet, and the information is transferred between the terminals 2 and 3 through the base station 1.

A schematic structural diagram of a base station 1 in which a chip module provided in the embodiment of the present application is disposed is described below, and fig. 2 shows a schematic structural diagram of a base station 1 according to the embodiment of the present application.

As shown in fig. 2, the base station 1 may include a central processor 110, a signal receiver 101, a signal transmitter 102, a power module 140, a memory 130, a video monitoring instrument control chip 150, and a video monitoring instrument 103. It is understood that the central processing unit 110, the power module 140, the memory 130, the video monitoring apparatus control chip 150 and the video monitoring apparatus 103 may be integrated into the chip module mentioned in the present application.

Specifically, the signal receiver 101, the signal transmitter 102, the power supply module 140, the memory 130 and the video monitoring instrument 103 are respectively connected to the central processing unit 110.

The power module 140 is used for supplying power to the central processing unit 110, the signal receiver 101, the signal transmitter 102, the power module 140, the memory 130, the video monitoring instrument control chip 150 and the video monitoring instrument 103; the memory 130 is used for storing part of the data sent by the central processing unit 110; the video monitoring instrument control chip 150 is used for controlling the working state of the video monitoring instrument 103; the video monitoring instrument 103 is used for shooting video and sending the video data to the central processing unit 110 for processing through the video monitoring instrument control chip 150, and the central processing unit 110 may further send the shot video data to the memory 130 for storage.

The signal receiver 101 is configured to receive information sent by other devices, and the signal transmitter 102 is configured to forward the information received by the signal receiver 101 to other devices. In the application scenario shown in fig. 1, it is assumed that a user 1 wants to send information to a terminal 2 of a user 2 by using a terminal 1, and the terminal 1 needs to forward the information to the terminal 2 of the user 2 through a base station 2. Specifically, the user 1 uses the terminal 1 to transmit the signal receiver 101 for receiving information, for example, information of the terminal 1, and transmits the received information to the central processing unit 110, the central processing unit 110 encodes the received information and transmits the encoded information to the signal transmitter 102, and the signal transmitter 102 transmits the encoded information to other devices, for example, the terminal 2.

It can be understood that, in order to ensure the normal operation of the cpu 110, the power module 140 is required to provide a large and stable current to the cpu 110. However, as mentioned above, the current power supply circuit for supplying power to the cpu 110 by the power module 140 cannot effectively suppress the drop of the output voltage of the power module 140 to the cpu 110.

In order to solve the above technical problem, an embodiment of the present application discloses a chip module, which may include the power module 140 and the central processing unit 110, and in the chip module, an additional capacitor is added in a line for supplying power to the central processing unit 110 by the power module 140, so as to reduce impedance on a power supply line for supplying power to the central processing unit 110 by the power module 140, and reduce voltage drop in a process of supplying power to the central processing unit 110 by the power module 140, and compared with a structure in which no additional capacitor is provided in the prior art, the additional capacitor added can store more capacitors, and under a condition that an instantaneous voltage drop is generated in a process of supplying power to the central processing unit 110 by the power module 140, the instantaneous voltage drop can be reduced by using electric energy stored by the additional capacitor.

To make the objects, technical solutions and advantages of the present application more clear, embodiments of the present application will be described in further detail below with reference to the accompanying drawings. For convenience of description, the chip module in the present application is described below by taking the base station 1 as an example, but it is understood that the chip module in the present application may also be applied to other electronic devices, such as a server, a satellite system, and the like.

Fig. 3 illustrates a schematic structural diagram of a generic chip module, according to some embodiments of the present application. The chip module may include the central processing unit 110, the memory 130, the power module 140, and the video monitoring apparatus control chip 150 of the base station 1.

As shown in fig. 3, the chip module 100 includes a chip package structure 110, a Printed Circuit Board (PCB) 120, a memory 130, a power module 140, and a video monitoring instrument control chip 150.

The Chip package structure 110 is the central processing unit 110 in the base station 1, which is also called a Chip package (Chip package), and is a structure that a bare Chip is packaged and arranged as a plurality of pins for electrically connecting with other electronic devices.

Specifically, a DIE (DIE) is a chip produced in a manufacturing plant, that is, a wafer is not packaged after a dicing test, and only a bonding pad (pad) for packaging on the DIE cannot be directly applied to an actual circuit. However, the bare chip is easily affected by the temperature, impurities and physical force of the external environment and is easily damaged, so the bare chip must be sealed in a closed space to lead out corresponding pins to be used as a basic component. The die is usually mounted on a Chip package carrier, the internal circuits of the die are electrically connected to the package pins by gold wires through bonding wires (bonding), and the die is packaged by a black glue after bonding to form a Chip package.

Furthermore, it is understood that the chip package structure 110 may refer to a modem processor, a graphic processor, an image signal processor, a controller, a video codec, a digital signal processor, a baseband processor, a neural network processor, etc. in other devices besides the central processor 110 in the base station 1 shown in fig. 2, and an integration of at least two of the application processor, the modem processor, the graphic processor, the image signal processor, the controller, the video codec, the digital signal processor, the baseband processor, and the neural network processor. I.e. the different processing units may be separate devices or may be integrated in one or more processors.

The Printed Circuit Board (PCB) 120 is a support for electronic components and is a carrier electrically connected to the electronic components. Specifically, in some electronic structures, on the upper surface 121 of the PCB120, the chip package structure 110 and the memory 130, the power module 140, the video monitoring instrument control chip 150, and the like are disposed, but are not limited thereto.

In the XYZ coordinate system, the chip module 100 is substantially located in a plane (XY plane) in which the Z-axis direction (referred to as "normal") is oriented in a direction from the chip module 100 toward the viewer, that is, the thickness direction of the chip module 100. The X-axis direction is defined as a length direction of the chip module 100 from left to right. The Y-axis direction is defined as a width direction of the chip module 100 from front to back.

A Printed Circuit Board (PCB) 120 and a chip package structure 110 are sequentially disposed in the y-axis direction. The chip package structure 110 and the Printed Circuit Board (PCB) 120 may be electrically connected through a conductive medium (not shown).

Fig. 4 is an exploded view of the chip module 100 in fig. 3 along the Y-axis direction. As shown in fig. 4, in some electronic structures, the PCB120 has an upper surface 121 facing the Z-axis direction, the upper surface 121 has a chip disposing region 122 thereon, and the chip packaging structure 110 is disposed on the chip disposing region 122. The non-chip-mounting area 123 on the upper surface 121 of the PCB120 adjacent to the chip-mounting area 122 is used for mounting some electronic devices, such as, but not limited to, a memory 130, a power module 140, a video monitoring instrument control chip 150, and the like.

With reference to fig. 4, the chip package structure 110 has a lower surface 111 facing the opposite direction of the Z-axis, and the lower surface 111 is used for being attached to a chip mounting region 122 on an upper surface 121 of the PCB 120. In some embodiments, the chip package structure 110 may be a Ball Grid Array (BGA) printed circuit board, which is a packaging method for an integrated circuit using an organic carrier.

For convenience of describing the technical solution of the present application, the distribution of the various pins in the chip module 100 is defined below. Specifically, fig. 5 is a schematic diagram illustrating the distribution of different types of pins on the lower surface 111 of the chip package structure 110 and the upper surface 121 of the PCB120 according to different connecting devices of the pins based on the chip module structure of fig. 3.

(1) Chip power pin area 1112 and chip power contact area 1212

As shown in fig. 5, a chip power pin region 1112 is disposed on the lower surface 111 of the chip package structure 110, and the power module 140 can supply power to the chip package structure 110 through the power pins in the chip power pin region 1112.

Corresponding to chip power pin area 1112 on lower surface 111 of upper chip package structure 110, chip power contact area 1212 is provided on upper surface 121 of pcba 120, wherein power contacts in chip power contact area 1212 are adapted to electrically connect with power pins in chip power pin area 1112, and power module 140 is capable of supplying power to chip package structure 110 through the power contacts and power pins.

It is understood that in some embodiments, the chip power pin area 1112 may be disposed in a middle region of the lower surface 111 of the chip package structure 110, but is not limited thereto.

(2) Storage pin area 1113 and storage contact area 1213

Continuing to refer to fig. 5, a memory pin area 1113 is disposed on the lower surface 111 of the chip package structure 110, the chip package structure 110 can send data to be stored to the memory 130 through a memory pin in the memory pin area 1113, and the memory pin area 1113 may also be referred to as a DDR area or a DDR area.

A storage contact area 1213 is provided on the upper surface 121 of the pcbs 120 corresponding to the storage pin area 1113 on the lower surface 111 of the upper chip package structure 110, wherein the memory contacts in the storage contact area 1213 are used for connecting with the memory pins in the storage pin area 1113, and the chip package structure 110 is capable of sending data to be stored to the memory 130 via the memory pins and the memory contacts. It is understood that in some embodiments, the storage pin region 1113 may be disposed in a peripheral region of the lower surface 111 of the chip package structure 110 adjacent to the chip power pin region 1112, but is not limited thereto.

(3) Input-output pin area 1114 and input-output contact area 1214

Continuing to refer to fig. 5, the lower surface 111 of the chip package structure 110 is provided with an Input/output pin area 1114, the chip package structure 110 can perform command interaction and data transmission with the video monitoring instrument control chip 150 through the Input/output pins of the Input/output pin area 1114, and the Input/output pin area 1114 may also be referred to as a high speed I/O (Input/output) area or a high speed I/O area.

Corresponding to the input/output pin area 1114 on the lower surface 111 of the upper chip package 110, an input/output contact area 1214 is disposed on the upper surface 121 of the pcba 120, wherein the input/output contacts in the input/output contact area 1214 are used for connecting with the input/output pins, and the chip package 110 can perform command interaction and data transmission with the video monitor instrument control chip 150 through the input/output contacts and the input/output pins. The input and output pin region 1114 may be disposed at a peripheral region of the lower surface 111 of the chip package structure 110 adjacent to the chip power pin region 1112, but is not limited thereto.

(4) Power pin zone 1111 and power contact zone 1211

With reference to fig. 5, the lower surface 111 of the chip package structure 110 is provided with a power pin region 1111, and the chip package structure 110 can supply power to the electronic device such as the memory 130 through the power pins of the power pin region 1111.

Corresponding to power pin area 1111 on lower surface 111 of upper chip package structure 110, power contact area 1211 is disposed on upper surface 121 of pcba 120, wherein power contacts in power contact area 1211 are capable of providing power to electronic devices such as memory 130 through power pins and power contacts.

It is to be understood that the input-output contact area 1214 and the storage contact area 1213 are collectively referred to as a non-chip power contact area, and the input-output pin area 1114, the input-output contact area 1214, the storage pin area 1113, and the storage contact area 1213 are collectively referred to as a non-power area.

As described above, in the related art, the power supply circuit between the power module 140 and the chip package structure 110 is provided with a plurality of capacitors connected in parallel for filtering and stabilizing the electric signals (current and/or voltage) between the power module 140 and the chip package structure 110, which are generally disposed in the region corresponding to the chip power contact region 1212 on the lower surface 124 of the PCB120 shown in fig. 4.

However, the existing power supply circuit disposed on the PCB120 has a small capacitance, and there is a contradiction between the dynamic performance of the load current and the insufficient capacitance, that is, the power supply circuit cannot effectively suppress the drop of the output voltage of the power supply circuit to the chip.

To solve this problem, the capacitance in the power supply circuit may be increased in the area corresponding to the area outside the power contact area 1212 on the lower surface 124 of the PCB120, for example, fig. 6 shows a distribution diagram in which an expansion board and an additional capacitance are added on the lower surface 124 of the PCB 120.

As shown in fig. 6, the area of the lower surface 124 of the PCB120 corresponding to the storage contact area 1213. There is a problem of short circuits in the additional capacitance for the power supply circuit in the area on the lower surface 124 of the PCB120 corresponding to the storage contact area 1213. This problem is explained below with reference to fig. 7.

To more clearly illustrate the problems in the related art, fig. 7 illustratesbase:Sub>A cross-sectional view of the chip module 100 taken along thebase:Sub>A-base:Sub>A direction shown in fig. 3 in some embodiments, corresponding to fig. 6.

It should be understood that, unlike the power lines for transmitting current, signal lines are provided in the thickness direction (Z axis) of the non-power supply area of the PCB120, and the signal lines mainly refer to lines for transmitting non-power supply signals, or lines for transmitting sensing information and control information, or lines for transmitting signals and commands.

For example, as shown in fig. 7, between the storage contact region 1213 of the upper surface 121 of the PCB120 to the lower surface 124 of the PCB120, there are a plurality of conductive vias 127a extending in the thickness direction (Z axis) of the PCB120 and penetrating through the PCB120, a plurality of conductive vias 127b extending in the thickness direction (Z axis) of the PCB120 but not completely penetrating through the PCB120, and a conductive via 127c extending in the length direction (X axis) of the PCB120, and one end of a part of the conductive via 127c may be electrically connected to one end of the conductive via 127b, and a middle portion of the part of the conductive via 127a may be electrically connected to one end of the conductive via 127b. And the conductive vias 127a, the conductive paths 127b of the memory contact area 1213 may serve as signal lines for passing signals other than power. For example, the conductive vias 127a and the conductive vias 127b of the storage contact region 1213 may be used as ground lines for command data signals.

If the additional capacitor F is disposed in the non-power region (e.g., the storage contact region 1213) of the lower surface 124 of the PCB120, the additional capacitor F is electrically connected to the signal line on the non-power region of the lower surface 124 of the PCB120, and a non-power signal is introduced between the power supply line between the power module 140 and the chip package structure 110, and since the voltage required by the signal line and the power line is different, for example, the current on the signal line is very small, but the power source is used to drive a subsequent circuit, the current on the power line is large, and thus the power circuit and other non-power circuits are easily shorted.

For example, continuing to participate in local region C in fig. 7. As shown in fig. 7, the additional capacitor F is a chip capacitor, and includes a capacitor body F2, and a first electrode terminal F1 and a second electrode terminal disposed at two ends of the capacitor body F2, where if the conductive via 127a is a signal line, because the position between two adjacent conductive vias 127a is limited, if the additional capacitor F is disposed at the position between two adjacent conductive vias 127a, the first electrode terminal F1 and the second electrode terminal F3 of the additional capacitor F are electrically connected to two conductive vias 127a serving as signal lines, respectively, so that a non-power signal is introduced between a power supply line between the power module 140 and the chip package structure 110, and signal transmission in the signal line is interfered. And because the voltage required by the signal line and the power line is different, for example, the current on the signal line is very small, but the power supply is used for driving the subsequent stage circuit, the current on the power line is large, and the problem of short circuit between the power supply circuit and other non-power circuits is easily caused.

In order to avoid the problem of the short circuit, the application also provides a structure of the chip module. In the chip module, an expansion board is additionally arranged on the lower surface 124 of the PCB120 where the chip package structure 110 is located and in a non-power supply area where the conductive path 127b that does not completely penetrate through the PCB120 is arranged. The additional capacitor is arranged in the expansion board, and the expansion board isolates the additional capacitor from the PCB120, so that the additional capacitor is not in direct contact with the PCB120, and the risk of short circuit on a power supply circuit of the power module 140 for the central processing unit 110 is reduced.

For example, as shown in fig. 9, if the conductive channel 127b that does not completely penetrate through the PCB120 is included between two adjacent conductive vias 127a, the distance d2 between the two adjacent conductive vias 127a that includes the conductive channel 127b that does not completely penetrate through the PCB120 is greater than the distance d1 between the two adjacent conductive vias 127a, and there is a larger space (X-axis direction, Y-axis direction, Z-axis direction) where the conductive channel connected to the power line can be disposed, and several chip module structures for solving the above short circuit problem are specifically described below.

Fig. 8 shows a schematic diagram of a distribution of additional spreading plates and additional capacitors on the bottom surface 124 of the printed circuit board 120. As shown in fig. 8, an extension plate 170 is added to the lower surface 124 of the PCB120 in an area corresponding to the storage contact area 1213, and an additional capacitor F added thereto is provided.

Specifically, fig. 9 showsbase:Sub>A cross-sectional view of the chip module taken along thebase:Sub>A-base:Sub>A direction in fig. 3, corresponding to fig. 8.

As shown in fig. 9, the expansion board 170 has an upper surface 171 facing the Y-axis direction and a lower surface 172 facing the Y-axis direction, the additional capacitance F is located on the lower surface 172 of the expansion board 170, and the upper surface 173 of the expansion board 170 is electrically connected to the lower surface 124 of the printed circuit board 120. The additional capacitor F is electrically connected to a power line in the printed circuit board 120, so as to reduce the impedance of the power line of the power module 140 to the chip package structure 110, reduce the voltage drop of the power module 140 in the process of supplying power to the chip package structure 110, and reduce the instantaneous voltage drop by using the electric energy stored in the additional capacitor when the power module 140 generates the instantaneous voltage drop in the process of supplying power to the chip package structure 110. Two conductive vias 173 penetrating in the Z-axis direction are provided on the expansion board 170, and a conductive via 129 having an opening on the lower surface 124 and extending in the Z-axis direction is provided in the PCB 120. The conductive channel 129 is located between two adjacent conductive vias 127a, and the two adjacent conductive vias 127a include a conductive channel 127b that does not completely penetrate through the PCB 120.

It will be appreciated that the conductive paths 129 provided on the PCB120 are all present in pairs, one conductive path 129 being used to connect one electrode of the additional capacitance F to the power supply line and the other conductive path 129 being used to connect the other electrode of the additional capacitance F to ground.

One end of the conductive via 173 is electrically connected to the second electrode terminal F2, for example, by Surface Mount Technology (SMT), the other end of the conductive via 173 is soldered to one end of the conductive channel 129 on the lower Surface 124 of the PCB120 by a solder ball 200, and the conductive channel 129 is electrically connected to the power line inside the PCB120, so that the additional capacitor F is electrically connected to the power line. It is understood that in some embodiments, the conductive via 127b along the Z-axis of the PCB120, and not completely through the PCB120, may be in line with the conductive via 129. I.e., conductive via 127b and conductive via 129, may be two components of a conductive via that extends through PCB120 in the Z-axis direction of PCB120, as will be described in more detail below. It can be understood that the PCB120 and the expansion board 170 are distributed through the conductive vias, so that the pins on the PCB120 and the contacts on the expansion board 170 are consistent, and the number of the linked PCBs 120 and the expansion board 170 needs to be comprehensively evaluated through the weight, adhesion and loop DCR effects of the expansion board.

If the conductive via 127a is used as a ground line, one end of the conductive via 173 is electrically connected to the second electrode terminal F1, for example, by Surface Mount Technology (SMT), and the other end of the conductive via 173 is soldered to one end of the conductive via 127a on the lower Surface 124 of the pcb120 by a solder ball 200. In this way, additional capacitive grounding may be achieved.

It should be understood that, for convenience of describing the technical solution of the present application, fig. 9 only shows a smaller expansion board 170 and one or additional capacitors F disposed on the expansion board 170, but in the embodiment of the present application, the expansion board 170 may be a longer printed circuit board extending along the X direction, and further more additional capacitors F may be disposed on the expansion board 170 in parallel, so that the above-mentioned voltage drop and instantaneous voltage drop problems may be better reduced. In addition, other power devices, such as resistors and inductors, besides capacitors, may be disposed on the extension board 170. Other power devices than the capacitor may be connected in series or in parallel with the additional capacitor F, or the like.

In addition, it can be understood that the conductive channels 129 disposed on the PCB120 are all paired, one conductive channel 129 is used for connecting one electrode of the additional capacitor F to the power line, and the other conductive channel 129 is used for grounding the other electrode of the additional capacitor F, in the case that the additional capacitor F uses one of the conductive channels 129 to connect the power line, in this embodiment, the other conductive channel for grounding may also be added to the conductive channel for grounding instead of using the conductive via 127 for grounding originally disposed in the PCB120, and fig. 10, corresponding to fig. 8, showsbase:Sub>A cross-sectional view of another chip module taken along the directionbase:Sub>A-base:Sub>A in fig. 3. As shown in fig. 10, the PCB120 is further provided with an opening at the lower surface 124, and a conductive path 129 for grounding is further provided extending along the Z-axis direction. The conductive channel 129 is located between two adjacent conductive vias 127a, and the two adjacent conductive vias 127a include a conductive channel 127b that does not completely penetrate through the PCB 120. One end of the conductive via 173 is electrically connected to the second electrode terminal F1, and the other end of the conductive via 173 is soldered to one end of the conductive channel 129 for grounding on the lower surface 124 of the printed circuit board 120 by a solder ball 200, so that the additional capacitor grounding can be realized.

To describe the structure of the power lines in the PCB120 more clearly, a cross-sectional view of the power lines (power channels) distributed inside the PCB is introduced, for example, fig. 11 shows a cross-sectional view of the chip module 100 taken along the B-B direction shown in fig. 3, as shown in fig. 11, a conductive channel 126 serving as the power line is disposed in the PCB120, the conductive channel 126 is a bent channel extending along the thickness (z axis) direction of the PCB120 from the upper surface 121 of the PCB120, then extending along the thickness (z axis) direction of the PCB120, and then reaching the upper surface 121 of the PCB120, and the inner wall of the bent channel is disposed with a conductive medium, such as copper, but not limited thereto.

To more clearly illustrate the connection structure of the conductive vias 126 and the conductive vias 129 in the PCB120, for example, corresponding to the D '-D' direction in fig. 9, fig. 12 shows a cross-sectional view of a chip module in the YZ plane. As shown in fig. 12, one end of the conductive via 129 extends in the Y-axis direction and is electrically connected to the conductive via 126. The other end of the conductive channel 129 can be soldered to one end of the conductive via 173 on the expansion board 170 through the solder ball 200, and the other end of the conductive via 173 is electrically connected to the second electrode terminal F2, so that the additional capacitor F can be electrically connected to the conductive via 171 and the conductive channel 129 in parallel to serve as a power line, which, on one hand, is used to reduce the impedance of the power supply line of the power module 140 to the chip package structure 110 and reduce the voltage drop of the power module 140 in the process of supplying power to the chip package structure 110, and compared with the prior art in which no additional capacitor is provided, the additional capacitor F can store more capacitors, and can reduce the instantaneous voltage drop by using the electric energy stored by the additional capacitor when the power module 140 generates the instantaneous voltage drop in the process of supplying power to the chip package structure 110. It is understood that the electrical connection is made by solder balls, and may be made by conductive paste, which is not limited herein.

In the structure of the chip module 100 shown in fig. 9, 10, and 11, the additional capacitance F is provided on the surface of the expansion board 170, and in other embodiments, the additional capacitance F may be provided inside the expansion board 170. For example, the additional capacitance F may also be provided inside the extension board 170. For example, fig. 13 shows a partial cross-sectional view on a YZ plane in which an additional capacitance is provided in an extension board, and as shown in fig. 13, an additional capacitance F is buried inside an extension board 170. The additional capacitor F is provided inside the extension plate 170. One end of a conductive via 173 is electrically connected to the second electrode terminal F2 of the additional capacitor F, and the other end of the conductive via 173 is electrically connected to the conductive channel 129 via a solder ball 200, so that the additional capacitor F can be electrically connected to a power line (power channel) in parallel via the conductive via 173; one end of another conductive via 173 is electrically connected to the first electrode terminal F1 of the additional capacitor F, and the other end of the another conductive via 173 is electrically connected to the conductive path 129 for grounding through a solder ball 200.

In other embodiments, the additional capacitor F may be disposed inside the expansion board 170 or outside the expansion board 170.

For example, fig. 14 shows a partial cross-sectional view on a YZ plane in which an additional capacitance is provided in an extension board, and as shown in fig. 14, an additional capacitance F is provided on a lower surface 172 of an extension board 170, and the additional capacitance F is also provided inside the extension board 170.

The second electrode terminal F2 of the additional capacitor F disposed inside the extension board 170 is electrically connected to the middle of the conductive via 173, the second electrode terminal F2 of the additional capacitor F disposed on the lower surface 172 of the extension board 170 is electrically connected to one end of the conductive via 173, and the other end of the conductive via 173 is electrically connected to the conductive via 129 for grounding through the solder ball 200.

One end of the other conductive via 173 is electrically connected to the first electrode terminal F1 of the additional capacitor F disposed inside the extension plate 170, and the middle portion of the other conductive via 173 is electrically connected to the first electrode terminal F1 of the additional capacitor F disposed on the lower surface 172 of the extension plate 170.

The other end of the other conductive via 173 is electrically connected to the conductive path 129 for grounding through a solder ball 200.

In this way, the additional capacitor F disposed inside the extension board 170 and the additional capacitor F disposed on the lower surface 172 of the extension board 170 can be electrically connected in parallel to a power line (power channel) through the conductive via 173.

Of course, those skilled in the art will understand that the additional capacitor may be a high-frequency decoupling capacitor 0402, or a high-capacitance capacitor 0805 or 1206, but is not limited thereto.

The extension plate 170 may be a structure in the form of a silicon substrate, a thin film, or the like. The VIA hole 171 adopts a VIA10 large hole scheme to ensure the current capacity of a single hole, reduce ESR, equivalent Inductance (ESL) and the like, and improve the filtering performance; the thickness of the extension plate 170 may be controlled within 1mm to provide excellent loop characteristics.

The technical solution mentioned above is described as follows: conductive via 127b and conductive via 129 may be two components of a conductive via that extends through PCB120 in the Z-axis direction of PCB 120.

As shown in fig. 9, a conductive path 127b that does not penetrate through the thickness direction (Y-axis direction) of the PCB120 is disposed in the PCB120, and a conductive path 129 is disposed in order to fully utilize the space of the conductive path 127b in the thickness direction (Y-axis direction) of the PCB120, so that the additional capacitor F is electrically connected to a power line in the PCB120 through the conductive path 129, thereby achieving the functions of reducing the impedance of the power supply line of the power module 140 to the chip package structure 110, reducing the voltage drop of the power module 140 in the process of supplying power to the chip package structure 110, and reducing the instantaneous voltage drop of the power stored in the additional capacitor in the process of supplying power to the chip package structure 110 by the power module 140. The extension board 170 is provided with a conductive via 171 penetrating in the Z-axis direction. An opening is provided in PCB120 at lower surface 124 and a conductive via 129 extending in the Z-axis direction. The PCB120 of the present application may also adopt a single-hole multi-signal design, for example, the conductive channel 127b in fig. 11 may perform command interaction and data transmission with the video monitoring instrument control chip 150, and extend the conductive channel 127b in fig. 11 along the PCB thickness direction (the direction opposite to the Y axis) by a drilling technique through command and data signals to form a conductive via hole penetrating through the PCB thickness direction (the Y axis direction). The additional capacitor and the power supply module are connected by a power supply path extending in the thickness direction (Y-axis direction) of the PCB using the conductive path 127b. The power channel, which causes the conductive via 127b to extend in the thickness direction (Y-axis direction) of the PCB, receives a power signal.

The single-hole-site multi-signal design of the PCB120 is described below by the structure shown in table 1, and table 1 is a schematic diagram of single-signal-site multi-hole-site stacking of the PCB 120.

As shown in table 1 below, if the PCB120 includes an 18-layer substrate, assuming that the command and data signals are in the upper half of the stack, e.g., 1-7 layers in the stack in table 1, which is a signal VIA (VIA 5/8), e.g., the conductive VIA 127b shown in fig. 11 that does not penetrate through the thickness direction (Y-axis direction) of the PCB120, the signal VIA (VIA 5/8) is drilled out of the 8-18 layers by the back-drilling process.

Correspondingly, the power VIAs VIA10/12 are electroplated again on the 10 th layer to the 18 th layer, and the power VIAs below are electrically connected with the additional capacitors (the capacitor 180 and/or the capacitor 190) after being electroplated and filled up, i.e., secondary electroplating is performed by adopting a one-hole multi-signal process, and corresponding to fig. 11, the power VIAs VIA10/12 in the PCB120 are electrically connected with the conductive VIAs 171 in the expansion board 170. Therefore, the additional capacitor F is electrically connected to the power line in the printed circuit board 120, so as to reduce the impedance of the power line from the power module 140 to the chip package structure 110, reduce the voltage drop during the power supply from the power module 140 to the chip package structure 110, and reduce the instantaneous voltage drop by using the electric energy stored in the additional capacitor when the instantaneous voltage drop is generated during the power supply from the power module 140 to the chip package structure 110. A conductive via 171 penetrating in the Z-axis direction is provided on the extension plate 170. An opening is provided in PCB120 at lower surface 124 and a conductive via 129 extending in the Z-axis direction.

Table 1:

referring to another chip module structure provided in this embodiment of the application, fig. 15 shows a distribution diagram of adding an expansion board and an additional capacitor to the lower surface 124, as shown in fig. 15, an expansion board is added to a region corresponding to the input/output contact region 1214 on the lower surface 124 of the PCB120, and the additional capacitor is added to the expansion board.

Specifically, fig. 16 showsbase:Sub>A cross-sectional view of the general chip module taken along thebase:Sub>A-base:Sub>A direction in fig. 3. The structure of the chip module shown in fig. 16 is different from the structure shown in fig. 7 in that an extension plate 170 is additionally provided in a region corresponding to the input/output contact region 1214 on the lower surface 124 of the PCB120, and an additional capacitance F is provided in the extension plate 170.

The enlarged schematic diagram of the local region F in fig. 16 is the same as the technical solutions of the local region D in fig. 9 and 10, and the technical solutions of fig. 12 to 14, and is not repeated here.

Referring to another chip module structure provided in the present embodiment, fig. 17 is a schematic diagram illustrating a distribution of an additional expansion board and an additional capacitor on the lower surface 124, as shown in fig. 17, an expansion board is added to a region of the lower surface 124 of the PCB120 corresponding to the storage contact region 1213 and the input/output contact region 1214, and the additional capacitor is disposed on the expansion board.

Specifically, fig. 18 showsbase:Sub>A cross-sectional view of the general chip module taken along thebase:Sub>A-base:Sub>A direction in fig. 3. The structure of the chip module shown in fig. 21 is different from the structure shown in fig. 7 in that an extension plate 180 is additionally provided on the lower surface 124 of the PCB120 in regions corresponding to the storage contact region 1213 and the storage contact region 1213, and an additional capacitance F is provided on the extension plate 180.

The enlarged schematic diagrams of the local region D and the local region E in fig. 18 are the same as the technical solutions of the local region D in fig. 9 and 10 and the technical solutions of fig. 12 to 14, and are not repeated herein.

It is understood that, for the convenience of describing the technical solution of the present application, fig. 9 to 18 only show a smaller expansion board 170 and one or more additional capacitors F disposed on the expansion board 170, but in the embodiment of the present application, the expansion board 170 may be a longer printed circuit board extending along the X direction, and further more additional capacitors F may be disposed on the expansion board 170 in parallel, so that the above-mentioned problems of voltage drop and instantaneous voltage drop can be better reduced. In addition, other power devices, such as resistors and inductors, besides capacitors, may be disposed on the extension board 170. Other power devices than the capacitor may be connected in series or in parallel with the additional capacitor F, or the like.

Fig. 19 isbase:Sub>A cross-sectional view ofbase:Sub>A chip module taken alongbase:Sub>A-base:Sub>A in fig. 3, corresponding to fig. 8, according to an embodiment of the present application.

As shown in a partial region G in fig. 19, four additional capacitors F are disposed in parallel on the extension board 170 on the PCB120, but it is understood that more additional capacitors F may be disposed on the extension board 170 of the PCB 120.

Fig. 20 is a circuit diagram illustrating a simple structure among the power module 140, the chip package structure 110, the capacitor 160, the capacitor 180, and the capacitor 190 according to an embodiment of the present disclosure, as shown in fig. 11, in which a plurality of capacitors, such as the capacitor 160, the capacitor 180, and the capacitor 190, are connected in parallel between the power module 140 and the chip package structure 110, so as to reduce impedance between the power module 140 and the chip package structure 110, thereby reducing a voltage drop between the power module 140 and the chip package structure 110, and in which a plurality of capacitors 1071 can store more electric energy, so that the plurality of capacitors 1071 can provide electric energy to maintain a voltage between the power module 140 and the chip package structure 110 when a voltage between the power module 140 and the chip package structure 110 is momentarily reduced.

Fig. 21 is a schematic diagram of a Power Delivery Network (PDN) of the chip module 100 without the expansion board 170.

As shown in fig. 21, the ordinate represents impedance, and the abscissa represents frequency. If the target impedance of the power supply line from the power module 140 to the chip package structure 110 is

When the expansion board 170 is not attached to the back, the layout area of the main board of the PCB120 is limited, the number of low-frequency filter (BUCK) capacitors is not enough to cause the PDN curve to exceed the target impedance within the frequency range of 1e +4 (10K) Hz-1e +6 (1M) Hz, the voltage drop of the power supply line of the chip packaging structure 110 by the power module 140 is too large, the voltage output to the chip packaging structure 110 by the power module 140 is lower than the target voltage, the electronic device where the chip module 100 is located cannot normally operate, and the filtering performance of the chip module 100 can be affected, that is, the frequency point of specific frequency in the power line or the frequency other than the frequency point cannot be effectively filtered.

As shown in fig. 21, the ordinate represents impedance, and the abscissa represents frequency. After the back-attached expansion board 170 is introduced in the embodiment of the application, a low-frequency BUCK capacitor is placed on the expansion board 170, the number of the whole filtering capacitors of the single board is additionally increased, the number of the low-frequency filtering (BUCK) capacitors is enough to cause that a PDN curve is basically lower than a target impedance within a frequency range of 1e +4 (10K) Hz-1e +6 (1M) Hz, the low-frequency impedance of the single board PDN is effectively reduced, the voltage drop on a power supply line of the chip packaging structure 110 by the power module 140 is reduced, the voltage output from the power module 140 to the chip packaging structure 110 is higher than or equal to the target voltage, the electronic device where the chip module 100 is located can normally work, the filtering performance in the chip module 100 can be improved, and a frequency point of a specific frequency in the power supply line or a frequency other than the frequency point can be effectively filtered.

In summary, according to the embodiment of the present application, by reasonably utilizing the unused layout space in the non-chip power supply area on the printed circuit board 120, on one hand, the impedance of the power supply circuit of the power module 140 to the chip package structure 110 can be reduced, so that the voltage drop of the power supply circuit of the chip package structure 110 by the power module 140 is reduced; on the other hand, compared with the chip module 100 structure before the additional capacitor is not arranged, at least one additional capacitor arranged in the chip module 100 can store more capacitors, and under the condition that an instant voltage drop is generated in the process of supplying power to the chip packaging structure 110 by the power module 140, the instant voltage drop can be reduced by using the electric energy stored in the additional capacitor; on the other hand, since the extension board plays a role in insulating the pins of the additional capacitor from each other and from the conductive vias on the printed circuit board and other electrical components, the pins of the additional capacitor are not easily contacted with the conductive vias on the printed circuit board and other electrical components in the printed circuit board, thereby reducing the risk of short circuit on the power supply line for the chip package structure 110 by the power module 140.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.

Claims

1. A filtering module is characterized by comprising a printed circuit board, a chip packaging structure, a power supply module, a plurality of capacitors, an expansion board and at least one additional capacitor;

the printed circuit board has an upper surface and a lower surface opposite the upper surface;

the expansion board is arranged in the second area;

the at least one additional capacitor is connected in parallel with the plurality of capacitors and is arranged on the expansion board.

2. The filter module of claim 1, wherein the expansion board has at least one conductive via and at least one ground via disposed thereon;

3. The filter module of claim 2, further comprising a first conductive via that does not extend through the printed circuit board in a thickness direction of the printed circuit board;

4. The filter module of any of claims 1 to 3, wherein the at least one additional capacitor is disposed on a lower surface of the expansion board.

5. The filter module according to any one of claims 1 to 3, wherein a portion of the at least one additional capacitor is disposed on a lower surface of the expansion board, and the rest of the additional capacitors are disposed inside the expansion board.

6. The filter module of any of claims 1-3, wherein the at least one additional capacitor is disposed inside the expansion board.

7. The filter module according to any one of claims 2 or 3, wherein the printed circuit board has a multi-layer structure, and the conductive via is a conductive via hole electrically connected in sequence in a part of the multi-layer structure in the printed circuit board.

8. The filter module of any of claims 1 to 7, wherein the non-chip power contact area is a contact area adjacent to the chip power contact area.

9. The filter module of any one of claims 1 to 8, wherein the chip package structure is an integrated structure of any one or more of an application processor, a modem processor, a graphics processor, an image signal processor, a controller, a video codec, a digital signal processor, a baseband processor, and a neural network processor.

10. The filter module according to any one of claims 1 to 9, further comprising a power device disposed on the expansion board.

11. An electronic device, characterized in that it comprises a filtering module according to any one of claims 1 to 8.