CN115547991A - Manufacturing method of packaging structure, storage system and electronic equipment - Google Patents

Manufacturing method of packaging structure, storage system and electronic equipment Download PDF

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Publication number
CN115547991A
CN115547991A CN202211223478.1A CN202211223478A CN115547991A CN 115547991 A CN115547991 A CN 115547991A CN 202211223478 A CN202211223478 A CN 202211223478A CN 115547991 A CN115547991 A CN 115547991A
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China
Prior art keywords
chip
package
electromagnetic shielding
shielding layer
controller
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CN202211223478.1A
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Chinese (zh)
Inventor
曾心如
陈鹏
周厚德
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Yangtze Memory Technologies Co Ltd
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Yangtze Memory Technologies Co Ltd
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Priority to CN202211223478.1A priority Critical patent/CN115547991A/en
Publication of CN115547991A publication Critical patent/CN115547991A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/06—Containers; Seals characterised by the material of the container or its electrical properties
    • H01L23/08—Containers; Seals characterised by the material of the container or its electrical properties the material being an electrical insulator, e.g. glass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto

Abstract

The present disclosure provides a package structure and a method for manufacturing the same, the package structure including: a package body including a chip molding assembly, an electromagnetic shielding layer, and a package case; the electromagnetic shielding layer covers the chip molding assembly, and the packaging shell covers the electromagnetic shielding layer; a redistribution layer disposed at a first surface of the package body. The electromagnetic shielding layer of the packaging structure is arranged in the packaging body, so that the contact resistance of the electromagnetic shielding layer can be reduced, the electromagnetic shielding layer is prevented from being damaged, and the heat dissipation effect is improved.

Description

Manufacturing method of packaging structure, storage system and electronic equipment
Technical Field
The present disclosure relates to the field of semiconductors, and more particularly, to a chip package structure and a method for manufacturing the same.
Background
In the fabrication of integrated circuits, chips are obtained by the steps of wafer fabrication, forming integrated circuits, and dicing wafers. The chips formed by wafer dicing may be coupled to a carrier such as a leadframe or a package substrate, and the chips are encapsulated by a chip packaging technique to prevent the chips from contacting the outside world and from damaging the chips from the outside world. With the rapid development of photoelectric and micro-electrical manufacturing technologies, electronic products are always developed toward smaller, lighter and cheaper products, and therefore, the packaging form of chip components is also continuously improved.
When an operating circuit formed by semiconductors receives external Electromagnetic Interference (EMI) during operation, the operation performance may be affected. Even when the interference is strong, some sensitive chip package structures may be at risk of damage. Besides various external interference sources, in high-speed PCB and system design, high-frequency signal lines, integrated circuit pins, various connectors, etc. may also become radiation interference sources with antenna characteristics, which can emit electromagnetic waves and affect the normal operation of various devices including chip package structures in the system.
Disclosure of Invention
The disclosure provides a chip packaging structure and a preparation method thereof, which have an anti-electromagnetic interference function.
According to a first aspect of the present disclosure, there is provided a package structure, comprising: a package body including a chip molding assembly, an electromagnetic shielding layer, and a package case; the electromagnetic shielding layer covers the chip molding assembly, and the packaging shell covers the electromagnetic shielding layer; a redistribution layer disposed at a first surface of the package body.
In an embodiment of the present disclosure, the chip molding assembly includes at least two chips, a conductive element, and a chip housing; the at least two chips are in a stacked structure; one end of the conductive element is coupled with the chip, and the other end of the conductive element is flush with the surface of the chip shell; the chip housing covers the chip and the conductive element.
In an embodiment of the present disclosure, the package body includes at least two of the chip-molding assemblies, and further includes a controller and a passive device; the bottom surfaces of the chip molding assemblies, the controller and the passive device are flush, and the controller and the passive device are arranged between the two chip molding assemblies; the electromagnetic shielding layer covers the chip molding assembly, the controller and the passive device.
In an embodiment of the present disclosure, an insulator is included within the electromagnetic shielding layer, the insulator covering the chip-molding assembly, controller, or passive device.
In an embodiment of the present disclosure, the insulator is an insulating layer covering the chip molding assembly, the controller, and the passive device, and the electromagnetic shielding layer covers the insulating layer.
In an embodiment of the present disclosure, the insulator is an insulating paste covering the controller and the passive device, and the electromagnetic shielding layer covers the chip molding assembly and the insulating paste.
In one embodiment of the present disclosure, the insulating layer between the two chip-molding assemblies and around the chip-molding assemblies has an opening through which the electromagnetic shielding layer is coupled to a ground line.
In one embodiment of the present disclosure, there is an opening at the insulating paste at the periphery of the chip molding assembly, and the electromagnetic shielding layer is coupled with a ground line through the opening.
In an embodiment of the disclosure, the redistribution layer includes functional wiring and ground, the chip is coupled to the functional wiring by a conductive element, and the electromagnetic shielding layer is coupled to the ground or directly coupled to the ground by a conductive element.
In an embodiment of the present disclosure, the package structure is a ball grid array package or a grid array package.
In another aspect of the present disclosure, a method for manufacturing a package structure is provided, including: providing a chip-molding assembly; disposing a chip molding assembly on a substrate; forming an electromagnetic shielding layer outside the chip molding assembly; encapsulating the electromagnetic shielding layer to form an encapsulation shell to obtain an encapsulation body; a redistribution layer is formed on the first surface of the package body.
In one embodiment of the present disclosure, the step of forming the package body includes, forming at least two chip-molding assemblies; disposing a chip-molding assembly, a controller and a passive device on a substrate, the controller and the passive device being disposed between two chip-molding assemblies; forming an electromagnetic shielding layer covering the chip molding assembly, the controller and the passive device; and forming a packaging shell, wherein the packaging shell covers the electromagnetic shielding layer.
In an embodiment of the present disclosure, before forming the electromagnetic shielding layer, a step of forming an insulator covering the chip-molding assembly, the controller, or the passive device is further included, and after forming the insulator, the electromagnetic shielding layer is formed, the electromagnetic shielding layer covering the insulator.
In an embodiment of the present disclosure, the step of forming an insulator includes forming an insulating layer covering the chip-molding assembly, the controller, and the passive device.
In an embodiment of the present disclosure, the step of forming an insulator includes forming an insulating paste covering the controller and the passive device.
In an embodiment of the present disclosure, the step of forming the insulator includes forming an insulating layer including a plurality of openings at a periphery of the chip-molded component between two of the chip-molded components, and forming an electromagnetic shielding layer coupled to a ground line through the openings.
In one embodiment of the present disclosure, the step of forming the insulator includes forming an insulating paste including a plurality of openings at a periphery of the chip molding assembly; forming an electromagnetic shielding layer coupled with a ground line through the opening.
In an embodiment of the present disclosure, the redistribution layer includes functional wiring and ground lines, the chip-molding assembly is coupled with the functional wiring by a conductive element, and the electromagnetic shielding layer is coupled with the ground lines by a conductive element or directly coupled with the ground lines.
In another aspect of the present disclosure, a memory system is provided, which includes any one of the above package structures or a package structure prepared by any one of the above manufacturing methods.
In another aspect of the present disclosure, an electronic device is provided, which includes the above storage system.
Compared with the prior art, the technical scheme adopted by the disclosure has the following remarkable advantages:
(1) In the traditional packaging method, the electromagnetic shielding layer is positioned outside the packaging body, the ground wire is positioned on the side surface of the substrate, the contact area between the electromagnetic shielding layer and the ground wire is small, and the contact resistance is large; according to the packaging method disclosed by the invention, the ground wire is arranged at the horizontal position in the packaging body, and the contact area is large, so that the contact resistance is reduced;
(2) Compared with the traditional method, the electromagnetic shielding layer is prevented from being damaged by scratching and the like, and the shielding effect of the electromagnetic shielding layer is prevented from being influenced;
(3) The electromagnetic shielding layer is positioned in the packaging body, and the metal electromagnetic shielding layer is in direct contact with the chip molding assembly, so that better heat dissipation is facilitated.
(4) The electromagnetic shielding layer is positioned inside the packaging body, the appearance of the packaging structure is not affected, and the mark of the appearance is clearer.
(5) Compared with the traditional packaging method, the electromagnetic shielding layer is directly manufactured on the insulator, the manufacturing process steps of the whole packaging structure are reduced, the flow is short, the production period can be shortened, and the risk of chip damage is reduced.
Drawings
In order to more clearly illustrate the technical solutions in the present disclosure, the drawings needed to be used in some embodiments of the present disclosure will be briefly described below, and it is apparent that the drawings in the following description are only drawings of some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art according to these drawings. Furthermore, the drawings in the following description may be regarded as schematic diagrams, and do not limit actual sizes of products, actual flows of methods, actual timings of signals, and the like according to embodiments of the present disclosure.
Fig. 1 is a flow chart of a method of fabricating a package structure according to an exemplary embodiment of the present disclosure;
fig. 2 a-2 t are schematic diagrams of implementation steps of a method of fabricating a package structure according to an exemplary embodiment of the present disclosure;
fig. 3a is a cross-sectional schematic view of a package structure according to an exemplary embodiment of the present disclosure;
fig. 3b is a schematic top view of a package structure according to an exemplary embodiment of the present disclosure;
fig. 4a is a cross-sectional schematic view of a package structure according to another exemplary embodiment of the present disclosure;
fig. 4b is a schematic top view of a package structure according to another exemplary embodiment of the present disclosure.
Fig. 5 is a schematic top view of a package structure according to another exemplary embodiment of the present disclosure;
fig. 6 is a cross-sectional schematic view of a package structure according to another exemplary embodiment of the present disclosure;
fig. 7 is a cross-sectional schematic view of a package structure according to another exemplary embodiment of the present disclosure;
fig. 8 is a cross-sectional schematic view of a package structure according to another exemplary embodiment of the present disclosure;
Detailed Description
Technical solutions in some embodiments of the present disclosure will be described clearly and completely with reference to the accompanying drawings, and it is to be understood that the described embodiments are only a part of the embodiments of the present disclosure, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments provided by the present disclosure belong to the protection scope of the present disclosure.
In the description of the present disclosure, it is to be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience in describing and simplifying the disclosure, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the disclosure.
Throughout the specification and claims, the term "comprising" is to be interpreted in an open, inclusive sense, i.e., as "including, but not limited to," unless the context requires otherwise. In the description herein, the terms "one embodiment," "some embodiments," "an example embodiment," "exemplary" or "some examples" or the like are intended to indicate that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the disclosure. The schematic representations of the above terms are not necessarily referring to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be included in any suitable manner in any one or more embodiments or examples.
In the following, the terms "first", "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the embodiments of the present disclosure, "a plurality" means two or more unless otherwise specified.
The use of "adapted to" or "configured to" herein is meant to be an open and inclusive language that does not exclude devices adapted to or configured to perform additional tasks or steps.
Additionally, the use of "based on" is meant to be open and inclusive in that a process, step, calculation, or other action that is "based on" one or more stated conditions or values may, in practice, be based on additional conditions or exceed the stated values.
As used herein, "about," "approximately," or "approximately" includes the stated values as well as average values that are within an acceptable range of deviation for the particular value, as determined by one of ordinary skill in the art in view of the measurement in question and the error associated with measurement of the particular quantity (i.e., the limitations of the measurement system).
In the context of this disclosure, the meaning of "on … …," above, "and" over "should be interpreted in the broadest manner such that" on.
Example embodiments are described herein with reference to cross-sectional and/or plan views as idealized example figures. In the drawings, the thickness of layers and regions are exaggerated for clarity. Variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the exemplary embodiments.
Fig. 1 is a flowchart of a method of fabricating a package structure according to an exemplary embodiment of the present disclosure. As shown in fig. 1, the manufacturing method of the package structure includes the following steps:
step S100, providing a chip molding assembly;
step S200, arranging the chip molding assembly on a substrate;
step S300, forming an electromagnetic shielding layer outside the chip molding assembly;
step S400, encapsulating the electromagnetic shielding layer to form an encapsulation shell to obtain an encapsulation body;
step S500, forming a redistribution layer on the first surface of the package body.
A method for fabricating a package structure according to an embodiment of the disclosure is described below with reference to fig. 2a to 2 t.
Fig. 2 a-2 t are schematic cross-sectional views of package structure implementation steps according to exemplary embodiments of the present disclosure. It should be understood that the operations shown in fig. 2 a-2 t are not exclusive, and that other operations may be performed before, after, or between any of the operations shown.
First, step S100 is performed, as shown in fig. 2f, to provide at least one chip-molding assembly 10. Each of the chip-molding assemblies 10 includes a plurality of chips (Memory Die) 102 stacked, a chip case 104 covering the plurality of chips 102, and at least one conductive element 103 led out from the chip 102 through the chip case 104; each of the chip 102 surfaces is provided with at least one bonding pad 105 not covered by an adjacent chip 102; a first end of the conductive element 103 is disposed on and coupled to a bonding pad 105 of at least one of the chips, and a second end thereof may be exposed on a surface of the chip housing 104 and flush with the surface of the chip housing.
In one embodiment, the plurality of chips 102 may be, but is not limited to, NAND flash memory chips; each of the plurality of chips 102 includes an insulating layer on a side surface and a bottom surface to isolate each chip 102; the material of the chip housing 104 may include Epoxy Molding Compound (EMC); the conductive element 103 is perpendicular to the surface of the chip 102, and the material of the conductive element 103 may include at least one conductive material, such as gold, copper, aluminum, silver, and/or other suitable metal materials.
In one embodiment, as shown in fig. 2 a-2 f, the providing at least one chip-molding assembly 10 includes:
providing a first substrate 101; stacking a plurality of chips 102 on the first substrate 101;
forming one or more conductive elements 103 on at least one bond pad 105 of the plurality of chips 102, the first ends of the conductive elements being coupled to the bond pad 105;
forming a chip shell 104 covering the plurality of chips 102 and the conductive pillars 102;
removing the first substrate 101;
a portion of the chip housing 104 is removed, thereby exposing a second end of the one or more conductive elements 103.
In one embodiment, as shown in fig. 2a, a first substrate 101 is provided. In one embodiment, the first substrate 101 further includes a Temporary Bonding Film (Temporary Bonding Film).
As shown in fig. 2b, next, a plurality of chips 102 are stacked on the first substrate 101, and each chip 102 is provided with at least one bonding pad 105 on the surface thereof, which is not covered by the adjacent chip 102.
In one embodiment, the plurality of chips 102 are pasted right side up onto the temporary bonding film of the first substrate 101. Here, the face of the chip 102 on which the bonding pads 105 are located is the front face of the chip 102.
In one embodiment, the plurality of dies 102 may be offset in any direction parallel to the surface of the plurality of dies 102. Specifically, two chips 102 adjacent in the stacking direction may have both of the bonding pads 105 of the surface of the other chip 102 exposed by the offset of one of the chips 102.
Next, as shown in fig. 2c, at least one conductive element 103 having one end coupled to the bonding pad 105 is formed on at least one bonding pad 105 of the plurality of chips 102.
In one embodiment, the conductive element 103 is perpendicular to the surface of the chip 102 and is in electrical contact with at least one bond pad 105 of the chip 102. Here, electrical contact may be understood as two structures contacting and coupled.
Next, as shown in fig. 2d, a chip housing 104 covering the plurality of chips 102 and the conductive elements 103 is formed. In one embodiment, the chip housing 104 may completely cover the plurality of chips 102 and the conductive element 103, and the chip housing 104 may protect the plurality of chips 102 and reduce physical damage and/or chemical damage (such as oxidation, damage caused by moisture) to the plurality of chips 102.
In one embodiment, the material of the chip housing 104 includes EMC, it being understood that the particular material used for the chip housing 104 is not limiting.
Next, as shown in fig. 2e, the first substrate 101 is removed.
Next, as shown in fig. 2f, a portion of the chip housing 104 is removed, thereby exposing the second end of the one or more conductive elements 103.
In an alternative embodiment, a portion of the chip housing 104 may be removed first, and then the first substrate 101 may be removed.
In one embodiment, a portion of the die housing 104 may be removed by grinding to expose the second end of the at least one conductive element 103, thereby forming the die molded component 10. In one embodiment, when the chip housing 104 covers a plurality of chip-molding assemblies 10 at the same time, the chip housing 104 may be divided into a plurality of portions individually covering one chip-molding assembly 10 according to the requirements of the subsequent process. For example, the chip housing 104 in fig. 2f is cut into two parts, each covering a respective one of the chip-molding assemblies 10. It should be noted that the number of chip-molding assemblies 10 shown in fig. 2b is only for example and is not intended to limit the number of chip-molding assemblies 10 in the embodiments of the present disclosure.
In the above embodiment, a plurality of chip mold assemblies 10 may be formed by the same chip housing 104. That is, a plurality of chip-molded components 10 can be formed in the same process, i.e., a plurality of chip-molded components 10 can be formed at the same time, thereby greatly improving production efficiency and reducing production costs.
Next, step 200 is performed to place the chip molding assembly on the substrate. As shown in fig. 2g, the step includes providing a second substrate 201, and attaching at least one chip molding assembly 10 on an upper surface of the second substrate 201.
In one embodiment, the second carrier 201 further comprises a temporary bonding film thereon. Here, the temporary bonding film includes an adhesive layer for attaching the chip mold assembly 10 in a subsequent process.
In one embodiment, as shown in fig. 2h, the package structure further includes one or more controllers 21 and passive devices 212 disposed on the substrate 201, and a surface 211 of the controller 21 is provided with an extraction pad 210. In one embodiment, the passive devices 212 include capacitors, resistors, inductors, and the like. It will be understood that the number, arrangement position, type, etc. of the passive devices 212 may be specifically selected and arranged according to the function of the package structure.
In one embodiment, the chip-molding assembly 10, the controller 21 and the passive devices 212 are pasted face down onto the temporary bonding film of the first carrier 101. Here, the face of the conductive element 103 of the chip molding assembly 10 at which the second end is located is the front face of the chip molding assembly 10; the surface of the controller 21 where the lead-out pad 210 is located is the front surface of the controller 21; the face of the passive device 212 in conductive contact is the front face of the passive device. It is understood that when the first carrier 101 and the temporary bonding film on the first carrier 101 are removed in a subsequent process, the second ends of the conductive elements 103 of the chip-molding assembly 10, the lead-out pads 210 of the controller 21, and the conductive contacts of the passive devices are exposed, so as to facilitate coupling with the redistribution layer 30.
In one embodiment, the package structure may include one or more chip-molding assemblies 10. When the package structure includes a plurality of the die mold assemblies 10, the arrangement of the surface mount die mold assemblies 10 and the controller 21 on the second carrier 201 may include various arrangements.
In one embodiment, as shown in fig. 2h, the at least one chip-molding assembly includes a first chip-molding assembly 10A and a second chip-molding assembly 10B. Attaching the first chip mold assembly 10A, the second chip mold assembly 10B, the controller 21, and the passive devices 212 face down onto the temporary bonding film of the first carrier 101; wherein the controller 21 and passive devices 212 are located between the first chip-molding assembly 10A and the second chip-molding assembly 10B.
It is to be understood that the controller 21 is located between the first chip-molding assembly 10A and the second chip-molding assembly 10B, and the first chip-molding assembly 10A and the second chip-molding assembly 10B are arranged substantially symmetrically based on the controller 21. That is, the signal path from the first chip mold assembly 10A to the controller 21 and the signal path from the second chip mold assembly 10B to the controller 21 may be substantially symmetrical and uniform, thereby improving the high frequency performance of the package structure.
In order to electrically insulate the chip-molding assembly 10, the controller 21, and the passive device 212, before performing step 300, a step of covering the chip-molding assembly 10, the controller 21, or the passive device 212 with an insulator 22 is further included. The insulator 22 includes, but is not limited to, an insulating layer 221 and an insulating paste 222. The insulator 22 may electrically insulate the chip-molding assembly 10, the controller 21, or the passive device 212. It is understood that suitable organic or inorganic materials may be used for the insulating layer and the insulating paste.
In one embodiment, the chip-molding assembly 10, controller 21 and passive devices 212 are covered with an insulating layer 221, as depicted in fig. 2 i. The insulating layer 221 covers the back and side surfaces of the chip-molding assembly 10, the controller 21, and the passive device 212, and the back surfaces of the chip-molding assembly 10, the controller 21, and the passive device 212 are surfaces opposite to the front surfaces of the chip-molding assembly 10, the controller 21, and the passive device 212.
In one embodiment, an opening 220 is formed in the insulating layer 221 between two of the chip-molding assemblies 10 and at the periphery of the chip-molding assemblies, the opening 220 being used for coupling the subsequent electromagnetic shielding layer 23 with the ground line of the redistribution layer. It is understood that the opening 220 may be formed at any position between two of the chip mold assemblies 10, as shown in fig. 2i, and the opening 220 may be formed between the controller 21 and the passive device 212.
In one embodiment, as shown in fig. 2j, the controller 21 and passive devices 212, as well as the periphery of the chip-molding assembly 10, are covered with an insulating glue 222. The insulating glue 222 covers the back and side surfaces of the controller 21 and the passive device 212, and the back surfaces of the controller 21 and the passive device 212 are the surfaces opposite to the front surfaces of the controller 21 and the passive device 212.
In one embodiment, the insulating glue around the chip molding assembly 10 is formed with an opening 220 for coupling the subsequent electromagnetic shielding layer with the ground line.
Next, step 300 is performed to form an electromagnetic shield layer 23 outside the chip-molded assembly. The electromagnetic shield layer 23 covers the chip-molding assembly 10, the controller 21, or the passive device 212. The electromagnetic shielding layer 23 is coupled to the ground line of the redistribution layer 30 to block the transmission of electromagnetic waves.
In one embodiment, electromagnetic shield layer 23 may be prepared by any suitable method, including but not limited to sputtering or spraying. The material of the electromagnetic shield layer 23 includes, but is not limited to, metal.
In one embodiment, as shown in fig. 2k, the electromagnetic shielding layer 23 covers the insulating layer 221. An opening 220 is formed in the insulating layer 221 between the two chip mold assemblies 10 and at the periphery of the chip mold assemblies. The electromagnetic shield layer 23 is coupled to the ground line of the rewiring layer through the opening 220. In the traditional packaging method, the electromagnetic shielding layer is positioned outside the packaging body, the ground wire is positioned on the side surface of the substrate, the contact area between the electromagnetic shielding layer and the ground wire is small, and the contact resistance is large; in the packaging method of the present embodiment, the ground wire is provided in the opening 220 at the horizontal position inside the package, and the contact area between the electromagnetic shield layer 23 and the ground wire is large, so that the contact resistance can be effectively reduced.
In another embodiment, as shown in fig. 2l, the electromagnetic shielding layer 23 covers the insulating glue 222 and the back and side surfaces of the chip-molding assembly 10. The insulating glue around the chip-molding assembly 10 is formed with an opening 220. The electromagnetic shield layer 23 is coupled to the ground line of the rewiring layer through the opening 220. It will be appreciated that the electromagnetic shield 23 is located inside the package, as shown in fig. 2l, and the metallic electromagnetic shield 23 is in direct contact with the chip-molding assembly 10, which is advantageous for better heat dissipation.
Next, step 400 is performed to encapsulate the electromagnetic shielding layer 23. Encapsulating the electromagnetic shielding layer 23 with an encapsulating material to form an encapsulation case 24, thereby obtaining an encapsulation body including the chip mold assembly 10, the electromagnetic shielding layer 23, and the encapsulation case 24. In one embodiment, the package includes a chip-molding assembly 10, a controller 21, and a passive device 212. In one embodiment, the package further includes an insulator 22 within the electromagnetic shield.
In one embodiment, as shown in fig. 2m, the package housing 24 covers the electromagnetic shielding layer 23, and the electromagnetic shielding layer 23 covers the insulating layer 221. In another embodiment, as shown in fig. 2n, the package housing 24 covers the electromagnetic shielding layer 23, and the electromagnetic shielding layer 23 covers the insulating glue 222 and the chip-molding assembly 10. The package housing 24 may protect the chip-molded component 10, the controller 21, and the passive devices 212 and reduce physical and/or chemical damage (such as oxidation, damage by moisture) to the chip-molded component 10, the controller 21, and the passive devices 212. The package housing 24 may include, but is not limited to, an Epoxy Molding Compound (EMC) or an Ajinomoto Build-up Film (ABF Film). It can be understood that the electromagnetic shielding layer 23 is located inside the package housing 24, and compared with the conventional method, damage such as scratching of the electromagnetic shielding layer is avoided, and the shielding effect of the electromagnetic shielding layer is prevented from being affected; and, packaging structure's outward appearance is not influenced, and the mark of outward appearance can directly be made on the encapsulation casing, and the mark is more clear.
Compared with the traditional packaging method, the electromagnetic shielding layer 23 is directly manufactured on the insulator 22 and inside the packaging shell 24, the manufacturing process steps of the whole packaging structure are reduced, the flow is short, the production period can be shortened, and the chip damage risk is reduced.
Next, step 500 is performed to form a Redistribution Layer (RDL) on the first surface of the package body.
In one embodiment, as shown in fig. 2o and 2p, the insulator 22 in the package in fig. 2o is an insulating layer and the insulator 22 in the package in fig. 2p is an insulating glue 222, and the second carrier 201 is removed before the redistribution layer is formed. As such, the second ends of the conductive elements 103 in the chip-molding assembly 10, the lead pads 210 of the controller 21 and the conductive contacts of the passive devices are exposed at the first surface 223 of the package body. Here, the first surface 223 of the package is a surface of the package in contact with the second carrier 201.
As shown in fig. 2q and 2r, the insulator 22 in the package in fig. 2q is an insulating layer, the insulator 22 in the package in fig. 2r is an insulating glue 222, and the redistribution layer 30 is formed on the first surface 223 of the package; wherein the chip-molding assembly 10 is in physical contact with and coupled to the redistribution layer 30 through the second end of the conductive element 103, and the controller 21 is coupled to the redistribution layer 30 through the lead-out pad 210.
In one embodiment, the redistribution layer 30 may include at least one conductive layer and at least one insulating layer. Wherein the conductive layer can be coupled to the second end of the conductive element 103. The conductive layer may comprise a metal, any other suitable conductive material, or a combination thereof, and the insulating layer may comprise an organic or inorganic material (such as silicon oxide, silicon nitride, silicon oxynitride, any other suitable insulating material, or a combination thereof).
It is understood that in the foregoing process, the second ends of the conductive elements 103 in the chip-molding assembly 10, the lead-out pads 210 of the controller 21 and the conductive contacts of the passive devices are exposed on the first surface 223 of the package body, so that when the redistribution layer 30 is formed in step 500, the controller 21 may be coupled to the redistribution layer 30 by soldering, thereby shortening the signal transmission path of the controller 21 and improving the high-frequency performance of the package structure.
In one embodiment, as shown in fig. 2s and 2t, the insulator 22 in the package in fig. 2s is an insulating layer, the insulator 22 in the package in fig. 2t is an insulating glue 222, and metal solder balls 31 are formed on a first surface of the redistribution layer 30, and the metal solder balls 31 are coupled to the chip-molding assembly 10 and the controller 21 on a second surface of the redistribution layer 30 through the redistribution layer 30; the second surface of the redistribution layer 30 is the surface in contact with the first surface 223 of the package body, and the first surface and the second surface are opposite to each other.
In one embodiment, the insulating layer may have a plurality of openings in redistribution layer 30 to expose portions of the conductive layer. The package structure may further include a plurality of metal solder balls 31 in contact with the exposed portion of the conductive layer. That is, the metal solder balls 31 correspond to a plurality of openings in the insulating layer. In this case, the metal solder ball 31 can function as a signal input/output terminal. Through the metal solder balls 31 (i.e., signal input/output terminals), signals from an external device may be input into the package structure, and/or signals from the package structure may be output to the external device. Here, a metal solder ball 31 may be coupled to the at least one conductive element 103 and the controller 21 to form a ball grid array package.
In another embodiment, the redistribution layer 30 connects to grid pins, forming a grid array package.
It is noted that although an exemplary method of forming a package structure is described herein, it is understood that one or more steps may be omitted from the formation of such a package structure.
The present disclosure also provides a package structure. Fig. 3a is a cross-sectional view of the package structure according to an exemplary embodiment of the present disclosure, and fig. 3b is a top view of the package structure according to an exemplary embodiment of the present disclosure. The package structure includes: a package body including the chip mold assembly 10, the electromagnetic shield layer 23, and the package case 24; the electromagnetic shield 23 layer covers the chip mold assembly 10, and the package housing 24 covers the electromagnetic shield layer 23; a redistribution layer 30 disposed at the first surface 223 of the package body.
In one embodiment, the chip-molding assembly 10 includes at least two chips 102, a conductive element 103, and a chip housing 104; the at least two chips 102 are stacked; the conductive element 103 has one end coupled to the chip 102 and the other end flush with the surface of the chip housing 104; the chip housing 104 covers the chip and the conductive elements.
In one embodiment, the package includes at least two of the die-molded components 10, further including a controller 21 and passive devices 212; the chip mold assembly 10, the controller 21, and the passive device 212 may be horizontally disposed on the second substrate 201 during a packaging process, and thus, bottom surfaces of the chip mold assembly 10, the controller 21, and the passive device 212 are flush. A surface 211 of the controller 21 is provided with an exit pad 210, the controller 21 being coupled to the redistribution layer 30 via the exit pad 210.
In one embodiment, the controller 21 and passive devices 212 are disposed between two chip-molding assemblies 10. In another embodiment, the controller 21 and passive devices 212 are disposed on one side of a plurality of die mold assemblies 10. It will be appreciated that the positional relationship of the controller 21 and passive devices 212 to the die assembly can be adjusted as needed for coupling. The electromagnetic shield layer 23 covers the chip mold assembly 10, the controller 21, and the passive devices 212.
In one embodiment, in order to electrically insulate the chip-molded package 10, the controller 21, and the passive device 212, the package further includes an insulator 22, and the insulator 22 covers the chip-molded package 10, the controller 21, or the passive device 212. The insulator 22 may electrically insulate the chip-molding assembly 10, the controller 21, or the passive device 212. It is understood that suitable organic or inorganic materials may be used for the insulating layer and the insulating paste.
In one embodiment, as shown in fig. 3a, the insulator 22 is an insulating layer 221. As shown in fig. 3a, an insulating layer 221 covers the chip-molding assembly 10, the controller 21, and the passive devices 212. The insulating layer 221 covers the back and side surfaces of the chip-molding assembly 10, the controller 21, and the passive device 212, and the back surfaces of the chip-molding assembly 10, the controller 21, and the passive device 212 are surfaces opposite to the front surfaces of the chip-molding assembly 10, the controller 21, and the passive device 212.
In one embodiment, as shown in fig. 3a, the electromagnetic shielding layer 23 covers the insulating layer 221; in one embodiment, as shown in fig. 3b, an opening 220 is formed in the insulating layer 221 between two of the chip-molding assemblies 10 and at the periphery of the chip-molding assemblies, and the opening 220 is used for coupling the electromagnetic shielding layer 23 with the ground line of the redistribution layer 30. It is understood that the opening 220 may be formed at any position between the two chip mold assemblies 10, and the opening 220 may be formed between the controller 21 and the passive component 212. The shape of the opening is any suitable shape, such as circular, oval, triangular, quadrilateral, polygonal, irregular. Fig. 5 is a schematic top view of a package structure according to another exemplary embodiment of the disclosure, as shown in fig. 5, the opening has a rectangular shape.
In one embodiment, as shown in fig. 3a, the package housing 24 covers the electromagnetic shielding layer 23. The package housing 24 may protect the chip-molded component 10, the controller 21, and the passive devices 212 and reduce physical and/or chemical damage (such as oxidation, damage by moisture) to the chip-molded component 10, the controller 21, and the passive devices 212. The package housing 24 may include, but is not limited to, an Epoxy Molding Compound (EMC) or an Ajinomoto Build-up Film (ABF Film).
In one embodiment, as shown in fig. 3a, redistribution layer 30 is on a first surface 223 of the package body; wherein the chip-molding assembly 10 is coupled to the redistribution layer 30 via the second end of the conductive element 103, the controller 21 is coupled to the redistribution layer 30 via the lead-out pad 210, and the passive device is coupled to the redistribution layer 30 via the conductive contact.
In one embodiment, the redistribution layer 30 may include at least one conductive layer and at least one insulating layer. Wherein the conductive layer can be coupled to the second end of the conductive element 103. The conductive layer may comprise a metal, any other suitable conductive material, or a combination thereof, and the insulating layer may comprise an organic or inorganic material (such as silicon oxide, silicon nitride, silicon oxynitride, any other suitable insulating material, or a combination thereof).
In one embodiment, as shown in fig. 3a, the redistribution layer 30 includes metal solder balls 31 on a first surface thereof, forming a ball grid array package. The metal solder balls 31 are coupled to the chip-molding assembly 10 and the controller 21 on the second surface of the redistribution layer 30 through the redistribution layer 30; the second surface of the redistribution layer 30 is a surface in contact with the first surface 223 of the package body, and the first surface and the second surface of the redistribution layer 30 are opposite to each other.
In one embodiment, the insulating layer may have a plurality of openings in redistribution layer 30 to expose portions of the conductive layer. The package structure may further comprise a plurality of metal solder balls 31 in contact with the exposed portions of the conductive layer. That is, the metal solder balls 31 correspond to a plurality of openings in the insulating layer. In this case, the metal solder ball 31 can function as a signal input/output terminal. Through the metal solder balls 31 (i.e., signal input/output terminals), signals from an external device may be input into the package structure, and/or signals from the package structure may be output to the external device. Here, a metal solder ball 31 may be coupled to the at least one conductive element 103 and the controller 21.
In another embodiment, the redistribution layer 30 connects to grid pins, forming a grid array package. It is noted that although exemplary package structures are described herein, redistribution layer 30 may be connected to other types of pins to form different types of package structures.
The packaging structure is not only suitable for system in package (Sip), but also suitable for Fan out package (Fan-out package), flip chip package (Flip-chip package) and Wire-bonding package (Wire-bonding package). Fig. 6-8 disclose cross-sectional schematic views of package structures according to further embodiments of the present disclosure, fig. 6 discloses a cross-sectional schematic view of a generic fan-out package structure, fig. 7 discloses a cross-sectional schematic view of a generic flip chip package structure, and fig. 8 discloses a cross-sectional schematic view of a wire-bond package structure. Electromagnetic shield 23 in fig. 6-8 is located within an enclosure 24.
In one embodiment, another package structure is provided. As shown in fig. 4 a-4 b, unlike the package structure shown in fig. 3 a-3 b, the insulator 22 in the package structure shown in fig. 4 a-4 b is an insulating glue 222. The insulating paste 222 covers the controller 21 and the passive devices 212, and the periphery of the chip mold assembly 10. The insulating glue 222 covers the back and side surfaces of the controller 21 and the passive device 212, and the back surfaces of the controller 21 and the passive device 212 are the surfaces opposite to the front surfaces of the controller 21 and the passive device 212.
In one embodiment, as shown in fig. 4a, the electromagnetic shielding layer 23 covers the chip-molding assembly 10 and the insulating paste 222. In one embodiment, as shown in fig. 4b, the insulating glue on the periphery of the chip molding assembly 10 is formed with an opening 220, and the opening 220 is used for coupling the electromagnetic shielding layer 23 and the ground line of the redistribution layer 30. The electromagnetic shielding layer 23 is coupled to the ground line of the redistribution layer 30 to block the transmission of electromagnetic waves. The material of the electromagnetic shielding layer 23 includes, but is not limited to, metal.
It should be noted that the package structure of the above example can be used to form various storage systems, such as universal flash memory (UFS), embedded multimedia card (eMMC), PC card (PCMCIA), CF card, smart Media (SM) card, memory stick, multimedia card (MMC, RS-MMC, MMCmicro), SD card (SD, miniSD, microSD, SDHC), SSD, etc. The controller 21 in the package structure may control the operation of one or more of the chips 102 of the chip-molding assembly 10, such as read, write, erase operations. Controller 21 may be configured to control operations of chip 102, such as read operations, erase operations, and program operations; the controller 21 may also be configured to manage various functions with respect to data stored or to be stored in the chip 102, including but not limited to bad block management, garbage collection, wear leveling, and the like; any other suitable function may also be performed by controller 21, such as formatting chip 102; controller 21 may communicate with external devices (e.g., host 108) according to a particular communication protocol; for example, the controller 21 may communicate with the external device through at least one of various interface protocols, such as a USB protocol, a multimedia card (MMC) protocol, a Peripheral Component Interconnect (PCI) protocol, a serial bus (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a serial-ATA protocol, a parallel-ATA 20 protocol, a Small Computer System Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, and the like.
Some embodiments of the present disclosure also provide an electronic device. The electronic device may be any one of a mobile phone, a desktop computer, a tablet computer, a notebook computer, a server, an in-vehicle device, a wearable device (e.g., a smart watch, a smart bracelet, smart glasses, etc.), a mobile power source, a game console, a digital multimedia player, and the like.
The electronic device may include the storage system described above, and may further include at least one of a Central Processing Unit (CPU), a buffer (cache), and the like.
The above description is only for the specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present disclosure, and all the changes or substitutions should be covered within the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims (20)

1. A package structure, comprising:
a package body including a chip molding assembly, an electromagnetic shielding layer, and a package case;
the electromagnetic shielding layer covers the chip molding assembly, and the packaging shell covers the electromagnetic shielding layer;
a redistribution layer disposed at a first surface of the package body.
2. The package structure of claim 1,
the chip molding assembly comprises at least two chips, a conductive element and a chip shell; the at least two chips are in a stacked structure;
one end of the conductive element is coupled with the chip, and the other end of the conductive element is flush with the surface of the chip shell;
the chip housing covers the chip and the conductive element.
3. The package structure of claim 1,
the packaging body comprises at least two chip molding assemblies, a controller and a passive device;
the bottom surfaces of the chip molding assemblies, the controller and the passive device are flush, and the controller and the passive device are arranged between the two chip molding assemblies;
the electromagnetic shielding layer covers the chip molding assembly, the controller, and the passive device.
4. The package structure of claim 3,
the electromagnetic shielding layer includes an insulator therein, the insulator covering the chip-molding assembly, the controller, or the passive device.
5. The package structure of claim 4,
the insulator is an insulating layer, the insulating layer covers the chip molding assembly, the controller and the passive device, and the electromagnetic shielding layer covers the insulating layer.
6. The package structure of claim 4,
the insulator is insulating glue, the insulating glue covers the controller and the passive device, and the electromagnetic shielding layer covers the chip molding assembly and the insulating glue.
7. The package structure of claim 5,
the insulating layer between the two chip-molded components and around the chip-molded components has an opening through which the electromagnetic shield layer is coupled to a ground line.
8. The package structure of claim 6,
the insulating glue at the periphery of the chip molding assembly is provided with an opening, and the electromagnetic shielding layer is coupled with a ground wire through the opening.
9. The package structure of claim 1,
the redistribution layer includes functional wiring and ground, the chip is coupled to the functional wiring by a conductive element, and the electromagnetic shield layer is coupled to the ground or directly coupled to the ground by a conductive element.
10. The package structure of claim 1, wherein the package structure comprises a system in package (Sip), a Fan out package (Fan-out package), a Flip-chip package (Flip-chip package), and a Wire-bonding package (Wire-bonding package).
11. A method for manufacturing a package structure, the method comprising,
providing a chip-molding assembly;
disposing a chip-molding assembly on a substrate;
forming an electromagnetic shielding layer outside the chip molding assembly;
encapsulating the electromagnetic shielding layer to form an encapsulation shell to obtain an encapsulation body;
a redistribution layer is formed on the first surface of the package body.
12. The method of claim 11, wherein the step of forming the package structure comprises,
the step of forming the package body includes,
forming at least two chip-molding assemblies;
disposing a chip-molding assembly, a controller and a passive device on a substrate, the controller and the passive device being disposed between two chip-molding assemblies;
forming an electromagnetic shielding layer covering the chip molding assembly, the controller and the passive device;
and forming a packaging shell, wherein the packaging shell covers the electromagnetic shielding layer.
13. The method of claim 11, wherein the step of forming the package structure comprises the step of forming a semiconductor package,
before forming the electromagnetic shielding layer, further comprising the step of forming an insulator covering the chip molding assembly, the controller or the passive device,
after the insulator is formed, an electromagnetic shielding layer is formed, the electromagnetic shielding layer covering the insulator.
14. The method of claim 13, wherein the step of forming an insulator comprises forming an insulating layer covering the chip-molding assembly, the controller, and the passive device.
15. The method of claim 13, wherein the step of forming an insulator comprises forming an insulating glue covering the controller and the passive device.
16. The method of claim 14, wherein the step of forming an insulator comprises forming an insulating layer including a plurality of openings between two of the die mold assemblies and around the die mold assemblies,
forming an electromagnetic shielding layer coupled with a ground line through the opening.
17. The method of claim 15, wherein the step of forming the insulator comprises forming an insulating paste including a plurality of openings at the periphery of the chip-molding assembly;
forming an electromagnetic shielding layer coupled with a ground line through the opening.
18. The method of claim 11, wherein the redistribution layer comprises functional wiring and ground, the chip-molding assembly is coupled to the functional wiring by conductive elements, and the electromagnetic shielding layer is coupled to the ground by conductive elements or directly coupled to the ground.
19. A storage system comprising a package structure according to any one of claims 1 to 10 or a package structure prepared by the method of manufacture according to any one of claims 11 to 18.
20. An electronic device comprising the storage system of claim 19.
CN202211223478.1A 2022-10-08 2022-10-08 Manufacturing method of packaging structure, storage system and electronic equipment Pending CN115547991A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202211223478.1A CN115547991A (en) 2022-10-08 2022-10-08 Manufacturing method of packaging structure, storage system and electronic equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
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Publications (1)

Publication Number Publication Date
CN115547991A true CN115547991A (en) 2022-12-30

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Application Number Title Priority Date Filing Date
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Country Link
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