CN115547825A - Substrate groove etching method - Google Patents

Substrate groove etching method Download PDF

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Publication number
CN115547825A
CN115547825A CN202211201417.5A CN202211201417A CN115547825A CN 115547825 A CN115547825 A CN 115547825A CN 202211201417 A CN202211201417 A CN 202211201417A CN 115547825 A CN115547825 A CN 115547825A
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etching
groove
substrate
gas
layer
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郑浩田
蒋中伟
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Beijing Naura Microelectronics Equipment Co Ltd
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Beijing Naura Microelectronics Equipment Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials

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  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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Abstract

The invention discloses a substrate groove etching method, which comprises the following steps: forming a groove with an inclined side wall on the surface of the substrate; forming a protective layer on the inner surface of the groove; removing the protective layer in the central area of the groove and reserving the protective layer on the inclined side wall of the edge of the groove; and etching the substrate, forming a groove with a set depth in the substrate, removing the protective layer on the inclined side wall of the edge of the groove and forming a rounded top angle appearance on the edge of the top of the groove. The invention can obtain ideal rounded silicon vertex angle appearance and reduce the electric leakage risk caused by sharp vertex angles after the subsequent medium filling.

Description

Substrate groove etching method
Technical Field
The invention belongs to the technical field of semiconductor etching, and particularly relates to a substrate groove etching method.
Background
In the existing Shallow Trench Isolation (STI) etching process, the shape of a silicon trench determines whether a hole defect exists in subsequent oxide layer filling. Whether the corners of the silicon trench are smooth or not determines the performance of tip leakage. The sharp apex angle forms a high fringe electric field on the shallow trench isolation sidewall, and the electric leakage can form a double hump on a grid current-voltage curve, which can cause dielectric breakdown in severe cases to influence the electrical property. This problem can be solved with a rounded tip angle (Top Corner Rounding). In the industry, it is common practice to perform a lateral etching on the hard mask by using hot phosphoric acid and diluted hydrofluoric acid after the dry etching is completed, so that the sharp corners of the silicon trench and the hard mask can be exposed, and the sharp corners can be passivated during the subsequent substrate oxidation, thereby reducing the leakage caused by the sharp corners, as shown in fig. 1a-1 c.
However, the problem of insufficient sharp angle passivation exists only by means of the sharp angle at the top of the substrate silicon oxide groove, and the hidden danger of tip leakage still exists, so that in the process of etching the shallow groove with smaller critical dimension, one step of etching is added before silicon etching for forming a rounded top angle, and the difficulty of realizing the rounded top angle only by means of dry etching is very high due to the protection of the hard mask. The top angle topography of silicon after common dry etching is shown in fig. 1 a. If the ideal appearance as shown in figure 2 is formed by rounding the top corner, the method has great significance for reducing electric leakage caused by subsequent sharp corners.
Disclosure of Invention
The invention aims to provide a silicon substrate shallow trench etching method, which realizes a rounded silicon top corner and reduces the electric leakage risk caused by a sharp top corner after subsequent medium filling.
In order to achieve the above object, the present invention provides a substrate trench etching method, including:
forming a groove with an inclined side wall on the surface of the substrate;
forming a protective layer on the inner surface of the groove;
removing the protective layer in the central area of the groove and reserving the protective layer on the inclined side wall of the edge of the groove;
and etching the substrate, forming a groove with a set depth in the substrate, removing the protective layer on the inclined side wall of the edge of the groove and forming a rounded top angle appearance on the edge of the top of the groove.
Optionally, the substrate includes a single crystal silicon layer, a hard mask layer, an amorphous carbon layer, and a patterned photoresist layer, which are sequentially distributed from bottom to top.
Optionally, the forming a groove with a tilted sidewall on the surface of the substrate includes:
etching openings exposing the surface of the monocrystalline silicon layer in the amorphous carbon layer and the hard mask layer by using first etching gas;
and etching a groove with an inclined side wall on the surface of the monocrystalline silicon layer exposed by the opening by using a second etching gas.
Optionally, the first etching gas comprises a hydrogen-containing fluorocarbon gas, a diluent gas and oxygen;
the second etching gas comprises hydrogen-containing fluorocarbon gas, diluent gas, oxygen and chlorine.
Optionally, the forming a protective layer on the inner surface of the groove includes:
and etching the substrate by using a third etching gas, removing the amorphous carbon layer, oxidizing the monocrystalline silicon on the inner surface of the groove into silicon oxide, and forming the protective layer.
Optionally, the third etch gas comprises oxygen, nitrogen, and helium.
Optionally, the removing the protective layer in the central region of the groove and retaining the protective layer on the inclined sidewall of the edge of the groove includes:
and etching the hard mask layer and the monocrystalline silicon layer by using fourth etching gas, removing the protective layer in the central area of the groove, and reserving the protective layer on the inclined side wall of the edge of the groove.
Optionally, the fourth etching gas includes hydrogen-containing fluorocarbon gas and hydrogen bromide, and a flow ratio of the hydrogen-containing fluorocarbon gas to the hydrogen bromide in the fourth etching gas ranges from 2.5.
Optionally, the forming a trench with a set depth in the substrate, and simultaneously removing the protective layer on the inclined sidewall of the edge of the groove and forming a rounded top corner profile at the top edge of the trench includes:
and etching the hard mask layer and the monocrystalline silicon layer by using a fifth etching gas, forming a groove with a set depth in the monocrystalline silicon layer, removing the protective layer on the inclined side wall of the edge of the groove and forming a rounded top angle appearance on the edge of the top of the groove.
Optionally, the fifth etching gas comprises hydrogen-containing fluorocarbon gas and hydrogen bromide, and the flow ratio of the hydrogen-containing fluorocarbon gas to the hydrogen bromide in the fifth etching gas is in a range of 1.
Optionally, the hydrogen-containing fluorocarbon gas is CHF 3 、CH 2 F 2 、CH 3 At least one of F.
Optionally, during the etching of the single crystal silicon layer by using the fifth etching gas, a lower electrode pulse radio frequency mode is used for etching.
The invention has the beneficial effects that:
according to the method, firstly, a groove with an inclined side wall is formed on the surface of a substrate, then a protective layer is formed on the inner surface of the groove, then the protective layer in the central area of the groove is removed, the protective layer on the inclined side wall of the edge of the groove is reserved, the residual protective layer can be used as an equivalent mask for etching the top of the side wall of the groove, and the top edge of the side wall of the groove is protected, so that the etching of the top edge of the etching morphology lags behind the etching of the middle part in the subsequent groove etching process, a rounded vertex angle morphology is finally formed on the top edge of the groove, and the electric leakage risk caused by a sharp vertex angle after subsequent medium filling is reduced.
The system of the present invention has other features and advantages which will be apparent from or are set forth in detail in the accompanying drawings and the following detailed description, which are incorporated herein, and which together serve to explain certain principles of the invention.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent by describing in more detail exemplary embodiments thereof with reference to the attached drawings, in which like reference numerals generally represent like parts.
Fig. 1a-1c respectively show the topography schematic diagrams after dry etching, wet etching and substrate oxidation of a silicon substrate in the shallow trench isolation etching process.
Figure 2 shows a topographical schematic of an ideal rounded silicon top corner.
Fig. 3 shows a schematic diagram of a film structure and a principle of a corner rounding method in the prior art.
Fig. 4 is a schematic diagram illustrating an etching effect of a corner rounding method according to the first prior art.
Figure 5 shows an atomic micrograph of an etched feature of a corner rounding method of prior art one.
Fig. 6 is a step diagram illustrating a method for etching a substrate trench according to an embodiment of the present invention.
Fig. 7 is a schematic diagram illustrating a film structure of a silicon substrate in a substrate trench etching method according to an embodiment of the present invention.
Fig. 8 is a schematic diagram illustrating the formation of a recess with sloped sidewalls in a substrate trench etching method according to an embodiment of the present invention.
Fig. 9a and 9b show electron microscope effect graphs of the "micro-trench" morphology and the inclined sidewall morphology of the groove in the substrate trench etching method according to the embodiment of the invention.
FIG. 10 is a schematic diagram illustrating the formation of a silicon oxide protective layer on top of a single crystal silicon layer in a substrate trench etching method according to an embodiment of the present invention.
Fig. 11 is a schematic diagram illustrating a method for etching a substrate trench according to an embodiment of the present invention, wherein a central portion of the protective layer is removed and an edge portion is remained.
Fig. 12 is a schematic diagram illustrating the formation of rounded silicon top corners in a substrate trench etching method according to an embodiment of the present invention.
FIG. 13a shows the electron microscope effect of the sharp silicon vertex angle obtained by the existing shallow trench etching.
Fig. 13b shows an electron microscope effect diagram of a rounded silicon vertex angle obtained by the substrate trench etching method according to the embodiment of the invention.
Detailed Description
As shown in fig. 3, the prior art provides a method for rounding the top corner of a silicon wafer by using fluorocarbon polymer, which is a reactive ion etching after forming a channel 11 structure on the surface of a substrate silicon wafer 10 placed on a pedestal at the bottom of a processing chamber, and comprises the following steps:
step 1, introducing mixed gas containing fluorocarbon and inert gas into a vacuum treatment chamber;
step 2, applying a high-frequency radio frequency source in the processing chamber to generate plasma of fluorocarbon in the mixed gas;
step 3, forming a fluorocarbon-containing polymer film 20 at the vertex angle 12 position of the channel 11 on the surface of the silicon wafer 10;
and 4, chemically etching the surface of the silicon wafer 10 by using the polymer containing the fluorocarbon to round the top corner 12, wherein the etching time of the polymer to the top corner is longer than 30s, and preferably, the etching time of the polymer to the top corner is longer than 60s.
In step 1, the fluorocarbon is a gas of carbon tetrafluoride CF4, perfluorobutadiene C4F6 or octafluorocyclobutane C4F 8. The fluorocarbon also contains trifluoromethane CHF3, which accelerates the reaction of the mixed gas on the surface of the silicon wafer 10 to form a thin film 20 of its polymer and covering the sidewalls and top corners 12 of the trench 11. The mixed gas also comprises oxygen O2 and argon Ar, and the O2 flow is less than the fluorocarbon flow.
The method for rounding the top angle of the silicon wafer by the fluorocarbon-containing polymer also comprises a low-frequency radio frequency power supply which is applied to a base of a chamber processing base to accelerate charged ions generated by ionization of a high-frequency radio frequency source and control the energy of incident particles.
The effect of using this corner rounding method is shown in fig. 4 and 5.
The method has the following disadvantages:
1. the top angle rounding processing is post-processing performed after silicon etching is completed, a long time (> 60s, 120s is needed for the best effect) is needed for realizing the effect, and for the mainstream film structure of the current IC etching, the selection ratio of C/F base gas used by the top angle rounding processing to a hard mask is not enough, so that the etching effect is very obvious, the surplus of the mask 30 is easily insufficient, and the follow-up wet cleaning and the grabbing of a CMP (chemical mechanical polishing) terminal point are influenced.
2. The method needs to add low-frequency radio frequency bias and argon (Ar) to provide physical sputter etching ions for realizing the slope control of top angle rounding, and for the advanced process, the processing of the extremely small key size, high depth-to-width ratio and silicon side wall and bottom needs to be more cautious.
The substrate groove etching method can realize the rounded silicon top angle by using dry etching, and reduce the electric leakage risk caused by the sharp top angle after the subsequent medium is filled.
The invention will be described in more detail below with reference to the accompanying drawings. While the preferred embodiments of the present invention are shown in the drawings, it should be understood that the present invention may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.
Examples
As shown in fig. 6, a method for etching a substrate trench includes:
s1: forming a groove with an inclined side wall on the surface of the substrate;
the substrate adopted in the embodiment comprises a monocrystalline silicon layer 105, a hard mask layer 104 and an amorphous carbon layer 103 which are sequentially distributed from bottom to top; the specific film structure of the substrate is shown in fig. 7, and includes, from top to bottom, a photoresist layer 101 (PR), a dielectric anti-reflection layer 102 (Darc), an amorphous carbon layer 103 (ACL), a Hard mask layer 104 (ONO Hard mask) composed of silicon oxide, silicon nitride, and silicon oxide, and a single crystal silicon layer 105.
Generally, the shallow trench etching process is divided into dielectric antireflection layer etching, amorphous carbon layer etching, hard mask etching, ashing etching to remove the top amorphous carbon layer, through etching and monocrystalline silicon etching according to the distribution of a film layer. The dielectric anti-reflection layer etching is used for defining a Critical Dimension (CD) and improving a Critical Dimension Uniformity (CDU), the amorphous carbon layer etching is used for pattern transfer, a patterning process needs to be performed on the photoresist layer 101 before step S1 is performed, and the hard mask layer 104 is subjected to opening etching by using the patterned photoresist layer 101 as a mask.
The step S1 comprises a hard mask layer main etching process step and a hard mask layer over-etching process step, and specifically comprises the following steps:
s101: performing a hard mask layer main etching process step, and etching an opening exposing the top surface of the monocrystalline silicon layer in the amorphous carbon layer and the hard mask layer by using first etching gas;
preferably, the first etching gas in this step includes a hydrogen-containing fluorocarbon gas, a diluent gas, and an oxygen gas. The technological parameters of the main etching process step of the hard mask layer comprise:
the pressure of the chamber ranges from 5 mT to 10mT;
the radio frequency power range of the upper electrode is 500-1000W;
the radio frequency power range of the lower electrode is 200-300W;
the temperature of the chamber ranged from 40-60 ℃.
The hard mask layer 104 is completely etched by the above etching process parameters to expose the surface of the single crystal silicon layer.
S102: performing a hard mask layer over-etching process step, and etching a groove shape with an inclined side wall at the edge on the top surface of the monocrystalline silicon layer exposed by the opening by using second etching gas;
preferably, the second etching gas in this step includes a hydrogen-containing fluorocarbon gas, a diluent gas, an oxygen gas, and a chlorine gas. The technological parameters of the hard mask layer over-etching technological step comprise:
the pressure of the chamber ranges from 10mT to 40mT;
the radio frequency power range of the upper electrode is 500-1000W;
the radio frequency power range of the lower electrode is 300-500W;
the temperature range of the chamber is 40-70 ℃;
the process time ranges from 10 to 30s.
The top of the single crystal silicon layer 105 is pretreated by the etching process parameters to form an over-etched shallow groove profile at the top of the single crystal silicon layer 105, and in the specific implementation process, because the sidewall angle formed by the over-etched groove profile needs to be inclined as much as possible, a "Micro Trench" (Micro Trench) type adverse profile (the transmission of the type profile to the bottom of the single crystal silicon can affect the filling of subsequent media) can be formed if necessary, as shown in fig. 8, 9a and 9 b.
In this step, the over-etching sloped profile or the "micro-trench" type recess profile results in a significant protrusion of the single crystal silicon compared to the upper hard mask, which is an important component of the subsequent rounded top corner, and the subsequent ashing etching forms an oxide layer (passivation layer) on the surface of the portion, as shown in fig. 10. The oxide layer of the part is retained to act as an equivalent mask through the etching process step, as shown in fig. 11, in order to protect the monocrystalline silicon etching of the part from lagging behind the monocrystalline silicon etching of the middle part as much as possible, and finally, a rounded top corner of the top of the monocrystalline silicon is formed.
S2: forming a protective layer on the inner surface of the groove;
the step is to execute an ashing etching process step, remove the amorphous carbon layer by using a third etching gas, oxidize the monocrystalline silicon passing through the inner surface of the groove into silicon oxide, and form a protective layer;
preferably, the third etching gas in this step includes oxygen, nitrogen and helium, and the protective layer is a silicon oxide layer. The technological parameters of the ashing etching process step comprise:
the pressure of the chamber ranges from 5 mT to 20mT;
the radio frequency power range of the upper electrode is 800W-1500W;
the radio frequency power range of the lower electrode is 50-200W;
the temperature range of the chamber is 40-70 ℃;
the process time ranges from 50 to 100s.
The residual amorphous carbon layer 103 on the top of the hard mask layer 104 is completely removed by the etching process parameters, so that in the subsequent monocrystalline silicon etching process, the hard mask layer 104 is used as a mask for etching instead of the amorphous carbon layer 103, and the monocrystalline silicon on the inner surface of the groove is oxidized at the same time, so that the inner surface of the groove is covered with a layer of silicon oxide to form a protective layer, as shown in fig. 10.
S3: and removing the protective layer in the central area of the groove and reserving the protective layer on the inclined side wall of the edge of the groove.
The step of executing a through etching process, removing the protective layer in the central area of the groove by using a fourth etching gas, and reserving the protective layer on the inclined side wall of the edge of the groove;
preferably, in this step, the fourth etching gas includes a hydrogen-containing fluorocarbon gas (CHF) and hydrogen bromide, wherein the hydrogen-containing fluorocarbon gas is CHF 3 、CH 2 F 2 、CH 3 At least one of F. The flow ratio range of the hydrogen-containing fluorocarbon gas to the hydrogen bromide in the fourth etching gas is (2.5); the technological parameters throughout the etching process step include:
the pressure of the chamber ranges from 20mT to 50mT;
the radio frequency power range of the upper electrode is 800W-1500W;
the lower radio frequency power range is 50-200W;
the temperature range of the chamber is 40-60 ℃;
the process time range is 10-30s.
Specifically, unlike CHF in the prior art I 3 +O 2 Gas, O 2 Combined with C and H elements to promote CHF 3 To accelerate the etching rate of the silicon oxide. This step requires a reduction in the etch rate of the silicon oxide, so a combination of CHF + HBr is used. Since HBr contains H, which is a polymer component, and Br has a low etching rate for Si — O, the etching rate for silicon oxide is slow for the combination of CHF + HBr, and the deposition of polymer on the sidewalls makes the middle of the protective layer easier to be etched and the edges less prone to be etched, which is equivalent to adding an equivalent mask to the single crystal silicon at the top edge of the single crystal silicon layer, which improves the etching resistance of the single crystal silicon at the edge of the trench, and the combination of hydrogen bromide and the hydrofluorocarbon gas has a slow etching rate for silicon oxide and the hydrofluorocarbon gas has the effect of forming polymer and depositing on the sidewalls, so that the silicon oxide layer (protective layer) formed by the ashing step is always etched first in the middle and then at the edges, as shown in fig. 11.
S4: etching the substrate, forming a groove with a set depth in the substrate, simultaneously removing the protective layer on the inclined side wall of the edge of the groove and forming a rounded vertex angle shape on the edge of the top of the groove;
the step is a step of executing a monocrystalline silicon etching process, etching the monocrystalline silicon layer 105 by using a fifth etching gas, forming a groove with a set depth in the monocrystalline silicon layer 105, and simultaneously removing the protective layer on the inclined side wall at the edge of the groove and forming a rounded silicon vertex angle shape at the edge of the top of the groove.
The fifth etching gas adopted in the step comprises hydrogen-containing fluorocarbon gas and hydrogen bromide, and the flow ratio of the hydrogen-containing fluorocarbon gas to the hydrogen bromide in the fifth etching gas is lower than that of the hydrogen-containing fluorocarbon gas to the hydrogen bromide in the fourth etching gas, so that the etching rate of the monocrystalline silicon is improved.
Preferably, the flow ratio of the hydrogen-containing fluorocarbon gas to the hydrogen bromide in the fifth etching gas ranges from 1. The technological parameters of the monocrystalline silicon etching process step comprise:
chamber pressure: 20-50mT;
upper electrode radio frequency power: 800W-1500W;
lower electrode radio frequency power: 50-200W, the duty ratio range of the lower electrode radio frequency pulse is 30-60%, and the pulse frequency range is 100-300Hz;
the temperature of the chamber ranges from 50 to 70 ℃.
As shown in fig. 12, in this step, the inclination of the bottom of the single crystal silicon or the shape of the micro-groove can be improved by using the lower electrode rf pulse mode, and the influence of the inclination of the top of the single crystal silicon or the shape of the micro-groove transferred to the bottom of the single crystal silicon after the hard mask etching process on the subsequent dielectric filling can be solved.
Fig. 13a shows an electron microscope effect diagram of a sharp silicon vertex angle obtained by existing shallow trench etching, and fig. 13b shows an electron microscope effect diagram of a rounded silicon vertex angle obtained by a substrate trench etching method according to an embodiment of the present invention, which shows that an ideal rounded vertex angle morphology can be obtained by the etching method according to the embodiment of the present invention, so that the risk of electric leakage caused by the sharp vertex angle after subsequent medium filling is effectively reduced, and the performance of a semiconductor device is provided.
Having described embodiments of the present invention, the foregoing description is intended to be exemplary, not exhaustive, and not limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments.

Claims (12)

1. A substrate groove etching method is characterized by comprising the following steps:
forming a groove with an inclined side wall on the surface of the substrate;
forming a protective layer on the inner surface of the groove;
removing the protective layer in the central area of the groove and reserving the protective layer on the inclined side wall of the edge of the groove;
and etching the substrate, forming a groove with a set depth in the substrate, removing the protective layer on the inclined side wall of the edge of the groove and forming a rounded top angle appearance on the edge of the top of the groove.
2. The method according to claim 1, wherein the substrate comprises a monocrystalline silicon layer, a hard mask layer, an amorphous carbon layer and a patterned photoresist layer which are sequentially distributed from bottom to top.
3. The substrate trench etching method of claim 2, wherein the forming of the recess with the inclined sidewall on the substrate surface comprises:
etching openings exposing the surface of the monocrystalline silicon layer in the amorphous carbon layer and the hard mask layer by using first etching gas;
and etching a groove with an inclined side wall on the surface of the single crystal silicon layer exposed by the opening by using a second etching gas.
4. The substrate trench etching method of claim 3, wherein the first etching gas comprises a hydrogen-containing fluorocarbon gas, a diluent gas, and oxygen;
the second etching gas comprises hydrogen-containing fluorocarbon gas, diluent gas, oxygen and chlorine.
5. The substrate trench etching method of claim 2, wherein the forming of the protective layer on the inner surface of the recess comprises:
and etching the substrate by using a third etching gas, removing the amorphous carbon layer, oxidizing the monocrystalline silicon on the inner surface of the groove into silicon oxide, and forming the protective layer.
6. The substrate trench etching method of claim 5, wherein the third etching gas comprises oxygen, nitrogen and helium.
7. The substrate trench etching method of claim 2, wherein the removing the protective layer in the central region of the groove and retaining the protective layer on the inclined sidewall of the edge of the groove comprises:
and etching the hard mask layer and the monocrystalline silicon layer by using fourth etching gas, removing the protective layer in the central area of the groove, and reserving the protective layer on the inclined side wall of the edge of the groove.
8. The substrate trench etching method according to claim 7, wherein the fourth etching gas comprises hydrogen-containing fluorocarbon gas and hydrogen bromide, and the flow ratio of the hydrogen-containing fluorocarbon gas to the hydrogen bromide in the fourth etching gas is in a range of 2.5.
9. The substrate trench etching method of claim 2, wherein the forming a trench with a set depth in the substrate while removing the protection layer on the inclined sidewall of the edge of the groove and forming a rounded top corner profile at the top edge of the trench comprises:
and etching the hard mask layer and the monocrystalline silicon layer by using a fifth etching gas, forming a groove with a set depth in the monocrystalline silicon layer, removing the protective layer on the inclined side wall of the edge of the groove and forming a rounded top angle appearance on the edge of the top of the groove.
10. The substrate trench etching method according to claim 9, wherein the fifth etching gas comprises hydrogen-containing fluorocarbon gas and hydrogen bromide, and the flow ratio of the hydrogen-containing fluorocarbon gas to the hydrogen bromide in the fifth etching gas is in a range of 1.
11. The substrate trench etching method according to any one of claims 4, 8 and 10, wherein the hydrogen-containing fluorocarbon gas is CHF 3 、CH 2 F 2 、CH 3 At least one of F.
12. The substrate trench etching method according to claim 9, wherein in the process of etching the single crystal silicon layer with the fifth etching gas, etching is performed in a lower electrode pulse radio frequency mode.
CN202211201417.5A 2022-09-29 2022-09-29 Substrate groove etching method Pending CN115547825A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116053195A (en) * 2023-03-27 2023-05-02 合肥晶合集成电路股份有限公司 Method for forming shallow trench isolation structure

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116053195A (en) * 2023-03-27 2023-05-02 合肥晶合集成电路股份有限公司 Method for forming shallow trench isolation structure
CN116053195B (en) * 2023-03-27 2023-06-30 合肥晶合集成电路股份有限公司 Method for forming shallow trench isolation structure

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