CN115544937A - Method for calculating body resistance of partial depletion type SOI MOSFET - Google Patents

Abstract

The invention belongs to the technical field of semiconductor integrated circuits, and particularly relates to a method for calculating the body resistance of a silicon metal oxide semiconductor field effect transistor on a partially depleted insulating layer. According to the structural characteristics of the H-shaped gate MOSFET, the depletion charge quantity generated in the bulk silicon of the device by the front gate voltage and the back gate voltage is solved by utilizing a capacitance induced charge principle. And then obtaining depletion charges of the pn junction in the bulk silicon according to the pn junction model of the source electrode and the pn junction model of the drain electrode. On the basis, a basic body region multi-sub-charge model is established, and all residual multi-sub-charge electric quantity in the body region is obtained. And then, according to the charge movement rule, a bulk silicon resistance model is established so as to rapidly and accurately obtain the body resistance. The model result is highly consistent with both simulation and experimental results. The method has clear physical concept, easy calculation and high calculation precision, and provides an effective calculation method for extracting the key parameters of the SOI MOSFET.

Description

A Calculation Method of Body Resistance of Partially Depleted SOI MOSFET

technical field

The invention belongs to the technical field of semiconductor integrated circuits, specifically a partially depleted (PD, Partially Depleted) insulating layer silicon (SOI, Silicon-on-Insulator) metal oxide semiconductor field effect transistor (MOSFET, Metal-Oxide-Semiconductor Field-Effect Transistor) calculation method of body region resistance.

Background technique

With the continuous development of integrated circuit technology, as well as the progress of communication technology and digital signal processing technology, the working circuit under high frequency band has become the focus of design and research. This requires the model of the device in the circuit to be accurate, fast, and robust enough to meet the needs of circuit simulation under different conditions. SOI MOSFET is an ideal device, and its process is similar to CMOS process. However, due to the limited thickness of bulk silicon, the channel punch-through effect can be well suppressed and the subthreshold characteristics of the device can be improved. At the same time, the effect of the back gate can adjust the threshold voltage of the device. For this new type of structural device, when the bulk silicon is floating, its potential is prone to change, which in turn affects the threshold voltage. Therefore, before the device is actually applied, it must be able to quickly and accurately calculate its key parameters, such as channel potential, threshold voltage, etc., so that it can be used for circuit analysis and circuit simulation.

Body resistance is an important parameter affecting the performance of SOI devices. It will affect the ability of the body contact to control the body potential. It is defined as: making electrodes in the body region, measuring the current flowing from the body region under different conditions, and using The region voltage is divided by the body region current to finally obtain the body region resistance. To accurately describe the current-voltage characteristics of the device under different body bias voltages, a reasonable calculation of the body resistance is indispensable.

Contents of the invention

The object of the present invention is to provide a method for calculating the body region resistance of partially depleted SOIMOSFET with concise physics, fast calculation and accurate model.

The method for calculating the body region resistance of a partially depleted SOI MOSFET provided by the present invention, according to the structural characteristics of the H-type gate MOSFET, uses the principle of capacitance-induced charge to solve the amount of depletion charge generated by the front gate voltage and the back gate voltage in the bulk silicon of the device ; Then according to the source pn junction and drain pn junction models, the depletion charge of the pn junction in bulk silicon is obtained; on this basis, a basic body region multi-sub (for nMOSFET, for holes) charge model is established, and Obtain all the remaining multi-sub-charges in the bulk region; then, according to the law of charge movement, establish the resistance model of bulk silicon in order to quickly and accurately obtain the bulk resistance. The model results are in good agreement with the simulation and experimental results.

Specific steps are as follows.

(1) First, construct the multi-sub-charge model in PDSOI MOSFET bulk silicon, which is given by the following formula:

Q _nbr =qN _eff LWt _si -Q _B , (1)

Among them, Q _nbr is the multi-sub-charge, q is the electron charge, N _eff is the effective channel doping concentration (including halo doping), W and L are the channel width and length, respectively, t _si is the bulk silicon thickness, Q _B Deplete the charge for the body region; when the partially depleted SOI device is working, the interior is not completely depleted, so here it can be considered that the original total charge in the device is greater than the depleted charge;

_The total amount QB of body charge depletion due to each port, the composition of which is given by:

Q _B ＝Q _bf +Q _e +Q _js +Q _jd , (2)

Among them, Q _bf is the top gate induced charge, Q _e is the back gate induced charge, Q _js and Q _jd are the depletion layer charges of the source junction and drain junction respectively; the definitions of the charges are:

(1) Top gate induced charge:

Q _bf = WLC _ox (V _gs -V _FB -V _bs ), (3)

(2) Back gate induced charge:

Q _e =WLC _oxb (V _es -V _fbb -V _bs ), (4)

Where C _ox is the oxide layer capacitance per unit area of the top gate, V _gs is the voltage between the gate and the source, V _FB is the flat band voltage of the top gate, V _bs is the voltage between the body and the source, and V _es is the voltage between the substrate and the source , V _fbb is the flat band voltage of the back gate, C _oxb is the oxide layer capacitance per unit area of the back gate;

Construct the PDSOI MOSFET source-drain depletion charge model:

(1) Source junction depletion charge:

Wherein, A _sd is the source junction area, A _sd =Wt _si , ε _si is the silicon dielectric constant, V _in is the built-in potential, N _sd is the source/drain doping concentration;

(2) The drain junction depletes the charge:

Among them, V _ds is the voltage between drain and source.

(2) Construct the analytical model of resistance between body and source

There is a pn junction between the body and the source. In general, the current density is:

为n型半导体平衡时空穴浓度，

为p型半导体平衡时电子浓度，V_J为外加偏压。where D _p and D _n are the hole and electron diffusion coefficients, respectively, L _p and L _n are the diffusion lengths, W _p and W _n are the junction lengths,

is the hole concentration in n-type semiconductor equilibrium,

is the electron concentration of the p-type semiconductor in equilibrium, and V _J is the applied bias voltage.

For our research problem, the pn junction length is very short, that is, W _n << L _p , W _p << L _n , the above formula can be approximated as:

The current is:

When the injected minority carrier concentration reaches or exceeds the majority carrier concentration, the large injection effect must be considered. At this time, the diffusion coefficient is doubled, and the ideal factor m is increased. The above formula is modified as:

The value of m is between 1-2, D' _p =2D _p , D' _n =2D _n .

Therefore, the resistance between body and source is:

Among them, V _bs is the voltage between body and source, and I _bs is the current between body and source.

(3) Fitting that enhances the fitting effect

For the pn junction between source/body and drain/body, due to LDD and Halo doping, its built-in potential is more difficult to accurately describe with common analytical model, the present invention adds a fitting parameter in standard formula, by the following gives:

Among them, _ni is the intrinsic carrier concentration, f ₅ is the fitting parameter.

(4) For the H-type gate structure, the resistance generated by the multi-substances (for nMOSFET, holes) in the bulk silicon moving from the front end to the back end along the channel width direction is given by the following formula:

Among them, μ _B is the effective mobility of many particles, and Q _nbr is the charge of many particles, which is given by (1).

(5) The bulk region resistance is modeled as follows for the multi-carrier effective mobility: Considering that the gate voltage and the drain voltage will cause the carrier mobility to decrease, the effective mobility is expressed as:

Among them, f ₆ and f ₇ are two fitting parameters, which can be an integer between 5 and 20, μ ₀ is the low field mobility, which is related to the doping concentration, and for holes, μ ₀ is generally 75cm ² / Vs.

(6) The total bulk resistance can be regarded as the resistance R _bW between the front and rear ends of the bulk silicon, and the resistance R _bs between the front end and the source is connected in parallel, and finally:

The method of the invention has clear physical concept, is easy to calculate, and has high calculation precision, and provides an efficient calculation method for extracting key parameters of SOI MOSFET.

Description of drawings

Figure 1 is a cross-sectional view of the TCAD simulation structure.

Figure 2 is a bird's-eye view of the TCAD simulation structure.

Figure 3 is a schematic front view of the device structure.

FIG. 4 is a schematic diagram of the charge distribution in the bulk silicon of the device.

FIG. 5 is a schematic top view of an H-type gate device structure.

Fig. 6 is a flowchart of the method of the present invention.

Figure 7 is a graph comparing the model results with the simulation and experimental results.

Figure 8 is a comparison chart between the model results and the simulation results.

detailed description

The invention compares the numerical calculation results of the analytical model with the experimental results and the TCAD simulation results.

In Figure 7, we compare the relationship between the body resistance and the body region bias under different back gate bias voltages. The dots are the experimental results, the solid lines are the model results, and the dotted lines are the simulation results (to calibrate the simulation tool). The experiment uses H-type gate SOIMOSFET, the bias voltage of the device is: V _gs =-0.3V, V _DS =0V, V _ES is 0 and -10V respectively, and the flat band voltage V fb of the front gate and the rear gate is V _fb =V _fbb = -1V. The device size is: width W=3μm, length L=65nm, back gate oxide thickness _tbox =282nm, front gate oxide thickness _tfox =5nm, bulk silicon thickness _tsi =45nm, channel doping concentration _Neff =1.3×10 ¹⁸ cm ^-3 , source/drain doping concentration is 3×10 ²⁰ cm ^-3 , W _n =20nm, W _p =65nm. Material parameters for silicon: D _n =25 cm ² /s, D _p =10 cm ² /s, n _i =1.5×10 ¹⁰ cm ^-3 , μ ₀ =75 cm ² /Vs, T=300K. The values of the 7 fitting parameters in the model used are: f ₁ =0.57, f ₂ =0.12, f ₃ =0.02, f ₄ =0.786, f ₅ =0.2, f ₆ =9, f ₇ =6 . It is not difficult to see that the model results are in good agreement with the experimental results.

In addition, in order to calibrate the simulation tool, we simulate this device, and we can also see that the simulation results are in good agreement with the experimental results.

Figure 8 compares the relationship between body resistance and drain voltage under different gate voltages. The dots are the simulation results, and the solid lines are the model results. It can be seen that the analytical model agrees well with the simulation results. The bias voltages of the device during simulation are: V _gs =-0.5, 0, 0.5, 1V, V _ES is 0V, and the flat-band voltages of the front gate and the rear gate are V _fb =V _fbb =-1V. The device size is: width W=2μm, length L=200nm, back gate oxide thickness _tbox =200nm, front gate oxide thickness _tfox =5.3nm, bulk silicon thickness _tsi =250nm, channel doping concentration N _eff =3.3×10 ¹⁷ cm ^-3 , source/drain doping concentration is 6×10 ²⁰ cm ^-3 , W _n =20nm, W _p =65nm. The selection of material parameters for silicon is the same as that in FIG. 7 . The values of the 7 fitting parameters in the used model are: f ₁ =0.01, f ₂ =0.4, f ₃ =0.01, f ₄ =0.8, f ₅ =0.3, f ₆ =15, f ₇ =19.

It can be seen that the present invention can quickly and accurately extract SOI MOSFET body resistance and related key parameters, can quickly verify the functional design of integrated circuits, and provide an effective method for extracting body resistance parameters for circuit optimization design and electrical behavior simulation .

Claims (5)

1. A method for calculating the body resistance of a partial depletion type SOI MOSFET is characterized by comprising the following steps:

firstly, calculating the total body depletion charge Q caused by each port by the body charge model expression of the PDSOI MOSFET _B ，：

Q _B ＝Q _bf +Q _e +Q _js +Q _jd ， (1)

Wherein Q is _bf Is a top gate induced charge, Q _e Is a back gate induced charge, Q _js ,Q _jd Is the depletion layer charge of the source junction and the drain junction, and the definition formulas are respectively as follows:

(1) Top gate induced charge:

Q _bf ＝WLC _ox (V _gs -V _FB -V _bs ) (2)

(2) Back gate induced charge:

Q _e ＝WLC _oxb (V _es -V _fbb -V _bs ) (3)

wherein W is the device width, L is the device length, C _ox Is a top gate unit area oxide layer capacitor, V _gs Is the voltage between gate and source, V _FB Is the top gate flat band voltage, V _bs Is the voltage between the sources, V _es Is the voltage between the substrate and the source, V _fbb Is the back gate flat band voltage, C _oxb The unit area oxide layer capacitance of the back gate;

(3) Source junction depletion charge:

wherein A is _sd Is the source junction area, A _sd ＝Wt _si ，t _si Is the thickness of bulk silicon,. Epsilon _si Is the dielectric constant of silicon, V _in For built-in potential, N _eff For effective doping concentration of channel, N _sd Is the source/drain doping concentration, q is the electron electric quantity;

(4) Drain junction depletion charge:

wherein, V _ds Is the drain-source voltage;

(II) calculating the total charge carrier quantity Q of all the current carriers providing the body region _nbr ：

Q _nbr ＝qN _eff LWt _si -Q _B ， (6)

(III) obtaining the resistance R generated when the carriers move along the width direction of the channel according to the definition of the resistance _bW ：

Wherein, mu _B Is the carrier effective mobility.

2. The calculation method according to claim 1, wherein in the step (III), the resistance R between the body sources is considered _bs The resistance is modeled with a pn junction, and the final total body resistance is:

it is composed of a resistor R along the width direction of the channel _bW And source resistance R _bs Are connected in parallel to obtain the product.

3. The calculation method of claim 1, wherein the body charge model has a certain deviation in the analytical calculation, and in order to solve the problem, each charge is multiplied by a fitting parameter to improve the accuracy of the model; for four charge compositions: q _bf ，Q _e ，Q _js ,Q _jd Multiplying by fitting parameters respectively, namely:

Q _B ＝f ₁ Q _bf +f ₂ Q _e +f ₃ Q _js +f ₄ Q _jd ， (9)

wherein f is ₁ ，f ₂ ，f ₃ And f ₄ And is a fitting parameter between 0 and 1.

4. The method of claim 1, wherein the mobility μ of the bulk resistance is _B The expression of (a) is modified as follows:

considering that gate and drain voltages cause a reduction in carrier mobility, mobility is modeled as follows:

wherein f is ₆ And f ₇ Is 2 fitting parameters, μ ₀ Low field mobility.

5. The method of claim 2, wherein the inter-source resistance R _bs The expression of (a) is given by:

wherein, V _bs Is the voltage between the sources, I _bs Is inter-source current, W _n And Wp is the n-region and p-region lengths of the pn junction,

the hole concentration is balanced for the n-type semiconductor,

is the electron concentration at p-type semiconductor equilibrium, m is an ideality factor, and has a size between 1 and 2, k _B Is the Boltzmann constant, T is the temperature, V _J Is an applied voltage; d' _p And D' _n Hole and electron diffusion coefficients of 2 times, respectively.

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