CN115544937A - Method for calculating body resistance of partial depletion type SOI MOSFET - Google Patents

Method for calculating body resistance of partial depletion type SOI MOSFET Download PDF

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CN115544937A
CN115544937A CN202211168809.6A CN202211168809A CN115544937A CN 115544937 A CN115544937 A CN 115544937A CN 202211168809 A CN202211168809 A CN 202211168809A CN 115544937 A CN115544937 A CN 115544937A
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胡光喜
陆叶
于天晔
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Fudan University
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Abstract

The invention belongs to the technical field of semiconductor integrated circuits, and particularly relates to a method for calculating the body resistance of a silicon metal oxide semiconductor field effect transistor on a partially depleted insulating layer. According to the structural characteristics of the H-shaped gate MOSFET, the depletion charge quantity generated in the bulk silicon of the device by the front gate voltage and the back gate voltage is solved by utilizing a capacitance induced charge principle. And then obtaining depletion charges of the pn junction in the bulk silicon according to the pn junction model of the source electrode and the pn junction model of the drain electrode. On the basis, a basic body region multi-sub-charge model is established, and all residual multi-sub-charge electric quantity in the body region is obtained. And then, according to the charge movement rule, a bulk silicon resistance model is established so as to rapidly and accurately obtain the body resistance. The model result is highly consistent with both simulation and experimental results. The method has clear physical concept, easy calculation and high calculation precision, and provides an effective calculation method for extracting the key parameters of the SOI MOSFET.

Description

Method for calculating body resistance of partial depletion type SOI MOSFET
Technical Field
The invention belongs to the technical Field of Semiconductor integrated circuits, and particularly relates to a method for calculating a body resistance of a Partially Depleted (PD) Silicon-on-Insulator (SOI) Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET).
Background
With the continuous development of integrated circuit technology and the advancement of communication technology and digital signal processing technology, the circuit operating in high frequency band becomes the focus of design and research. This requires that the model of the devices in the circuit be accurate, fast, and robust enough to meet the needs of circuit simulation under different conditions. An SOI MOSFET is a preferred device and its process is similar to a CMOS process. But because the thickness of the bulk silicon is limited, the channel punch-through effect can be well inhibited, and the subthreshold characteristic of the device is improved. Meanwhile, the threshold voltage of the device can be adjusted due to the influence of the back grid. For the novel structural device, when bulk silicon is floated, the potential of the bulk silicon is easy to change, and the threshold voltage is further influenced. Therefore, before the device is practically applied, it must be able to quickly and accurately calculate its key parameters, such as channel potential, threshold voltage, etc., for circuit analysis and circuit simulation.
Bulk resistance is an important parameter affecting SOI device performance, which affects the ability of the bulk contact to control the bulk potential, defined as: and manufacturing electrodes in the body region, measuring the current flowing through the body region under different conditions, and dividing the body region voltage by the body region current to finally obtain the body region resistance. To accurately describe the current-voltage characteristics of the device under different body bias voltages, reasonable calculation of the body resistance is indispensable.
Disclosure of Invention
The invention aims to provide a method for calculating the body resistance of a partially depleted SOI MOSFET, which is simple in physics, quick to calculate and accurate in model.
According to the calculation method of the body resistance of the partial depletion type SOI MOSFET, the depletion charge quantity generated in the bulk silicon of a device by the front grid voltage and the back grid voltage is solved by utilizing the principle of capacitance induced charge according to the structural characteristics of the H-shaped grid MOSFET; then obtaining depletion charges of the pn junction in the bulk silicon according to the pn junction model of the source electrode and the pn junction model of the drain electrode; on the basis, a basic body region multi-son (for nMOSFET, a hole) charge model is established, and all residual multi-son charge electric quantity in the body region is obtained; and then, according to the charge movement rule, a bulk silicon resistance model is established so as to rapidly and accurately obtain the body resistance. The model result is highly consistent with both simulation and experimental results.
The method comprises the following specific steps.
Firstly, a model of multi-photon charge in bulk silicon of a PDSOI MOSFET is constructed, and is given by the following formula:
Q nbr ＝qN eff LWt si -Q B ， (1)
wherein Q is nbr Is a majority charge, q is an electron charge, N eff For effective channel doping concentration (halo-containing doping), W and L are the channel width and length, respectively, t si Is the thickness of bulk silicon, Q B Depleting the body region of charge; when the partially depleted SOI device works, the inside of the partially depleted SOI device is not completely depleted, so that the total charge quantity in the device is considered to be larger than the depleted charge quantity;
total amount of body charge depletion Q caused by each port B The composition is given by:
Q B ＝Q bf +Q e +Q js +Q jd ， (2)
wherein Q bf Is a top gate induced charge, Q e Is a back gate induced charge, Q js And Q jd Depletion layer charges of the source and drain junctions, respectively; the definitions of the charges are:
(1) Top gate induced charge:
Q bf ＝WLC ox (V gs -V FB -V bs )， (3)
(2) Back gate induced charge:
Q e ＝WLC oxb (V es -V fbb -V bs )， (4)
wherein C is ox Is a top gate unit area oxide layer capacitor, V gs Is the voltage between gate and source, V FB For flat band voltage of top gate, V bs Is the voltage between the sources, V es Is the voltage between the substrate and the source, V fbb Is back gate flat band voltage, C oxb For back gate unit area oxidationA layer capacitance;
constructing a source drain depletion charge model of the PDSOI MOSFET:
(1) Source junction depletion charge:
Figure BDA0003862665400000021
wherein A is sd Is the source junction area, A sd ＝Wt si ，ε si Is the dielectric constant of silicon, V in For built-in potential, N sd Source/drain doping concentration;
(2) Drain junction depletion charge:
Figure BDA0003862665400000022
wherein, V ds Is the drain-source voltage.
(II) construction of analytical model of resistance between source sources
Between the sources is a pn junction, and the current density is generally:
Figure BDA0003862665400000023
wherein D is p And D n Respectively hole and electron diffusion coefficients, L p And L n Is a diffusion length, W p And W n In order to be the length of the knot,
Figure BDA0003862665400000024
the hole concentration is balanced for the n-type semiconductor,
Figure BDA0003862665400000025
electron concentration at equilibrium of p-type semiconductor, V J Is an applied bias.
For the problem we have studied, the pn junction length is very short, i.e., W n ＜＜L p ,W p ＜＜L n The above formula can be approximated as:
Figure BDA0003862665400000031
the current is as follows:
Figure BDA0003862665400000032
when the injected minority carrier concentration reaches or exceeds the majority carrier concentration, the large injection effect is considered, the diffusion coefficient is increased by 1 time, the ideality factor m is increased, and the above formula is modified as follows:
Figure BDA0003862665400000033
m takes a value of between 1 and 2, D' p ＝2D p ,D′ n ＝2D n 。
Thus, the inter-source resistance is:
Figure BDA0003862665400000034
wherein, V bs Is the voltage between the sources, I bs Is the current between the source sources.
(III) fitting to enhance fitting Effect
For the pn junction between the source/body and the drain/body, because of LDD and Halo doping, the built-in potential is difficult to be accurately described by a common analytic model, and a fitting parameter is added in a standard formula and is given by the following formula:
Figure BDA0003862665400000035
wherein n is i Is the intrinsic carrier concentration, f 5 Are fitting parameters.
(IV) for an H-type gate structure, the resistance generated by the movement of a majority electron (hole for nMOSFET) in bulk silicon from front to back in the channel width direction is given by:
Figure BDA0003862665400000036
wherein, mu B For effective mobility of majority element, Q nbr The amount of charge is given by the formula (1).
And (V) modeling the effective mobility of the majority carriers by using the body resistance as follows: considering that the gate voltage and the drain voltage cause the carrier mobility to be reduced, the effective mobility is expressed as:
Figure BDA0003862665400000037
wherein f is 6 And f 7 Is 2 fitting parameters, which may be an integer between 5 and 20, mu 0 For low field mobility, depending on the doping concentration, for holes, μ 0 Typically 75cm 2 /Vs。
(VI) the total bulk resistance can be regarded as the resistance R between the front end and the rear end of the bulk silicon bW And a resistance R between the front end and the source bs Parallel connection, and finally obtaining:
Figure BDA0003862665400000041
the method has clear physical concept, easy calculation and high calculation precision, and provides an efficient calculation method for extracting the key parameters of the SOI MOSFET.
Drawings
FIG. 1 is a cross-sectional view of a TCAD simulation structure.
FIG. 2 is a schematic view of a TCAD simulation structure.
Fig. 3 is a schematic front view of a device structure.
Fig. 4 is a schematic diagram of the charge distribution in bulk silicon of the device.
Fig. 5 is a schematic top view of an H-gate device structure.
FIG. 6 is a flow chart of the method of the present invention.
FIG. 7 is a graph comparing model results with simulation and experimental results.
FIG. 8 is a graph comparing model results with simulation results.
Detailed Description
The invention compares the numerical calculation result of the analytical model with the experimental result and the TCAD simulation result.
In fig. 7, we compared the body resistance with the body bias voltage for different back gate bias voltages, the circles are experimental results, the solid lines are model results, and the dashed lines are simulation results (for calibration of the simulation tool). The experimental H-type gate SOI MOSFET is used, and the bias voltages of the devices are respectively as follows: v gs ＝-0.3V,V DS ＝0V,V ES 0 and-10V, respectively, flat band voltage V of front and back gates fb ＝V fbb And = 1V. The device dimensions were: width W =3 μm, length L =65nm, back gate oxide thickness t box =282nm, the thickness of the front gate oxide layer is t fox =5nm, bulk silicon thickness t si =45nm, channel doping concentration N eff ＝1.3×10 18 cm -3 Source/drain doping concentration of 3 × 10 20 cm -3 ，W n ＝20nm,W p =65nm. Material parameters for silicon: d n ＝25cm 2 /s,D p ＝10cm 2 /s,n i ＝1.5×10 10 cm -3 ,μ 0 ＝75cm 2 Vs, T =300K. The values of 7 fitting parameters in the used model are respectively as follows: f. of 1 ＝0.57，f 2 ＝0.12，f 3 ＝0.02，f 4 ＝0.786，f 5 ＝0.2，f 6 ＝9，f 7 And (6). It can be seen that the model results agree well with the experimental results.
In addition, in order to calibrate the simulation tool, the device is simulated, and the simulation result is also well matched with the experimental result.
Fig. 8 compares the resistance variation with drain voltage under different gate voltages, where the dots are simulation results and the solid lines are model results. It can be seen that the analytical model fits well with the simulation results. The device bias voltages during simulation are respectively: v gs ＝-0.5,0,0.5,1V,V ES 0V, flat band voltage V of front and rear gates fb ＝V fbb And = 1V. The device dimensions were: width W =2 μm, length L =200nm, back gate oxide thickness t box =200nm, the thickness of the front gate oxide layer is t fox =5.3nm, bulk silicon thickness t si =250nm, channel doping concentration N eff ＝3.3×10 17 cm -3 The source/drain doping concentration is 6 x 10 20 cm -3 ，W n ＝20nm,W p =65nm. The material parameters for silicon were chosen as in fig. 7. The values of 7 fitting parameters in the used model are respectively as follows: f. of 1 ＝0.01，f 2 ＝0.4，f 3 ＝0.01，f 4 ＝0.8，f 5 ＝0.3，f 6 ＝15，f 7 ＝19。
Therefore, the invention can rapidly and accurately extract the SOI MOSFET body resistance and related key parameters, can rapidly verify the functional design of the integrated circuit, and provides an effective body resistance parameter extraction method for circuit optimization design and electrical behavior simulation.

Claims (5)

1. A method for calculating the body resistance of a partial depletion type SOI MOSFET is characterized by comprising the following steps:
firstly, calculating the total body depletion charge Q caused by each port by the body charge model expression of the PDSOI MOSFET B ，：
Q B ＝Q bf +Q e +Q js +Q jd ， (1)
Wherein Q is bf Is a top gate induced charge, Q e Is a back gate induced charge, Q js ,Q jd Is the depletion layer charge of the source junction and the drain junction, and the definition formulas are respectively as follows:
(1) Top gate induced charge:
Q bf ＝WLC ox (V gs -V FB -V bs ) (2)
(2) Back gate induced charge:
Q e ＝WLC oxb (V es -V fbb -V bs ) (3)
wherein W is the device width, L is the device length, C ox Is a top gate unit area oxide layer capacitor, V gs Is the voltage between gate and source, V FB Is the top gate flat band voltage, V bs Is the voltage between the sources, V es Is the voltage between the substrate and the source, V fbb Is the back gate flat band voltage, C oxb The unit area oxide layer capacitance of the back gate;
(3) Source junction depletion charge:
Figure FDA0003862665390000011
wherein A is sd Is the source junction area, A sd ＝Wt si ，t si Is the thickness of bulk silicon,. Epsilon si Is the dielectric constant of silicon, V in For built-in potential, N eff For effective doping concentration of channel, N sd Is the source/drain doping concentration, q is the electron electric quantity;
(4) Drain junction depletion charge:
Figure FDA0003862665390000012
wherein, V ds Is the drain-source voltage;
(II) calculating the total charge carrier quantity Q of all the current carriers providing the body region nbr ：
Q nbr ＝qN eff LWt si -Q B ， (6)
(III) obtaining the resistance R generated when the carriers move along the width direction of the channel according to the definition of the resistance bW ：
Figure FDA0003862665390000013
Wherein, mu B Is the carrier effective mobility.
2. The calculation method according to claim 1, wherein in the step (III), the resistance R between the body sources is considered bs The resistance is modeled with a pn junction, and the final total body resistance is:
Figure FDA0003862665390000021
it is composed of a resistor R along the width direction of the channel bW And source resistance R bs Are connected in parallel to obtain the product.
3. The calculation method of claim 1, wherein the body charge model has a certain deviation in the analytical calculation, and in order to solve the problem, each charge is multiplied by a fitting parameter to improve the accuracy of the model; for four charge compositions: q bf ，Q e ，Q js ,Q jd Multiplying by fitting parameters respectively, namely:
Q B ＝f 1 Q bf +f 2 Q e +f 3 Q js +f 4 Q jd ， (9)
wherein f is 1 ，f 2 ，f 3 And f 4 And is a fitting parameter between 0 and 1.
4. The method of claim 1, wherein the mobility μ of the bulk resistance is B The expression of (a) is modified as follows:
considering that gate and drain voltages cause a reduction in carrier mobility, mobility is modeled as follows:
Figure FDA0003862665390000022
wherein f is 6 And f 7 Is 2 fitting parameters, μ 0 Low field mobility.
5. The method of claim 2, wherein the inter-source resistance R bs The expression of (a) is given by:
Figure FDA0003862665390000023
wherein, V bs Is the voltage between the sources, I bs Is inter-source current, W n And Wp is the n-region and p-region lengths of the pn junction,
Figure FDA0003862665390000024
the hole concentration is balanced for the n-type semiconductor,
Figure FDA0003862665390000025
is the electron concentration at p-type semiconductor equilibrium, m is an ideality factor, and has a size between 1 and 2, k B Is the Boltzmann constant, T is the temperature, V J Is an applied voltage; d' p And D' n Hole and electron diffusion coefficients of 2 times, respectively.
CN202211168809.6A 2022-09-24 2022-09-24 Method for calculating body resistance of partial depletion type SOI MOSFET Pending CN115544937A (en)

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