CN115543901A - Radio frequency signal quality optimization algorithm and device based on FPGA - Google Patents

Abstract

The invention relates to an efficient high-precision software radio (SDK) radio frequency signal quality optimization algorithm and device based on an FPGA. The equipment comprises a signal generator, an AD/DAC, an FPGA, an oscilloscope and an upper computer; the algorithm of the invention is based on the above device, and specifically comprises: firstly, two paths of radio frequency cosine signals S1 and S2 are input through a high-speed interface GTX; secondly, storing the data into DDR3 respectively; reading out the phase difference from DDR3 as the input of a phase calculation algorithm module so as to calculate the phase difference of the two paths of signals, wherein the phase calculation algorithm comprises an FFT algorithm and a Cordic algorithm; inputting the phase difference and a signal S1 to be calibrated into a phase calibration module so as to obtain QPSK _ Singal with the same frequency and phase as S2, wherein the phase calibration algorithm is mainly a QPSK algorithm; and finally, outputting QPSK _ Singal and S2 through a high-speed interface GTX.

Description

Radio frequency signal quality optimization algorithm and device based on FPGA

Technical Field

The invention relates to the field of software radio and digital signal processing, in particular to a radio frequency signal quality optimization algorithm and device based on an FPGA (field programmable gate array).

Background

Since Xilinx corporation introduced commercialized FPGA for the first time in 1985, it is less than 40 years to date, and has replaced ASIC chip in some fields to become mainstream because of its advantages of short design cycle, programmability, fast computing speed, low power consumption and low cost. In recent years, with the development of image processing technology, artificial intelligence, big data and other technologies, data processing systems with FPGAs as cores have been rapidly developed. In the radio field, due to the influence of channel materials and environment, a certain phase difference exists between radio frequency signals, and the problem of solving the signal quality by using a software radio technology is an urgent problem to be solved nowadays.

Disclosure of Invention

The invention aims to overcome the incompleteness of the prior art and provides an efficient high-precision software radio frequency signal quality optimization algorithm and device based on an FPGA.

The invention relates to radio frequency signal quality optimization equipment based on an FPGA (field programmable gate array), which comprises a signal generator, an analog-digital/digital-analog converter (AD/DAC), the FPGA, an oscilloscope and an upper computer, wherein the signal generator is electrically connected with the AD/DAC through an output channel 1 and a channel 2, the AD/DAC is electrically connected with the FPGA through an SMA (surface-mounted memory) interface, the AD/DAC is also electrically connected with the oscilloscope through a BNC (bayonet nut connector) connecting wire, the FPGA is electrically connected with the upper computer through a USB (universal serial bus) interface wire, and the upper computer is computer software capable of directly sending an operation command and receiving data.

The invention relates to a radio frequency signal quality optimization algorithm based on FPGA, which comprises an input high-speed interface module GTX, a DDR3 cache module, a phase resolving module, a phase calibration module, an upper computer waveform monitoring module and an output high-speed interface module GTX, and the algorithm comprises the following specific steps:

1) The GTX high-speed serial transceiver inputs two paths of radio frequency signals S1 and S2;

2) The DDR3 cache module caches time domain data of the signals of the S1 and the S2;

3) The phase resolving module obtains the phase difference theta _ diff of the two paths of radio frequency signals S1 and S2;

4) The phase calibration module calibrates an original signal S1 to obtain two paths of radio frequency signals QPSK _ Single and S2 with the same frequency and phase, and outputs the signals through the output high-speed interface module GTX;

5) And monitoring the change of the input/output signal waveform by using an upper computer waveform monitoring module.

Further, in step 4) of the algorithm of the present invention, the phase calibration module mainly uses Quadrature Phase Shift Keying (QPSK) modulation, and the error of the phase calibration is less than 0.01%.

Further, the algorithm of the present invention adopts 64PSK modulation in step 4), corresponding to 128 angle values in the whole circumference, to modulate the angles in the first quadrant and the fourth quadrant; firstly, a ph2gray module is utilized to convert the phase difference theta _ diff obtained in the step 3) into gray codes corresponding to a 64PSK first quadrant and a 64PSK fourth quadrant angle, then 6-bit gray codes are input into the 64PSK module as binary information, according to the input different gray codes, different I-path signals and Q-path signals are multiplied by the sine and cosine forms of residual carriers (namely signals S1 to be calibrated) respectively, then two paths of multipliers are added to obtain a final calibration signal QPSK (namely calibrated signal QPSK _ Single), at the moment, the QPSK _ Single and S2 have the same frequency and the same phase, and the GTX data path is utilized to output the QPSK _ Single and S2.

Further, the phase difference range in the step 3) of the algorithm is [ - π/2, π/2], and the error of phase calculation is less than 0.001%.

Further, the phase solving module in step 3) of the algorithm of the present invention includes an FFT algorithm and a Cordic algorithm, and the process specifically includes: firstly, inputting time domain data of two paths of signals S1 and S2 into a two-channel Fast Fourier Transform (FFT) algorithm module, simultaneously carrying out FFT transformation on the two paths of signals by the two channels, solving frequency domain data of the two paths of signals, and solving the square sum of a real part and an imaginary part of the frequency domain data so as to solve amplitude spectra of the two paths of signals; then inputting the amplitude spectrums of the two paths of signals into a maximum value searching module so as to obtain the maximum value of the amplitude spectrums and the index number corresponding to the maximum value; then, the real part and the imaginary part of the frequency domain data corresponding to the maximum value of the amplitude spectrum are taken and input into a Cordic algorithm module, and the arctangent values of the input real part and the imaginary part are solved in a vector mode of a circumferential coordinate system by utilizing a Cordic algorithm, so that the initial phases theta1 and theta2 of the two paths of radio frequency signals are obtained; and finally, the phase difference theta _ diff of the two paths of radio frequency signals is obtained by carrying out difference on the two initial phases.

Further, a two-channel Fast Fourier Transform (FFT) algorithm module in the step 3) of the algorithm adopts a radix-2 butterfly FFT algorithm; the specific process is as follows: in the fast Fourier transform, a time extraction FFT algorithm (DIT) is used, an input sequence x (N) is divided into two groups according to the parity of N, namely, the transformation process of DFT transformation is carried out on a sequence length N point x (N), and the DFT transformation can be equivalently carried out on two sequence length N/2 points;

and every two points in two sequence length N/2 points can calculate two point values with the interval of N/2 in the DFT of the sequence length N point, and the calculation form is called butterfly operation, namely:

A'＝A+BW (1)

B'＝A-BW (2)。

further, a ping-pong structure memory is adopted in the FFT operation process of the step 3) of the algorithm for processing the access of the internal butterfly transformation intermediate data of each stage; two groups of RAM memories with the same size are respectively used for reading data in the first-stage butterfly transformation and writing operation results, and each group of RAM memories is two; storing a real part cosine value and an imaginary part sine value of a twiddle factor required by N-point FFT conversion into a ROM, wherein for an N-point input sequence, N/2 twiddle factor values are required by the system FFT conversion, the specification of the twiddle factor ROM is 16bit N/2, and each data word is 16bits; the front 8bits of the data unit stores a real part cosine value, and the rear 8bits of the data unit stores an imaginary part sine value.

Further, the algorithm of the present invention only stores cos values of N/4+1 twiddle factors by using the address mapping function in step 3).

Further, step 1) of the algorithm of the present invention includes a GTX data path, where the GTX data path includes a transmission data path TX and a reception data path RX; parallel data input from outside firstly enters a high-speed serial transceiver through a TX interface, is subjected to channel coding, phase alignment, polarity control, parallel-serial conversion and pre-emphasis processing, and finally is output to a channel in the form of a high-speed serial differential signal through a TX driver;

and the high-speed serial signals enter the high-speed serial transceiver through an RX buffer, are recovered into parallel data after signal equalization, clock data recovery, serial-to-parallel conversion, polarity control, comma detection, channel decoding and phase alignment, and finally enter the FPGA internal logic through an RX interface.

Compared with the prior art, the invention has the following beneficial technical effects:

the radio frequency signal quality optimization algorithm and the radio frequency signal quality optimization equipment based on the FPGA solve the problem of phase quality of radio frequency signals by using a software radio technology, realize related complex algorithms based on the FPGA with large scale, high performance and high reliability, and overcome the problem of hardware resource limitation existing in software radio. In the invention, the data transmission is carried out by utilizing the high-speed interface GTX, so that the real-time high-speed signal processing can be carried out, and the maximum transmission rate can reach 10Gbps, thereby solving the problem that the rate of the common I/O interface does not reach the standard in the transmission process of the real-time high-speed signal; moreover, DDR3 is used for caching data, because the read-write speed of the DDR3 is higher than that of other common storage equipment, the maximum read-write speed can reach 1500MT/s, and therefore the problem that the rates of real-time high-speed signals are not matched in the two processes of data transmission and data processing is solved; finally, the invention also measures the phase difference of the radio frequency signals based on the FFT algorithm, the Cordic algorithm and the 64PSK algorithm realized by the FPGA, modulates the phase of the radio frequency signals and utilizes the parallel characteristic of the FPGA to a great extent, thereby greatly improving the operation efficiency of the related algorithm; in the process of carrying out algorithm processing on the data, fixed-point signed numbers are adopted, resource consumption is considered, and meanwhile, the data bit width is greatly increased, so that the calculation error can be reduced to a certain extent, the finally obtained phase error is less than 0.001%, and the operation precision is greatly improved; in addition, the invention utilizes the development waveform monitoring upper computer to monitor the change condition of the input/output waveform in real time, thereby solving the visualization problem in the real-time processing process of the high-speed signal.

Drawings

Fig. 1 is a schematic structural diagram of an rf signal quality optimizing apparatus according to the present invention;

FIG. 2 is an architecture diagram of the RF signal quality optimization algorithm of the present invention;

FIG. 3 is a read-write state transition diagram of the DDR3 cache module according to the invention;

FIG. 4 is a diagram of the DIT radix-2 FFT butterfly unit according to the present invention;

FIG. 5 is a diagram of the 12-stage pipeline architecture of the Cordic algorithm of the present invention;

FIG. 6 is a diagram of a QPSK modulation implementation of the present invention;

FIG. 7 is a flowchart illustrating the operation of the upper computer according to the present invention.

Detailed Description

The present invention will be described in further detail with reference to specific examples.

Example 1:

the radio frequency signal quality optimization device based on the FPGA comprises a signal generator, an analog-digital/digital-analog converter (AD/DAC), the FPGA, an oscilloscope and an upper computer, wherein the signal generator is electrically connected with the AD/DAC through an output channel 1 and a channel 2, the AD/DAC is electrically connected with the FPGA through an SMA interface, the AD/DAC is also electrically connected with the oscilloscope through a BNC connecting line, the FPGA is electrically connected with the upper computer through a USB (universal serial bus) interface line, and the upper computer is computer software capable of directly sending control commands and receiving data. In this embodiment, the signal generator is a three-channel SYN5651 RF signal generator, which can generate various signals with frequency range of 10uHz-30 GHzD; the analog-digital/digital-analog converter is an enhanced line ADC with a double channel of 5.2GSPS and a DAC with a double channel of low delay of 3.2 GSPS; the FPGA is a K7 series FPGA development board of Xilinx; the oscilloscope is an MSO64B type oscilloscope, and the highest analog bandwidth can reach 10GHz.

Example 2:

the invention relates to a radio frequency signal quality optimization algorithm based on FPGA, which is realized based on the equipment described in embodiment 1, vivado software of xilinx company and a K7 series development board. As shown in fig. 2, the algorithm includes an input high-speed interface module GTX, a DDR3 cache module, a phase calculation module, a phase calibration module, an upper computer waveform monitoring module, and an output high-speed interface module GTX.

The input high-speed interface module GTX and the output high-speed interface module GTX are mainly high-speed serial transceivers embedded in K7 series FPGA development boards, the architecture of the transceiver comprises a plurality of paths of data channels and a shared clock (QPLL), each channel further comprises a sending (TX) data channel and a Receiving (RX) data channel, data receiving and sending are achieved jointly, a channel phase-locked loop (CPLL) is embedded in each channel, and a reference clock when each channel transmits data can be provided by the CPLL or the QPLL. The sending data path carries out channel coding on input parallel data, and the input parallel data is output as a high-speed differential serial signal after parallel-serial conversion and pre-emphasis processing; the receiving data channel receives a high-speed differential serial signal from a transmission channel, converts the high-speed differential serial signal into parallel data after signal equalization processing, clock extraction and data recovery, and transmits the parallel data to FPGA internal logic in a parallel data mode after operations such as channel decoding, clock calibration, channel alignment and the like.

The IP core of the GT is called in vivado, configured as a GTX interface, and sets a required communication rate, a reference clock, and the like. The GTX interface may receive external signal source data, when RX and TX are short-circuited, output data of the interface is input data, a data loopback is implemented, when data is transmitted to the transmission port TX, the same data may be received at the reception end RX (when data shift does not occur), and if data shift occurs, the data may be recombined by the reception end control signal gt0_ rxcharisk _ i. The transmitting end TX starts to transmit data after transmitting the K-code control word, and transmits a transmission word gt0_ txcharisk _ i 0001 every 100 data lengths to observe whether the data is shifted or not. The character control signal gt0_ rxcharisk _ i at the receiving end is stable after a period of time, when the character control signal gt0_ rxcharisk _ i at the receiving end starts to receive data after the character control signal is stable, the character control signal gt0_ rxcharisk _ i data 0100 at the receiving end has two-bit offset compared with the character control signal at the sending end 0001, namely, the data at the receiving end has two-byte offset, the high 16bits of the data are received data, and the received data are the same as the signal source.

The DDR3 cache module is a data storage module of the invention, and mainly designs a DDR3 read-write controller, controls the DDR3 to cache data, stores the data input by a high-speed interface into the DDR3, and then reads the data from the DDR3 to process the data. Because the time sequence of the DDR3 is very complex, for simple design, an axinx official MIG (Memory Interface Generators) IP core is called, a READ-WRITE control command of an MIG IP core user Interface end is further controlled, and READ-WRITE control over the DDR3 is more convenient, as shown in fig. 3, the READ-WRITE state of the DDR3 is totally divided into four states, the IDLE state is started at the beginning of power-on, the WRITE (DDR 3 WRITE) state is jumped to after the initialization of the DDR3 chip is completed, the WAIT state is jumped to when a WRITE counter equals to the WRITE data length, the READ (DDR 3 READ) state is unconditionally jumped to after one period is consumed, and the IDLE state is jumped to when the READ counter equals to the READ data length.

The write state firstly judges signals app _ rdy and app _ wdf _ rdy sent by the MIG IP core, when the two signals are high at the same time, app _ en and app _ wdf _ wren are pulled up, and a write-out command is given at the same time, namely app _ cmd is 0, and at this moment, a DDR3 write process is formally carried out. During the write, write data app _ wdf _ data and address count wr _ addr _ cnt self-increment by 1 at each clock. In addition, app _ addr adds 8 for each time, because the user side performs 256-bit data transmission at each user clock, 8 times of transmission are needed at the DDR3 physical chip side, and 8 addresses are needed for each time of transmitting one address bit wide 32bit and 8 times. In the read state, the signal app _ rdy sent by the MIG IP core is determined, when the signal is high, app _ en is pulled high, and a read command is given, that is, app _ cmd is 1, and then a read operation is started. App _ addr also self-increments by 8 at a time when a read operation is performed. The read operation ends and jumps back to the idle state.

The phase resolving module mainly comprises an FFT algorithm and a Cordic algorithm, firstly, two paths of signal time domain data read out from DDR3 are input into the two-channel FFT algorithm module, the two channels simultaneously carry out FFT transformation on the two paths of signals to solve the frequency domain data of the two paths of signals, and the real part and the imaginary part of the frequency domain data are taken to solve the square sum, so that the respective magnitude spectra of the two paths of signals are solved; inputting the amplitude spectrums of the two paths of signals into a maximum value searching module so as to obtain the maximum value of the amplitude spectrums and the corresponding index number; the real part and the imaginary part of frequency domain data corresponding to the maximum value of the amplitude spectrum are taken and input into a Cordic algorithm module, and the arctangent values of the input real part and the imaginary part are solved in a vector mode of a circumferential coordinate system by utilizing a Cordic algorithm, so that the initial phases theta1 and theta2 of the two paths of radio frequency signals are obtained; and (3) obtaining the phase difference theta _ diff of the two radio frequency signals by carrying out difference on the two initial phases, wherein the range of the phase difference is [ -pi/2, pi/2 ], and the phase resolving error is less than 0.001%.

Further, the dual-channel FFT module mainly adopts a radix-2 butterfly FFT algorithm. By "radix-2" is meant that in the fast fourier transform, if the time-decimated FFT algorithm (DIT) is used, the input sequence x (N) is divided into two groups according to the parity of N, i.e. the transform process of DFT transform is performed on the sequence length N points x (N), which can be equivalent to two DFT transforms of sequence length N/2 points. In addition, the "butterfly" is so-called because in the process of calculating a DFT transform with a sequence length of N points by a DFT transform with two sequence lengths of N/2 points, the calculation form can be simplified to a '= a + BW and B' = a-BW, which is similar to the butterfly. Therefore, two points in two sequence length N/2 points can calculate two-point values with a sequence length N points DFT middle interval of N/2, and the calculation form is usually called butterfly operation, namely:

A'＝A+BW (1)

B'＝A-BW (2)

fig. 4 shows a butterfly unit. According to the data characteristics, a ping-pong structure memory is adopted in the FFT operation process for processing the access of the internal butterfly transformation intermediate data of each stage; the structure is characterized in that two groups of RAM memories with the same size are respectively used for reading data in the first-stage butterfly transformation and writing operation results, and because the input and output of the butterfly unit are two parallel complex numbers, each group of the RAM memories is two. The real part cosine value and imaginary part sine value of the twiddle factor required by the N-point FFT conversion are further stored in a ROM, for the N-point input sequence, N/2 twiddle factor values are required by the system FFT conversion, and the specification of the twiddle factor ROM is 16bit N/2, and each data word is 16bits; the front 8bits of the data unit stores a real part cosine value, and the rear 8bits of the data unit stores an imaginary part sine value. The address mapping function can be used to store only cos values of N/4+1 twiddle factors to reduce ROM resource consumption.

The Cordic algorithm module, cordic (Coordinate Rotation Digital Computer) algorithm, namely Coordinate Rotation Digital calculation method, can realize the operation of trigonometric function, square root, arctangent and the like in FPGA. The core of the CORDIC algorithm is the (pseudo) rotation angle, in the vector mode, y is driven to 0 through continuous iteration. To achieve this goal, each iteration determines the direction of rotation by determining the sign of yi, eventually rotating the initial vector to the positive half of the X-axis, and this process also causes the angle of rotation θ for each micro-rotation to be accumulated and stored in a variable z, where tan θ ⁱ ＝2 ^-i The corresponding iterative process is as follows:

x _i+1 ＝x _i -d _i y _i 2 ^-i (3)

y _i+1 ＝y _i +d _i x _i 2 ^-i (4)

z _i+1 ＝z _i –d _i tan ^-1 2 ^-I (5)

and has when y _i <When =0, d _i = 1; when y is _i >At 0, d _i ＝-1。

From the iterative relationship, it can be seen that the basic processing unit of CORDIC algorithm mainly consists of three adders and a LUT (memory angle), plus two shift operations, which is the advantage of CORDIC algorithm. In the invention, a hardware framework of a 12-stage parallel assembly line is adopted, and an independent CORDIC processing unit is provided for each iteration process, so that a control circuit is not needed, the operation of shifting, adding and subtracting can be completed, the error after 12-stage assembly line iteration is very small, and the requirement of high-precision phase measurement can be met. Fig. 5 is a 12-stage parallel pipeline architecture of Cordic algorithm.

The phase calibration module is characterized in that quadrature phase shift keying 64PSK modulation is mainly utilized, the phase difference theta _ diff is used as a reference signal, and a signal S1 to be calibrated is used as a carrier signal to be input into a QPSK module, so that the phase of the signal S1 to be calibrated is modulated to be the same as that of the signal S2; because the phase difference theta _ diff ranges from [ -pi/2, pi/2 ], only the angles in the first quadrant and the fourth quadrant need to be modulated, and the phase calibration error is less than 0.01 percent. As shown in fig. 6, which is a 64PSK implementation schematic diagram, firstly, a ph2gray module is used to convert the phase difference theta _ diff into gray codes corresponding to the first quadrant and the fourth quadrant of the 64PSK, then the 6-bit gray codes are input to the 64PSK module as binary information, according to the input different gray codes, the different I-path signals and Q-path signals are multiplied by the sine and cosine forms of the remaining carriers (i.e., the signal S1 to be calibrated) respectively, and then the two paths of multipliers are added to obtain the final calibration signal QPSK _ single, where the QPSK _ single signal should be in the same frequency and phase as the original S2 signal.

As shown in fig. 7, the upper computer waveform monitoring module is characterized in that an upper computer with serial communication is developed by using C # language, the upper computer and the lower computer are directly connected through a USB-to-serial connection line for data interaction, and can receive waveform data sent by the lower computer and display the change condition of the waveform in real time. The working mode of the upper computer is serial communication based on byte transmission, the lower computer sends data to the upper computer one bit by one bit and receives data one bit by one bit according to the byte as a unit. And the upper computer analyzes the data after receiving the data, and removes the check bit, the stop bit and the like according to the agreed communication mode to obtain the original data. Our data form is 16-bit two's complement, and the transmission process is transmitted according to bytes, so the upper computer also splices and converts the data. And after the upper computer analyzes the data, displaying the data waveform in a waveform window, converting the data into a 16-system data and displaying the data in a control window. After one path of signal transmission is finished (one path of signal has 16384 data), the upper computer stores the signal waveform image into a local file so as to compare waveforms before and after modulation.

Claims (10)

1. The radio-frequency signal quality optimization equipment based on the FPGA is characterized by comprising a signal generator, an analog-digital-to-digital converter (AD/DAC), the FPGA, an oscilloscope and an upper computer, wherein the signal generator is electrically connected with the AD/DAC through an output channel 1 and a channel 2, the AD/DAC is electrically connected with the FPGA through an SMA interface, the AD/DAC is also electrically connected with the oscilloscope through a BNC connecting wire, the FPGA is electrically connected with the upper computer through a USB (universal serial bus) switching port wire, and the upper computer is computer software capable of directly sending an operation command and receiving data.

2. The radio frequency signal quality optimization algorithm based on the FPGA is characterized by comprising an input high-speed interface module GTX, a DDR3 cache module, a phase resolving module, a phase calibration module, an upper computer waveform monitoring module and an output high-speed interface module GTX, and specifically comprises the following steps:

1) The GTX high-speed serial transceiver inputs two paths of radio frequency signals S1 and S2;

2) The DDR3 cache module caches time domain data of the signals of the S1 and the S2;

3) The phase resolving module obtains the phase difference theta _ diff of the two paths of radio frequency signals S1 and S2;

4) The phase calibration module calibrates an original signal S1 to obtain two paths of radio frequency signals QPSK _ Single and S2 with the same frequency and phase, and outputs the radio frequency signals through the output high-speed interface module GTX;

5) And monitoring the change of the input/output signal waveform by using an upper computer waveform monitoring module.

3. The FPGA-based rf signal quality optimization algorithm of claim 2, wherein the phase calibration module in step 4) mainly utilizes Quadrature Phase Shift Keying (QPSK) modulation, and the error of the phase calibration is less than 0.01%.

4. The FPGA-based radio frequency signal quality optimization algorithm of claim 3, wherein 64PSK modulation is adopted in the step 4), and the angles in the first quadrant and the fourth quadrant are modulated corresponding to 128 angle values in a whole circle; firstly, a ph2gray module is utilized to convert the phase difference theta _ diff obtained in the step 3) into gray codes corresponding to a 64PSK first quadrant and a 64PSK fourth quadrant angle, then 6-bit gray codes are input into the 64PSK module as binary information, according to the input different gray codes, different I-path signals and Q-path signals are multiplied by the sine and cosine forms of residual carriers (namely signals S1 to be calibrated) respectively, then two paths of multipliers are added to obtain a final calibration signal QPSK (namely calibrated signal QPSK _ Single), at the moment, the QPSK _ Single and S2 have the same frequency and the same phase, and the GTX data path is utilized to output the QPSK _ Single and S2.

5. The FPGA-based radio frequency signal quality optimization algorithm of claim 4, wherein the phase difference in the step 3) ranges from [ -pi/2, pi/2 ], and the error of phase solution is less than 0.001%.

6. The FPGA-based radio frequency signal quality optimization algorithm of claim 5, wherein the phase solution module in step 3) comprises an FFT algorithm and a Cordic algorithm, and the process specifically comprises: firstly, inputting time domain data of two paths of signals S1 and S2 into a two-channel Fast Fourier Transform (FFT) algorithm module, simultaneously carrying out FFT transformation on the two paths of signals by the two channels, solving frequency domain data of the two paths of signals, and solving the square sum of a real part and an imaginary part of the frequency domain data so as to solve amplitude spectra of the two paths of signals; then inputting the amplitude spectrums of the two paths of signals into a maximum value searching module so as to obtain the maximum value of the amplitude spectrums and the corresponding index number; then, the real part and the imaginary part of the frequency domain data corresponding to the maximum value of the amplitude spectrum are taken and input into a Cordic algorithm module, and the arctangent values of the input real part and the imaginary part are solved in a vector mode of a circumferential coordinate system by utilizing a Cordic algorithm, so that the initial phases theta1 and theta2 of the two paths of radio frequency signals are obtained; and finally, the phase difference theta _ diff of the two paths of radio frequency signals is obtained by carrying out difference on the two initial phases.

7. The FPGA-based radio frequency signal quality optimization algorithm of claim 6, wherein the two-channel Fast Fourier Transform (FFT) algorithm module in the step 3) adopts a radix-2 butterfly FFT algorithm; the specific process is as follows: in the fast Fourier transform, a time extraction FFT algorithm (DIT) is used, an input sequence x (N) is divided into two groups according to the parity of N, namely, the transformation process of DFT transformation is carried out on a sequence length N point x (N), and the DFT transformation can be equivalently carried out on two sequence length N/2 points;

and every two points in two sequence length N/2 points can calculate two point values with the interval of N/2 in the DFT of the sequence length N point, and the calculation form is called butterfly operation, namely:

A'＝A+BW (1)

B'＝A-BW (2)。

8. the FPGA-based radio frequency signal quality optimization algorithm of claim 7, wherein a ping-pong structure memory is used for processing access of internal butterfly transformation intermediate data of each stage in the FFT operation process of the step 3); two groups of RAM memories with the same size are respectively used for reading data in the first-stage butterfly transformation and writing operation results, and each group of RAM memories is two; storing a real part cosine value and an imaginary part sine value of a twiddle factor required by N-point FFT conversion into a ROM, wherein for an N-point input sequence, N/2 twiddle factor values are required by the system FFT conversion, the specification of the twiddle factor ROM is 16bit N/2, and each data word is 16bits; the front 8bits of the data unit stores a real part cosine value, and the rear 8bits of the data unit stores an imaginary part sine value.

9. The FPGA-based rf signal quality optimization algorithm of claim 8, wherein only cos values of N/4+1 twiddle factors are stored in said step 3) using an address mapping function.

10. The FPGA-based radio frequency signal quality optimization algorithm of claim 9, wherein said step 1) comprises a GTX data path, said GTX data path comprising a transmit data path TX and a receive data path RX; parallel data input from outside firstly enters a high-speed serial transceiver through a TX interface, is subjected to channel coding, phase alignment, polarity control, parallel-serial conversion and pre-emphasis processing, and finally is output to a channel in the form of a high-speed serial differential signal through a TX driver;

and the high-speed serial signals enter the high-speed serial transceiver through an RX buffer, are recovered into parallel data after signal equalization, clock data recovery, serial-to-parallel conversion, polarity control, comma detection, channel decoding and phase alignment, and finally enter the FPGA internal logic through an RX interface.

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