CN115529481B

CN115529481B - Video synchronous display system and method based on fusion signal source and input equipment

Info

Publication number: CN115529481B
Application number: CN202110714746.9A
Authority: CN
Inventors: 冯禹; 胡春波; 许李尚
Original assignee: Hangzhou Hikvision Digital Technology Co Ltd
Current assignee: Hangzhou Hikvision Digital Technology Co Ltd
Priority date: 2021-06-25
Filing date: 2021-06-25
Publication date: 2024-05-03
Anticipated expiration: 2041-06-25
Also published as: CN115529481A

Abstract

The embodiment of the application provides a video synchronous display system, a method and input equipment based on a fusion signal source, wherein the system comprises a plurality of input equipment and a plurality of display screens of a plurality of output equipment, one input equipment is at least connected with one output equipment, one output equipment is connected with one display screen, and the input equipment, the output equipment and the output equipment are connected through network communication. The input device acquires a first scheduling clock and a first time difference when the video image blocks are acquired, calculates a first PHY clock corresponding to the acquired video image blocks according to the first scheduling clock and the first time difference, converts a second PHY clock when interrupt triggering according to the first PHY clock and clock conversion parameters, and ensures that the video image blocks fed into the input device at the same time are clocked with the same second PHY clock, thereby ensuring the synchronization of output pictures of all the output devices.

Description

Video synchronous display system and method based on fusion signal source and input equipment

Technical Field

The present application relates to the field of video display technologies, and in particular, to a system, a method, and an input device for video synchronous display based on a fused signal source.

Background

In video display systems, particularly in high-definition video display systems, it is often necessary to enlarge and then play video images in order to better show the detailed effects of the video images. Because the size and the resolution of a single display screen are limited, the practical requirement cannot be met, and the large-screen splicing technology splices a plurality of display screens into a whole large screen, so that the size and the resolution of the screen are improved by times. And the spliced large screen is used for playing the video, the video image is amplified, and the display of the detail effect is clearer.

The video display system at present is mainly divided into a video display system based on a single signal source and a video display system based on a fusion signal source, wherein the video play flow under the video display system based on the fusion signal source is shown as a figure 1, the video display system comprises a signal source, a plurality of input devices, a plurality of output devices and display screens respectively connected with the output devices, a video card in the signal source splits a video image into M x N blocks (corresponding to 1 x 2 blocks in figure 1) by utilizing a relevant fusion technology (for example, a NVIDIA video card utilizes a Mosaic technology, an AMD video card utilizes a EYEFINITY technology and the like), and sends part of pictures of each block of the video image to M x N input devices through M x N video interfaces respectively, and then each output device outputs part of pictures to the display screens respectively connected with the output devices for splicing display.

The large screen is formed by splicing a plurality of display screens, that is, video images displayed on the large screen are spliced by each part of pictures displayed on each display screen, so that the pictures output by different output devices are required to be ensured to have synchronism, otherwise, the video images displayed on the large screen are displayed in disorder, and the display effect of the video images is seriously affected.

Disclosure of Invention

The embodiment of the application aims to provide a video synchronous display system, a method and input equipment based on a fusion signal source, so as to ensure the synchronization of pictures output by each output equipment in large-screen video display based on the fusion signal source. The specific technical scheme is as follows:

In a first aspect, an embodiment of the present application provides a video synchronization display system based on a fusion signal source, where the system includes: a plurality of input devices, a plurality of output devices and a plurality of display screens, wherein one input device is at least connected with one output device, and one output device is connected with one display screen;

The input device is configured to obtain a first time difference and a first scheduling clock when a video image block is acquired, where the first time difference is: the time difference between the port physical layer PHY clock and the scheduling clock when the input device receives the interrupt signal; determining a first PHY clock corresponding to the video image block acquired according to the first scheduling clock and the first time difference; according to the first PHY clock time Zhong Huansuan parameters, converting a second PHY clock when interrupt triggering is performed, wherein the clock conversion parameters are calculated by a main input device and distributed to non-main input devices; carrying the second PHY clock into each divided picture and sending the divided picture to each connected output device, wherein the divided picture is obtained by dividing the video image block;

The output device is used for receiving the split pictures sent by the connected input device; before outputting the split picture to the connected display screen, acquiring a current third PHY clock, reading a second PHY clock carried in the split picture, determining a second time difference between the third PHY clock and the second PHY clock, and outputting the split picture to the connected display screen under the condition that the second time difference is a preset standard time difference.

In a second aspect, an embodiment of the present application provides a video synchronization display method based on a fusion signal source, which is applied to a video synchronization display system, where the system includes: a plurality of input devices, a plurality of output devices and a plurality of display screens, wherein one input device is at least connected with one output device, and one output device is connected with one display screen; the method comprises the following steps:

The input device obtains a first time difference and a first scheduling clock when a video image block is acquired, wherein the first time difference is as follows: the time difference between the PHY clock and the scheduling clock when the input device receives the interrupt trigger; determining a first PHY clock corresponding to the video image block acquired according to the first scheduling clock and the first time difference; according to the first PHY clock time Zhong Huansuan parameters, converting a second PHY clock when interrupt triggering is performed, wherein the clock conversion parameters are calculated by a main input device and distributed to non-main input devices; carrying the second PHY clock into each divided picture and sending the divided picture to each connected output device, wherein the divided picture is obtained by dividing the video image block;

The output equipment receives the split pictures sent by the connected input equipment; before outputting the split picture to the connected display screen, acquiring a current third PHY clock, reading a second PHY clock carried in the split picture, determining a second time difference between the third PHY clock and the second PHY clock, and outputting the split picture to the connected display screen under the condition that the second time difference is a preset standard time difference.

In a third aspect, an embodiment of the present application provides a video synchronization display method based on a fusion signal source, which is applied to an input device in a video synchronization display system; the method comprises the following steps:

acquiring a first time difference and a first scheduling clock when a video image block is acquired, wherein the first time difference is as follows: the time difference between the PHY clock and the scheduling clock when the input device receives the interrupt trigger;

Determining a first PHY clock corresponding to the video image block acquired according to the first scheduling clock and the first time difference;

according to the first PHY clock time Zhong Huansuan parameters, converting a second PHY clock when interrupt triggering is performed, wherein the clock conversion parameters are calculated by a main input device and distributed to non-main input devices;

and carrying the second PHY clock to each divided picture and sending the second PHY clock to each connected output device so that each output device obtains a current third PHY clock before outputting the divided pictures to a connected display screen, determining a second time difference between the third PHY clock and the second PHY clock, and outputting the divided pictures to the connected display screen under the condition that the second time difference is a preset standard time difference, wherein the divided pictures are obtained by dividing the video image blocks.

In a fourth aspect, an embodiment of the present application provides a video synchronization display apparatus based on a fusion signal source, which is applied to an input device in a video synchronization display system; the device comprises: the system comprises a clock management module, a video acquisition module and a video output module;

The clock management module is used for acquiring a PHY clock and a scheduling clock when interrupt trigger is received, and calculating a first time difference between the PHY clock and the scheduling clock;

the video acquisition module is used for acquiring a first scheduling clock when the input equipment acquires the video image block, and sending the first scheduling clock to the clock management module;

The clock management module is further configured to determine a first PHY clock corresponding to when the video image block is acquired according to the first schedule clock and the first time difference; according to the first PHY clock time Zhong Huansuan parameters, converting a second PHY clock when interrupt triggering is performed, wherein the clock conversion parameters are calculated by a main input device and distributed to non-main input devices;

The video output module is configured to obtain the second PHY clock from the clock management module, carry the second PHY clock to each split picture, and send the second PHY clock to each connected output device, so that each output device obtains a current third PHY clock before outputting the split picture to a connected display screen, determine a second time difference between the third PHY clock and the second PHY clock, and output the split picture to the connected display screen when the second time difference is a preset standard time difference, where the split picture is obtained by splitting the video image block.

In a fifth aspect, an embodiment of the present application provides an input device including a processor and a memory;

a memory for storing a computer program;

and a processor, configured to implement the method provided in the third aspect of the embodiment of the present application when executing the computer program stored in the memory.

In a sixth aspect, embodiments of the present application provide a machine-readable storage medium having stored thereon a computer program which, when executed by a processor, implements a method provided by the third aspect of embodiments of the present application.

In a seventh aspect, embodiments of the present application also provide a computer program product comprising instructions which, when run on a computer, cause the computer to perform the method provided by the third aspect of the embodiments of the present application.

The embodiment of the application provides a video synchronous display system, a method and an input device based on a fusion signal source, wherein the system comprises a plurality of input devices, a plurality of output devices and a plurality of display screens, wherein one input device is at least connected with one output device, and one output device is connected with one display screen; the input device is used for acquiring a first time difference and a first scheduling clock when the video image block is acquired, wherein the first time difference is as follows: the method comprises the steps that when the input equipment receives an interrupt signal, the time difference between a port physical layer PHY clock and a scheduling clock is generated; determining a first PHY clock corresponding to the video image block acquired according to the first scheduling clock and the first time difference; according to the first PHY clock and clock conversion parameters, converting a second PHY clock when interrupt triggering is performed, wherein the clock conversion parameters are calculated by the main input equipment and distributed to all non-main input equipment; carrying a second PHY clock into each divided picture and sending the divided pictures to each connected output device, wherein the divided pictures are obtained by dividing video image blocks; the output device is used for receiving the split pictures sent by the connected input device; before outputting the split picture to the connected display screen, acquiring a current third PHY clock, reading a second PHY clock carried in the split picture, determining a second time difference between the third PHY clock and the second PHY clock, and outputting the split picture to the connected display screen under the condition that the second time difference is a preset standard time difference.

The network communication between the main input device and the non-main input devices is utilized, the main input device calculates clock conversion parameters and distributes the clock conversion parameters to the non-main input devices, so that all the input devices can convert a first dispatching clock into a second PHY clock according to the unified clock conversion parameters, video image blocks sent into the input devices at the same time are ensured to be marked with the same second PHY clock, the second PHY clocks of the divided pictures received by the output devices are the same, and then the divided pictures are output to a connected display screen according to the second time difference between a third PHY clock and the second PHY clock before the divided pictures are output, and the synchronization of the output pictures of the output devices is ensured under the condition that the second time difference is a preset standard time difference.

Drawings

In order to more clearly illustrate the embodiments of the application or the technical solutions in the prior art, the drawings that are necessary for the description of the embodiments or the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the application and that other embodiments may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of a video playback flow under a prior art video display system based on a converged signal source;

FIG. 2a is a schematic diagram of a video playing process in a video display system based on a single signal source in the prior art;

FIG. 2b is a schematic diagram of a video playback process in another prior art video display system based on a single source;

FIG. 3 is a flow chart of a video synchronization method in a prior art single source based video display system;

fig. 4 is a schematic structural diagram of a video synchronization display system based on a fusion signal source according to an embodiment of the present application;

FIG. 5 is a timing diagram of a clock converted by an input device according to an embodiment of the present application;

FIG. 6 is a schematic diagram of phase change under conventional clock scaling rules of the prior art;

FIG. 7 is a schematic diagram of phase change according to clock scaling rules according to an embodiment of the present application;

FIG. 8 is a flow chart of a video synchronization display method based on a fusion signal source applied to a video synchronization display system according to an embodiment of the application;

FIG. 9 is a flowchart of a video synchronization display method based on a fusion signal source applied to a video synchronization display system according to another embodiment of the present application;

Fig. 10 is a flowchart of a video synchronization display method based on a fusion signal source applied to an input device according to an embodiment of the present application;

fig. 11 is a schematic structural diagram of a video synchronization display device based on a fusion signal source according to an embodiment of the present application;

Fig. 12 is a schematic structural diagram of an input device according to an embodiment of the present application.

Detailed Description

The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. Based on the embodiments of the present application, all other embodiments obtained by the person skilled in the art based on the present application are included in the scope of protection of the present application.

First, terms in the present application will be explained:

And the spelling controller: the splice controller is equipment for realizing video splice control, and is responsible for ensuring that each screen displays a segmented block of a corresponding video and ensuring display synchronism among different screens.

Video stitching: the multiple screens are spliced into a large screen, so that the video is displayed on the large screen, and the large screen is equivalent to one screen for a user.

Ultrahigh-fraction fusion output: the multi-output port display card on the ultrahigh-resolution server divides a desktop image into a plurality of blocks by utilizing a related fusion technology and simultaneously sends the blocks to a plurality of output ports for outputting, thereby realizing ultrahigh-resolution desktop image output.

Sched_clock: the System running time is represented, and after the video acquisition is completed, a System on Chip (SoC Chip) uses a scheduling timestamp of the acquisition time as a frame timestamp.

PHY (Port PHYSICAL LAYER ) clock: and each submodule of the splice controller completes clock synchronization of the PHY chip by an IEEE1588 synchronization protocol, and each submodule after synchronization has a unified PHY clock.

CPLD (Complex Programmable Logic Device ) PHY timestamp: the CPLD is responsible for generating interrupt signals with certain frequency, and each interrupt signal triggers each sub-module of the spelling controller to acquire and store the PHY clock at the interrupt moment for subsequent input and output synchronization.

As shown in fig. 2a and fig. 2b, the video playing flow under the current video display system based on a single signal source may include, for a locally displayed scene, a local signal source, an input device, a plurality of output devices, and display screens respectively connected to the respective output devices, where in an example, one output device is connected to one display screen, and the plurality of display screens form a spliced screen; the local signal source sends the video image to the input device through the video interface; for any frame of image in the video image, the input device divides the frame of image into n divided blocks, wherein n is the number of the output devices, the n divided blocks are spliced into a complete image of the frame, the n divided blocks are respectively sent to the n output devices by the input device, and each output device respectively displays the divided blocks received by the output device on a display screen connected with the output device, so that the complete image of the frame can be displayed on the spliced screen. In one example, the input device and the plurality of output devices may be separate devices; in one example, the input device and the plurality of output devices are each sub-modules in the controller.

For a scene displayed by a network, the video display system can comprise a network signal source, a current converting device, a plurality of output devices and display screens respectively connected with the output devices; the network signal source sends the video image to the diversion equipment through the video interface; for any frame of image in the video image, dividing the frame of image into n dividing blocks by the current-transferring device, wherein n is the number of output devices, the n dividing blocks are spliced into a complete image of the frame, the n dividing blocks are respectively sent to the n output devices by the current-transferring device, and each output device displays the dividing blocks received by the output device on a display screen connected with the output device, so that the complete image of the frame can be displayed on the spliced screen. In one example, the diversion device and the plurality of output devices may be separate devices; in one example, the diversion device and the plurality of output devices are each sub-modules in the splice controller.

To synchronously display the complete images on the spliced screen, the synchronicity of the output pictures of different output devices needs to be ensured, otherwise, the video images displayed on the large screen are displayed in disorder.

In a related video display system based on a single signal source, the flow of a video synchronization scheme is shown in fig. 3, and network exchange is performed between an input device and an output device and between the output devices, namely, synchronization of a PHY (Port PHYSICAL LAYER ) clock is completed through an IEEE1588 protocol, which is also called PTP (Precision Time Protocol ), wherein the PHY clock refers to clock synchronization of PHY chips by each device through the IEEE1588 synchronization protocol, and each device after synchronization has a unified PHY clock; the CPLD (Complex Programmable Logic Device ) is responsible for distributing interrupt signals (the transmission frequency of the interrupt signals is consistent with the input and output frequency) to each input device and each output device, and is used for triggering the input device and the output device to acquire the PHY clock, and in one example, each input device and each output device receive the interrupt signals from the same CPLD; in one example, each input device and each output device respectively correspond to a CPLD, the corresponding CPLDs between different input devices, between different output devices and between different input devices and output devices are different, and interrupt signals between the CPLDs are in the same frequency and the same direction. In one example, the PHY clock may be obtained from a clock chip of the device; the clock management module is responsible for managing the acquired PHY clock.

After the input device completes video image acquisition, the current latest PHY clock T1 is acquired from the clock management module, the clock is carried in the video coding and code stream packaging stages, and then all the divided pictures of the video image are distributed to all the output devices through network exchange. The output device obtains the current latest PHY clock T2 from the clock management module before finishing code stream unpacking and video decoding and preparing the output split pictures, and judges whether T2-T1 is equal to delta T, wherein delta T is an empirical value estimated according to the delay from input encoding to decoding and outputting the whole link, is an integral multiple of a frame interval, for example, delta T is an integral multiple of 16.6ms when the frame rate is 60Hz, and is equal to the output split pictures, thereby realizing the synchronization of the output split pictures of each output device.

On the basis of a video display system based on a single signal source, in order to ensure the synchronization of the pictures output by each output device in large-screen video display based on a fusion signal source, the embodiment of the application provides a video synchronization display system based on the fusion signal source, a method and input devices.

As shown in fig. 4, the video synchronization display system includes a plurality of input devices 410, a plurality of output devices 420, and display screens 430 respectively connected to the respective output devices 420, in one example, the output devices 420 are in one-to-one correspondence with the display screens 430, i.e. one output device is uniquely connected to one display screen; the input devices 410, the output devices 420, and the input devices 410 and the output devices 420 are connected by network communication.

An input device 410, configured to obtain a first time difference and a first scheduling clock when the video image block is acquired, where the first time difference is: the time difference between the PHY clock and the schedule clock when the input device 410 receives the interrupt signal; determining a first PHY clock corresponding to the video image block acquired according to the first scheduling clock and the first time difference; according to the first PHY clock and clock conversion parameters, converting a second PHY clock when interrupt triggering is performed, wherein the clock conversion parameters are calculated by the main input equipment and distributed to all non-main input equipment; carrying the second PHY clock into each divided picture, wherein the divided picture is obtained by dividing a video image block, and sending the second PHY clock to each connected output device 420; the first scheduling clock is a frame time stamp of the video image block, i.e. a scheduling time stamp when the video image block was acquired.

An output device 420 for receiving the split picture transmitted by the connected input device; before outputting the split picture to the connected display screen 430, the output device 420 obtains the current third PHY clock, reads the second PHY clock carried in the split picture, determines a second time difference between the third PHY clock and the second PHY clock, and outputs the split picture to the connected display screen 430 when the second time difference is a preset standard time difference.

The scheduling clock represents the running time of the system, and after the video acquisition chip (typically, an SOC chip) completes video acquisition, the scheduling clock at the acquisition time is used as a time stamp of a frame of video image.

For each input device, a first schedule clock for the acquired video image block may be acquired when the video image block is acquired, that is, the current run time of the input device when the input device acquires the video image block. Of course, generally, the first schedule clock when each input device captures a video image block should be the same for different image blocks of the same video image, however, due to the influence of capturing performance, transmission delay, and the like, there may be a difference in the first schedule clock when each input device captures a video image block.

In order to cope with the above problem, in one implementation manner of the embodiment of the present application, the input device 410 obtains a first scheduling clock when a video image block is acquired, and specifically may receive a video image block sent by a signal source for the input device 410, where the video image block carries the first scheduling clock of the video image block sent by the signal source; the first schedule clock is read from the video image block.

The video image blocks are obtained after the video image is segmented by the signal source, the clocks of the signal source for sending the video image blocks to the input devices are the same, and the clock of the input devices for collecting the video image blocks is not greatly different from the clock of the signal source for sending the video image blocks, so that in order to ensure that the first scheduling clocks obtained by the input devices are the same, the clocks of the signal source for sending the video image blocks can be carried in the video image blocks as the first scheduling clocks, and the first scheduling clocks can be directly read from the video image blocks after the input devices receive the video image blocks.

The first time difference refers to the time difference between the PHY clock and the scheduling clock when the input device receives the interrupt signal, the interrupt signal may be generated by a special hardware device (for example, a CPLD), and the CPLD generates the interrupt signal at a certain frequency, which is also called interrupt triggering; when the CPLD is triggered by interrupt, a bottom layer driver of the input device can acquire a PHY clock and a scheduling clock at the current moment and buffer the PHY clock and the scheduling clock, then an application layer of the input device reads the PHY clock and the scheduling clock from the bottom layer driver, and the application layer calculates the time difference between the PHY clock and the scheduling clock, namely, the first time difference, and records the time difference for subsequent clock conversion.

The input device can determine the corresponding first PHY clock when the video image block is acquired according to the acquired first scheduling clock and the first time difference, and the first PHY clock=the first scheduling clock+the first time difference.

In one example, according to the first PHY clock, a second PHY clock at the time of interrupt triggering is scaled using a preset clock scaling rule, including: subtracting the clock conversion parameter from the first PHY clock, and subtracting one half of the video image block acquisition period to obtain an intermediate conversion clock; and selecting a clock which is larger than the intermediate conversion clock and has the smallest difference with the intermediate conversion clock from the interrupt trigger clock sequence as a second PHY clock in interrupt trigger, wherein the interrupt trigger clock sequence comprises all PHY clocks in periodic interrupt trigger.

In one example, the input device includes a clock management module and a video acquisition module, and the clock management module may be configured to manage the acquired clock, that is, when the interrupt is triggered, the clock management module may not only acquire the PHY clock at the current time from the interrupt processing function, insert the PHY clock into the queue, but also acquire the schedule clock at the current time from the interrupt processing function, and calculate the time difference Δt between the PHY clock and the schedule clock, as shown in fig. 5. The video image block acquired by the video acquisition module carries a first scheduling clock, the video acquisition module sends the first scheduling clock into the clock management module, the clock management module converts the first scheduling clock according to the calculated time difference delta T to obtain a corresponding first PHY clock T2 (T2 = T1+ delta T) when the video image block is acquired, and then converts a second PHY clock T3 when the video image block is triggered by interruption according to the first PHY clock T2 by using a preset clock conversion rule.

Fig. 6 is a conventional clock scaling rule of the related art, and the corresponding PHY clock when capturing video image blocks corresponds to a PHY clock that is smaller than itself and has the smallest difference from itself. However, since the frame rate of the video image block acquisition and the frequency generated by the interruption are not the same frequency, as the system is continuously operated, the phase between the video image block acquisition and the interruption is continuously changed, and the change of the phase brings about the critical situation in fig. 6: because of the subtle difference among the input devices, when the acquisition of the video image blocks is close to and coincident with the interruption, PHY clock differences of the video image blocks acquired at the close to unified moment when the interruption triggers corresponding to the different input devices can possibly occur for one frame according to the clock conversion rule.

In order to solve the critical situation caused by the phase change and avoid the second PHY clocks of different input devices from being different, in the embodiment of the present application, the concept of the master input device is introduced, in one example, the clock scaling rule of each input device is the same, and the clock scaling rule is a rule that scales based on a clock scaling parameter, where the clock scaling parameter is calculated by the master input device and distributed to each non-master input device. By utilizing network communication between the main input device and the non-main input devices, the main input device calculates clock conversion parameters and distributes the clock conversion parameters to the non-main input devices, so that all the input devices can finish conversion from a first dispatching clock to a second PHY clock according to a unified clock conversion rule, and video image blocks sent to the input devices at the same time are ensured to be clocked with the same second PHY clock.

In one implementation of an embodiment of the present application, the plurality of input devices includes a master input device.

A master input device, specifically configured to determine, for each video image block within a specified history period, a first clock (PHY clock when the master input device collects the video image block) and a second clock (a third time difference between the PHY clock and the PHY clock, i.e., the first clock, the PHY clock when the closest interrupt triggers); determining an average value of third time differences corresponding to each video image block in a specified historical period to obtain a clock conversion parameter; subtracting the clock conversion parameter from the first PHY clock, and subtracting one half of the video image block acquisition period to obtain an intermediate conversion clock; and selecting a clock which is larger than the intermediate conversion clock and has the smallest difference with the intermediate conversion clock from the interrupt trigger clock sequence as a second PHY clock in interrupt trigger, wherein the interrupt trigger clock sequence comprises all PHY clocks in periodic interrupt trigger. The specified history period may be set custom according to the actual situation, for example, 30 seconds, 1 minute, 3 minutes, 10 minutes, or half an hour before the current time.

One of the input devices is selected, in one example, the selection of the master input device may be random, and in one example, the most computationally powerful or least loaded input device may be selected as the master input device. The principle of clock conversion of the master input device is shown in fig. 7, and for each video image block in a specified history period, a third time difference Diff between a corresponding PHY clock T _VI when the master input device collects the video image block and a PHY clock T _CPLD when interrupt closest to the PHY clock is triggered is calculated; and calculating an average value of a third time difference corresponding to each video image block in a specified historical period, as a clock scaling parameter, for example, calculating a Diff average value D of nearly 100 frames of video images in the historical period, and when T _VI is converted to a second PHY clock, firstly converting the T _VI'＝T_VI -D-field time according to D, wherein the field time is half of a video image block acquisition period, for example, the video frame rate is 60Hz, the field time is 8.3ms, so that the phase of TVI' after conversion and the second PHY clock is maintained at the field, then determining the second PHY clock when interrupt triggering is carried out by taking a clock which is larger than an intermediate conversion clock and has the smallest difference value with the intermediate conversion clock as a rule in an interrupt triggering clock sequence, and the interrupt triggering clock sequence comprises each PHY clock when periodic interrupt triggering.

In one implementation manner of the embodiment of the present application, the input device further includes a non-primary input device, where other input devices in each input device except the primary input device are non-primary input devices;

The non-main input device is specifically used for receiving clock conversion parameters sent by the main input device; subtracting the clock conversion parameter from the first PHY clock, and subtracting one half of the video image block acquisition period to obtain an intermediate conversion clock; and selecting a clock which is larger than the intermediate conversion clock and has the smallest difference with the intermediate conversion clock from the interrupt trigger clock sequence as a second PHY clock in interrupt trigger, wherein the interrupt trigger clock sequence comprises all PHY clocks in periodic interrupt trigger.

The master input device may send the counted clock scaling parameters to other non-master input devices in a network transmission manner, and the non-master input device may perform clock scaling in the same manner as the master input device.

In the embodiment of the application, the backup of the main input device can be provided, that is, if the current main input device fails, one input device can be selected from other non-main input devices as the main input device to continue the video synchronization scheme of the embodiment of the application.

After converting the second PHY clock, the input device sends the second PHY clock carrying value to each connected output device, and for the same video image, as the second PHY clocks converted by each input device are the same, the output device can perform video synchronization in the same mode as the single signal source, that is, before the input device outputs the divided image to the connected display screen, the input device obtains the current third PHY clock, reads the second PHY clock carried in the divided image, calculates the second time difference between the third PHY clock and the second PHY clock, and outputs the divided image to the connected display screen under the condition that the second time difference is the preset standard time difference.

In an implementation manner of the embodiment of the present application, the output device may be further configured to, if the second time difference is not the standard time difference, wait for a preset duration and output the split picture to the connected display screen if the second time difference is less than the standard time difference, where the preset duration is a duration corresponding to the second time difference; and/or discarding the split picture if the second time difference is greater than the standard time difference.

If the second time difference calculated by the output device is not the standard time difference, the situation that the output split picture is out of sync at the moment is indicated, if the second time difference is smaller than the standard time difference, the current output split picture of the output device is indicated to be somewhat early, the split picture needs to be output to a connected display screen after waiting for the preset time, and if the second time difference is larger than the standard time difference, the current output split picture of the output device is indicated to be late, the requirement of synchronizing with other split pictures can not be met, and the split picture needs to be discarded.

In the embodiment of the application, the video synchronization display system based on the fusion signal source comprises a plurality of input devices, a plurality of output devices and a plurality of display screens, wherein one input device is at least connected with one output device, one output device is connected with one display screen, and the input devices, the output devices and the output devices are connected through network communication. The input device obtains a first time difference and a first scheduling clock when a video image block is acquired, determines a first PHY clock corresponding to the video image block according to the first scheduling clock and the first time difference, converts a second PHY clock when interrupt triggering according to the first PHY clock and clock conversion parameters, carries the second PHY clock to each divided picture to be sent to each connected output device, after the output device receives the divided pictures, obtains a current third PHY clock before outputting the divided pictures to a connected display screen, reads a second PHY clock carried in the divided pictures, determines a second time difference between the third PHY clock and the second PHY clock, and outputs the divided pictures to the connected display screen under the condition that the second time difference is a preset standard time difference.

The network communication between the main input device and the non-main input devices is utilized, the main input device calculates clock conversion parameters and distributes the clock conversion parameters to the non-main input devices, so that all the input devices can finish conversion from a first scheduling clock to a second PHY clock according to the unified clock conversion parameters, video image blocks sent into the input devices at the same time are ensured to be marked with the same second PHY clock, the second PHY clocks of the divided pictures received by the output devices are the same, and then the divided pictures are output to a connected display screen according to the second time difference between a third PHY clock and the second PHY clock before the divided pictures are output, and the synchronization of the output pictures of the output devices is ensured under the condition that the second time difference is a preset standard time difference.

Based on the video synchronous display system based on the fusion signal source provided by the embodiment of the application, the embodiment of the application also provides a video synchronous display method based on the fusion signal source, as shown in fig. 8, and the method comprises the following steps.

S801, the input device acquires a first time difference and a first scheduling clock when the video image block is acquired.

Wherein, the first time difference is: the time difference between the PHY clock and the schedule clock when the input device receives the interrupt trigger.

S802, the input device determines a first PHY clock corresponding to the video image block acquired according to the first scheduling clock and the first time difference.

S803, the input device converts the second PHY clock when the interrupt is triggered according to the first PHY clock and the clock conversion parameter.

Wherein the clock scaling parameters are calculated by the master input device and distributed to the non-master input devices.

S804, the input device carries the second PHY clock to each split picture and sends the second PHY clock to each connected output device.

The segmentation picture is obtained by segmenting a video image block.

S805, before outputting the split picture to the connected display screen, the output device acquires the current third PHY clock and reads the second PHY clock carried in the split picture.

S806, the output device determines a second time difference between the third PHY clock and the second PHY clock.

S807, the output device outputs the split picture to the connected display screen when the second time difference is the preset standard time difference.

By applying the embodiment of the application, the input device acquires the first time difference and the first scheduling clock when the video image block is acquired, calculates the corresponding first PHY clock when the video image block is acquired according to the first scheduling clock and the first time difference, converts the second PHY clock when the interrupt is triggered according to the first PHY clock and clock conversion parameters, carries the second PHY clock to each divided picture and sends the divided picture to each connected output device, the output device acquires the current third PHY clock before outputting the divided picture to the connected display screen after receiving the divided picture, reads the second PHY clock carried in the divided picture, determines the second time difference between the third PHY clock and the second PHY clock, and outputs the divided picture to the connected display screen under the condition that the second time difference is the preset standard time difference. The network communication between the main input device and the non-main input devices is utilized, the main input device calculates clock conversion parameters and distributes the clock conversion parameters to the non-main input devices, so that all the input devices can finish conversion from a first dispatching clock to a second PHY clock according to the unified clock conversion parameters, video image blocks sent into the input devices at the same time are ensured to be marked with the same second PHY clock, thus, the second PHY clocks of the divided pictures received by the output devices are the same, and then the divided pictures are output to a connected display screen according to the second time difference between a third PHY clock and the second PHY clock before the divided pictures are output, and the synchronization of the output pictures of the output devices is ensured under the condition that the second time difference is a preset standard time difference.

In order to cope with the above problem, in an implementation manner of the embodiment of the present application, S801 may specifically be: the input equipment receives a video image block sent by a signal source, wherein the video image block carries a first scheduling clock for the signal source to send the video image block; the first schedule clock is read from the video image block.

The first time difference refers to the time difference between the PHY clock and the scheduling clock when the interrupt trigger is received, some hardware devices (for example, CPLD) are generally in charge of generating interrupt signals with a certain frequency in the input device, when the CPLD interrupt trigger is received, the input device can acquire the PHY clock at the current moment and can also acquire the scheduling clock at the current moment, calculate the first time difference between the PHY clock and the scheduling clock, and record the first time difference for subsequent clock conversion.

According to the acquired first scheduling clock and first time difference, the input device can calculate a corresponding first PHY clock when the video image block is acquired, the first PHY clock=the first scheduling clock+the first time difference, and as the video image block acquisition is completed from the fusion output of the signal source to the input device, the time consumption of the process has slight difference in each input device, the time consumption is uniformly mapped to the PHY clock when the interrupt is triggered, and the difference can be removed, so that the second PHY clock when the interrupt is triggered can be converted by utilizing a preset clock conversion rule according to the first PHY clock.

In one implementation of the embodiment of the present application, after S806, the method may further include: if the second time difference is not the standard time difference, outputting the split picture to a connected display screen after waiting for a preset time length under the condition that the second time difference is smaller than the standard time difference, wherein the preset time length is the time length corresponding to the second time difference; and/or discarding the split picture if the second time difference is greater than the standard time difference.

Based on the embodiment shown in fig. 8, the embodiment of the application also provides a video synchronization display method based on the fusion signal source, as shown in fig. 9, which comprises the following steps.

S901, a main input device acquires a first time difference and a first scheduling clock when a video image block is acquired.

S901', the non-master input device obtains a first time difference and a first scheduling clock when the video image block is collected.

Wherein, the first time difference is: the time difference between the PHY clock and the schedule clock when the input device itself receives the interrupt trigger.

S902, the main input device determines a first PHY clock corresponding to the video image block acquired according to the first scheduling clock and the first time difference.

And S902', the non-main input device determines a first PHY clock corresponding to the video image block acquired according to the first scheduling clock and the first time difference.

S903, the main input device calculates a third time difference between a PHY clock corresponding to the acquired video image block and a PHY clock closest to the PHY clock when interrupt triggering is performed for each video image block in the appointed historical period, and determines an average value of the third time differences corresponding to each video image block in the appointed historical period to obtain a clock conversion parameter.

S904, the master input device distributes the calculated clock scaling parameters to the non-master input devices.

S905, subtracting a clock conversion parameter from the first PHY clock by the main input device, and subtracting one half of the acquisition period of the video image block to obtain an intermediate conversion clock; from the interrupt trigger clock sequence, a clock that is larger than the intermediate conversion clock and has the smallest difference from the intermediate conversion clock is selected as the second PHY clock at the time of interrupt trigger.

S905', subtracting a clock conversion parameter from the first PHY clock by the non-main input device, and subtracting half of the acquisition period of the video image block to obtain an intermediate conversion clock; from the interrupt trigger clock sequence, a clock that is larger than the intermediate conversion clock and has the smallest difference from the intermediate conversion clock is selected as the second PHY clock at the time of interrupt trigger.

The interrupt trigger clock sequence comprises each PHY clock in periodic interrupt trigger.

S906, the master input device carries the second PHY clock into each split picture and sends it to each connected output device.

S906', the non-master input device carries the second PHY clock into each split picture and sends it to each connected output device.

The segmentation picture is obtained by segmenting a video image block.

S907, before outputting the split picture to the connected display screen, the output device obtains the current third PHY clock and reads the second PHY clock carried in the split picture.

S908, the output device calculates a second time difference between the third PHY clock and the second PHY clock.

And S909, outputting the split picture to the connected display screen by the output device under the condition that the second time difference is a preset standard time difference.

In order to solve the critical situation caused by the phase change and avoid the second PHY clocks of different input devices from being different, in the embodiment of the present application, the concept of the master input device is introduced, and specifically, the clock conversion parameter is calculated by the master input device and distributed to each non-master input device. By utilizing network communication between the main input device and the non-main input devices, the main input device calculates clock conversion parameters and distributes the clock conversion parameters to the non-main input devices, so that all the input devices can finish conversion from a first dispatching clock to a second PHY clock according to the unified clock conversion parameters, and the video image blocks fed into the input devices at the same time are ensured to be clocked with the same second PHY clock.

The embodiment of the application also provides a video synchronous display method based on the fusion signal source, which is applied to the input equipment in the video synchronous display system, as shown in fig. 10, and comprises the following steps.

S1001, acquiring a first time difference and a first scheduling clock when a video image block is acquired, wherein the first time difference is: the input device receives the time difference between the PHY clock and the schedule clock when the interrupt trigger is received.

S1002, determining a first PHY clock corresponding to the video image block acquired according to the first scheduling clock and the first time difference.

S1003, converting a second PHY clock when interrupt triggering according to the first PHY clock and clock conversion parameters, wherein the clock conversion parameters are calculated by the main input device and distributed to all non-main input devices.

S1004, carrying the second PHY clock to each divided picture and sending the second PHY clock to each connected output device, so that each output device obtains the current third PHY clock before outputting the divided pictures to the connected display screen, determining a second time difference between the third PHY clock and the second PHY clock, and outputting the divided pictures to the connected display screen under the condition that the second time difference is a preset standard time difference, wherein the divided pictures are obtained by dividing video image blocks.

By using the network communication between the main input device and the non-main input devices, the main input device calculates the clock conversion parameters and distributes the clock conversion parameters to the non-main input devices, so that all the input devices can convert the first scheduling clock into the second PHY clock according to the unified clock conversion parameters, video image blocks sent to the input devices at the same time are ensured to be marked with the same second PHY clock, the second PHY clocks of the divided pictures received by the output devices are the same, and then the divided pictures are output to the connected display screen according to the second time difference between the third PHY clock and the second PHY clock before the divided pictures are output, and the synchronization of the output pictures of the output devices is ensured under the condition that the second time difference is the preset standard time difference.

In order to cope with the above problem, in an implementation manner of the embodiment of the present application, S1001 may specifically be: the input equipment receives a video image block sent by a signal source, wherein the video image block carries a first scheduling clock for the signal source to send the video image block; the first schedule clock is read from the video image block.

In order to solve the critical situation caused by the phase change and avoid the second PHY clocks of different input devices from being different, in the embodiment of the present application, the concept of the master input device is introduced, specifically, the clock scaling rule of each input device is the same, the clock scaling rule is a scaling rule based on clock scaling parameters, and the clock scaling parameters are calculated by the master input device and distributed to each non-master input device. By utilizing network communication between the main input device and the non-main input devices, the main input device calculates clock conversion parameters and distributes the clock conversion parameters to the non-main input devices, so that all the input devices can finish conversion from a first dispatching clock to a second PHY clock according to a unified clock conversion rule, and video image blocks sent to the input devices at the same time are ensured to be clocked with the same second PHY clock.

In one implementation manner of the embodiment of the present application, the input device is a main input device.

Prior to S1003, the method may further include: for each video image block in the appointed history period, calculating a third time difference between a corresponding PHY clock when the video image block is acquired and a PHY clock when interrupt trigger closest to the PHY clock is generated; and determining an average value of the third time differences corresponding to each video image block in the appointed historical period to obtain a clock conversion parameter.

S1003 may specifically be: the main input device subtracts the clock conversion parameter from the first PHY clock and subtracts one half of the acquisition period of the video image block to obtain an intermediate conversion clock; and selecting a clock which is larger than the intermediate conversion clock and has the smallest difference with the intermediate conversion clock from the interrupt trigger clock sequence as a second PHY clock in interrupt trigger, wherein the interrupt trigger clock sequence comprises all PHY clocks in periodic interrupt trigger.

Selecting a master input device from the input devices, wherein the selection of the master input device can be random, and the master input device calculates a third time difference Diff between a corresponding PHY clock T _VI when the video image block is acquired and a PHY clock T _CPLD when interrupt trigger closest to the PHY clock is triggered for each video image block in a history period; the average value of the third time difference corresponding to each video image block is calculated, for example, as a clock scaling parameter, the Diff average value D of the video image of nearly 100 frames in the historical period can be calculated, when scaling is performed from T _VI to the second PHY clock, scaling is performed according to D to obtain the T _VI'＝T_VI -D-field time, wherein the field time is half of the video image block acquisition period, for example, the video frame rate is 60Hz, the field time is 8.3ms, so that the phase of the TVI' after scaling and the second PHY clock can be ensured to be maintained at the field, then the second PHY clock with the minimum difference value from the intermediate scaling clock is selected as a rule from the interrupt trigger clock sequence, and the interrupt trigger clock sequence comprises each PHY clock with periodic interrupt trigger.

In one implementation of the embodiments of the present application, the input device is a non-primary input device;

prior to S1003, the method may further include: the non-master input device receives the clock scaling parameters sent by the master input device.

S1003 may specifically be: the non-main input device subtracts the clock conversion parameter from the first PHY clock and subtracts one half of the acquisition period of the video image block to obtain an intermediate conversion clock; and selecting a clock which is larger than the intermediate conversion clock and has the smallest difference with the intermediate conversion clock from the interrupt trigger clock sequence as a second PHY clock in interrupt trigger, wherein the interrupt trigger clock sequence comprises all PHY clocks in periodic interrupt trigger.

Corresponding to the embodiment of the method shown in fig. 10, the embodiment of the application provides a video synchronization display device based on a fusion signal source, which is applied to an input device in a video synchronization display system, as shown in fig. 11, and the device comprises: a clock management module 1110, a video acquisition module 1120, and a video output module 1130.

The clock management module 1110 is configured to obtain a PHY clock and a schedule clock when an interrupt trigger is received, and calculate a first time difference between the PHY clock and the schedule clock;

the video acquisition module 1120 is configured to acquire a first scheduling clock when the input device acquires a video image block, and send the first scheduling clock to the clock management module 1110;

The clock management module 1110 is further configured to determine, according to the first scheduling clock and the first time difference, a first PHY clock corresponding to when the video image block is acquired; according to the first PHY clock and clock conversion parameters, converting a second PHY clock when interrupt triggering is performed, wherein the clock conversion parameters are calculated by the main input equipment and distributed to all non-main input equipment;

The video output module 1130 is configured to obtain a second PHY clock from the clock management module 1110, carry the second PHY clock to each split picture and send the second PHY clock to each connected output device, so that each output device obtains a current third PHY clock before outputting the split picture to the connected display screen, determine a second time difference between the third PHY clock and the second PHY clock, and output the split picture to the connected display screen when the second time difference is a preset standard time difference, where the split picture is obtained by splitting a video image block.

Optionally, when the video acquisition module 1120 is configured to acquire the first scheduling clock when the video image block is acquired, the video acquisition module may be specifically configured to receive the video image block sent by the signal source, where the video image block carries the first scheduling clock when the signal source sends the video image block; the first schedule clock is read from the video image block.

Optionally, the input device is a master input device; the apparatus may further include: a statistics calculation module;

The statistics calculation module is used for determining a third time difference between a corresponding PHY clock when the video image block is acquired and a PHY clock when interrupt trigger closest to the PHY clock is performed for each video image block in a specified historical period; determining an average value of third time differences corresponding to each video image block in a specified historical period to obtain a clock conversion parameter;

The clock management module 1110, when converting the second PHY clock when triggering the interrupt according to the first PHY clock and the clock conversion parameter, may specifically be configured to subtract the clock conversion parameter from the first PHY clock and subtract half of the video image block acquisition period to obtain an intermediate conversion clock; and selecting a clock which is larger than the intermediate conversion clock and has the smallest difference with the intermediate conversion clock from the interrupt trigger clock sequence as a second PHY clock in interrupt trigger, wherein the interrupt trigger clock sequence comprises all PHY clocks in periodic interrupt trigger.

Optionally, the input device is a non-master input device; the apparatus may further include: a receiving module;

the receiving module is used for receiving clock conversion parameters sent by the main input equipment;

By applying the embodiment of the application, the clock conversion rule is a rule for conversion based on clock conversion parameters, the network communication between the main input device and the non-main input devices is utilized, the main input device calculates the clock conversion parameters and distributes the clock conversion parameters to the non-main input devices, so that all the input devices can finish conversion from a first scheduling clock to a second PHY clock according to the unified clock conversion rule, video image blocks sent into the input devices at the same time are ensured to be marked with the same second PHY clock, thus the second PHY clocks of the divided pictures received by the output devices are the same, and then the divided pictures are output to the connected display screen according to the condition that the second time difference is a preset standard time difference, thereby ensuring the synchronization of the output pictures of the output devices.

The embodiment of the application also provides an input device, as shown in fig. 12, comprising a processor 1201 and a memory 1202; wherein the memory 1202 is used for storing a computer program; the processor 1201 is configured to implement the above-described video synchronization display method based on the fusion signal source applied to the input device when executing the computer program stored in the memory 1202.

The Memory may include RAM (Random Access Memory ) or NVM (Non-volatile Memory), such as at least one disk Memory. Optionally, the memory may be at least one memory device located remotely from the processor.

The processor may be a general-purpose processor including a CPU (Central Processing Unit ), NP (Network Processor, network processor), and the like; but may also be a DSP (DIGITAL SIGNAL Processing), ASIC (Application SPECIFIC INTEGRATED Circuit), FPGA (Field-Programmable gate array), or other Programmable logic device, discrete gate or transistor logic device, discrete hardware components.

In addition, the embodiment of the application also provides a machine-readable storage medium, wherein a computer program is stored in the machine-readable storage medium, and the computer program realizes the video synchronization display method based on the fusion signal source, which is applied to the input device, when the computer program is executed by a processor.

The embodiment of the application also provides a computer program product containing instructions, which when run on a computer, cause the computer to execute the video synchronization display method applied to the input device and based on the fusion signal source.

In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, produces a flow or function in accordance with embodiments of the present invention, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by a wired (e.g., coaxial cable, fiber optic, DSL (Digital Subscriber Line, digital subscriber line)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that contains an integration of one or more available media. The usable medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a magnetic tape), an optical medium (e.g., a DVD (DIGITAL VERSATILE DISC, digital versatile disk)), or a semiconductor medium (e.g., an SSD (Solid state disk) STATE DISK), or the like.

For embodiments of the video synchronization display apparatus, the input device, the machine-readable storage medium and the computer program product based on the fusion signal source, the description is relatively simple, and the relevant matters are referred to in the description of the embodiments of the method, since the related method content is basically similar to the embodiment of the video synchronization display method based on the fusion signal source applied to the input device.

It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

In this specification, each embodiment is described in a related manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment mainly describes differences from other embodiments.

The foregoing description is only of the preferred embodiments of the present application and is not intended to limit the scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application are included in the protection scope of the present application.

Claims

1. A video synchronization display system based on a fused signal source, the system comprising: a plurality of input devices, a plurality of output devices and a plurality of display screens, wherein one input device is at least connected with one output device, and one output device is connected with one display screen;

The input device is configured to obtain a first time difference and a first scheduling clock when a video image block is acquired, where the first time difference is: the time difference between the port physical layer PHY clock and the scheduling clock when the input device receives the interrupt signal; determining a first PHY clock corresponding to the video image block acquired according to the first scheduling clock and the first time difference, wherein the first PHY clock is the sum of the first scheduling clock and the first time difference; according to the first PHY clock time Zhong Huansuan parameters, converting a second PHY clock when interrupt triggering is performed, wherein the clock conversion parameters are calculated by a main input device and distributed to non-main input devices; carrying the second PHY clock into each divided picture and sending the divided picture to each connected output device, wherein the divided picture is obtained by dividing the video image block;

The output device is used for receiving the split pictures sent by the connected input device; before outputting the split picture to a connected display screen, acquiring a current third PHY clock, reading a second PHY clock carried in the split picture, determining a second time difference between the third PHY clock and the second PHY clock, and outputting the split picture to the connected display screen under the condition that the second time difference is a preset standard time difference;

The plurality of input devices includes a primary input device;

The main input device is specifically configured to determine, for each video image block in a specified history period, a third time difference between a PHY clock corresponding to when the video image block is acquired and a PHY clock at an interrupt trigger closest to the PHY clock; and determining an average value of the third time difference corresponding to each video image block in the appointed historical period to obtain a clock conversion parameter.

2. The system according to claim 1, wherein the input device is configured to receive a video image block sent by a signal source when being used for acquiring a first scheduling clock when a video image block is acquired, where the video image block carries the first scheduling clock when the signal source sends the video image block; the first schedule clock is read from the video image block.

3. The system of claim 1, wherein the master input device subtracts the clock scaling parameter from the first PHY clock and subtracts one half of a video image block acquisition period to obtain an intermediate scaling clock; and selecting a clock which is larger than the intermediate conversion clock and has the smallest difference value with the intermediate conversion clock from an interrupt trigger clock sequence as a second PHY clock in interrupt trigger, wherein the interrupt trigger clock sequence comprises all PHY clocks in periodic interrupt trigger.

4. The system of claim 3, wherein other input devices of the plurality of input devices than the master input device are non-master input devices;

The non-main input device is specifically configured to receive the clock scaling parameter sent by the main input device; subtracting the clock conversion parameter from the first PHY clock, and subtracting one half of the video image block acquisition period to obtain an intermediate conversion clock; and selecting a clock which is larger than the intermediate conversion clock and has the smallest difference value with the intermediate conversion clock from an interrupt trigger clock sequence as a second PHY clock in interrupt trigger, wherein the interrupt trigger clock sequence comprises all PHY clocks in periodic interrupt trigger.

5. The system according to claim 1, wherein the output device is further configured to, when the second time difference is smaller than the standard time difference, wait for a preset time period, and then output the split picture to the connected display screen, where the preset time period is a time period corresponding to the second time difference; and/or discarding the split picture if the second time difference is greater than the standard time difference.

6. The video synchronous display method based on the fusion signal source is characterized by being applied to a video synchronous display system, and the system comprises the following steps: a plurality of input devices, a plurality of output devices and a plurality of display screens, wherein one input device is at least connected with one output device, and one output device is connected with one display screen;

The method comprises the following steps:

The input device obtains a first time difference and a first scheduling clock when a video image block is acquired, wherein the first time difference is as follows: the time difference between the PHY clock and the scheduling clock when the input device receives the interrupt trigger; determining a first PHY clock corresponding to the video image block acquired according to the first scheduling clock and the first time difference, wherein the first PHY clock is the sum of the first scheduling clock and the first time difference; according to the first PHY clock time Zhong Huansuan parameters, converting a second PHY clock when interrupt triggering is performed, wherein the clock conversion parameters are calculated by a main input device and distributed to non-main input devices; carrying the second PHY clock into each divided picture and sending the divided picture to each connected output device, wherein the divided picture is obtained by dividing the video image block;

The output equipment receives the split pictures sent by the connected input equipment; before outputting the split picture to a connected display screen, acquiring a current third PHY clock, reading a second PHY clock carried in the split picture, determining a second time difference between the third PHY clock and the second PHY clock, and outputting the split picture to the connected display screen under the condition that the second time difference is a preset standard time difference;

The plurality of input devices includes a primary input device;

before the step of scaling the second PHY clock at the time of interrupt triggering according to the first PHY clock in time Zhong Huansuan parameter, the method further includes:

The main input device determines, for each video image block in a specified history period, a third time difference between a corresponding PHY clock when the video image block is acquired and a PHY clock at an interrupt trigger closest to the PHY clock; and determining an average value of the third time difference corresponding to each video image block in the appointed historical period to obtain a clock conversion parameter.

7. The method of claim 6, wherein the step of the input device acquiring a first schedule clock at the time the video image block was acquired comprises:

the input equipment receives a video image block sent by a signal source, wherein the video image block carries a first scheduling clock for the signal source to send the video image block; the first schedule clock is read from the video image block.

8. The method of claim 6, wherein the step of providing the first layer comprises,

The step of converting the second PHY clock when the interrupt is triggered by the input device according to the first PHY clock time Zhong Huansuan parameters includes:

The main input device subtracts the clock conversion parameter from the first PHY clock and subtracts one half of the video image block acquisition period to obtain an intermediate conversion clock; and selecting a clock which is larger than the intermediate conversion clock and has the smallest difference value with the intermediate conversion clock from an interrupt trigger clock sequence as a second PHY clock in interrupt trigger, wherein the interrupt trigger clock sequence comprises all PHY clocks in periodic interrupt trigger.

9. The method of claim 8, wherein the other input devices of the plurality of input devices than the master input device are non-master input devices;

Before the step of converting, by the input device, the second PHY clock at the time of interrupt triggering according to the first PHY clock in-time Zhong Huansuan parameter, the method further includes:

the non-main input device receives the clock conversion parameter sent by the main input device;

The non-main input device subtracts the clock conversion parameter from the first PHY clock and subtracts one half of the video image block acquisition period to obtain an intermediate conversion clock; and selecting a clock which is larger than the intermediate conversion clock and has the smallest difference value with the intermediate conversion clock from an interrupt trigger clock sequence as a second PHY clock in interrupt trigger, wherein the interrupt trigger clock sequence comprises all PHY clocks in periodic interrupt trigger.

10. The method of claim 6, wherein after the step of the output device calculating a second time difference between the third PHY clock and the second PHY clock, the method further comprises:

When the second time difference is smaller than the standard time difference, outputting the split picture to a connected display screen after waiting for a preset time, wherein the preset time is the time corresponding to the second time difference; and/or

And discarding the divided picture in the case that the second time difference is larger than the standard time difference.

11. The video synchronous display method based on the fusion signal source is characterized by being applied to input equipment in a video synchronous display system; the method comprises the following steps:

determining a first PHY clock corresponding to the video image block acquired according to the first scheduling clock and the first time difference, wherein the first PHY clock is the sum of the first scheduling clock and the first time difference;

carrying the second PHY clock to each divided picture and sending the second PHY clock to each connected output device so that each output device obtains a current third PHY clock before outputting the divided pictures to a connected display screen, determining a second time difference between the third PHY clock and the second PHY clock, and outputting the divided pictures to the connected display screen under the condition that the second time difference is a preset standard time difference, wherein the divided pictures are obtained by dividing the video image blocks;

The input device is the main input device;

Before the step of converting the second PHY clock at the time of interrupt triggering according to the first PHY clock in-time Zhong Huansuan parameter, the method further includes:

The main input device calculates a third time difference between a corresponding PHY clock and a PHY clock when interrupt trigger closest to the PHY clock is triggered when the video image block is acquired for each video image block in a specified history period;

And determining an average value of the third time differences corresponding to each video image block in the appointed historical period to obtain a clock conversion parameter.

12. The method of claim 11, wherein the step of acquiring a first schedule clock at the time the video image block was acquired comprises:

Receiving a video image block sent by a signal source, wherein the video image block carries a first scheduling clock for the signal source to send the video image block;

the first schedule clock is read from the video image block.

13. The method of claim 11, wherein the step of determining the position of the probe is performed,

The step of converting the second PHY clock when the interrupt is triggered according to the first PHY clock time Zhong Huansuan parameter includes:

The main input device subtracts the clock conversion parameter from the first PHY clock and subtracts one half of the video image block acquisition period to obtain an intermediate conversion clock;

And selecting a clock which is larger than the intermediate conversion clock and has the smallest difference value with the intermediate conversion clock from an interrupt trigger clock sequence as a second PHY clock in interrupt trigger, wherein the interrupt trigger clock sequence comprises all PHY clocks in periodic interrupt trigger.

14. The method of claim 13, wherein the input device is the non-master input device;

receiving the clock conversion parameter sent by the main input device;

subtracting the clock conversion parameter from the first PHY clock, and subtracting one half of the video image block acquisition period to obtain an intermediate conversion clock;

15. The video synchronous display device based on the fusion signal source is characterized by being applied to input equipment in a video synchronous display system; the device comprises: the system comprises a clock management module, a video acquisition module and a video output module;

The clock management module is further configured to determine a first PHY clock corresponding to the video image block acquired according to the first schedule clock and the first time difference, where the first PHY clock is a sum of the first schedule clock and the first time difference; according to the first PHY clock time Zhong Huansuan parameters, converting a second PHY clock when interrupt triggering is performed, wherein the clock conversion parameters are calculated by a main input device and distributed to non-main input devices;

the video output module is configured to obtain the second PHY clock from the clock management module, carry the second PHY clock to each split picture, and send the second PHY clock to each connected output device, so that each output device obtains a current third PHY clock before outputting the split picture to a connected display screen, determine a second time difference between the third PHY clock and the second PHY clock, and output the split picture to the connected display screen when the second time difference is a preset standard time difference, where the split picture is obtained by splitting the video image block;

The input device is the main input device; the apparatus further comprises: a statistics calculation module;

The statistics calculation module is used for determining a third time difference between a corresponding PHY clock and a PHY clock when interrupt triggering closest to the PHY clock is performed when the video image block is acquired for each video image block in a specified historical period; and determining an average value of the third time differences corresponding to each video image block in the appointed historical period to obtain a clock conversion parameter.

16. The apparatus of claim 15, wherein the video acquisition module is configured to receive a video image block sent by a signal source when configured to acquire a first scheduling clock when acquiring a video image block, where the video image block carries the first scheduling clock when the signal source sends the video image block; the first schedule clock is read from the video image block.

17. The apparatus of claim 15, wherein the device comprises a plurality of sensors,

The clock management module is used for subtracting the clock conversion parameter from the first PHY clock and subtracting half of the video image block acquisition period when converting the second PHY clock when the interrupt trigger according to the first PHY clock time Zhong Huansuan parameter to obtain an intermediate conversion clock; and selecting a clock which is larger than the intermediate conversion clock and has the smallest difference value with the intermediate conversion clock from an interrupt trigger clock sequence as a second PHY clock in interrupt trigger, wherein the interrupt trigger clock sequence comprises all PHY clocks in periodic interrupt trigger.

18. The apparatus of claim 17, wherein the input device is the non-master input device; the apparatus further comprises: a receiving module;

The receiving module is used for receiving the clock conversion parameters sent by the main input equipment;

19. An input device comprising a processor and a memory;

The memory is used for storing a computer program;

the processor being adapted to carry out the method of any of claims 11-14 when executing a computer program stored on the memory.

20. A machine-readable storage medium, characterized in that it has stored therein a computer program which, when executed by a processor, implements the method of any of claims 11-14.