CN101005349A

CN101005349A - Clock synchronizing method and system

Info

Publication number: CN101005349A
Application number: CN 200710000099
Authority: CN
Inventors: 储育红
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2007-01-09
Filing date: 2007-01-09
Publication date: 2007-07-25
Anticipated expiration: 2027-01-09
Also published as: CN101005349B

Abstract

Using the synchronization system, the method includes steps: at multiple service transmission platforms (MSTP) device side, using phase locked loop makes of synchronous transmission module (STM) N line clock create working clock of PHY chip of Ethernet physical layer interface (EPLI) at MSTP device side; through EPLI, Ethernet PHY chip (EPC) at MSTP device side transfers working clock of EPC at MSTP device side to first EPC at receiving device side; first EPC at receiving device side picks working clock of EPC at MSTP device side; tracking and processing working clock picked up by first EPC at receiving device side to generate system clock as reference clock of receiving device. In IP network transmission mode, the invention realizes clock synchronization with low cost, and higher precision.

Description

A kind of clock synchronizing method and system

Technical field

The invention belongs to communication technical field, relate in particular to a kind of clock synchronizing method and system.

Background technology

As everyone knows, the good network net synchronization capability is great to telecommunication service influence, and the Synchronization Network of building for the performance that guarantees communication service has constituted three big supporting networks of telecommunication service with signaling network and telecommunication management network.Network Synchronization is bad to tend to bring a series of problem, problems such as especially in wireless network, synchronously badly tend to cause that voice quality is poor, cutting off rate height, handover success rate are low, can't insert.

From actual networking, general core net and base station controller equipment are because negligible amounts, can adopt the higher relatively GPS of cost (Global Position System, global positioning system) or BITS (Building Integrated Timing Supply System, complex building is feed system regularly) as the reference synchronization source, thereby than being easier to obtain good clock synchronization reference source, and wireless base station device is in the end of wireless network, concrete access way varies, and the quantity of base station is more relatively, consider and realize synchronous cost restriction, should not adopt GPS or BITS as timing reference input.If adopt common OCXO (Oven Control Crystal Oscillator, constant-temperature crystal oscillator) device, though with respect to GPS or BITS, cost is lower, but the carrier wave of eating dishes without rice or wine of wireless base station device is higher for the stability requirement of clock, according to 3GPP agreement regulation, need reach the precision of 0.05ppm.For satisfying the needed high precision clock requirement in wireless base station, need to follow the tracks of GPS or BITS or periodic calibration, overall cost is still higher.So comparatively speaking, the clock synchronization of base station is the part that solves least easily in the whole wireless network.

Along with 3G (3rd Generation, the 3G (Third Generation) Moblie technology) the continuous evolution of standard, its corresponding transmission network is also in evolution constantly, initial TDM (Time Division Multiplex, time division multiplexing), ATM (Asynchronous Transfer Mode, asynchronous transfer mode) extract synchronizing clock signals for the base station by physical carrier from business code flow, the now transmission network is gradually to IP (InternetProtocol, Internet protocol) network development.Because IP network is initial with the intercommunication mutually that solves between the computer, guarantee the reliability transmission of data, and be indifferent to the time delay and the shake of when transmission network, there is not public clock synchronization relation between each network element, therefore, the original low-cost solution under TDM and ATM transmission mode becomes more and more difficult utilizing under the IP transmission mode of Ethernet bearing.

MSTP (Multi-Service Transport platform, multiservice transport platform) technology comes from SDH (Synchronous Digital Hierarchy, SDH (Synchronous Digital Hierarchy)), through continuous development in a few years, included SDH, PDH (Pseudo-SDH, PDH (Pseudo-synchronous Digital Hierarchy)), POS (Packet OverSDH/SONET, bag transmission based on SDH (Synchronous Digital Hierarchy)/Synchronous Optical Network), Ethernet, ATM, RPR (Resilient Packet Ring, Resilient Packet Ring), SHDSL (Symmetrical High-bit-rate DigitalSubscriber Line, the symmetry high Bit Rate Digital Subscriber Loops), DDN (Digital Date Network, Digital Data Net) technology such as, it both can realize professional comprehensive transmission by the multi-service ethod of remittance, can realize the access and the processing of business again by self to the suitability of polymorphic type business, adapt to the development trend that multiple technologies merge mutually, become the perfect relatively technical system of a cover.From present form, the wireless base station inserts and adopts the MSTP networking is a selection preferably.

Adopting under the mode of MSTP networking as the wireless base station Access Network, the outer synchronous port of the 2048kHz that can utilize the MSTP access device to provide provides clock reference for the base station.But existing base station equipment not with the interface of the outer synchronous port coupling of 2048kHz, and the outer synchronous port of 2048kHz to zoom out distance limited, be not suitable for the environment that the base station is inserted by optical fiber.And, limited zooming out within the distance, also need to do work such as lightning protection, outdoor protection, cause the complexity of engineering relative with cost higher.

To sum up, be in the transmission network of leading position, not well not cheaply and have a solution of the clock synchronization of degree of precision at the current IP network.

Summary of the invention

The technical problem to be solved in the present invention provides a kind of method and system of clock synchronization, to be implemented under the IP network transmission mode cheaply and to have the clock synchronization of degree of precision.

For solving the problems of the technologies described above, the objective of the invention is to be achieved through the following technical solutions:

At first, the invention provides a kind of clock synchronizing method, comprising:

Synchronous Transport Module level-N STM-N line clock is generated the work clock of MSTP equipment side ethernet physical layer interface PHY chip at multiservice transport platform MSTP equipment side by phase-locked loop;

MSTP equipment side Ethernet PHY chip is delivered to the receiving equipment side first Ethernet PHY chip by the ethernet physical layer interface with the work clock of described MSTP equipment side Ethernet PHY chip;

The receiving equipment side first Ethernet PHY chip extracts the work clock of described MSTP equipment side Ethernet PHY chip;

The work clock that the described receiving equipment side first Ethernet PHY chip is extracted is followed the tracks of and handled, and the system clock that generates receiving equipment is as reference clock.

Optionally, before the described work clock that the described receiving equipment side first Ethernet PHY chip is extracted was followed the tracks of and handled, further the work clock that the described receiving equipment side first Ethernet PHY chip is extracted generated the clock that the receiving equipment reference clock will be followed the tracks of and handle by phase-locked loop.

Optionally, further comprise behind the system clock of generation receiving equipment:

Receiving equipment generates the work clock of the receiving equipment side second Ethernet PHY chip by phase-locked loop to the system clock of receiving equipment;

The receiving equipment side second Ethernet PHY chip is delivered to the cascade device side Ethernet PHY of subordinate chip by the ethernet physical layer interface with the work clock of described receiving equipment side the 2nd PHY chip;

Cascade device side Ethernet PHY chip extracts work clock;

The work clock that described cascade device side Ethernet PHY chip is extracted is followed the tracks of and handled, generate the system clock of cascade device.

Preferably, by network layer, MAC sublayer MAC layer, ethernet physical layer or by MAC layer, ethernet physical layer the Synchronization Status Message SSM of STM-N line clock is sent to the receiving equipment side, whether receiving equipment lost efficacy according to the SSM judgment standard clock that receives, if the clock frequency before then keeping losing efficacy is a reference clock.

Preferably, the described work clock that the receiving equipment side first Ethernet PHY chip is extracted is followed the tracks of and is handled by software phase-lock loop and undertaken.

Preferably, the described phase-locked loop that MSTP equipment side STM-N line clock and/or receiving equipment system clock are handled is the phase-locked loop of band VCXO.

Simultaneously, the invention provides a kind of clock system, comprising: MSTP equipment side phase locked-loop unit, MSTP equipment side Ethernet PHY chip, receiving equipment side first are with big net PHY chip, receiving equipment system clock unit, wherein:

MSTP equipment side phase locked-loop unit is handled the work clock that generates MSTP equipment side Ethernet PHY chip to the STM-N line clock;

The receiving equipment side first Ethernet PHY chip extracts the clock that receives;

The receiving equipment system clock unit is used for the clock that the described receiving equipment side first Ethernet PHY chip extracts is followed the tracks of and handled, and generates the system clock of receiving equipment.

Optionally, also comprise receiving equipment side chain phase ring element, be used for the clock that the receiving equipment side first Ethernet PHY chip is extracted is handled the clock that generation receiving equipment system clock unit will follow the tracks of and handle.

Optionally, also comprise: receiving equipment side second phase locked-loop unit, the receiving equipment side second Ethernet PHY chip, cascade device side Ethernet PHY chip, cascade device system clock unit, wherein:

Receiving equipment side second phase locked-loop unit is used for described receiving equipment system clock is handled the work clock that generates the receiving equipment side second Ethernet PHY chip;

The receiving equipment side second Ethernet PHY chip is used for the work clock of the described receiving equipment second Ethernet PHY chip is delivered to cascade device side Ethernet PHY chip;

Cascade device side Ethernet PHY chip is used to extract the described work clock that receives;

The cascade device system clock unit is used for the clock that described cascade device side Ethernet PHY chip extracts is followed the tracks of and handled, and generates the system clock of cascade device.

Preferably, clock system also comprises the SSM transmission unit, and system clock unit also comprises the clock holding unit, wherein:

The SSM transmission unit comprises MAC layer, ethernet physical layer, is used for the Synchronization Status Message SSM of STM-N line clock is delivered to the clock holding unit of receiving equipment;

The clock holding unit is used for when the SSM that receives shows that reference clock lost efficacy, with the clock that stored before losing efficacy as reference clock.

In above-mentioned clock system, described MSTP equipment side phase locked-loop unit and/or receiving equipment side second phase locked-loop unit comprise: phase discriminator, filter, oscillator, wherein:

Phase discriminator is used to judge the STM-N line clock of input and the phase difference of the clock frequency that described oscillator is exported, and produces corresponding to the control signal that differs;

Filter, the control signal that is used for phase discriminator is exported is carried out filtering, produces the control signal that is used for control generator;

Oscillator is regulated self frequency of oscillation under the control signal of the output of filter.

Preferably, described oscillator is a VCXO.

Above technical scheme as can be seen, with respect to the method that adopts GPS or BITS isochronon reference source in the receiving equipment side, the present invention adopt simple and the phase locked-loop unit that is easy to obtain and transmission network intrinsic Ethernet PHY chip realize clock synchronization, realize that cost is lower; Simultaneously, with respect to by the method for 2048kHz as External synchronous reference source, the present invention transmits the STM-N line clock by ethernet physical layer, the present invention does not need special maintenance, and maintenance cost is lower, therefore, on the whole, cost of the present invention is relatively low.

Simultaneously, the present invention will have the synchronised clock reference source of the STM-N line clock of good synchronization performance as the receiving equipment side, be not subjected to Impacts of Pointer Adjustment, and phase-locked loop has good clock recovery performance, and, directly clock being delivered to the receiving equipment side by ethernet physical layer, clock delay is little, therefore, the present invention can satisfy the needs that equipment such as wireless base station are had relatively high expectations to clock accuracy.

Further, receiving equipment is followed the tracks of and is handled the clock that receiving equipment side Ethernet PHY chip extracts by the software phase-lock loop unit, makes that the system clock that generates is more stable.

In addition, the present invention does not need to transmit clock by IP layer or MAC layer, not the outer transmission bandwidth of occupying volume.

Description of drawings

Fig. 1 is the theory diagram of the clock system of the embodiment of the invention one;

Fig. 2 is the theory diagram of the clock system of the embodiment of the invention two;

Fig. 3 is the theory diagram of the clock system of the embodiment of the invention three;

Fig. 4 is the theory diagram of the clock system of the embodiment of the invention four.

Embodiment

For making advantages and features of the invention clearer, the embodiment that develops simultaneously with reference to the accompanying drawings is further described the present invention.

The MSTP technology grows up on the SDH basis, can merge multiple services access.The main transmission bearer mode of MSTP network remains based on SDH, and the SDH network generally all passes through good synchronous planning.Wherein, the signal of SDH is made up of the Synchronous Transport Module level-N STM-N signal of one or more not same orders, and wherein N is a positive integer.For SDH optical cable connecting system, at present, N=1,4 or 16, the bit rate of basic module STM-1 signal is 155.52Mbit/s, the bit rate of STM-N signal is N * 155.520Mbit/s.The STM-N signal can be interleave and form through byte by N basic module STM-1.No matter why N is worth, and the frame repetition period of STM-N is 125 μ s, per second 8000 frames.The STM-N line clock is not subjected to Impacts of Pointer Adjustment, can be used as good reference synchronization source.

The STM-N line clock is generated the work clock of MSTP equipment side ethernet physical layer interface PHY chip at the MSTP equipment side by phase locked-loop unit, and by ethernet physical layer work clock is delivered to the receiving equipment side first Ethernet PHY chip by this Ethernet PHY chip, extract clock through the receiving equipment side first Ethernet PHY chip, this clock that extracts is followed the tracks of and handled, obtain the system clock of receiving equipment.The system clock of receiving equipment is promptly synchronous with the STM-N line clock maintenance of MSTP equipment side.

At present, under optical fiber and the support of twisted-pair feeder medium, 4 kinds of transmission rates are arranged, be respectively: the gigabit Ethernet GE of Fast Ethernet FE, the 1000Mbps of the standard ethernet of 10Mbps, 100Mbps and 10GE Ethernet with big net.Below each embodiment describe with Synchronization Network FE and GE commonly used.

Clock synchronization with the realization base station equipment is that example is elaborated.

Embodiment one, and MSTP equipment is delivered to base station side by ethernet physical layer with the STM-N line clock, with reference to Fig. 1, below is elaborated.

Step 11:MSTP equipment generates the work clock of MSTP equipment side ethernet physical layer interface PHY chip by phase locked-loop unit.

Phase locked-loop unit generally comprises phase discriminator, filter and oscillator, and wherein, phase discriminator produces a control signal by the STM-N line clock of relatively input and the phase difference of the output frequency of oscillator; Filter carries out filtering with level and smooth to the signal of input phase discriminator output, eliminates shake; Oscillator is regulated the self-oscillation frequency according to the control signal of filter output, draws close to the frequency of input signal, locks until eliminating error.

The protocol section of the physical/electrical characteristic of physical layer interface processing signals is also referred to as PHY.

Because the working clock frequency of PHY chip may be different with STM-N line clock frequency, therefore can be in phase-locked loop circuit at first to oscillator frequency frequency division or frequency multiplication, simultaneously to the STM-N line clock frequency division or the frequency multiplication of input, thereby produce the work clock of Ethernet PHY chip.

Step 12:MSTP equipment side Ethernet PHY chip sends data flow by the FE/GE interface work clock is delivered to the base station side first Ethernet PHY chip.

Wherein, the data flow that the MSTP equipment side produces comprises data and clock information simultaneously, and with data, clock is passed to the base station side first Ethernet PHY chip.

Step 13: the base station side first Ethernet PHY chip extracts clock from data flow.

Step 14: the base station system clock unit is followed the tracks of and is handled the clock that base station side Ethernet PHY chip is extracted, thereby generates the base station system clock, and the base station system clock is realized with the STM-N line clock synchronous.

Step 15: Service Processing Unit carries out Business Processing under the base station system clock control, carry out encoding and decoding, modulation as Service Processing Unit.

In order to satisfy Ethernet PHY chip better for the clock jitter performance demands, the oscillator that the MSTP equipment side is used for producing the phase-locked loop of the needed work clock of Ethernet PHY chip can adopt VCXO (Voltage Control Crystal Oscillator, VCXO).

In addition, can in the base station system clock unit, increase software phase-lock loop.Software phase-lock loop erasure signal shake better, thus a more stable system clock can be generated.Software phase-lock loop have hardware phase-locked-loop incomparable advantage, for example can utilize CPU flexible processing ability to realize optimizing filtering or adaptive-filtering, can change integrated value by force and realize quick lock in.

Embodiment one has realized the synchronous of base station system clock and MSTP equipment side STM-N line clock, in order to guarantee the superperformance of clock system, system clock still can have only very little frequency departure with reference clock when the reference clock that produces with embodiment two Benqs stations system clock unit lost efficacy in a period of time, with reference to Fig. 2.

Comprise with embodiment one something in common: still generate the needed clock frequency of MSTP equipment side Ethernet PHY chip by phase locked-loop unit at the MSTP equipment side, MSTP equipment side Ethernet PHY chip sends data flow by the FE/GE interface clock is delivered to the base station side first Ethernet PHY chip, the base station side first Ethernet PHY chip extracts clock from the data flow that receives, the base station system clock unit is followed the tracks of and is handled the clock that extracts, produce the system clock of base station, for the Service Processing Unit in the base station provides reference clock, for example, as back level encoding and decoding, the reference clock of modulation and middle radio frequency.

Difference is, if the MSTP network is two-layer networking mode, MSTP equipment simultaneously also will be with SSM (the Synchronization Status Message that receives, Synchronization Status Message) by MAC (Media Access Control, MAC sublayer) layer, physical layer sends to MSTP equipment side Ethernet PHY chip, MSTP equipment side Ethernet PHY chip is sent to the base station side first Ethernet PHY chip with SSM, the base station side first Ethernet PHY chip passes through physical layer with SSM message, the MAC layer sends to system clock unit, the performance of the reference clock that indication base station system clock is generated.

If the MSTP network is three layers of networking mode, MSTP equipment then needs the SSM that will receive to send to MSTP equipment side Ethernet PHY chip by IP layer, MAC layer, physical layer successively, MSTP equipment side Ethernet PHY chip is sent to the base station side first Ethernet PHY chip with SSM, the base station side first Ethernet PHY chip sends to the base station system clock unit by physical layer, MAC layer, IP layer successively with SSM message, the performance of the reference clock that the indication mechanism clock is generated.

System clock unit can be sampled to employed clock frequency, and calculating mean value also stores.When SSM shows that reference clock that the base station system clock unit is generated can not satisfy the quality requirement of base station system clock, reference clock lost efficacy, the base station system clock is no longer followed the tracks of, but work for its reference clock with the clock frequency of being stored before the inefficacy of base station system reference clock, the base station system clock unit works in the maintenance pattern.

SSM can only indicate the credit rating of current reference clock, can not artificially set.For example,, adopt 4 kinds of different credit ratings according to the ITU-T standard: primary resource clock, based on caesium clock, clock grade is for G.811; Transit exchange, is generally provided by BITS based on rubidium clock from clock, and clock grade is for G.812T; End office (EO) is used for the local digital Synchronization Network from clock, and the clock grade standard is for G.812L; The equipment timing source is provided by device interior, and the clock grade standard is for G.813.

Quote SSM, the synchronization status byte S1 of the MSOH in the available STM-N signal describes, and for example, represents the Synchronization Status Message indication with the 5th to 8 bit of S1.G.811 0010 represent, G.812T 0100 represent, G.812L 0111 represent, 1111 expressions are different from clock synchronization.

When the STM-N line clock lost efficacy, MSTP equipment can detect, and lost as LOS signal indication input signal.The clock frequency that the base station system clock was stored before promptly losing efficacy with reference clock is worked for its reference clock.

As seen, SSM is sent to of the performance indication of receiving equipment side such as base station as reference clock, when reference clock lost efficacy, clock frequency before receiving equipment side system clock keep to lose efficacy is as reference clock, thereby local clock continues to follow the tracks of and produce than mistake when having avoided that clock lost efficacy under exceptional condition.

On above-mentioned two embodiment bases, can after base station side Ethernet PHY chip, increase a phase-locked loop and produce the base station system clock, the software phase-lock loop in the base station system clock unit then is specifically designed to the shake of eliminating clock signal.As shown in Figure 3, this prioritization scheme is described as embodiment three.

Embodiment three, and is identical with preceding two examples, and this implementation also need be produced the work clock of Ethernet PHY chip and be delivered to the base station side first Ethernet PHY chip by phase-locked loop by MSTP equipment, and extracts clock by this chip.

Simultaneously, MSTP equipment sends to base station side with SSM that this equipment generated by IP layer, MAC layer, physical layer and by Ethernet PHY chip, the base station side first Ethernet PHY chip extracts SSM and is sent to the base station system clock unit by MAC layer, IP layer, the performance of indication base station system clock, if the base station system clock lost efficacy, the base station system clock unit enters the maintenance pattern, works as its reference clock with the clock frequency that stored before losing efficacy.

Its difference is, after extracting clock, the base station side first Ethernet PHY chip directly do not send to the base station system clock unit, but send to phase locked-loop unit, after phase locked-loop unit is carried out frequency multiplication or frequency division, produce the system clock of base station, as reference clock, the base station system clock unit is followed the tracks of and is handled, be met the base station system clock of quality requirement, be used for professional reference clocks such as back level encoding and decoding, modulation and radio frequency.

In addition, for the situation of a plurality of base cascades, the Ethernet of the downward cascade that base station equipment can be by its output comes for subordinate's cascade base-station provides clock reference, with reference to Fig. 4, with this scheme as embodiment four.

Embodiment four, as described in embodiment three, the STM-N line clock of base station and MSTP equipment side keeps synchronously, if another base station and this base cascade are arranged, so, this base station system clock can be used as the timing reference input of the base station equipment of another and its cascade, as shown in Figure 4, base station 1 obtains synchronised clock reference source (Fig. 4 does not show) by Ethernet from MSTP equipment, and base station 21 obtains the synchronised clock reference source by Ethernet from the base station.Below only describe with regard to the clock synchronization between the cascade base-station.

As shown in Figure 4, produce the needed work clock of base station 1 side, the second Ethernet PHY chip by phase locked-loop unit, base station 1 side, the second Ethernet PHY clock is delivered to base station 2 sides, the first Ethernet PHY chip by the FE/GE interface with work clock, owing to except clock information, also have other data in the data flow that base station 1 side sends, therefore, the first Ethernet PHY chip of base station 2 sides at first extracts clock from data flow.Then, eliminate shake by phase locked-loop unit, if desired, can also regulate incoming frequency, thereby produce the system clock of base station 2, the system clock unit of base station 2 can further be eliminated the shake of clock signal by software phase-lock loop, thereby generates the reference clock that satisfies quality requirement.

Simultaneously, base station 1 sends to the second Ethernet PHY chip of base station 1 side with the SSM of this equipment by IP layer, MAC layer, ethernet physical layer, and this chip is sent to the first Ethernet PHY chip of base station 2 sides by the FE/GE interface.Base station 2 sides, the first Ethernet PHY chip is sent to the system clock unit of base station 2 by ethernet physical layer, MAC layer, IP layer with SSM successively, as the performance indication of the reference clock that system clock unit generated of base station 2.

Like this, when SSM read clock quality satisfies quality requirement, the system clock of base station 2 is followed the tracks of the system clock of the base station 1 after phase-locked loop and the processing of Ethernet PHY chip, and for the Service Processing Unit of base station 2 provides reference clock, as reference clock as business such as back level encoding and decoding and modulation.

The system clock unit of base station 2 can be sampled to employed clock frequency, and calculating mean value also stores.When SSM read clock reference source lost efficacy, the system clock of base station 2 was in hold mode, and the clock frequency that stored before losing efficacy with reference clock is worked as reference clock.

For below the subordinate base station of cascade base-station again the clock synchronization of cascade base-station also be as a same reason, the clock information that utilization generates from the Ethernet that upper-level BTS comes, handle this base station system clock as the reference source of system clock unit, be delivered to subordinate's cascade base-station as timing reference input by ethernet physical layer simultaneously.Because base station controller equipment is less, and base station number is more.This method directly keeps synchronously a spot of several base stations and base station controller, keeps below these several base stations the clock synchronization of the whole network useful especially under the layout of cascade base-station.

As seen, but the base station by ethernet physical layer with local clock be delivered in the subordinate base station with its cascade, cascade base-station at different levels all the system clock of higher level cascade base-station as the reference synchronization source, thereby can realize the clock synchronization of whole network.

Certainly, if the base station of cascade is not to communicate by Ethernet, but by TDM or atm network, the method that also can take to extract clock from business code flow with the base station of its cascade realizes clock synchronization, is not described in detail at this.

Above embodiment is with under the MSTP networking mode, and the Ethernet transmission synchronised clock by FE or GE type certainly, also can adopt the Ethernet of other type, enumerates no longer one by one.

More than by embodiment the method that realizes clock synchronization has been carried out more detailed description, illustrate the system that realizes clock synchronization below.

Clock system as shown in Figure 1 comprises: MSTP equipment side phase locked-loop unit 11, Ethernet PHY chip 12 and base station side first Ethernet PHY chip 13 and the base station system clock unit 14, the below function of each unit of detailed description:

MSTP equipment side phase locked-loop unit 11 is by handling the work clock that generates MSTP equipment side Ethernet PHY chip 12 to the STM-N line clock;

MSTP equipment side Ethernet PHY chip 12 is delivered to the base station side first Ethernet PHY chip 13 by the FE/GE interface with described work clock;

The base station side first Ethernet PHY chip 13 extracts the clock that receives;

Base station system clock unit 14 is followed the tracks of and is handled the clock that the base station side first Ethernet PHY chip 13 extracts, and produces the system clock of base station equipment.

Above system promptly realized base station system clock and MSTP access device the STM-N line clock synchronously.

Like this, in base station side, base station system clock unit 14 just can be BTS service processing unit 15 reference clock is provided.BTS service processing unit 15 under the control of base station system clock unit, carry out encoding and decoding, modulation and in work such as radio frequency.

In above-mentioned clock system, MSTP equipment side phase locked-loop unit 11 is used for the STM-N line clock is handled the work clock that generates MSTP equipment side Ethernet PHY chip, comprises phase discriminator 11, filter 12, oscillator 13 at least, wherein:

Phase discriminator 11 is used to judge the phase difference of the frequency of the STM-N line clock frequency of input and oscillator 13 outputs, produces corresponding to the control signal of two signal phase differences and is input to filter 12;

Filter 12 is used for the control signal filtering to input, eliminates shake, and output control signal control generator 13;

Oscillator 13 is used under the effect of control signal regulating self frequency, and oscillator frequency is drawn close to frequency input signal gradually, eliminates frequency difference gradually and locks.

If the work clock of described MSTP equipment side Ethernet PHY chip 12 is different with the STM-N line clock, in described phase locked-loop unit 11, also comprise frequency divider or frequency multiplier, be used to generate the work clock of described MSTP equipment side Ethernet PHY chip 12.

Phase locked-loop unit can be discrete device, also can be the chip of phase locked-loop unit integrated.

Wherein, oscillator 12 can be VCXO, makes the jitter performance of the clock that MSTP side phase-locked loop 11 is generated can satisfy MSTP side Ethernet PHY chip better for the clock jitter performance demands.

In addition, also can comprise the software phase-lock loop unit in the base station system clock unit 14.The software phase-lock loop unit is used to follow the tracks of the clock that Ethernet PHY chip is extracted, and eliminates shake, produces the system clock of base station.

Clock system among Fig. 1 is done further to optimize, increase SSM, be used to indicate the performance of base station reference clock, as shown in Figure 2.

On the basis of the clock system of Fig. 1, increase the MAC layer, be used for SSM is sent to MSTP equipment side Ethernet PHY chip 12, and the SSM that the base station side first Ethernet PHY chip 13 is sent is transmitted base station system clock unit 14.As shown in Figure 2, at the MSTP equipment side, the MAC layer is sent to MSTP equipment side Ethernet PHY chip 12 with SSM; In base station side, the MAC layer is delivered to BTS service processing unit 14 with the SSM that the base station side first Ethernet PHY chip 13 is sent.

MSTP network shown in Figure 2 is two-layer networking mode, if the MSTP network is three layers of networking mode, then need increase IP layer, MAC layer on clock system basis shown in Figure 1.At this moment, at the MSTP equipment side, the IP layer is delivered to the MAC layer with SSM, and the MAC layer is delivered to SSM MSTP equipment side Ethernet PHY chip 12 again; In base station side, the MAC layer is delivered to the IP layer with the SSM that the base station side first Ethernet PHY chip 13 sends, and the IP layer is delivered to base station system clock unit 14 again.

The base station system clock unit also comprises the clock holding unit, can sample to employed clock frequency, and calculating mean value also stores.If SSM shows that the quality of reference clock can't satisfy operation quality requirement or when invalid, the clock holding unit works in the maintenance pattern, works as reference clock with the clock frequency of storage before losing efficacy.

Clock system shown in Figure 2 is done further to optimize, as shown in Figure 3, increase phase locked-loop unit 31 in base station side, the clock that is used for being extracted according to the base station side first Ethernet PHY chip 13 generates the system clock of base station system clock unit 14 as clock reference.Phase locked-loop unit 31 can further improve the jitter performance of system, for system clock unit 14 provides performance better reference clock.

If the clock frequency that the base station side first Ethernet PHY chip 13 is extracted is different with the clock frequency of base station system clock unit, described phase locked-loop unit 31 also comprises frequency modulation unit, so that the clock frequency that the base station side first Ethernet PHY chip is exported equates with the needed clock frequency of base station system.

Clock system described in the embodiment of the invention also can be used for realizing synchronously between the base station of STM-N line clock and its subordinate base station synchronously, clock system as shown in Figure 4 comprises: the system clock unit 14 that with STM-N is the base station 1 of timing reference input, phase locked-loop unit 41, second Ethernet PHY chip 42 of base station 1 side and the first Ethernet PHY chip 43 of base station 2 sides, phase locked-loop unit 44, the system clock unit 45 of base station 2, and SSM transmits the Service Processing Unit 46 of needed base station 1, the Service Processing Unit 46 of base station 2,

MAC layer

47,48.

The function of following each part of introducing system:

The system clock unit 14 of base station 1 keeps synchronously with the STM-N line clock, and the clock of native system is delivered to phase locked-loop unit 41;

Phase locked-loop unit 41 generates the work clock of base station 1 side, the second Ethernet PHY chip 42 according to the clock of system clock unit 14;

Base station 1 side, the second Ethernet PHY chip 42 is delivered to work clock by the FE/GE interface the first Ethernet PHY chip 43 of base station 2 sides;

The first Ethernet PHY chip 43 of base station 2 sides extracts the clock that receives;

Phase locked-loop unit 44 is handled the clock that the first Ethernet PHY chip 43 of base station 2 sides is extracted, and is delivered to the system clock unit 45 of base station 2;

The system clock unit 45 of base station 2 is followed the tracks of the clock that phase locked-loop unit 44 generates, and produces the system clock of base station 2; Under the indication of SSM, for the Service Processing Unit 46 of base station 2 provides reference clock.

MAC layer

47,48 as the SSM transmission unit, is used for the SSM that base station 1 generates is delivered to the system clock unit of base station 2.

As seen, the base station is delivered to local clock in the subordinate base station with its cascade by ethernet physical layer, but cascade base-station at different levels all the system clock of higher level cascade base-station as the reference synchronization source, thereby can realize the clock synchronization of whole network.

Certainly, if the base station equipment of cascade is not to communicate by Ethernet, but by TDM or atm network, the solution that also can take to extract clock from business code flow with the equipment of its cascade realizes clock synchronization, is not described in detail at this.

Above embodiment is with under the MSTP networking mode, and the ethernet physical layer transmission synchronised clock by FE or GE type certainly, also can adopt the ethernet physical layer of other type, enumerates no longer one by one.

More than a kind of clock synchronizing method provided by the present invention and system are described in detail, used specific case herein principle of the present invention and execution mode are set forth, the explanation of above embodiment just is used for helping to understand method of the present invention and core concept thereof; Simultaneously; for one of ordinary skill in the art; according to thought of the present invention; part in specific embodiments and applications all can change; for example, it is that clock is transmitted in the base station that the embodiment of the invention only is not limited to, and provides clock also at the row of of the present invention protection by physical layer for miscellaneous equipment with the STM-N line clock of employing MSTP equipment; in sum, this description should not be construed as limitation of the present invention.

Claims

1, a kind of clock synchronizing method is characterized in that, comprising:

2, clock synchronizing method as claimed in claim 1, it is characterized in that, before the described work clock that the described receiving equipment side first Ethernet PHY chip is extracted was followed the tracks of and handled, further the work clock that the described receiving equipment side first Ethernet PHY chip is extracted generated the clock that the receiving equipment reference clock will be followed the tracks of and handle by phase-locked loop.

3, clock synchronizing method as claimed in claim 2 is characterized in that, further comprises behind the system clock of generation receiving equipment:

Cascade device side Ethernet PHY chip extracts work clock;

4, as each described clock synchronizing method of claim 1 to 3, it is characterized in that, further comprise:

By network layer, MAC sublayer MAC layer, ethernet physical layer or by MAC layer, ethernet physical layer the Synchronization Status Message SSM of STM-N line clock is sent to the receiving equipment side, whether receiving equipment lost efficacy according to the SSM judgment standard clock that receives, if the clock frequency before then keeping losing efficacy is a reference clock.

As each described clock synchronizing method of claim 1 to 3, it is characterized in that 5, the described work clock that the receiving equipment side first Ethernet PHY chip is extracted is followed the tracks of and handled by software phase-lock loop and undertaken.

As each described clock synchronizing method of claim 1 to 3, it is characterized in that 6, the described phase-locked loop that MSTP equipment side STM-N line clock and/or receiving equipment system clock are handled is the phase-locked loop of band VCXO.

7, a kind of clock system is characterized in that, comprising: MSTP equipment side phase locked-loop unit, MSTP equipment side Ethernet PHY chip, the receiving equipment side first Ethernet PHY chip, receiving equipment system clock unit, wherein:

8, clock system as claimed in claim 7, it is characterized in that, also comprise receiving equipment side chain phase ring element, be used for the clock that the receiving equipment side first Ethernet PHY chip is extracted is handled the clock that generation receiving equipment system clock unit will follow the tracks of and handle.

9, clock system as claimed in claim 8 is characterized in that, also comprises: receiving equipment side second phase locked-loop unit, the receiving equipment side second Ethernet PHY chip, cascade device side Ethernet PHY chip, cascade device system clock unit, wherein:

10, as each described clock system of claim 7 to 9, it is characterized in that clock system also comprises the SSM transmission unit, system clock unit also comprises the clock holding unit, wherein:

As each described clock system of claim 7 to 9, it is characterized in that 11, described MSTP equipment side phase locked-loop unit and/or receiving equipment side second phase locked-loop unit comprise: phase discriminator, filter, oscillator, wherein:

12, clock system as claimed in claim 11 is characterized in that, described oscillator is a VCXO.