CN115529014A - Differential amplifier circuit and memory - Google Patents

Differential amplifier circuit and memory Download PDF

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Publication number
CN115529014A
CN115529014A CN202110704099.3A CN202110704099A CN115529014A CN 115529014 A CN115529014 A CN 115529014A CN 202110704099 A CN202110704099 A CN 202110704099A CN 115529014 A CN115529014 A CN 115529014A
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China
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voltage
transistor
input
transistors
source
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CN202110704099.3A
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Chinese (zh)
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刘星
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Xi'an Geyi Anchuang Integrated Circuit Co ltd
Zhaoyi Innovation Technology Group Co ltd
Hefei Geyi Integrated Circuit Co Ltd
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Xi'an Geyi Anchuang Integrated Circuit Co ltd
Zhaoyi Innovation Technology Group Co ltd
Hefei Geyi Integrated Circuit Co Ltd
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Priority to CN202110704099.3A priority Critical patent/CN115529014A/en
Publication of CN115529014A publication Critical patent/CN115529014A/en
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H03F3/45197—Pl types
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/30—Power supply circuits

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)

Abstract

The invention discloses a differential amplification circuit and a memory, wherein the differential amplification circuit comprises: inputting a pair of tubes; and a feedback circuit. The feedback circuit applies a voltage to the substrate of the output pair transistor based on the source voltage of the input pair transistor. By applying a voltage to the substrate of the input pair transistor, the threshold voltage of the input pair transistor is reduced, so that the transistor for providing the bias current has enough drain-source voltage to be in a saturation region, and the performance degradation caused by the fact that the transistor for providing the bias current enters a linear region is avoided.

Description

Differential amplifier circuit and memory
Technical Field
The invention relates to the field of analog circuits, in particular to a differential amplification circuit and a memory.
Background
The differential amplifier circuit is widely used in a Peripheral circuit (Peripheral circuit) of a memory. A differential amplifier circuit typically includes an input pair of transistors, a load, and a transistor for providing a bias current. The threshold voltage of a transistor in a flash memory process is much higher than that of a logic process. In low power and low voltage applications, too high a transistor threshold voltage limits the use and performance of many differential amplification circuits. For example, a threshold voltage of the input pair transistor is too high, which may cause a drain-to-source voltage of a transistor providing a bias current to be low, and the transistor providing the bias current enters a linear region, which may cause a reduction in the bias current, affecting the performance of the differential amplifier circuit.
Disclosure of Invention
The embodiment of the invention provides a differential amplification circuit and a memory, which are used for solving the problem that a bias current transistor enters a linear region due to overhigh threshold voltage of an input geminate transistor in a flash memory chip.
According to an aspect of the present invention, there is provided a differential amplification circuit including: inputting a pair of tubes; and a feedback circuit that applies a voltage to the substrates of the output pair transistors based on the source voltages of the input pair transistors.
Further, the input pair transistors are NMOS transistors, and when the source voltage of the input pair transistors is lower than a first preset value, the feedback circuit applies a positive voltage to the substrates of the input pair transistors.
Further, the input pair transistors are PMOS transistors, and the feedback circuit applies a positive voltage to the substrates of the input pair transistors when the source voltages of the input pair transistors are lower than the preset value.
Further, the input pair transistors are PMOS transistors, and when the source voltages of the input pair transistors are higher than a second preset value, the feedback circuit applies positive voltage to the substrates of the input pair transistors.
Further, the input pair transistors are NMOS transistors, the feedback circuit includes a comparator and a source follower, the source follower includes an NMOS transistor and a current source, the NMOS transistor and the current source are connected in series between a voltage terminal and ground, the voltage terminal is used for providing a first voltage, a drain of the NMOS transistor is connected to the voltage terminal, a gate of the NMOS transistor is connected to an output terminal of the comparator, and a source of the NMOS transistor is connected to the substrate of the input pair transistors. The first voltage is 0.4V.
Further, the feedback circuit further comprises a complementary to absolute temperature voltage generating circuit for providing a voltage of the first preset value to the input terminal of the comparator.
Further, the input geminate transistors are PMOS transistors, the feedback circuit comprises a comparator and a source follower, the source follower comprises PMOS transistors and a current source, the PMOS transistors and the current source are connected in series between a voltage end and a power supply, the voltage end is used for providing second voltage, drain electrodes of the PMOS transistors are connected with the voltage end, grid electrodes of the PMOS transistors are connected with output ends of the comparator, and source electrodes of the PMOS transistors are connected with substrates of the input geminate transistors. The second voltage is lower than the supply voltage by 0.4V.
Further, the feedback circuit further comprises a complementary to absolute temperature voltage generating circuit for providing a voltage of the second preset value to the input terminal of the comparator.
According to another aspect of the present invention, there is provided a memory including the differential amplifier circuit according to any one of the embodiments of the present invention.
By applying a voltage to the substrate of the input pair transistor, the threshold voltage of the input pair transistor is reduced, so that the transistor for providing the bias current has enough drain-source voltage to be in a saturation region, and the performance degradation caused by the fact that the transistor for providing the bias current enters a linear region is avoided.
Drawings
The technical solution and other advantages of the present invention will become apparent from the following detailed description of specific embodiments of the present invention, which is to be read in connection with the accompanying drawings.
Fig. 1 is a circuit diagram of a differential amplifier circuit according to an embodiment of the present invention.
Fig. 2 is a circuit diagram of a comparator according to an embodiment of the present invention.
Fig. 3 is a schematic structural diagram of an N-type MOS transistor according to an embodiment of the present invention.
Fig. 4 is a circuit diagram of a differential amplifier circuit according to a second embodiment of the present invention.
Fig. 5 is a schematic diagram of a memory according to a third embodiment of the present invention.
Detailed Description
The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly and may be, for example, fixedly connected, detachably connected, or integrally connected; may be mechanically, electrically or may be in communication with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
As shown in fig. 1, a schematic diagram of a differential amplifier circuit according to a first embodiment of the present invention is provided. The differential amplification circuit includes: input pair transistors and feedback circuit 100. The input pair transistor includes a first input transistor MN11 and a second input transistor MN12. The gate of the first input transistor MN1 serves as a first input terminal VIN, and the gate of the second input transistor MN2 serves as a second input terminal VIP. The differential amplification circuit receives a differential signal at a first input and a second input.
The differential amplification circuit further includes: transistor MN10, transistor MP11, transistor MP12. The gate of the transistor MN10 receives a bias voltage, and the drain of the transistor MN10 is connected to the source of the input pair transistor (node C1). Transistor MN10 is used to provide bias current to the input pair. The transistor MP11 and the transistor M12 are loads input to the pair transistors. The transistor MP11 is provided as a diode connection. The gates of the transistors MP11 and M12 are connected to the drain of the first input transistor MN 11. The transistor MP11 and the transistor M12 constitute a current mirror. The current mirror mirrors the current of the first input transistor MN11 to the transistor MP12. The drain terminal of the transistor M12 serves as an output terminal of the differential amplification circuit.
In the differential amplifier circuit shown in fig. 1, the input pair transistors are NMOS transistors, the transistor MN10 is an NMOS transistor, and the transistors MP11 and MP12 are PMOS transistors. The first input transistor MN11 and the second input transistor MN12 in the differential amplifier circuit are each a four-terminal device, as shown in fig. 4, and include a source 12, a drain 11, a gate 14, an insulating layer 13, and a substrate electrode 15.
An input terminal of the feedback circuit 100 is connected to the node C1, and an output terminal of the feedback circuit 100 is connected to the substrate electrodes 15 of the pair of input transistors. When the source voltage of the input pair transistors is lower than a first preset value, the feedback circuit 100 applies voltage to the substrates of the output pair transistors, so that the threshold voltage of the input pair transistors is reduced, the voltage of the node C1 is increased, the drain-source voltage of the transistor MN10 is increased, and the transistor MN10 is prevented from entering a linear region.
The threshold voltage formula of the NMOS transistor is:
Figure BDA0003131490890000041
phi f is substrate fermi potential, gamma is bulk effect factor, V BS Is the voltage between the substrate and the source, V TH0 Is when V BS The threshold voltage at zero. When V is BS Above 0, the threshold voltage is reduced. In order to prevent the parasitic diode from conducting from the substrate to the source and the drain in the forward direction, the substrate voltage is 0.4V at most. The substrate voltage of 0.4V can reduce the threshold voltage of the first input transistor MN11 and the second input transistor MN12 of the differential amplifier 10 by up to 100 mv, and improve the performance degradation of the differential amplifier caused by the high threshold of the input pair transistors.
The feedback circuit 100 includes a comparator 101 and a source follower. Comparator 101 has a first input, a second input, and an output. The first input terminal is, for example, a negative input terminal, and the second input terminal is, for example, a positive input terminal. The first input terminal is connected to the node C1 as an input terminal of the feedback circuit 100, and the second input terminal receives the voltage Vtarget with the first predetermined value. The comparator 101 is also implemented based on a differential pair, see in particular fig. 2. The pair of input transistors of the comparator 101 are PMOS transistors, and specifically, the first input terminal and the second input terminal are gates of the PMOS transistors. The first preset value is selected according to the following principle: when the voltage of the node C1 is lower than the first preset value, the transistor MN10 enters a linear region. The comparator 101 compares the voltage inputted to the source of the pair transistor (i.e., the voltage of the node C1) with the voltage Vtarget having the first preset value. When the voltage input to the sources of the pair transistors is smaller than a first preset value (about 0.1V), the comparator 101 outputs a high level, and when the voltage input to the sources of the pair transistors is larger than the first preset value, the comparator 101 outputs a low level.
In some embodiments, the feedback circuit 100 further comprises a Complementary To Absolute Temperature (CTAT) voltage generating circuit for generating the voltage Vtarget with the first preset value.
The output end of the comparator 101 is connected with the input end of the source follower, and the output end of the source follower is connected with the substrates of the input pair transistors. The source follower includes an NMOS transistor MN13 and a load. The NMOS transistor MN13 and the load are connected in series between the voltage terminal N1 and ground. The load is, for example, a resistor, a current source, etc. In fig. 1, a current source is taken as an example. The gate of the NMOS transistor MN13 is the input terminal of the source follower, and is connected to the output terminal of the comparator 101, and the source of the NMOS transistor MN13 is the output terminal of the source follower, and is connected to the substrate of the pair of input transistors. The drain of the NMOS transistor MN13 is connected to the voltage terminal N1, and a voltage (e.g., 0.4V) provided from the voltage terminal N1 is applied to the substrate of the input pair transistor through the turned-on NMOS transistor MN 13.
In this embodiment, when the source voltage of the input pair transistor is lower than the first preset value, the feedback circuit applies a voltage to the substrate of the output pair transistor, so as to reduce the threshold voltage of the input pair transistor and increase the bias current provided by the transistor MN 10.
As shown in fig. 5, a schematic diagram of a differential amplifier circuit according to a second embodiment of the present invention is provided. In the differential amplifier circuit according to the second embodiment, the first input transistor MP21 and the second input transistor MP22 as the pair input transistors are PMOS transistors. The transistor providing the bias current is a PMOS transistor MP20.NMOS transistors MN21 and MN22 act as current mirror loads for the input pair transistors. The Input terminal Input of the feedback circuit 100 is connected to the sources (node C2) of the first and second Input transistors MP21 and MP22, and the output terminal output of the feedback circuit 100 is connected to the substrates of the first and second Input transistors MP21 and MP 22. When the source voltages of the first and second input transistors MP21 and MP22 are greater than or equal to the second preset value, the feedback circuit 100 applies a positive voltage to the substrates of the first and second input transistors MP21 and MP 22.
The feedback circuit 100 includes a comparator 101 and a source follower. A first input terminal of the comparator 101 is connected to the node C2 as an input terminal of the feedback circuit 100, and a second input terminal of the comparator 101 is connected to a voltage Vtarget with a second predetermined value. The feedback circuit 100 further comprises a CTAT voltage generating circuit for generating a voltage Vtarget of said second predetermined value. The comparator 101 may also be implemented based on a differential pair, and the input pair transistors of the comparator 101 are NMOS transistors.
The source follower includes a PMOS transistor MP23 and a current source. The PMOS transistor MP23 and the current source are connected in series between the voltage terminal N2 and the power supply terminal. The voltage terminal N2 is used for providing a second voltage. The drain of the PMOS transistor is connected to the voltage terminal N2, the gate of the PMOS transistor MP23 is connected to the output terminal of the comparator 101, and the source of the PMOS transistor MP23 is connected to the substrates of the first input transistor MP21 and the second input transistor MP22, wherein the second voltage is 0.4V lower than the power voltage VDD.
When the voltage of the node C2 is higher than a second preset value (e.g., VDD-0.1V), the comparator 101 outputs a low level, and a second voltage is applied to the substrates of the first and second input transistors MP21 and MP22 through the PMOS transistor MP23, so that the threshold voltages of the first and second input transistors MP21 and MP22 are reduced, the voltage of the node C2 is raised, and the PMOS transistor MP20 that supplies the bias current has a sufficient drain-source voltage, and does not enter the linear region. When the voltage of the node C2 is lower than the second preset value, the comparator 101 outputs a high level.
Fig. 5 is a schematic structural diagram of a memory according to a third embodiment of the present invention. The memory 400 includes a peripheral circuit 600 and a memory cell array 500. Wherein the peripheral circuit 600 comprises the differential amplifying circuit 10 according to any of the above embodiments of the present invention. The memory is, for example, a Flash memory (Flash) including a NAND Flash memory and a NOR Flash memory. The peripheral circuit 600 includes, for example, a control logic, a read/write circuit, a decoder, an operation voltage generation circuit, and the like. The peripheral circuit 600 controls various operations of the memory cell array 500, such as a read operation, a write operation, an erase operation, and the like. The operation voltage generating circuit is used for providing operation voltages in reading operation, writing operation and erasing operation. The differential amplifier circuit 10 can be applied to an operating voltage generating circuit, a read/write circuit.
The principles and embodiments of the present invention have been explained herein using specific embodiments, which are merely used to help understand the method and its core ideas of the present invention; meanwhile, for those skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.

Claims (10)

1. A differential amplification circuit, comprising:
inputting a pair of tubes; and
a feedback circuit that applies a voltage to the substrate of the output pair transistor based on the source voltage of the input pair transistor.
2. The differential amplifier circuit according to claim 1, wherein the input pair transistors are NMOS transistors, and the feedback circuit applies a positive voltage to the substrates of the input pair transistors when source voltages of the input pair transistors are lower than a first preset value.
3. The differential amplifier circuit of claim 1, wherein the input pair transistors are PMOS transistors, and wherein the feedback circuit applies a positive voltage to the substrates of the input pair transistors when the source voltages of the input pair transistors are above a second predetermined value.
4. The differential amplifier circuit of claim 2, wherein the feedback circuit comprises a comparator and a source follower, the source follower comprises an NMOS transistor and a current source, the NMOS transistor and the current source are connected in series between a voltage terminal and ground, the voltage terminal is used for providing a first voltage, a drain of the NMOS transistor is connected to the voltage terminal, a gate of the NMOS transistor is connected to the output terminal of the comparator, and a source of the NMOS transistor is connected to the substrate of the input pair transistor.
5. The differential amplifier circuit according to claim 4, wherein the feedback circuit further comprises a complementary to absolute temperature voltage generating circuit for supplying a voltage of the first predetermined value to the input terminal of the comparator.
6. The differential amplification circuit according to claim 4, wherein the first voltage is 0.4V.
7. The differential amplifier circuit of claim 3, wherein the feedback circuit comprises a comparator and a source follower, the source follower comprises a PMOS transistor and a current source, the PMOS transistor and the current source are connected in series between a voltage terminal and a power supply, the voltage terminal is used for providing a second voltage, a drain of the PMOS transistor is connected to the voltage terminal, a gate of the PMOS transistor is connected to the output terminal of the comparator, and a source of the PMOS transistor is connected to the substrates of the input pair transistors.
8. The differential amplifier circuit of claim 7, wherein the feedback circuit further comprises a complementary-to-absolute-temperature voltage generating circuit for providing a voltage of the second predetermined value to the input of the comparator.
9. The differential amplification circuit of claim 7, wherein the second voltage is less than 0.4V below a supply voltage.
10. A memory comprising an array of memory cells and a differential amplifying circuit as claimed in any one of claims 1 to 9.
CN202110704099.3A 2021-06-24 2021-06-24 Differential amplifier circuit and memory Pending CN115529014A (en)

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CN202110704099.3A CN115529014A (en) 2021-06-24 2021-06-24 Differential amplifier circuit and memory

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CN202110704099.3A CN115529014A (en) 2021-06-24 2021-06-24 Differential amplifier circuit and memory

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CN115529014A true CN115529014A (en) 2022-12-27

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