CN115529014A - Differential amplifier circuit and memory - Google Patents

Abstract

The invention discloses a differential amplifier circuit and a memory. The differential amplifier circuit includes: an input pair tube; and a feedback circuit. The feedback circuit applies a voltage to the substrate of the output pair of transistors based on the source voltage of the input pair of transistors. By applying a voltage to the substrate of the input-to-transistor, the threshold voltage of the input-to-transistor is reduced, so that the transistor providing the bias current has enough drain-source voltage to be in the saturation region, preventing the transistor providing the bias current from entering the linear region resulting performance degradation.

Description

Differential amplifier circuit and memory

technical field

The invention relates to the field of analog circuits, in particular to a differential amplifier circuit and a memory.

Background technique

The differential amplifier circuit is widely used in the peripheral circuit of the memory (Peripheral circuit). A differential amplifier circuit usually includes an input pair of transistors, a load, and a transistor for providing bias current. The threshold voltage of transistors in flash memory technology is much higher than that in logic technology. In low-power low-voltage applications, excessively high transistor threshold voltages limit the use and performance of many differential amplifier circuits. For example, if the threshold voltage of the input pair transistor is too high, the drain-to-source voltage of the transistor that provides the bias current will be lower, and the transistor that provides the bias current will enter the linear region, resulting in a decrease in the bias current and affecting the performance of the differential amplifier circuit. .

Contents of the invention

The embodiment of the present invention provides a differential amplifier circuit and memory to solve the problem that the bias current transistor enters the linear region caused by the high threshold voltage of the input pair transistor in the flash memory chip.

According to one aspect of the present invention, the present invention provides a differential amplifier circuit, the differential amplifier circuit includes: an input pair of transistors; and a feedback circuit, the feedback circuit is based on the source voltage of the input pair of transistors to the output pair A voltage is applied to the substrate of the tube.

Further, the input pair transistor is an NMOS transistor, and when the source voltage of the input pair transistor is lower than a first preset value, the feedback circuit applies a positive voltage to the substrate of the input pair transistor.

Further, the input pair transistor is a PMOS transistor, and when the source voltage of the input pair transistor is lower than the preset value, the feedback circuit applies a positive voltage to the substrate of the input pair transistor.

Further, the input pair transistor is a PMOS transistor, and when the source voltage of the input pair transistor is higher than a second preset value, the feedback circuit applies a positive voltage to the substrate of the input pair transistor.

Further, the input pair is an NMOS transistor, the feedback circuit includes a comparator and a source follower, the source follower includes an NMOS transistor and a current source, and the NMOS transistor and the current source are connected in series between the voltage terminal and the Between the ground, the voltage terminal is used to provide the first voltage, the drain of the NMOS transistor is connected to the voltage terminal, the gate of the NMOS transistor is connected to the output terminal of the comparator, and the source of the NMOS transistor is connected to the The input pairs to the substrate of the tube. The first voltage is 0.4V.

Further, the feedback circuit further includes an absolute temperature complementary voltage generating circuit, configured to provide a voltage equal to the first preset value to the input terminal of the comparator.

Further, the input pair is a PMOS transistor, the feedback circuit includes a comparator and a source follower, the source follower includes a PMOS transistor and a current source, and the PMOS transistor and the current source are connected in series between the voltage terminal and the Between power supplies, the voltage terminal is used to provide a second voltage, the drain of the PMOS transistor is connected to the voltage terminal, the gate of the PMOS transistor is connected to the output terminal of the comparator, and the source of the PMOS transistor is connected to the The input pairs to the substrate of the tube. The second voltage is 0.4V lower than the power supply voltage.

Further, the feedback circuit further includes a voltage generation circuit complementary to the absolute temperature, configured to provide a voltage equal to the second preset value to the input terminal of the comparator.

According to another aspect of the present invention, the present invention provides a memory, and the memory includes the differential amplifier circuit described in any embodiment of the present invention.

By applying a voltage to the substrate of the input-to-tube, the threshold voltage of the input-to-tube is reduced, so that the transistor that provides the bias current has enough drain-source voltage to be in the saturation region, preventing the transistor that provides the bias current from entering the linear region resulting performance degradation.

Description of drawings

The technical solutions and other beneficial effects of the present invention will be apparent through the detailed description of specific embodiments of the present invention in conjunction with the accompanying drawings.

FIG. 1 is a circuit diagram of a differential amplifier circuit provided by Embodiment 1 of the present invention.

FIG. 2 is a circuit diagram of a comparator provided by an embodiment of the present invention.

FIG. 3 is a schematic structural diagram of an N-type MOS transistor provided by an embodiment of the present invention.

FIG. 4 is a circuit diagram of a differential amplifier circuit provided by Embodiment 2 of the present invention.

FIG. 5 is a schematic diagram of a memory provided by Embodiment 3 of the present invention.

detailed description

The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention. Apparently, the described embodiments are only some of the embodiments of the present invention, but not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative efforts fall within the protection scope of the present invention.

In the description of the present invention, it should be noted that unless otherwise specified and limited, the terms "installation", "connection" and "connection" should be understood in a broad sense, for example, it can be a fixed connection or a detachable connection. Connected, or integrally connected; it can be mechanically connected, or electrically connected, or can communicate with each other; it can be directly connected, or indirectly connected through an intermediary, and it can be the internal communication of two components or the interaction of two components relation. Those of ordinary skill in the art can understand the specific meanings of the above terms in the present invention according to specific situations.

As shown in FIG. 1 , it is a schematic structural diagram of a differential amplifier circuit provided by Embodiment 1 of the present invention. The differential amplifier circuit includes: an input pair transistor and a feedback circuit 100 . The input pair includes a first input transistor MN11 and a second input transistor MN12. The gate of the first input transistor MN1 serves as the first input terminal VIN, and the gate of the second input transistor MN2 serves as the second input terminal VIP. The differential amplifier circuit receives a differential signal at a first input terminal and a second input terminal.

The differential amplifier circuit also includes: transistor MN10, transistor MP11, and transistor MP12. The gate of the transistor MN10 receives a bias voltage, and the drain of the transistor MN10 is connected to the source of the input pair transistor (node C1 ). Transistor MN10 is used to provide bias current for the input pair transistor. Transistor MP11 and transistor M12 are the loads of the input pair. Transistor MP11 is arranged diode-connected. The gates of the transistor MP11 and the transistor M12 are connected to the drain of the first input transistor MN11. The transistor MP11 and the transistor M12 constitute a current mirror. The current mirror mirrors the current of the first input transistor MN11 to the transistor MP12. The drain terminal of the transistor M12 serves as the output terminal of the differential amplifier circuit.

In the differential amplifier circuit shown in FIG. 1 , the input pair transistors are NMOS transistors, the transistor MN10 is an NMOS transistor, and the transistors MP11 and MP12 are PMOS transistors. The first input transistor MN11 and the second input transistor MN12 in the differential amplifier circuit are four-terminal devices, as shown in FIG. 4 , including source 12 , drain 11 , gate 14 , insulating layer 13 and substrate electrode 15 .

The input terminal input of the feedback circuit 100 is connected to the node C1, and the output terminal output of the feedback circuit 100 is connected to the substrate electrode 15 of the input pair tube. When the source voltage of the input pair tube is lower than the first preset value, the feedback circuit 100 applies a voltage to the substrate of the output pair tube, thereby reducing the threshold voltage of the input pair tube and increasing the voltage of node C1 , increasing the drain-source voltage of the transistor MN10 to prevent the transistor MN10 from entering the linear region.

The formula for the threshold voltage of an NMOS transistor is:

Φf is the Fermi potential of the substrate, γ is the body effect factor, V _BS is the voltage between the substrate and the source, and V _TH0 is the threshold voltage when V _BS is zero. When V _BS is greater than 0, the threshold voltage decreases. In order to prevent the parasitic diodes from the substrate to the source and drain to conduct forward, the substrate voltage is at most 0.4V. The substrate voltage of 0.4V can reduce the threshold voltages of the first input transistor MN11 and the second input transistor MN12 of the differential amplifier 10 by up to 100 millivolts, and improve the performance degradation of the differential amplifier caused by the high threshold of the input transistors.

The feedback circuit 100 includes a comparator 101 and a source follower. The comparator 101 has a first input terminal, a second input terminal, and an output terminal. The first input end is, for example, a negative input end, and the second input end is, for example, a positive input end. The first input terminal serves as the input terminal input of the feedback circuit 100 and is connected to the node C1, and the second input terminal receives a voltage Vtarget equal to the first preset value. The comparator 101 is also implemented based on a differential pair, specifically, refer to FIG. 2 . The input pair of transistors of the comparator 101 is a PMOS transistor, specifically, the first input terminal and the second input terminal are gates of the PMOS transistor. The selection principle of the first preset value is: when the voltage of the node C1 is lower than the first preset value, the transistor MN10 enters the linear region. The comparator 101 compares the voltage input to the source of the transistor (ie, the voltage at the node C1 ) with a voltage Vtarget equal to a first preset value. When the voltage input to the source of the tube is less than the first preset value (about 0.1V), the comparator 101 outputs a high level, and when the voltage input to the source of the tube is greater than the first preset value, the comparator 101 outputs low level.

In some embodiments, the feedback circuit 100 further includes a complementary to absolute temperature (complimentary to absolute temperature, CTAT) voltage generating circuit for generating a voltage Vtarget equal to the first preset value.

The output terminal of the comparator 101 is connected to the input terminal of the source follower, and the output terminal of the source follower is connected to the substrate of the input pair transistor. The source follower includes an NMOS transistor MN13 and a load. The NMOS transistor MN13 and the load are connected in series between the voltage terminal N1 and ground. The load is, for example, a resistor, a current source, or the like. Figure 1 takes the current source as an example. The gate of the NMOS transistor MN13 is the input terminal of the source follower, connected to the output terminal of the comparator 101, and the source of the NMOS transistor MN13 is the output terminal of the source follower, connected to the substrate of the input pair transistor. The drain of the NMOS transistor MN13 is connected to the voltage terminal N1, and the voltage (for example, 0.4V) provided by the voltage terminal N1 is applied to the substrate of the input pair transistor through the turned-on NMOS transistor MN13.

In this embodiment, when the source voltage of the input pair of tubes is lower than a first preset value, the feedback circuit applies a voltage to the substrate of the output pair of tubes, thereby reducing the threshold voltage of the input pair of tubes, The bias current provided by transistor MN10 is increased.

As shown in FIG. 5 , it is a schematic structural diagram of a differential amplifier circuit provided by Embodiment 2 of the present invention. In the differential amplifier circuit of the second embodiment, the first input transistor MP21 and the second input transistor MP22 as the input pair are PMOS transistors. The transistor providing the bias current is a PMOS transistor MP20. NMOS transistors MN21 and MN22 are used as the current mirror load of the input pair tube. The input terminal Input of the feedback circuit 100 is connected to the sources (node C2) of the first input transistor MP21 and the second input transistor MP22, and the output terminal output of the feedback circuit 100 is connected to the substrates of the first input transistor MP21 and the second input transistor MP22. When the source voltages of the first input transistor MP21 and the second input transistor MP22 are higher than the second preset value, the feedback circuit 100 applies a positive voltage to the substrates of the first input transistor MP21 and the second input transistor MP22 .

The feedback circuit 100 includes a comparator 101 and a source follower. The first input terminal of the comparator 101 serves as the input terminal of the feedback circuit 100 and is connected to the node C2, and the second input terminal of the comparator 101 is connected to a voltage Vtarget of a second predetermined value. The feedback circuit 100 further includes a CTAT voltage generating circuit for generating a voltage Vtarget equal to the second preset value. The comparator 101 can also be implemented based on a differential pair, and the input pair transistors of the comparator 101 are NMOS transistors.

The source follower includes a PMOS transistor MP23 and a current source. The PMOS transistor MP23 and the current source are connected in series between the voltage terminal N2 and the power supply terminal. The voltage terminal N2 is used to provide a second voltage. The drain of the PMOS transistor is connected to the voltage terminal N2, the gate of the PMOS transistor MP23 is connected to the output terminal of the comparator 101, and the source of the PMOS transistor MP23 is connected to the substrates of the first input transistor MP21 and the second input transistor MP22, wherein the first The second voltage is a voltage lower than the power supply voltage VDD by 0.4V.

When the voltage of node C2 is higher than the second preset value (such as VDD-0.1V), the comparator 101 outputs a low level, and the second voltage is applied to the first input transistor MP21 and the second input transistor MP22 through the PMOS transistor MP23. Substrate, so that the threshold voltage of the first input transistor MP21 and the second input transistor MP22 is reduced, and the voltage of the node C2 is increased, so that the PMOS transistor MP20 that provides the bias current has sufficient drain-source voltage, and will not enter the linear Area. When the voltage of the node C2 is lower than the second preset value, the comparator 101 outputs a high level.

FIG. 5 is a schematic structural diagram of a memory provided by Embodiment 3 of the present invention. The memory 400 includes a peripheral circuit 600 and a memory cell array 500 . The peripheral circuit 600 includes the differential amplifier circuit 10 described in any one of the above-mentioned embodiments of the present invention. The memory is, for example, flash memory (Flash), which includes NAND flash memory and NOR flash memory. The peripheral circuit 600 includes, for example, a control logic, a read/write circuit, a decoder, an operating voltage generating circuit, and the like. The peripheral circuit 600 controls various operations of the memory cell array 500, such as read operation, write operation, erase operation, and the like. The operating voltage generating circuit is used for providing operating voltages in read operation, write operation, and erase operation. The differential amplifier circuit 10 can be applied in operating voltage generation circuits and read/write circuits.

Application of specific embodiment herein has explained principle of the present invention and implementation mode, and the description of above embodiment is only used to help understanding method of the present invention and core idea thereof; Simultaneously, for those skilled in the art, according to the present invention Thoughts, specific implementation methods and scope of application all have changes. In summary, the contents of this specification should not be construed as limiting the present invention.

Claims (10)

1. A differential amplifier circuit, characterized in that, comprising: input pair; and A feedback circuit that applies a voltage to the substrate of the output pair of transistors based on the source voltage of the input pair of transistors. 2. The differential amplifier circuit according to claim 1, wherein the input pair of transistors is an NMOS transistor, and when the source voltage of the input pair of transistors is lower than a first preset value, the feedback circuit supplies The input applies a positive voltage to the substrate of the tube. 3. The differential amplifier circuit according to claim 1, wherein the input pair of transistors is a PMOS transistor, and when the source voltage of the input pair of transistors is higher than a second preset value, the feedback circuit supplies The input applies a positive voltage to the substrate of the tube. 4. The differential amplifier circuit according to claim 2, wherein the feedback circuit includes a comparator and a source follower, the source follower includes an NMOS transistor and a current source, and the NMOS transistor and the current source connected in series between the voltage terminal and the ground, the voltage terminal is used to provide a first voltage, the drain of the NMOS transistor is connected to the voltage terminal, the gate of the NMOS transistor is connected to the output terminal of the comparator, and the NMOS The source of the transistor is connected to the substrate of the input pair transistor. 5. The differential amplifier circuit according to claim 4, wherein the feedback circuit further comprises a voltage generation circuit complementary to absolute temperature, which is used to provide the input terminal of the comparator with a magnitude equal to the first preset value voltage. 6. The differential amplifier circuit according to claim 4, wherein the first voltage is 0.4V. 7. The differential amplifier circuit according to claim 3, wherein the feedback circuit comprises a comparator and a source follower, the source follower comprises a PMOS transistor and a current source, and the PMOS transistor and the current source connected in series between the voltage terminal and the power supply, the voltage terminal is used to provide a second voltage, the drain of the PMOS transistor is connected to the voltage terminal, the gate of the PMOS transistor is connected to the output terminal of the comparator, and the PMOS The source of the transistor is connected to the substrate of the input pair transistor. 8. The differential amplifier circuit according to claim 7, wherein the feedback circuit further comprises a voltage generation circuit complementary to absolute temperature, which is used to provide the input terminal of the comparator with a magnitude equal to the second preset voltage. value voltage. 9. The differential amplifier circuit according to claim 7, wherein the second voltage is 0.4V lower than the power supply voltage. 10. A memory, comprising a memory cell array and the differential amplifier circuit according to any one of claims 1-9.

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