CN115528038A - Flash memory device and method of manufacturing the same - Google Patents
Flash memory device and method of manufacturing the same Download PDFInfo
- Publication number
- CN115528038A CN115528038A CN202211202226.0A CN202211202226A CN115528038A CN 115528038 A CN115528038 A CN 115528038A CN 202211202226 A CN202211202226 A CN 202211202226A CN 115528038 A CN115528038 A CN 115528038A
- Authority
- CN
- China
- Prior art keywords
- side wall
- control gate
- layer
- flash memory
- memory device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 24
- 239000010410 layer Substances 0.000 claims abstract description 158
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 239000011229 interlayer Substances 0.000 claims abstract description 26
- 239000000463 material Substances 0.000 claims abstract description 18
- 239000002184 metal Substances 0.000 claims abstract description 13
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 13
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 13
- 238000000034 method Methods 0.000 claims description 41
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 14
- 229920005591 polysilicon Polymers 0.000 claims description 14
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 12
- 230000015654 memory Effects 0.000 claims description 10
- 239000011241 protective layer Substances 0.000 claims description 7
- 238000001039 wet etching Methods 0.000 claims description 7
- 125000006850 spacer group Chemical group 0.000 claims 2
- 238000005530 etching Methods 0.000 abstract description 10
- 230000015556 catabolic process Effects 0.000 abstract description 8
- 230000015572 biosynthetic process Effects 0.000 abstract description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 11
- 229910052814 silicon oxide Inorganic materials 0.000 description 11
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- 238000001312 dry etching Methods 0.000 description 4
- 239000002131 composite material Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000013500 data storage Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Non-Volatile Memory (AREA)
Abstract
The invention provides a flash memory device and a manufacturing method thereof, wherein a word line is arranged on a substrate of the flash memory device, a floating gate, an interlayer dielectric layer and a control gate which are vertically stacked are arranged on two sides of the word line, a first side wall is arranged on the control gate, the material of the first side wall is the same as that of the control gate, a second side wall is arranged between the control gate and the word line, and a third side wall is arranged between the floating gate and the word line. According to the invention, the first side wall and the control gate which are made of the same material are arranged, so that the etching damage possibly suffered by the first side wall is reduced or avoided, the step formation at the junction of the first side wall and the control gate layer is avoided, and the breakdown voltage of the flash memory device is further maintained. Furthermore, a metal silicide layer is arranged on the first side wall of the flash memory device, so that the contact resistance of a control gate is reduced, and the reading speed of the flash memory device is improved.
Description
Technical Field
The present invention relates to the field of integrated circuit manufacturing technologies, and in particular, to a flash memory device and a method for manufacturing the same.
Background
With the development of technology, data storage media applications are shifted from some traditional non-volatile memories to flash memory type memories, and mass solid-state storage devices with flash memories as main storage media have become one of the mainstream schemes for data storage nowadays. Nord flash memory (Nord flash) devices have become increasingly important in the memory field due to their performance advantages, such as low cost, low power consumption, and fast access speed. However, with the continuous scaling of the size of the Nord flash memory device, in order to avoid the decrease of the erasing performance and the operating voltage of the Nord flash memory device with the scaling of the device size, it is necessary to provide more strict requirements on the breakdown voltage inside the Nord flash memory device.
Referring to fig. 1, the nord flash memory device generally includes a Floating Gate (FG) 10 and a Control Gate (CG) 20 stacked together with a composite dielectric layer 30 (e.g., an ONO stack structure) formed between the Floating Gate 10 and the Control Gate 20. In the conventional preparation process of the Nord flash memory device, the first sidewall 40 formed on the surface of the control gate 20 is usually made of an Oxide (Oxide) material, and when the composite dielectric layer 30 is subsequently wet-etched, the first sidewall 40 is etched by hydrofluoric acid (HF) in the wet process, so that a step a is formed at the junction between the first sidewall 40 and the control gate 20. In the process of forming the second sidewall 41, since the second sidewall 41 covers the surface of the first sidewall 40 and the sidewall of the control gate layer 21 at the same time, and a step a is formed at the boundary between the first sidewall 40 and the control gate 20, the finally formed second sidewall 41 with a smooth surface may have uneven thickness, that is, the thickness of the portion of the second sidewall 41 covering the step a is the thinnest, thereby reducing the breakdown voltage between the subsequently formed control gate and the word line.
In view of this, a method is needed to reduce or avoid the etching damage to the first sidewall, and to avoid the step formed at the boundary between the first sidewall and the control gate layer, so as to maintain the breakdown voltage of the flash memory device.
Disclosure of Invention
The invention aims to provide a flash memory device and a manufacturing method thereof, which can reduce or avoid the etching damage possibly suffered by a first side wall and avoid the step formation at the junction of the first side wall and a control gate layer, thereby maintaining the breakdown voltage of the flash memory device.
In order to achieve the above object, the present invention provides a method of manufacturing a flash memory device, including:
providing a substrate, wherein a floating gate layer, an interlayer dielectric layer, a control gate layer and a hard mask layer are sequentially formed on the substrate, and an opening for exposing the control gate layer is formed on the hard mask layer;
forming a first side wall on the side wall of the opening, wherein the material of the first side wall is the same as that of the control gate layer;
removing the control gate layer exposed by the opening and the interlayer dielectric layer below the opening, exposing the floating gate layer by the opening, and forming a second side wall on the side wall and the bottom wall of the opening;
removing the second side wall at the bottom of the opening and the floating gate layer below the opening to enable the opening to expose the substrate, and forming a third side wall on the side wall and the bottom wall of the opening;
forming a word line in the opening; and the number of the first and second groups,
and removing the hard mask layer and the control gate layer, the interlayer dielectric layer and the floating gate layer below the hard mask layer to form a control gate and a floating gate.
Optionally, the control gate layer and the first sidewall are made of polysilicon.
Optionally, a wet etching process is used to remove the interlayer dielectric layer below the opening, and an etchant of the wet etching process is hydrofluoric acid.
Optionally, after forming the word line and before removing the hard mask layer, the method further includes:
forming a protective layer at least covering the word line.
Optionally, the second side wall covers a part of the surface of the first side wall.
Optionally, after the floating gate and the control gate are formed, the method further includes:
and forming a metal silicide layer on the surface of the first side wall.
Accordingly, the present invention also provides a flash memory device comprising:
a substrate;
word lines disposed on the substrate;
floating gates disposed at both sides of the word lines;
the control gate is arranged on the floating gate;
the interlayer dielectric layer is arranged between the floating gate and the control gate;
the first side wall is arranged on the control gate, and the material of the first side wall is the same as that of the control gate;
the second side wall is arranged between the control gate and the word line, and at least covers part of the surface of the first side wall and the side wall of the control gate; and the number of the first and second groups,
and the third side wall is arranged between the floating gate and the word line, and at least covers part of the surface of the second side wall and the side wall of the floating gate.
Optionally, the control gate and the first sidewall are made of polysilicon.
Optionally, the flash memory device further includes a metal silicide layer disposed on the first sidewall.
Optionally, the flash memory device is a nor flash memory.
In summary, the present invention provides a flash memory device and a method for manufacturing the same, wherein a word line is disposed on a substrate of the flash memory device, a floating gate, an interlayer dielectric layer and a control gate which are vertically stacked are disposed on two sides of the word line, a first side wall is disposed on the control gate, the material of the first side wall is the same as that of the control gate, a second side wall is disposed between the control gate and the word line, and a third side wall is disposed between the floating gate and the word line. According to the invention, the first side wall and the control gate which are made of the same material are arranged, so that the etching damage possibly suffered by the first side wall is reduced or avoided, the step formation at the junction of the first side wall and the control gate layer is avoided, and the breakdown voltage of the flash memory device is further maintained.
Furthermore, a metal silicide layer is arranged on the first side wall of the flash memory device, so that the contact resistance of a control gate is reduced, and the reading speed of the flash memory device is improved.
Drawings
FIG. 1 is a diagram of a Nord flash memory;
fig. 2 is a flowchart of a method for manufacturing a flash memory device according to an embodiment of the invention;
fig. 3 to 13 are schematic structural diagrams corresponding to steps in a method for manufacturing a flash memory device according to an embodiment of the invention;
wherein the reference numbers are as follows:
10-a floating gate; 20 a control gate; 30-a composite dielectric layer; 40-a first side wall; 41-a second side wall; a-a step;
100-a substrate; 101-a gate oxide layer; 110-a floating gate layer; 111-floating gate; 120-interlayer dielectric layer; 130-control gate layer; 131-a control gate; 140-a hard mask layer; 150-opening; 151-first side wall; 152-a second side wall; 153-third side wall; 160-word lines; 161-a protective layer; 170-metal silicide layer.
Detailed Description
The following describes in more detail embodiments of the present invention with reference to the schematic drawings. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Fig. 2 is a flowchart of a method for manufacturing a flash memory device according to an embodiment of the invention. Referring to fig. 2, the method for manufacturing the flash memory device according to the present embodiment includes:
step S01: providing a substrate, wherein a floating gate layer, an interlayer dielectric layer, a control gate layer and a hard mask layer are sequentially formed on the substrate, and an opening for exposing the control gate layer is formed on the hard mask layer;
step S02: forming a first side wall on the side wall of the opening, wherein the material of the first side wall is the same as that of the control gate layer;
step S03: removing the control gate layer exposed by the opening and the interlayer dielectric layer below the opening to enable the opening to expose the floating gate layer and form second side walls on the side walls and the bottom wall of the opening;
step S04: removing the second side wall at the bottom of the opening and the floating gate layer below the opening to enable the opening to expose the substrate, and forming a third side wall on the side wall and the bottom wall of the opening;
step S05: forming a word line in the opening; and the number of the first and second groups,
step S06: and removing the hard mask layer and the control gate layer, the interlayer dielectric layer and the floating gate layer below the hard mask layer to form a control gate and a floating gate.
Fig. 3 to 13 are schematic structural diagrams corresponding to each step in the manufacturing method of the flash memory device provided in this embodiment, and the manufacturing method of the flash memory device according to this embodiment is described in detail below with reference to fig. 3 to 13.
First, referring to fig. 3, step S01 is performed to provide a substrate 100, on which a floating gate layer 110, an interlayer dielectric layer 120, a control gate layer 130 and a hard mask layer 140 are sequentially formed, and an opening 150 exposing the control gate layer 140 is formed on the hard mask layer 140.
In this embodiment, the hard mask layer 140 is subjected to a photolithography process and an etching process to pattern the hard mask layer 140, thereby forming the opening 150. Optionally, a gate oxide layer 101 is further formed between the substrate 100 and the floating gate layer 110.
In this embodiment, the substrate 100 is a silicon substrate. The gate oxide layer 110 is a silicon oxide layer. The floating gate layer 110 and the control gate layer 130 are both polysilicon layers. The interlayer dielectric layer 120 is an ONO stacked structure formed by stacking a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer. In other embodiments of the present invention, the material of each film layer in the flash memory device shown in fig. 3 may be selected according to actual needs, which is not limited by the present invention.
Next, referring to fig. 4 and 5, step S02 is performed to form a first sidewall 151 on a sidewall of the opening 150, where a material of the first sidewall 151 is the same as a material of the control gate layer 130.
Illustratively, the process of forming the first side walls 151 includes: first, referring to fig. 4, a first sidewall 151 is deposited in the opening 150, and the first sidewall 151 extends to cover the hard mask layer 140 on two sides of the opening 150; next, referring to fig. 5, the first sidewalls 151 are etched, and the first sidewalls 151 on the hard mask layer 140 and the first sidewalls 151 at the bottom of the opening 150 are removed, so that the remaining first sidewalls 151 cover the sidewalls of the opening 150 and a portion of the surface of the control gate layer 130. Optionally, the first sidewall 151 is formed by a chemical vapor deposition process, and the first sidewall 151 is etched by a dry etching process.
In this embodiment, the control gate layer 130 is made of polysilicon, and the control gate layer 130 is made of the same material as the first sidewall 151, so that the first sidewall 151 is made of polysilicon.
Subsequently, referring to fig. 6 and 7, step S03 is performed to remove the control gate layer 130 exposed by the opening 150 and the interlayer dielectric layer 120 under the opening 150, so that the opening 150 exposes the floating gate layer 110, and form a second sidewall 152 on the sidewall and the bottom wall of the opening 150.
Illustratively, the process of forming the second side walls 152 includes: firstly, referring to fig. 6, a dry etching process is adopted to remove the control gate layer 130 exposed by the opening 150, and then a wet etching process is adopted to remove the interlayer dielectric layer 120 below the opening 150, so that the floating gate layer 110 below the opening 150 is exposed; next, referring to fig. 7, a second sidewall 152 is formed on the sidewall and the bottom wall of the opening 150 (the forming process of the second sidewall 152 is similar to the forming process of the first sidewall 151, and is not repeated herein). Optionally, an etchant of the wet etching process is hydrofluoric acid (HF).
It should be noted that, because the first sidewall 151 is made of polysilicon, the first sidewall 151 is not etched by an etchant (i.e., hydrofluoric acid) during the wet etching process to remove the interlayer dielectric layer 120 under the opening 150, so that a step is prevented from occurring at a boundary between the first sidewall 151 and the control gate layer 130.
In this embodiment, the second side wall 152 covers a part of the surface of the first side wall 151, and in other embodiments of the present invention, the second side wall 152 may also completely cover the surface of the first side wall 151, which is not limited in the present invention. Alternatively, the second sidewall 152 may be a silicon oxide layer, a silicon nitride layer, or a stacked structure of the two.
Next, referring to fig. 8 and 9, step S04 is performed to remove the second sidewall 152 at the bottom of the opening 150 and the floating gate layer 110 under the opening 150, so that the opening 150 exposes the substrate 100, and a third sidewall 153 is formed on the sidewall and the bottom wall of the opening 150.
Illustratively, the process of forming the third side walls 153 includes: firstly, referring to fig. 8, removing the second sidewall 152 at the bottom of the opening 150, and the floating gate layer 110 and the gate oxide layer 101 below the opening 150 by using a dry etching process, so as to expose the substrate 100 below the opening 150; next, referring to fig. 9, a third sidewall 153 is formed on the sidewall and the bottom wall of the opening 150 (the forming process of the third sidewall 153 is similar to the forming process of the first sidewall 151, and is not repeated here).
In this embodiment, the third side wall 153 covers a part of the surface of the second side wall 155, in other embodiments of the present invention, the third side wall 153 may also completely cover the surface of the second side wall 152, which is not limited in the present invention. Optionally, the third sidewall 153 is a silicon oxide layer.
Subsequently, referring to fig. 10 and 11, step S05 is performed to form a word line 160 in the opening 150.
Illustratively, referring to fig. 10, the process of forming the word line 160 includes: firstly, filling a polysilicon layer (not shown) in the opening 150, wherein the polysilicon layer extends to cover the hard mask layer 140 on both sides of the opening 150; next, the polysilicon layer is etched to remove the polysilicon layer on the hard mask layer 140, thereby forming a word line 160 in the opening 150. In this embodiment, the word line 160 is a polysilicon layer.
Referring to fig. 11, after forming the word line 160 and before performing step S06, the method for manufacturing a flash memory device according to the present embodiment further includes: a protective layer 161 is formed covering at least the word line 160. Optionally, the protective layer 161 is a silicon oxide layer or a silicon nitride layer.
Next, referring to fig. 12, step S06 is performed to remove the hard mask layer 140 and the control gate layer 130, the interlayer dielectric layer 120 and the floating gate layer 110 under the hard mask layer 140 to form the control gate 131 and the floating gate 111. In this embodiment, the hard mask layer 140 and the control gate layer 130, the interlayer dielectric layer 120, the floating gate layer 110 and the gate oxide layer 101 under the hard mask layer 140 are removed by a dry etching process. The protective layer 161 protects the word line 160 from being damaged during the etching process, and the protective layer is removed together during the etching process.
In addition, referring to fig. 13, after the floating gate 111 and the control gate 131 are formed, the method for manufacturing the flash memory device according to the present embodiment further includes: a metal silicide layer 170 is formed on the surface of the first sidewall 151.
It should be noted that, if the second side walls 152 formed in the step S02 only cover a part of the surface of the first side walls 151, the metal silicide layer 170 may be directly formed on the exposed part of the surface of the first side walls 151; if the second side walls 152 formed in step S02 completely cover the surfaces of the first side walls 151, an etching process is performed to remove a portion of the second side walls 152 on the first side walls 151, so that a portion of the surfaces of the first side walls 151 are exposed, and then the metal silicide layer 170 is formed on the exposed surfaces of the first side walls 151.
Accordingly, with continued reference to fig. 13, the present invention also provides a flash memory device comprising:
a substrate 100;
a word line 160 disposed on the substrate 100;
floating gates 111 disposed at both sides of the word line 160;
a control gate 131 disposed on the floating gate 111;
an interlayer dielectric layer 120 disposed between the floating gate 111 and the control gate 131;
a first sidewall 151 disposed on the control gate 131, wherein the material of the first sidewall 151 is the same as that of the control gate 131;
a second sidewall 152 disposed between the control gate 131 and the word line 160, wherein the second sidewall 152 at least covers a part of the surface of the first sidewall 151 and a sidewall of the control gate 131; and the number of the first and second groups,
and a third sidewall 153 disposed between the floating gate 111 and the word line 160, wherein the third sidewall 153 covers at least a part of the surface of the second sidewall 152 and the sidewall of the floating gate 111.
In this embodiment, the word line 160, the floating gate 111, the control gate 131, and the first sidewall 151 are all made of polysilicon. The substrate 100 is a silicon substrate. The interlayer dielectric layer 120 is an ONO stacked structure formed by stacking a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer. The second sidewall 152 is a stacked structure of silicon oxide layers, silicon nitride layers, or both. The third sidewall 153 is a silicon oxide layer. Optionally, a gate oxide layer 101 is further disposed between the substrate 100 and the floating gate 111, and the gate oxide layer 101 is a silicon oxide layer. Optionally, the flash memory device further includes a metal silicide layer 170 disposed on the first sidewall 151.
In this embodiment, the flash memory device is a nor flash memory, the manufacturing method of the flash memory device may be used to prepare the nor flash memory device, in other embodiments of the present invention, the flash memory device may be other semiconductor devices having the same or similar structure, and the manufacturing method of the flash memory device may be used to manufacture other semiconductor devices having the same or similar structure, which is not limited in this disclosure.
As can be seen from comparing fig. 1 and fig. 13, by arranging the first side wall and the control gate which are made of the same material, the invention reduces or prevents the first side wall from being damaged by etching, thereby preventing a step from being formed at a junction of the first side wall and the control gate layer, and further maintaining the breakdown voltage of the flash memory device. In addition, the metal silicide layer is arranged on the first side wall of the flash memory device, so that the contact resistance of a control gate is reduced, and the reading speed of the flash memory device is improved.
In summary, the present invention provides a flash memory device and a method for manufacturing the same, wherein a word line is disposed on a substrate of the flash memory device, a floating gate, an interlayer dielectric layer and a control gate which are vertically stacked are disposed on two sides of the word line, a first side wall is disposed on the control gate, the material of the first side wall is the same as that of the control gate, a second side wall is disposed between the control gate and the word line, and a third side wall is disposed between the floating gate and the word line. According to the invention, the first side wall and the control gate which are made of the same material are arranged, so that the etching damage possibly suffered by the first side wall is reduced or avoided, the step formation at the junction of the first side wall and the control gate layer is avoided, and the breakdown voltage of the flash memory device is further maintained.
Furthermore, a metal silicide layer is arranged on the first side wall of the flash memory device, so that the contact resistance of a control gate is reduced, and the reading speed of the flash memory device is improved.
The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any way. It will be understood by those skilled in the art that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A method of manufacturing a flash memory device, comprising:
providing a substrate, wherein a floating gate layer, an interlayer dielectric layer, a control gate layer and a hard mask layer are sequentially formed on the substrate, and an opening for exposing the control gate layer is formed on the hard mask layer;
forming a first side wall on the side wall of the opening, wherein the material of the first side wall is the same as that of the control gate layer;
removing the control gate layer exposed by the opening and the interlayer dielectric layer below the opening to enable the opening to expose the floating gate layer and form second side walls on the side walls and the bottom wall of the opening;
removing the second side wall at the bottom of the opening and the floating gate layer below the opening to enable the opening to expose the substrate, and forming a third side wall on the side wall and the bottom wall of the opening;
forming word lines in the openings; and the number of the first and second groups,
and removing the hard mask layer and the control gate layer, the interlayer dielectric layer and the floating gate layer below the hard mask layer to form a control gate and a floating gate.
2. The method of claim 1, wherein the control gate layer and the first sidewall spacers are made of polysilicon.
3. The method of claim 1, wherein the interlayer dielectric layer under the opening is removed by a wet etching process, and an etchant of the wet etching process is hydrofluoric acid.
4. The method of manufacturing a flash memory device according to claim 1, wherein after forming the word line and before removing the hard mask layer, further comprising:
and forming a protective layer at least covering the word lines.
5. The method of manufacturing a flash memory device according to claim 1, wherein the second sidewall covers a part of a surface of the first sidewall.
6. The method of manufacturing a flash memory device according to claim 5, further comprising, after forming the floating gate and the control gate:
and forming a metal silicide layer on the surface of the first side wall.
7. A flash memory device, comprising:
a substrate;
word lines disposed on the substrate;
the floating gates are arranged on two sides of the word lines;
the control gate is arranged on the floating gate;
the interlayer dielectric layer is arranged between the floating gate and the control gate;
the first side wall is arranged on the control gate, and the material of the first side wall is the same as that of the control gate;
the second side wall is arranged between the control gate and the word line, and at least covers part of the surface of the first side wall and the side wall of the control gate; and (c) a second step of,
and the third side wall is arranged between the floating gate and the word line, and at least covers part of the surface of the second side wall and the side wall of the floating gate.
8. The flash memory device of claim 1, wherein the control gate and the first sidewall spacers are both polysilicon.
9. The flash memory device of claim 1, further comprising a metal silicide layer disposed on the first sidewall.
10. The flash memory device of claim 1, wherein the flash memory device is a Nord flash memory.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211202226.0A CN115528038A (en) | 2022-09-29 | 2022-09-29 | Flash memory device and method of manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211202226.0A CN115528038A (en) | 2022-09-29 | 2022-09-29 | Flash memory device and method of manufacturing the same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115528038A true CN115528038A (en) | 2022-12-27 |
Family
ID=84699405
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211202226.0A Pending CN115528038A (en) | 2022-09-29 | 2022-09-29 | Flash memory device and method of manufacturing the same |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115528038A (en) |
-
2022
- 2022-09-29 CN CN202211202226.0A patent/CN115528038A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11056498B2 (en) | Semiconductor device and manufacturing method therefor | |
| CN106356374B (en) | Flash memory and manufacturing method thereof | |
| JP2002359308A (en) | Semiconductor memory and its fabricating method | |
| US20070128797A1 (en) | Flash memory device and method for fabricating the same | |
| US6984559B2 (en) | Method of fabricating a flash memory | |
| CN112071844B (en) | Mask plate of flash memory device and manufacturing method | |
| US7713820B2 (en) | Method for manufacturing non-volatile memory | |
| CN113192824B (en) | Mask plate of split gate type flash memory and manufacturing method | |
| CN115528038A (en) | Flash memory device and method of manufacturing the same | |
| CN113394222A (en) | Preparation method of flash memory | |
| US7592036B2 (en) | Method for manufacturing NAND flash memory | |
| CN115528039A (en) | Flash memory device and method of manufacturing the same | |
| CN113903789A (en) | Flash memory and manufacturing method and operating method thereof | |
| CN113451318A (en) | Semiconductor device and forming method thereof | |
| US20090065846A1 (en) | Non-volatile memory and manufacturing method thereof | |
| US20090047765A1 (en) | Method of manufacturing non-volatile memory | |
| US7109082B2 (en) | Flash memory cell | |
| CN115528040A (en) | Method for manufacturing flash memory device | |
| CN113380812B (en) | Method for forming semiconductor device | |
| KR100602126B1 (en) | Flash memory cell and method for manufacturing the same | |
| CN115835634A (en) | Method for manufacturing flash memory device | |
| CN115000071A (en) | Flash memory device and method of manufacturing the same | |
| US7060561B2 (en) | Method for fabricating memory device | |
| CN115811883A (en) | Method for manufacturing flash memory device | |
| CN115084148A (en) | Method for manufacturing flash memory device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |