CN115527479A - Display panel and display device - Google Patents

Display panel and display device Download PDF

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Publication number
CN115527479A
CN115527479A CN202211209189.6A CN202211209189A CN115527479A CN 115527479 A CN115527479 A CN 115527479A CN 202211209189 A CN202211209189 A CN 202211209189A CN 115527479 A CN115527479 A CN 115527479A
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China
Prior art keywords
sub
line
electrically connected
metal layer
display panel
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CN202211209189.6A
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Chinese (zh)
Inventor
陆韦
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Xiamen Tianma Display Technology Co Ltd
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Xiamen Tianma Display Technology Co Ltd
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Priority to CN202211209189.6A priority Critical patent/CN115527479A/en
Publication of CN115527479A publication Critical patent/CN115527479A/en
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Abstract

The invention discloses a display panel and a display device, wherein a first shift register and a second shift register of the display panel are both driven by a single side, the first shift register provides a light-emitting control signal, the second shift register provides a first control signal, the first shift register is electrically connected with the light-emitting control signal line through a first connecting line, the connecting point of the first connecting line and the light-emitting control signal line is positioned in the middle area of a display area, and/or the second shift register is electrically connected with a first scanning signal line through a second connecting line, and the connecting point of the second connecting line and the first scanning signal line is positioned in the middle area.

Description

Display panel and display device
Technical Field
The present invention relates to the field of display technologies, and in particular, to a display panel and a display device.
Background
Currently, display technologies have penetrated various aspects of people's daily lives, and accordingly, more and more materials and technologies are used for display screens. The display panel is used as an important component of the display device to realize the display function of the display device. Nowadays, the mainstream display screen mainly includes a liquid crystal display panel and an Organic Light-Emitting display panel (OLED).
Organic Light Emitting Diodes (OLEDs) are increasingly used in high performance display as a current-mode light emitting device, and OLED display panels have many excellent characteristics such as self-luminescence, wide viewing angle, fast response speed, high contrast, wide color gamut, low energy consumption, thin panels, rich colors, flexible display, and wide operating temperature range, and are therefore known as "star" flat panel display technologies of the next generation. The OLED display panel comprises an anode, a cathode, a hole transport layer, an organic light emitting layer and an electron transport layer, wherein the hole transport layer, the organic light emitting layer and the electron transport layer are arranged between the anode and the cathode, the anode provides hole injection, the cathode provides electron injection, holes and electrons injected by the cathode and the anode are combined in the organic light emitting layer under the driving of an external voltage to form electron hole pairs (namely excitons) at a bound energy level, and the excitons are radiated and de-excited to emit photons to generate visible light.
In a driving circuit of an organic light emitting display panel in the prior art, 7T1C (T is a transistor, and C is a storage capacitor), 8T1C, 16T1C and the like are generally used, but the problem of uneven pixel column display exists.
Therefore, it is desirable to provide a display panel and a display device capable of improving the display unevenness of the pixel rows.
Disclosure of Invention
In view of the above, the present invention provides a display panel and a display device, which are used to solve the problem of non-uniform display of pixel columns.
In one aspect, the present invention provides a display panel, comprising: a display area and a non-display area at least partially surrounding the display area, the display area including a plurality of pixel rows each including a plurality of pixel circuits therein, the non-display area including a first non-display area and a second non-display area oppositely disposed in a first direction, wherein,
the first non-display area includes a plurality of cascaded first shift registers, the second non-display area includes a plurality of cascaded second shift registers, the first shift registers provide light emission control signals to the pixel circuits, and the second shift registers provide first control signals to the pixel circuits;
the display area comprises a middle area, a first area and a second area which are adjacent to the middle area, and the middle area is positioned between the first area and the second area along the first direction;
the display panel further comprises a light-emitting control signal line and a first scanning signal line which extend along the first direction and are arranged along the second direction, and the light-emitting control signal line and the first scanning signal line are both electrically connected with the pixel circuit;
the display panel further comprises a first connecting wire, one end of the first connecting wire is electrically connected with the first shift register, the other end of the first connecting wire is electrically connected with the light-emitting control signal wire, and a connecting point of the first connecting wire and the light-emitting control signal wire is positioned in the middle area;
and/or the display panel further comprises a second connecting line, one end of the second connecting line is electrically connected with the second shift register, the other end of the first connecting line is electrically connected with the first scanning signal line, and a connecting point of the second connecting line, which is electrically connected with the first scanning signal line, is positioned in the middle area.
On the other hand, the invention also provides a display device which comprises the display panel.
Compared with the prior art, the display panel and the display device provided by the invention at least realize the following beneficial effects:
the display panel comprises a first non-display area and a second non-display area which are oppositely arranged along a first direction, wherein a first shift register for providing a light-emitting control signal for a pixel circuit and a second shift register for providing the first control signal for the pixel circuit are both single-side areas, the first shift register is positioned in the first non-display area, and the second shift register is positioned in the second non-display area. In the related art, because the first shift register and the second shift register are both single-side driven, a whole row of pixel rows is loaded on a light-emitting control signal line connected with the first shift register, and the same row of pixel rows is loaded on a first scanning signal line connected with the second shift register, because a pixel circuit generates a certain resistance load, a light-emitting control signal received by a pixel circuit farther from the first shift register is gradually reduced and is lower than a light-emitting control signal received by a pixel circuit closer to the first shift register, and similarly, a first control signal received by a pixel circuit farther from the second shift register is gradually reduced and is lower than a first control signal received by a pixel circuit closer to the second shift register, so that pixels of different pixel columns are displayed unevenly. In the invention, along the first direction, the display area comprises a middle area, a first area and a second area which are positioned at two sides of the middle area, a first connecting line can be arranged on the display panel, one end of the first connecting line is electrically connected with the first shift register, the other end of the first connecting line is connected with a light-emitting control signal line, the light-emitting control signal line is not directly electrically connected with the first shift register but electrically connected with the first shift register through the first connecting line, and the connecting point of the first connecting line and the light-emitting control signal line is positioned in the middle area, namely, the access point of the light-emitting control signal provided by the first shift register is not positioned in the first non-display area but positioned in the middle area of the display area, so that the light-emitting control signal is transmitted to the left side and the right side of the connecting point through the light-emitting control signal line after being electrically connected with the light-emitting control signal line from the connecting point, and the problem of uneven display caused by the weakening of the light-emitting control signal generated by the load of the pixel circuit is improved to a certain extent. Of course, a second connection line may also be disposed on the display panel, one end of the second connection line is electrically connected to the second shift register, and the other end of the second connection line is connected to the first scanning signal line, the first scanning signal line is not directly electrically connected to the second shift register, but is electrically connected to the second shift register through the second connection line, and a connection point where the second connection line is electrically connected to the first scanning signal line is located in the middle area, that is, an access point of the first control signal provided by the second shift register is not located in the second non-display area but located in the middle area of the display area, so that the first control signal is transmitted to the left and right sides of the connection point through the first scanning signal line after being accessed from the connection point where the second connection line is electrically connected to the first scanning signal line, thereby improving the problem of uneven display caused by the attenuation of the first control signal generated by the load of the pixel circuit to a certain extent.
Of course, it is not necessary for any product in which the present invention is practiced to achieve all of the above-described technical effects simultaneously.
Other features of the present invention and advantages thereof will become apparent from the following detailed description of exemplary embodiments of the invention, which proceeds with reference to the accompanying drawings.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention.
Fig. 1 is a schematic plan view of a display panel in the related art;
FIG. 2 is a schematic plan view of a display panel according to the present invention;
FIG. 3 is a schematic plane structure diagram of another display panel provided by the present invention;
FIG. 4 is a schematic plane structure diagram of another display panel provided by the present invention;
FIG. 5 is a circuit diagram of a pixel circuit provided by the present invention;
FIG. 6 is a schematic plane structure diagram of another display panel provided by the present invention;
FIG. 7 is a schematic plan view of another display panel provided in the present invention;
FIG. 8 is a schematic plane structure diagram of another display panel provided by the present invention;
FIG. 9 is a schematic plan view of a display panel according to another embodiment of the present invention;
FIG. 10 is a schematic plan view of another display panel provided in the present invention;
FIG. 11 is a schematic plan view of a display panel according to another embodiment of the present invention;
FIG. 12 isbase:Sub>A cross-sectional view taken along line A-A' of FIG. 2;
FIG. 13 is a schematic plane view of another display panel provided by the present invention;
FIG. 14 is a cross-sectional view of B-B' of FIG. 13;
FIG. 15 is a schematic plan view of a display panel according to another embodiment of the present invention;
FIG. 16 is a cross-sectional view of C-C' of FIG. 15;
fig. 17 is a schematic plan view of a display device according to an embodiment of the present invention.
Detailed Description
Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that: the relative arrangement of the components and steps, the numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present invention unless specifically stated otherwise.
The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.
Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.
In all examples shown and discussed herein, any particular value should be construed as exemplary only and not as limiting. Thus, other examples of the exemplary embodiments may have different values.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.
In view of the problem of non-uniform display of pixel columns in the display panel of the related art, the inventor has studied the related art, referring to fig. 1, where fig. 1 is a schematic plane structure of the display panel of the related art, where the display panel 000 of fig. 1 includes a display area AA 'and a non-display area BB' surrounding the display area AA ', the display area AA' includes a pixel P ', the pixel P' has a pixel circuit Q ', the non-display area BB' includes a first non-display area BB1 'and a second non-display area BB2' oppositely disposed along a first direction X, the first non-display area BB1 'has a first shift register 021 therein, the first shift register 021 provides a light emission control signal Emit for the pixel circuit Q', the light emission control signal line 050 is directly electrically connected to the first shift register 021, the second non-display area BB2 'has a second shift register 022 therein, the second shift register provides the pixel circuit Q' with a first control signal S1, the first scan signal S030 is directly electrically connected to the second shift register 022, the first shift register 022 has a load signal line 030, the first load signal line 023 is directly electrically connected to the first shift register Q ', each of the first non-display area BB' and the second non-display area BB 'has a distance Q', the pixel circuit BB 'is inevitably reduced, the first load signal 023, the first load signal S control signal S0 is inevitably generated from the first load control signal 023, each pixel circuit BB' and the first load control circuit BB 'in the first non-Q', the first non-display area BB 'and the first non-display area BB' is inevitably generated on the first non-display area BB1, the pixel P2 'is close to the second shift register 022, and the pixel P1' is far from the second shift register 022, so the emission control signal Emit received by the pixel P1 'is greater than the emission control signal Emit received by the pixel P2', and the first control signal S1 received by the pixel P2 'is greater than the emission control signal S1 received by the pixel P1', thereby causing the problem that the pixel P1 'and the pixel P2' are not uniform in displaying.
In view of the above, the present invention provides a display panel and a display device, which are used to improve the above problems, and the detailed description of the specific embodiments of the display panel will be provided below.
Referring to fig. 2 to 5, fig. 2 is a schematic plane structure diagram of a display panel provided by the present invention, fig. 3 is a schematic plane structure diagram of another display panel provided by the present invention, fig. 4 is a schematic plane structure diagram of another display panel provided by the present invention, and fig. 5 is a circuit diagram of a pixel circuit provided by the present invention. The display panel 1000 in fig. 2 to 4 includes: a display area AA and a non-display area BB at least partially surrounding the display area AA, the display area AA including a plurality of pixel rows 1, each pixel row 1 including a plurality of pixel circuits Q therein, the non-display area BB including a first non-display area BB1 and a second non-display area BB2 oppositely disposed along a first direction X, wherein the first non-display area BB1 includes a plurality of cascade-connected first shift registers 21, the second non-display area BB2 includes a plurality of cascade-connected second shift registers 22, the first shift registers 21 provide light emission control signals to the pixel circuits Q, and the second shift registers 22 provide first control signals to the pixel circuits Q; the display area AA includes a middle area 11, a first area 12 and a second area 13 adjacent to the middle area 11, the middle area 11 being located between the first area 12 and the second area 13 in the first direction X; the display panel 1000 further includes a light emission control signal line 50 and a first scan line signal line 30 extending in the first direction X and arranged in the second direction Y, both the light emission control signal line 50 and the first scan line signal line 30 being electrically connected to the pixel circuit Q; the display panel 1000 further includes first connecting lines 60, one end of the first connecting lines 60 is electrically connected to the first shift register 21, the other end of the first connecting lines 60 is electrically connected to the light emission control signal lines 50, and a connection point where the first connecting lines 60 are electrically connected to the light emission control signal lines 50 is located in the middle area 11; and/or, the display panel 1000 further includes a second connection line 70, one end of the second connection line 70 is electrically connected to the second shift register 22, the other end of the first connection line 60 is electrically connected to the first scan line signal line 30, and a connection point of the second connection line 70 and the first scan line signal line 30 is located in the middle area 11.
Specifically, the display panel 1000 in fig. 2 to 4 includes a display area AA and a non-display area BB surrounding the display area AA, and only the case that the non-display area BB completely surrounds the display area AA is shown, but the non-display area BB may also partially surround the display area AA, such as a water drop screen, and is not limited herein. The non-display area BB includes a first non-display area BB1 and a second non-display area BB2, i.e. a left frame and a right frame, which are oppositely disposed along the first direction X, and certainly, the non-display area BB also includes an upper frame and a lower frame (not shown in the figure) which are oppositely disposed along the second direction Y, and a driving chip (not shown in the figure) is usually bonded in the lower frame, and the driving chip provides a signal during displaying. Of course, the display panel 1000 further includes data lines (not shown) extending along the first direction X and the second direction Y for transmitting data signals to the pixel circuits Q.
In fig. 2 to 4, the display area AA includes a middle area 11, a first area 12 adjacent to the middle area 11, and a second area 13, the middle area 11 is located between the first area 12 and the second area 13 along the first direction X, where the middle area 11 refers to an area of the middle area 11 located in the display area AA along the first direction X, and a length of the middle area 11 in the first direction X is not specifically limited, although a length of the first area 12 in the first direction X and a length of the second area 13 in the first direction X are not specifically limited.
The first shift register 21 is located in the first non-display area BB1, that is, the first shift register 21 is driven by one side, so that the arrangement can reduce the width of the first non-display area BB1 in the first direction X, thereby implementing a narrow frame, the first shift register 21 provides a light-emitting control signal for the pixel circuit Q, and similarly, the second shift register 22 is located in the second non-display area BB2, that is, the second shift register 22 is driven by one side, so that the arrangement can reduce the width of the second non-display area BB2 in the first direction X, thereby implementing a narrow frame, and the second shift register 22 provides a first control signal for the pixel circuit Q. The positions of the first shift register 21 and the second shift register 22 are not particularly limited as long as the first shift register 21 and the second shift register 22 are located on opposite sides of the non-display area BB, for example, the first shift register 21 is located on the left frame, the second shift register 22 is located on the right frame, or the first shift register 21 is located on the right frame, and the second shift register 22 is located on the left frame.
Fig. 2 to 4 also show a third shift register 23, where the third shift register 23 is located in both the first non-display area BB1 and the second non-display area BB2, that is, the third shift register 23 is driven by two sides, and the third shift register 23 can provide a second control signal for the pixel circuit Q.
Each pixel P in the display area AA of the display panel 1000 includes a pixel circuit Q, which can be 7T1C with reference to fig. 5, and includes: a first transistor M1, a control end of the first transistor M1 being electrically connected to the first control signal input terminal S1, a first end of the first transistor M1 being electrically connected to the reference voltage signal input terminal Vref, a second end of the first transistor M1 being electrically connected to the first node N1; a control end of the second transistor M2 is electrically connected to the first control signal input end S1, a first end of the second transistor M2 is electrically connected to the first node N1, and a second end of the second transistor M2 is electrically connected to a second end of the driving transistor M and a first end of the fifth transistor M5; a control end of the third transistor M3 is electrically connected to the light-emitting signal input end, a first end of the third transistor M3 is electrically connected to the first power signal end PVDD, and a second end of the third transistor M3 is electrically connected to the first end of the driving transistor M; a fourth transistor M4, a control end of the fourth transistor M4 is electrically connected to the second control signal input end S2, a first end of the fourth transistor M4 is electrically connected to the data signal input end Vdata, and a second end of the fourth transistor M4 is electrically connected to the first end of the driving transistor M; a control end of the driving transistor M is electrically connected with the first node N1, and a first end of the driving transistor M is electrically connected with a second end of the third transistor M3 and a second end of the fourth transistor M4; a fifth transistor M5, a control terminal of the fifth transistor M5 is electrically connected to the emission signal input terminal Emit, a first terminal of the fifth transistor M5 is electrically connected to the second terminal of the driving transistor M and the second terminal of the second transistor M2, and a second terminal of the fifth transistor M5 is electrically connected to the anode of the light emitting element O; a sixth transistor M6, a control terminal of the sixth transistor M6 being electrically connected to the second control signal input terminal S2, a first terminal of the sixth transistor M6 being electrically connected to the reference voltage signal input terminal Vref, and a second terminal of the sixth transistor M6 being electrically connected to the first terminal of the light emitting element O; a first end of the light emitting element O is electrically connected to the second end of the fifth transistor M5 and the second end of the sixth transistor M6, and a second end of the light emitting element O is electrically connected to the second power signal terminal PVEE; a first end of the storage capacitor Cst is electrically connected to the first power signal terminal PVDD, and a second end of the storage capacitor Cst is electrically connected to the first node N1. The emission signal input terminal Emit in fig. 5 is electrically connected to the emission control signal line 50 in fig. 2 to 4, the first control signal input terminal S1 is electrically connected to the first scan line signal line 30, and the second control signal input terminal S2 is electrically connected to the second scan line signal line 40.
In fig. 2, the display panel 1000 further includes a first connecting line 60, one end of the first connecting line 60 is electrically connected to the first shift register 21, the other end of the first connecting line 60 is electrically connected to the light-emitting control signal line 50, and a connection point of the first connecting line 60 and the light-emitting control signal line 50 is located in the middle area 11;
in fig. 3, the display panel 1000 further includes a second connection line 70, one end of the second connection line 70 is electrically connected to the second shift register 22, the other end of the first connection line 60 is electrically connected to the first scan line signal line 30, and a connection point of the second connection line 70 and the first scan line signal line 30 is located in the middle area 11;
in fig. 4, the display panel 1000 further includes a first connection line 60, one end of the first connection line 60 is electrically connected to the first shift register 21, the other end of the first connection line 60 is electrically connected to the light-emitting control signal line 50, a connection point of the first connection line 60 and the light-emitting control signal line 50 is located in the middle area 11, the display panel 1000 further includes a second connection line 70, one end of the second connection line 70 is electrically connected to the second shift register 22, the other end of the first connection line 60 is electrically connected to the first scan line signal line 30, and a connection point of the second connection line 70 and the first scan line signal line 30 is located in the middle area 11.
Compared with the prior art, the display panel 1000 of the invention has at least the following beneficial effects:
the display panel 1000 of the present invention includes a first non-display area BB1 and a second non-display area BB2 disposed opposite to each other along a first direction X, and both of a first shift register 21 for providing a light emission control signal to a pixel circuit Q and a second shift register 22 for providing a first control signal to the pixel circuit Q are single-sided areas, the first shift register 21 is located in the first non-display area BB1, and the second shift register 22 is located in the second non-display area BB2. In the related art, since the first shift register 21 and the second shift register 22 are both single-side driven, a whole row of pixel rows 1 is loaded on the light emission control signal line 50 connected to the first shift register 21, and the same row of pixel rows 1 is loaded on the first scan line signal line 30 connected to the second shift register 22, since the pixel circuit Q generates a certain resistive load, the light emission control signal received by the pixel circuit Q farther from the first shift register 21 is gradually reduced, which is lower than the light emission control signal received by the pixel circuit Q closer to the first shift register 21, and similarly, the first control signal received by the pixel circuit Q farther from the second shift register 22 is gradually reduced, which is lower than the first control signal received by the pixel circuit Q closer to the second shift register 22, which results in uneven pixel display of different pixel columns. In the present invention, along the first direction X, the display area AA includes the middle area 11, and the first area 12 and the second area 13 located at both sides of the middle area 11, the first connection line 60 may be disposed on the display panel 1000, one end of the first connection line 60 is electrically connected to the first shift register 21, the other end of the first connection line 60 is connected to the light emission control signal line 50, the light emission control signal line 50 is not directly electrically connected to the first shift register 21, but is electrically connected to the first shift register 21 through the first connection line 60, a connection point where the first connection line 60 is electrically connected to the light emission control signal line 50 is located in the middle area 11, that is, an access point of the light emission control signal provided by the first shift register 21 is not located in the first non-display area BB1 but located in the middle area 11 of the display area AA, so that the light emission control signal is transmitted to both sides of the connection point through the light emission control signal line 50 after being connected from the connection point where the first connection line 60 is electrically connected to the light emission control signal line 50, and a display unevenness caused by a reduction of the load of the pixel circuit Q is improved to a certain extent. Of course, the display panel 1000 may be provided with the second connection line 70, one end of the second connection line 70 is electrically connected to the second shift register 22, the other end of the second connection line 70 is connected to the first scan line signal line 30, the first scan line signal line 30 is not directly electrically connected to the second shift register 22, but is electrically connected to the second shift register 22 through the second connection line 70, and a connection point where the second connection line 70 is electrically connected to the first scan line signal line 30 is located in the middle area 11, that is, an access point of the first control signal provided by the second shift register 22 is not located in the second non-display area BB2 but located in the middle area 11 of the display area AA, so that the first control signal is transmitted to both sides of the connection point through the first scan line signal line 30 after being accessed from the connection point where the second connection line 70 is electrically connected to the first scan line signal line 30, thereby improving the problem of display unevenness caused by the decrease in the first control signal generated by the load of the pixel circuit Q to some extent.
In some alternative embodiments, with continued reference to fig. 2 to 4, the first connecting line 60 includes a first sub-connecting line 601 and a second sub-connecting line 602, one end of the first sub-connecting line 601 is electrically connected to the first shift register 21, the other end is electrically connected to the second sub-connecting line 602, the second sub-connecting line 602 is located in the middle area 11, and the other end of the second sub-connecting line 602 is electrically connected to the light-emitting control signal line 50;
and/or the second connection line 70 includes a third sub-connection line 701 and a fourth sub-connection line 702, one end of the third sub-connection line 701 is electrically connected to the second shift register 22, the other end is electrically connected to the fourth connection, the fourth sub-connection line 702 is located in the middle area 11, and the other end of the fourth sub-connection line 702 is electrically connected to the first scan line signal line 30.
In fig. 2, the first connection line 60 includes a first sub-connection line 601 and a second sub-connection line 602, the first sub-connection line 601 extends along the first direction X, the second sub-connection line 602 extends along the second direction Y, the first sub-connection line 601 and the second sub-connection line 602 may be integrated, one end of the first sub-connection line 601 is electrically connected to the first shift register 21, the other end is electrically connected to the second sub-connection line 602, the second sub-connection line 602 is located in the middle area 11, the other end of the second sub-connection line 602 is electrically connected to the emission control signal line 50, the emission control signal line 50 is not directly electrically connected to the first shift register 21, but is electrically connected to the first shift register 21 through the first sub-connection line 601 and the second sub-connection line 602, the second sub-connection line 602 is located in the middle area 11 and is electrically connected to the emission control signal line 50, that is, that the access point of the emission control signal provided by the first shift register 21 is not located in the middle area 11 of the first non-display area AA, so that the emission control signal is accessed from the connection point where the second sub-connection line 602 is electrically connected to the emission control signal line 50, and the pixel control signal line is transmitted to both sides of the display area AA, thereby reducing the load control circuit.
In fig. 4, the second connection line 70 includes a third sub-connection line 701 and a fourth sub-connection line 702, the third sub-connection line 701 extends along the first direction X, the fourth sub-connection line 702 extends along the second direction Y, the third sub-connection line 701 and the fourth sub-connection line 702 may be of an integral structure, one end of the third sub-connection line 701 is electrically connected to the second shift register 22, the other end is electrically connected to the fourth connection, the fourth sub-connection line 702 is located in the middle area 11, the other end of the fourth sub-connection line 702 is electrically connected to the first scan line signal line 30, the first scan line signal line 30 is not directly electrically connected to the second shift register 22, but is electrically connected to the second shift register 22 through the third sub-connection line 701 and the fourth sub-connection line 702, the fourth sub-connection line 702 is located in the middle area 11, that the connection point electrically connected to the first scan line signal line 30 is located in the middle area 11 instead of the second non-display area AA, that the access point of the first control signal supplied from the second shift register 22 is not located in the middle area 11 but in the second non-display area AA, such that the first control signal is electrically connected from the fourth sub-connection point 702 to the first sub-connection point 702, and the left and right sub-connection point of the first scan line 30 is electrically connected to reduce the problem of the pixel signal line 30, thereby reducing the pixel load of the pixel.
The embodiment of fig. 5 in which the first connecting lines 60 and the second connecting lines 70 are simultaneously disposed is not described again, and the effect of improving the display unevenness is better because the first connecting lines 60 and the second connecting lines 70 are simultaneously disposed in fig. 5.
In some alternative embodiments, referring to fig. 6 to 8, fig. 6 is a schematic plane structure diagram of another display panel provided by the present invention, fig. 7 is a schematic plane structure diagram of another display panel provided by the present invention, and fig. 8 is a schematic plane structure diagram of another display panel provided by the present invention.
In fig. 6, the first sub-connection lines 601 are located between the adjacent pixel rows 1, and the second sub-connection lines 602 are electrically connected to two adjacent light-emitting control signal lines 50 along the second direction Y, so that the first connection lines 60 can be electrically connected to the light-emitting control signal lines 50 of two adjacent pixel rows 1 at the same time, thereby reducing the number of the first connection lines 60, on one hand, reducing the number of traces in the display panel 1000, and on the other hand, reducing the cost.
In fig. 7, the third sub-connection line 701 is located between the adjacent pixel rows 1, and the fourth sub-connection line 702 is electrically connected to the two adjacent first scan line signal lines 30 along the second direction Y, so that the second connection line 70 can be electrically connected to the first scan line signal lines 30 of the two adjacent pixel rows 1 at the same time, thereby reducing the number of the second connection lines 70, on one hand, reducing the number of traces in the display panel 1000, and on the other hand, reducing the cost.
In fig. 8, the first sub-connection lines 601 are located between the adjacent pixel rows 1, the second sub-connection lines 602 are electrically connected to the two adjacent light-emitting control signal lines 50 along the second direction Y, the third sub-connection lines 701 are located between the adjacent pixel rows 1, and the fourth sub-connection lines 702 are electrically connected to the two adjacent first scanning line signal lines 30 along the second direction Y, so that the number of the first connection lines 60 and the second connection lines 70 can be reduced, the number of the wirings in the display panel 1000 can be reduced, and the cost can be reduced.
In some alternative embodiments, with continued reference to fig. 4, the length of the first sub-connecting line 601 is a, the length of the third sub-connecting line 701 is b, the distance between the first shift register 21 and the second shift register 22 is c, and the sum of a and b is not greater than c.
Specifically, in the display panel 1000 of this embodiment, the first connection line 60 and the second connection line 70 are simultaneously disposed, the first sub-connection line 601 is electrically connected to the first shift register 21, the length is a, the third sub-connection line is electrically connected to the second shift register 22, the length is b, the distance between the first shift register 21 and the second shift register 22 is c, if a + b > c, the first sub-connection line 601 and the third sub-connection line 701 overlap by a distance, on one hand, the length of the first sub-connection line 601 and the third sub-connection line 701 is longer, the resistance of the first sub-connection line 601 itself increases with the increase of the length, the resistance of the third sub-connection line 701 itself increases with the increase of the length, and thus the resistance of the first connection line 60 and the second connection line 70 is larger, the load is also increased, and in the other direction, in the second direction Y, after the first sub-connection line 601 and the third sub-connection line 701 overlap, signal coupling is generated, and the display is affected. In this embodiment, the sum of a and b is not greater than c, that is, the lengths of the first sub-link 601 and the third sub-link 701 can be shortened as much as possible, the resistance of the first sub-link 601 and the resistance of the third sub-link 701 can be reduced, and the signal coupling between the first sub-link 601 and the third sub-link 701 can be prevented from affecting the display.
In some alternative embodiments, with continued reference to fig. 4, a =1/2c, or b =1/2c.
In this embodiment, a =1/2c, b =1/2c, a + b = c, so that the lengths of the first sub-connection line 601 and the third sub-connection line 701 can be shortened as much as possible, the resistance of the first sub-connection line 601 and the resistance of the third sub-connection line 701 can be reduced, and meanwhile, signal coupling between the first sub-connection line 601 and the third sub-connection line 701 does not affect the display. On the other hand, since the number of pixels on the left and right sides of the connection point between the second sub-connection line 602 and the light emission control signal line 50 is the same, that is, the load is the same, it is possible to ensure symmetrical display of the pixels on the left and right sides of the connection point as much as possible.
In some alternative embodiments, referring to fig. 9, fig. 9 is a schematic plan view of another display panel provided in the present invention, where a =1/4c, b =1/4c.
In this embodiment, a =1/4c, b =1/4c, a + b =1/2c < c, so that the lengths of the first sub-connection line 601 and the third sub-connection line 701 can be shortened as much as possible, and the resistances of the first sub-connection line 601 and the third sub-connection line 701 can be reduced, while the signal coupling between the first sub-connection line 601 and the third sub-connection line 701 does not affect the display.
In some alternative embodiments, with continued reference to fig. 9, a =1/3c, b =1/3c.
In this embodiment, a =1/3c, b =1/3c, a + b =2/3c < c, so that the lengths of the first sub-connection line 601 and the third sub-connection line 701 can be shortened as much as possible, the resistance of the first sub-connection line 601 and the resistance of the third sub-connection line 701 can be reduced, and meanwhile, signal coupling between the first sub-connection line 601 and the third sub-connection line 701 can be prevented from affecting the display.
In some alternative embodiments, referring to fig. 10, fig. 10 is a schematic plan view illustrating a display panel according to still another embodiment of the present invention, the number of the second sub-connecting lines 602 is at least 2-5, and the second sub-connecting lines 602 are uniformly distributed in the middle area 11 along the first direction X.
In fig. 10, only 3 second sub-connection lines 602 are taken as an example for illustration, but of course, the number of the second sub-connection lines 602 may also be 2, 4, and 5, and optionally, the plurality of sub-connection lines are uniformly distributed, that is, the intervals between adjacent second sub-connection lines 602 are equal, it can be understood that the second sub-line connections are respectively electrically connected to the first sub-connection line 601 and the light-emitting control signal line 50, and when the number of the second sub-connection lines is 2 to 5, which is equivalent to the parallel connection relationship of the plurality of second sub-connection lines 602, the resistance of the plurality of second sub-connection lines 602 after being connected in parallel is smaller than the resistance of one second sub-connection line 602, of course, an excessive number of the second sub-connection lines 602 also increases the material cost, and an excessive number of the second sub-connection lines 602 in the display panel 1000 also increases the manufacturing complexity and process degree.
In some alternative embodiments, referring to fig. 11, fig. 11 is a schematic plan view illustrating a display panel according to still another embodiment of the present invention, the number of the fourth sub-connection lines 702 is 2-5, and the fourth sub-connection lines 702 are uniformly distributed in the middle area 11 along the first direction X.
In fig. 11, only 4 fourth sub-connection lines 702 are taken as an example for illustration, but of course, the number of the fourth sub-connection lines 702 may also be 2, 3, and 5, and optionally, the plurality of fourth sub-connection lines 702 are uniformly distributed, that is, the distance between adjacent fourth sub-connection lines 702 is equal, it can be understood that, the fourth sub-connection lines 702 are respectively electrically connected to the third sub-connection lines 701 and the first scan line signal line 30, when the number of the fourth sub-connection lines 702 is 2 to 5, which is equivalent to that the plurality of fourth sub-connection lines 702 are in a parallel relationship, the resistance of the plurality of fourth sub-connection lines 702 after being connected in parallel is smaller than that of one fourth sub-connection line 702, of course, too many fourth sub-connection lines 702 also increase the material cost, and too many fourth sub-connection lines 702 in the display panel 1000 also increase the manufacturing complexity.
In some alternative embodiments, with continued reference to fig. 5, the pixel circuit Q includes a driving transistor M, and a first transistor M1 and a second transistor M2 connected to a gate of the driving transistor M, the first transistor M1 resets the gate of the driving transistor M when turned on, the second transistor M2 threshold-compensates the gate of the driving transistor M when turned on, the first transistor M1 and the second transistor M2 are oxide thin film transistors, and the first scan line signal line 30 is electrically connected to the first transistor M1 and the second transistor M2.
Specifically, the control end of the first transistor M1 is electrically connected to the first control signal input end S1, the first end of the first transistor M1 is electrically connected to the reference voltage signal input end Vref, the second end of the first transistor M1 is electrically connected to the first node N1, the first transistor M1 is turned on under the control of the first control signal input by the first control signal input end S1, the reference voltage signal input by the reference voltage signal input end Vref is written into the first node N1, and the gate of the driving transistor M is reset; a control end of the second transistor M2 is electrically connected to the first control signal input end S1, a first end of the second transistor M2 is electrically connected to the first node N1, a second end of the second transistor M2 is electrically connected to a second end of the driving transistor M, the second transistor M2 is turned on under the control of a first control signal input by the first control signal input end S1, a data signal input by the data signal input end Vdata is written into the first node N1 through the driving transistor M and the second transistor M2, and threshold compensation is performed on the first node N1, that is, threshold compensation is performed on a gate of the driving transistor M.
It can be understood that, when the light emitting element O emits light, the gate potential of the driving transistor M, that is, the potential of the first node N1 needs to be kept stable, the light emitting duration of the light emitting element O is ensured in a layer, if a leakage current occurs in a transistor electrically connected to the first node N1, the potential of the first node N1 is reduced, which affects the light emitting duration of the light emitting element O, the material of the oxide semiconductor layer 1203 in the oxide thin film transistor may be IGZO (indium gallium zinc oxide) or the like, and a Thin Film Transistor (TFT) based on an oxide semiconductor (in particular, indium gallium zinc oxide InGaZnO) has advantages of smaller off-state current and higher electron mobility, so when the first transistor and the second transistor are set as oxide transistors, the leakage current of the first node can be reduced, the potential of the first node is maintained, the light emitting duration of the light emitting element O is extended, and the light emitting performance is improved.
In some alternative embodiments, referring to fig. 12, fig. 12 isbase:Sub>A cross-sectional view alongbase:Sub>A-base:Sub>A' direction in fig. 2, the display panel 1000 includesbase:Sub>A substrate 1201,base:Sub>A first metal layer 1202 located onbase:Sub>A side of the substrate 1201, an oxide semiconductor layer 1203 located onbase:Sub>A side of the first metal layer 1202 away from the substrate 1201,base:Sub>A second metal layer 1204 located onbase:Sub>A side of the oxide semiconductor layer 1203 away from the substrate 1201, andbase:Sub>A third metal layer 1205 located onbase:Sub>A side of the second metal layer 1204 away from the substrate 1201, gates of the first transistor M1 and the second transistor M2 are in the same layer with the first metal layer 1202 and the second metal layer 1204, andbase:Sub>A gate of the driving transistor M is in the same layer with the third metal layer 1205.
Specifically, the first transistor M1 and the second transistor M2 in the present invention are oxide thin film transistors, and when the display panel 1000 is manufactured, compared to the display panel 1000 in the related art, a first metal layer 1202 and a second metal layer 1204 are additionally provided on a film arrangement, the first metal layer 1202 is located on a side of the oxide semiconductor layer 1203 close to the substrate 1201, the second metal layer 1204 is located on a side of the oxide semiconductor layer 1203 far from the substrate 1201, and the first metal layer 1202 and the second metal layer 1204 simultaneously form a double gate with the oxide semiconductor layer, which is shown in fig. 12 that the display panel includes the first metal layer 1202, the second metal layer 1204, and the third metal layer 1205, and insulating layers 1208 are provided between the first metal layer 1202 and the oxide semiconductor layer 1203, and between the oxide semiconductor layer 1203 and the second metal layer 1204. The first transistor M1 and the second transistor M2 have the advantages of smaller off-state current and higher electron mobility, the gates of the first transistor M1 and the second transistor M2 are on the same level as the first metal layer 1202 and the second metal layer 1204, of course, the first transistor M1 and the second transistor M2 also have the sources and the drains, the sources and the drains of the first transistor M1 and the second transistor M2 are on the same level as the fourth metal layer 1206, and the optional fourth metal layer 1206 is located on the side of the third metal layer 1205 away from the substrate base plate 1201. As shown in fig. 12, the gate of the driving transistor M is on the same layer as the third metal layer 1205, the third metal layer 1205 is located on the side of the second metal layer 1204 away from the substrate 1201, and the source and the drain of the driving transistor M may also be located on the fourth metal layer 1206, and the semiconductor layer 1207 (which may be a low temperature polysilicon active layer) and the oxide semiconductor layer 1203 of the driving transistor M are also on the same layer, which is not specifically limited herein.
The display panel 1000 of the invention is an LTPO (Low Temperature Polycrystalline Oxide), combines the advantages of two technologies of LTPS (Low Temperature Polycrystalline semiconductor) and Oxide semiconductor, and has the advantages of Low production cost, higher charge mobility, high stability and expandability.
In some alternative embodiments, with continued reference to fig. 12, the first sub-connection line 601, the second sub-connection line 602 are in the same layer as the third metal layer 1205, and the light emission control signal line 50 is in the same layer as the third metal layer 1205;
the third sub-connection lines 701, the fourth sub-connection lines 702 and the first metal layer 1202 are in the same layer, and the first scan line signal lines 30 and the first metal layer 1202 are in the same layer.
Fig. 12 schematically shows that the light emission control signal line 50 is in the same layer as the third metal layer 1205, the first sub-connection line 601, the second sub-connection line 602 and the third metal layer 1205 are in the same layer, the third sub-connection line 701 and the fourth sub-connection line 702 are electrically connected to the first metal layer 1202, and the first scan line signal line 30 is in the same layer as the first metal layer 1202.
It can be understood that, if the light-emitting control signal line 50 is in the same layer as the third metal layer 1205, if the first sub-connecting line 601 and the second sub-connecting line 602 are also disposed in the third metal layer 1205, the first sub-connecting line 601 and the second sub-connecting line 602 can be fabricated in the same process as the light-emitting control signal line 50, and the second sub-connecting line 602 is in the same layer as the third metal layer 1205, and no wire-changing punch hole is required at the connection position of the second sub-connecting line 602 and the light-emitting control signal line 50, thereby simplifying the fabrication process.
Similarly, the first scan line signal line 30 and the first metal layer 1202 are on the same layer, and if the third sub-connecting line 701 and the fourth sub-connecting line 702 are also disposed on the first metal layer 1202, the third sub-connecting line 701 and the fourth sub-connecting line 702 can be fabricated in the same process as the first scan line signal line 30, and the fourth sub-connecting line 702 and the first metal layer 1202 are on the same layer, and no line replacement and punching are required at the connection position of the fourth sub-connecting line 702 and the first scan line signal line 30, thereby simplifying the fabrication process.
In some alternative embodiments, with continued reference to FIG. 12, the material of first metal layer 1202, the material of the second metal layer 1204, and the material of the third metal layer 1205 each comprise molybdenum.
It can be understood that the material of the first metal layer 1202, the second metal layer 1204 and the third metal layer 1205 is usually molybdenum, and the material of the first connecting line 60 and the second connecting line 70 in this embodiment may also be molybdenum, which does not require other materials, and the materials are easily available and are more widely used, and the manufacturing process can be simplified by manufacturing the first connecting line 60 and the second connecting line 70 and the first metal layer 1202, the second metal layer 1204 and the third metal layer 1205 with the same material.
In some alternative embodiments, referring to fig. 13, 14, 15 and 16, fig. 13 is a schematic plane structure diagram of another display panel provided by the present invention, fig. 14 is a cross-sectional view of B-B 'in fig. 13, fig. 15 is a schematic plane structure diagram of another display panel provided by the present invention, fig. 16 is a cross-sectional view of C-C' in fig. 15, a part of the data line 80 is omitted in fig. 13 and 15, only a part of the data line 80 connected to the data link line 900 is shown, and of course, for clarity, the film layer relationship among the first metal layer 1202, the second metal layer 1204, the third metal layer 1205 and the fourth metal layer 1206 is shown, and the structures of the first transistor (the second transistor) and the driving transistor are also shown in fig. 14 and 16.
The display panel 1000 of this embodiment further includes data lines 80 extending along the second direction Y and arranged in the first direction X, and further includes fan-out traces 800 located on one side of the display area AA and data connection lines 900 located in the display area AA, where the data connection lines 900 connect the fan-out traces 800 and the data lines 80; the display panel 1000 further includes a fourth metal layer 1206 located on a side of the third metal layer 1205 away from the substrate 1201, and a fifth metal layer 1209 located on a side of the fourth metal layer 1206 away from the substrate 1201, where the source and the drain of the driving transistor are on the same layer as the fourth metal layer 1206, and at least a portion of the data connection line 900 is on the same layer as the fifth metal layer 1209; the data link line 900 is at least partially disposed in the same layer as the first sub-link line 601 and/or the second sub-link line 602; and/or the data link line 900 is at least partially in the same layer as the third sub-link line 701 and/or the fourth sub-link line 702.
It should be noted that, as the requirement of a user on the performance of the display panel 1000 is higher and higher, the display panel 1000 gradually has a narrow-frame technology, and the lower frame of the display panel 1000 is further compressed, for the fan-out trace 800, because the fan-out trace 800 connects the driving chip and the data line 80, the number of the fan-out trace 800 is larger, and the fan-out trace 800 needs to have a certain angle to be able to arrange enough fan-out traces 800 between the driving chip and the display area AA, so that the space occupied by the fan-out trace 800 in the second direction Y is larger, and in order to compress the lower frame, FIAA (Fanout in) appears, so that a part of the data connection lines 900 connecting the fan-out trace 800 and the data line 80 are arranged in the display area AA, and the number of the fan-out traces 800 in the lower frame is reduced, thereby further compressing the lower frame.
As shown in fig. 14, the source and the drain of the driving transistor are in the same layer as the fourth metal layer 1206, at least a portion of the data connection line 900 is in the same layer as the fifth metal layer 1209, that is, a portion of the data connection line 900 runs through the fifth metal layer 1209, the fifth metal layer 1209 is a metal layer additionally arranged in the display panel 1000, the data connection line 900 is at least partially arranged in the same layer as the first sub-connection line 601 and/or the second sub-connection line 602, that is, the first sub-connection line 601 and/or the second sub-connection line 602 are arranged in the fifth metal layer 1209, on one hand, fewer traces are arranged on the fifth metal layer 1209, space is left, the first sub-connection line 601 and/or the second sub-connection line 602 can be conveniently manufactured, on the other hand, the material of the fifth metal layer 1209 includes titanium aluminum titanium, the resistance of which is one tenth of the resistance of molybdenum, the first sub-connection line 601 and/or the second sub-connection line 602 are arranged in the fifth metal layer 1209, and the resistance of the first sub-connection line 601 and/or the second sub-connection line 602 can be greatly reduced, and is particularly suitable for the display panel 1000.
Of course, since the first sub-link 601 extends along the first direction X, the second sub-link 602 extends along the second direction Y, and the data link 900 includes both the portion extending along the first direction X and the portion extending along the second direction Y, it is necessary to avoid the cross short between the data link 900 and the first sub-link 601 or the second sub-link 602, and fig. 15 illustrates that the data link 900 is located in the fifth metal layer 1209, and the first sub-link 601 is located in the fourth metal layer 1206, and the second sub-link 602 is located in the fifth metal layer 1209.
As shown in fig. 16, the source and the drain of the driving transistor are in the same layer as the fourth metal layer 1206, at least a portion of the data connection line 900 is in the same layer as the fifth metal layer 1209, the fifth metal layer 1209 is a metal layer additionally disposed in the display panel 1000, at least a portion of the data connection line 900 is in the same layer as the third sub-connection line 701 and/or the fourth sub-connection line 702, that is, the third sub-connection line 701 and/or the fourth sub-connection line 702 are disposed in the fifth metal layer 1209, on one hand, the third sub-connection line 701 and/or the fourth sub-connection line 702 are disposed in the fifth metal layer 1209 with less routing and more space, and the third sub-connection line 701 and/or the fourth sub-connection line 702 can be conveniently fabricated, on the other hand, the material of the fifth metal layer 1209 includes tiain which the resistance is one tenth of the resistance of molybdenum, and on the other hand, the material of the ti — the fifth metal layer 1209 is disposed in the fifth metal layer 1209, and the third sub-connection line 701 and/or the fourth sub-connection line 702 can also reduce the resistance of the second connection line 70 itself, and the third sub-connection line 701 and/or the fourth sub-connection line 702 is disposed in the fifth metal layer 1209, and is particularly suitable for reducing the size of the display panel 1000.
Of course, since the third sub-link lines 701 extend along the first direction X, the fourth sub-link lines 702 extend along the second direction Y, and the data link lines 900 include both the portions extending along the first direction X and the portions extending along the second direction Y, it is necessary to avoid the data link lines 900 from being crossed and shorted with the third sub-link lines 701 or the fourth sub-link lines 702, and fig. 15 illustrates that only the data link lines 900 are located in the fifth metal layer 1209, and the third sub-link lines 701 are located in the fourth metal layer 1206, and the fourth sub-link lines 702 are located in the fifth metal layer 1209.
In some alternative embodiments, with continued reference to fig. 13 to 16, it is shown in fig. 13 and 15 that the data link lines 900 include connected first and second data link lines 901 and 902, the first data link lines 901 extending in the first direction X and the second data link lines 902 extending in the second direction Y;
in fig. 14, the first data link lines 901 are on the same layer as the first sub-link lines 601, and the second data link lines 902 are on the same layer as the second sub-link lines 602; in fig. 16, the first data link lines 901 and the third sub-link lines 701 are at the same level, and the second data link lines 902 and the fourth sub-link lines 702 are at the same level.
Of course, the first data link lines 901 and the first sub-link lines 601 may be in the same layer, the second data link lines 902 and the second sub-link lines 602 may be in the same layer, and the first data link lines 901 and the third sub-link lines 701 are in the same layer, and the second data link lines 902 and the fourth sub-link lines 702 are in the same layer, which is not particularly limited herein.
It can be understood that the first sub-link lines 601 and the first data link lines 901 extend along the first direction X, and the second sub-link lines 602 and the second data link lines 902 extend along the second direction Y, so that it is more convenient to fabricate the first data link lines 901 and the first sub-link lines 601 in the same layer, and the second data link lines 902 and the second sub-link lines 602 in the same layer.
Similarly, the third sub-link lines 701 and the first data link lines 901 extend along the first direction X, the fourth sub-link lines 702 and the second data link lines 902 extend along the second direction Y, the first data link lines 901 and the third sub-link lines 701 have the same layer, and the second data link lines 902 and the fourth sub-link lines 702 have the same layer and are more convenient to manufacture.
In some alternative embodiments, with continued reference to fig. 13 and 15, the second sub-connection line 602 is electrically connected to the light emission control signal line 50 through a via; the fourth sub-connection line 702 is electrically connected to the first scan line signal line 30 through a via hole.
As shown in fig. 13, the second data connecting line 902 is on the same layer as the first sub-connecting line 601, the second sub-connecting line 602 is on the same layer as the first data connecting line 901, and the first data line 80 may be disposed on the fourth metal layer 1206 or the fifth metal layer 1209, so that the second sub-connecting line 602 may also be disposed on the fourth metal layer 1206 or the fifth metal layer 1209, and the second sub-connecting line 602 and the light-emitting control signal line 50 may be electrically connected through a via hole; similarly, as shown in fig. 15, the fourth sub-connecting line 702 is on the same layer as the first data connecting line 901, the third sub-connecting line 701 is on the same layer as the second data connecting line 902, and the first data line 80 may be disposed on the fourth metal layer 1206 or the fifth metal layer 1209, so that the fourth sub-connecting line 702 may also be disposed on the fourth metal layer 1206 or the fifth metal layer 1209, and the fourth sub-connecting line 702 may be electrically connected to the first scan line signal line 30 through the via hole.
In some alternative embodiments, please refer to fig. 17, where fig. 17 is a schematic plan view illustrating a display device according to an embodiment of the present invention, and the display device 2000 provided in this embodiment includes the display panel 1000 provided in the foregoing embodiment. The embodiment of fig. 17 is only an example of a mobile phone, and the display device 2000 is described, it is understood that the display device 2000 provided in the embodiment of the present invention may be another display device 2000 having a display function, such as a computer, a television, and a vehicle-mounted display device, and the present invention is not limited thereto. The display device 2000 provided in the embodiment of the present invention has the beneficial effects of the display panel 1000 provided in the embodiment of the present invention, and specific descriptions on the display panel 1000 in the above embodiments may be specifically referred to, and this embodiment is not described herein again.
According to the embodiment, the display panel and the display device provided by the invention at least realize the following beneficial effects:
the display panel comprises a first non-display area and a second non-display area which are oppositely arranged along a first direction, wherein a first shift register for providing a light-emitting control signal for a pixel circuit and a second shift register for providing the first control signal for the pixel circuit are both single-side areas, the first shift register is positioned in the first non-display area, and the second shift register is positioned in the second non-display area. In the related art, because the first shift register and the second shift register are both single-side driven, a whole row of pixel rows is loaded on a light-emitting control signal line connected with the first shift register, and a same row of pixel rows is loaded on a first scanning signal line connected with the second shift register, because a certain resistance load is generated by a pixel circuit, a light-emitting control signal received by a pixel circuit farther from the first shift register is gradually reduced, and is lower than a light-emitting control signal received by a pixel circuit closer to the first shift register, and similarly, a first control signal received by a pixel circuit farther from the second shift register is gradually reduced, and is lower than a first control signal received by a pixel circuit closer to the second shift register, so that pixels of different pixel columns are displayed unevenly. In the invention, along the first direction, the display area comprises a middle area, a first area and a second area which are positioned at two sides of the middle area, a first connecting line can be arranged on the display panel, one end of the first connecting line is electrically connected with the first shift register, the other end of the first connecting line is connected with a light-emitting control signal line, the light-emitting control signal line is not directly electrically connected with the first shift register but electrically connected with the first shift register through the first connecting line, and the connecting point of the first connecting line and the light-emitting control signal line is positioned in the middle area, namely, the access point of the light-emitting control signal provided by the first shift register is not positioned in the first non-display area but positioned in the middle area of the display area, so that the light-emitting control signal is transmitted to the left side and the right side of the connecting point through the light-emitting control signal line after being electrically connected with the light-emitting control signal line from the connecting point, and the problem of uneven display caused by the weakening of the light-emitting control signal generated by the load of the pixel circuit is improved to a certain extent. Of course, a second connection line may also be disposed on the display panel, one end of the second connection line is electrically connected to the second shift register, and the other end of the second connection line is connected to the first scanning signal line, the first scanning signal line is not directly electrically connected to the second shift register, but is electrically connected to the second shift register through the second connection line, and a connection point where the second connection line is electrically connected to the first scanning signal line is located in the middle area, that is, an access point of the first control signal provided by the second shift register is not located in the second non-display area but located in the middle area of the display area, so that the first control signal is transmitted to the left and right sides of the connection point through the first scanning signal line after being accessed from the connection point where the second connection line is electrically connected to the first scanning signal line, thereby improving the problem of uneven display caused by the attenuation of the first control signal generated by the load of the pixel circuit to a certain extent.
Although some specific embodiments of the present invention have been described in detail by way of examples, it should be understood by those skilled in the art that the above examples are for illustrative purposes only and are not intended to limit the scope of the present invention. It will be appreciated by those skilled in the art that modifications may be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.

Claims (17)

1. A display panel, comprising: a display area and a non-display area at least partially surrounding the display area, the display area including a plurality of pixel rows each including a plurality of pixel circuits therein, the non-display area including a first non-display area and a second non-display area oppositely disposed in a first direction, wherein,
the first non-display area includes a plurality of cascade-connected first shift registers, the second non-display area includes a plurality of cascade-connected second shift registers, the first shift registers provide light emission control signals to the pixel circuits, and the second shift registers provide first control signals to the pixel circuits;
the display area comprises a middle area, a first area and a second area which are adjacent to the middle area, and the middle area is positioned between the first area and the second area along the first direction;
the display panel further comprises a light-emitting control signal line and a first scanning signal line which extend along the first direction and are arranged along the second direction, and the light-emitting control signal line and the first scanning signal line are electrically connected with the pixel circuit;
the display panel further comprises a first connecting wire, one end of the first connecting wire is electrically connected with the first shift register, the other end of the first connecting wire is electrically connected with the light-emitting control signal wire, and a connecting point of the first connecting wire and the light-emitting control signal wire is positioned in the middle area;
and/or the display panel further comprises a second connecting line, one end of the second connecting line is electrically connected with the second shift register, the other end of the first connecting line is electrically connected with the first scanning signal line, and a connecting point of the second connecting line and the first scanning signal line is positioned in the middle area.
2. The display panel according to claim 1, wherein the first connection lines include first sub-connection lines and second sub-connection lines, the first sub-connection lines have one ends electrically connected to the first shift register and the other ends electrically connected to the second sub-connection lines, the second sub-connection lines are located in the middle area, and the other ends of the second sub-connection lines are electrically connected to the light emission control signal lines;
and/or the second connecting line comprises a third sub-connecting line and a fourth sub-connecting line, one end of the third sub-connecting line is electrically connected with the second shift register, the other end of the third sub-connecting line is electrically connected with the fourth sub-connecting line, the fourth sub-connecting line is positioned in the middle area, and the other end of the fourth sub-connecting line is electrically connected with the first scanning signal line.
3. The display panel according to claim 2, wherein the first sub-connection line is between adjacent pixel rows, and the second sub-connection line is electrically connected to two light emission control signal lines adjacent in the second direction;
and/or the third sub-connection line is positioned between adjacent pixel rows, and the fourth sub-connection line is electrically connected with two adjacent first scanning signal lines along the second direction.
4. The display panel according to claim 2, wherein the first sub-connection line has a length a, the third sub-connection line has a length b, a distance between the first shift register and the second shift register is c, and a sum of a and b is not greater than c.
5. The display panel according to claim 1, wherein a =1/2c, b =1/2c.
6. The display panel according to claim 1, wherein a =1/4c and b =1/4c.
7. The display panel according to claim 1, wherein a =1/3c, b =1/3c.
8. A display panel according to claim 2, wherein the number of the second sub-connection lines is at least 2-5, and the second sub-connection lines are uniformly distributed in the middle area along the first direction.
9. The display panel according to claim 2, wherein the number of the fourth sub-connecting lines is 2-5, and the fourth sub-connecting lines are uniformly distributed in the middle area along the first direction.
10. The display panel according to claim 2, wherein the pixel circuit comprises a driving transistor, and a first transistor and a second transistor which are connected to a gate of the driving transistor, wherein the first transistor resets the gate of the driving transistor when turned on, wherein the second transistor threshold-compensates the gate of the driving transistor when turned on, wherein the first transistor and the second transistor are oxide thin film transistors, and wherein the first scan signal line is electrically connected to the first transistor and the second transistor.
11. The display panel according to claim 10, comprising a substrate, a first metal layer on a side of the substrate, an oxide semiconductor layer on a side of the first metal layer away from the substrate, a second metal layer on a side of the oxide semiconductor layer away from the substrate, and a third metal layer on a side of the second metal layer away from the substrate, wherein gates of the first transistor and the second transistor are on a same layer as the first metal layer and the second metal layer, and a gate of the driving transistor is on a same layer as the third metal layer.
12. The display panel according to claim 11, wherein the first sub-connection line and the second sub-connection line are electrically connected to the third metal layer, and the light emission control signal line is on the same layer as the third metal layer;
the third sub-connection line and the fourth sub-connection line are electrically connected with the first metal layer or the second metal layer, and the first scanning signal line and the first metal layer are on the same layer.
13. The display panel according to claim 12, wherein a material of the first metal layer, a material of the second metal layer, and a material of the third metal layer each include molybdenum.
14. The display panel of claim 11, further comprising data lines extending in a second direction and arranged in the first direction, fan-out traces on one side of the display area, and data connection lines on the display area, the data connection lines connecting the fan-out traces and the data lines;
the display panel further comprises a fourth metal layer located on one side, far away from the substrate base plate, of the third metal layer and a fifth metal layer located on one side, far away from the substrate base plate, of the fourth metal layer, the material of the fifth metal layer comprises titanium-aluminum-titanium, a source electrode and a drain electrode of the driving transistor are on the same layer as the fourth metal layer, and at least part of the data connecting lines are on the same layer as the fifth metal layer;
the data connecting line is at least partially arranged at the same layer with the first sub-connecting line and/or the second sub-connecting line; and/or the data connection line is at least partially in the same layer as the third sub-connection line and/or the fourth sub-connection line.
15. The display panel according to claim 14, wherein the data link lines include a first data link line and a second data link line connected, the first data link line extending in the first direction, the second data link line extending in the second direction;
the first data connecting line and the first sub-connecting line are at the same layer, and the second data connecting line and the second sub-connecting line are at the same layer;
and/or the first data connecting line and the third sub-connecting line are at the same layer, and the second data connecting line and the fourth sub-connecting line are at the same layer.
16. The display panel according to claim 15, wherein the second sub-connection line is electrically connected to the light emission control signal line through a via hole;
the fourth sub-connecting line is electrically connected with the first scanning signal line through a via hole.
17. A display device comprising the display panel according to any one of claims 1 to 16.
CN202211209189.6A 2022-09-30 2022-09-30 Display panel and display device Pending CN115527479A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202211209189.6A CN115527479A (en) 2022-09-30 2022-09-30 Display panel and display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202211209189.6A CN115527479A (en) 2022-09-30 2022-09-30 Display panel and display device

Publications (1)

Publication Number Publication Date
CN115527479A true CN115527479A (en) 2022-12-27

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN202211209189.6A Pending CN115527479A (en) 2022-09-30 2022-09-30 Display panel and display device

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Country Link
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