CN115514372A - Conversion circuit and electronic chip - Google Patents
Conversion circuit and electronic chip Download PDFInfo
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- CN115514372A CN115514372A CN202210518973.9A CN202210518973A CN115514372A CN 115514372 A CN115514372 A CN 115514372A CN 202210518973 A CN202210518973 A CN 202210518973A CN 115514372 A CN115514372 A CN 115514372A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
- H03M3/30—Delta-sigma modulation
- H03M3/322—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M3/324—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement
- H03M3/344—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement by filtering other than the noise-shaping inherent to delta-sigma modulators, e.g. anti-aliasing
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
- H03M3/30—Delta-sigma modulation
- H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
- H03M3/412—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution
- H03M3/422—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only
- H03M3/424—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only the quantiser being a multiple bit one
- H03M3/426—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only the quantiser being a multiple bit one the quantiser being a successive approximation type analogue/digital converter
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Abstract
The invention discloses a conversion circuit and an electronic chip, wherein the conversion circuit comprises: the device comprises an input end coarse quantization module, a discrete domain amplification module, a continuous domain amplification module and an output end fine quantization module which are connected in sequence, wherein the discrete domain amplification module is used for pre-amplifying a conversion result input into the coarse quantization module so as to inhibit gain noise of the continuous domain amplification module, and the conversion circuit is a capacitance digital conversion circuit or an analog-digital conversion circuit. The invention realizes the fusion of the discrete domain and the continuous domain in the analog-digital conversion or capacitance-digital conversion circuit, so that the whole circuit not only has the advantages of high energy efficiency but also has high precision.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a conversion circuit and an electronic chip.
Background
With the development of the internet of things technology, more and more sensor chips are deployed at the nodes of the internet of things, and the chips at the nodes need to accurately sense environmental parameters. Usually, the Digital-to-Analog Converter (ADC) or the Capacitance-to-Digital Converter (CDC) is used to implement the method.
ADCs or CDCs are generally divided into two categories, discrete domain and continuous domain, which have their respective advantages and disadvantages, and discrete domain ADCs are generally selectable with much higher energy efficiency amplification, whereas when designing multi-bit (bit) quantization, additional design is generally required to reduce the effect of non-linearity, which increases system design complexity and power consumption. The continuous domain analog-to-digital converter has more advantages in designing multi-bit quantization, but has the problem of poor noise energy efficiency of continuous domain operational amplifier.
Disclosure of Invention
The invention provides a conversion circuit and an electronic chip, which are used for fusing a discrete domain and a continuous domain in an analog-to-digital conversion or capacitance-to-digital conversion circuit, so that the whole circuit has the advantages of high energy efficiency and high precision.
The invention provides a conversion circuit, comprising: the input end coarse quantization module, the discrete domain amplification module, the continuous domain amplification module and the output end fine quantization module are sequentially connected, the discrete domain amplification module is used for pre-amplifying a conversion result of the input coarse quantization module so as to inhibit gain noise of the continuous domain amplification module, and the conversion circuit is a capacitance digital conversion circuit or an analog-digital conversion circuit.
The invention also provides an electronic chip which comprises the conversion circuit.
The invention pre-amplifies the voltage difference value which is input in a fine quantization mode by arranging the discrete domain amplifying circuit, improves the input swing amplitude of the delta-sigma modulator, relieves the quantization pressure of the delta-sigma modulator, simultaneously, pre-amplifies the input signal which is input in a fine quantization mode, equivalently improves the pre-amplifying capability of gain transconductance, has higher energy efficiency, equivalently improves the energy efficiency of a gain transconductance stage, solves the energy efficiency problem of transconductance, improves the energy efficiency of a system, ensures the conversion precision of the fine quantization stage, and realizes a circuit framework which integrates a discrete domain and a continuous domain.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and those skilled in the art can obtain other drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a conversion circuit according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of another conversion circuit according to an embodiment of the present invention;
FIG. 3 is a detailed circuit diagram of the circuit shown in FIG. 2;
fig. 4 is a specific circuit diagram of a discrete domain amplifying module according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a differential operational amplifier powered by the floating capacitor in FIG. 4;
fig. 6a-6b are schematic diagrams of a circuit for performing gain error compensation by adjusting an integrating capacitor according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In order to make the technical solution of the present invention clearer, embodiments of the present invention are described in detail below with reference to the accompanying drawings.
In an existing ZOOM (ZOOM) -type structure-based conversion circuit, a first stage generally employs a Successive Approximation Register (SAR) analog-to-digital conversion circuit to perform coarse quantization on a detection signal, and then an output signal is sent to a delta-sigma modulator (DSM) of a second stage to perform analog-to-digital conversion for fine quantization. The delta-sigma modulator of the second-stage continuous domain has advantages in multi-bit quantization, but before the second-stage fine quantization, operational amplifier noise of a gain transconductance for converting a discrete output signal of a previous stage into a continuous signal for fine quantization is more and more non-negligible, so that energy efficiency improvement of the whole circuit is greatly limited, and therefore, before the second-stage fine quantization, noise of the gain transconductance needs to be suppressed to improve the whole energy efficiency of the circuit.
Fig. 1 is a schematic structural diagram of a conversion circuit according to an embodiment of the present invention, as shown in fig. 1, the circuit according to the embodiment includes: the system comprises an input end coarse quantization module 10, a discrete domain amplification module 20, a continuous domain amplification module 30 and an output end fine quantization module 40 which are connected in sequence, wherein the discrete domain amplification module 20 is used for pre-amplifying a conversion result input into the coarse quantization module 10 so as to inhibit gain noise of the continuous domain amplification module 30.
In this embodiment, the input end coarse quantization module 10 is configured to perform preliminary quantization on a detection signal, which is generally an analog signal or a detection capacitance value, that is, perform analog-to-digital conversion coarse quantization on the detection signal; the output-side fine quantization module 40 is used for performing further a/d conversion fine quantization on the quantization result of the input-side coarse quantization module 10,
since the continuous domain analog-to-digital conversion circuit has the advantage of multi-bit quantization, the output-side fine quantization module 40 in the embodiment of the present invention employs a delta-sigma modulator in a continuous domain, and therefore, the input terminal of the output-side fine quantization module 40 is provided with a continuous domain amplification module 30 for converting the quantization result in the discrete domain output by the input-terminal coarse quantization module 10 into voltage or current in the continuous domain, and the continuous domain amplification module may be a gain transconductance for re-amplifying and converting the signal amplified by the discrete domain amplification module into voltage or current, so as to control the oscillator in the output-side fine quantization module, that is, the voltage or current in the continuous domain converted by the output-side fine quantization module can directly drive the oscillator in the output-side fine quantization module 40.
In practical application, the final conversion accuracy of the conversion circuit with the ZOOM architecture also depends on the driving capability of the transconductance, but the gain of the transconductance is increased, and the thermal noise of the transconductance is more and more non-negligible, so that the conversion accuracy of the circuit is limited by the thermal noise of the transconductance, which is not beneficial to improving the energy efficiency of the whole circuit, that is, the improvement of the transconductance through the gain is limited in order to obtain both better energy efficiency and higher conversion accuracy. In order to make the subsequent stage circuit have a larger driving capability and not lower the energy efficiency, in the embodiment, the discrete domain amplifying module 20 is added before the continuous domain amplifying module 30 to equivalently improve the energy efficiency of the continuous domain amplifying module, so as to significantly suppress the noise in the continuous domain. Meanwhile, the discrete domain amplification module 20 may adopt an operational amplifier with high energy efficiency, such as an inverter type amplifier based on floating capacitor power supply, which not only improves the driving capability of the rear-stage circuit, but also meets the requirement of high energy efficiency, so that the whole circuit can realize high precision and low power consumption. In the case of higher accuracy requirements, the method can also be implemented by a method of compensating the gain error of the inverter type amplifier based on floating capacitor power supply, such as using the related level-shifting technique of charge redistribution in the following embodiments to compensate the gain error.
Fig. 2 is a schematic structural diagram of another conversion circuit provided in an embodiment of the present invention, and fig. 3 is a specific circuit diagram of the circuit shown in fig. 2, as shown in fig. 2 and fig. 3, the conversion circuit mainly includes an SAR digital-to-analog conversion loop, a discrete domain amplification and sampling module, and a continuous domain Δ Σ digital-to-analog conversion loop, where the SAR digital-to-analog conversion loop is used to perform first-stage analog-to-digital conversion on an input detection signal, and mainly includes a dynamic comparator, an SAR logic algorithm unit, and an SAR capacitor array. Completing input detection of capacitor C through SAR loop CDC Preliminary quantization of (2), wherein the detection capacitance C is input CDC The difference value of the corresponding base line capacitance in the SAR capacitor array is also input to a DP-CLS FIA in a discrete domain amplifying and Sampling module (DT) for operation and amplification, and the amplification result is stored in a Sampling capacitor (Sampling) for a back-end continuous domain delta-sigma digital-to-analog conversion loop (CT) to carry out fine quantization. Wherein, the gain transconductance Gm in the back-end continuous domain delta-sigma digital-to-analog conversion loop firstly amplifies and converts the voltage input by the front-end sampling capacitor into the voltage or the current of the continuous domain to driveThe moving back end refines the quantization loop.
Fig. 4 is a specific circuit diagram of a discrete domain amplification module according to an embodiment of the present invention, and fig. 5 is a schematic structural diagram of a floating capacitor powered differential operational amplifier in fig. 4, that is, the floating capacitor powered differential operational amplifier represented by diff.fia in a dashed box in fig. 4 selects an operational amplifier type according to requirements on power consumption and product performance in a specific application. As shown in fig. 4, the discrete domain amplifying module 20 may include: a first operational amplifier (Diff. FIA), a first sampling capacitor, a first integrating capacitor (C) INT ) And a correlated level sampling capacitor (C) connected to the output of the first operational amplifier CLS ) The first sampling capacitor is connected to the input end of the operational amplifier, samples and holds the input signal of the first operational amplifier, and during the operation of the first operational amplifier, according to the gain error of the first operational amplifier, the compensation voltage with the same error level and the opposite direction corresponding to the gain error is generated by adjusting the first integrating capacitor or adjusting the correlated level sampling capacitor. The gain error compensation is performed in two ways, as will be described in detail later.
In practical applications, when the requirement on the performance of the circuit is not very high, the discrete domain amplifying module may also be an operational Amplifier (FIA) powered by a conventional Inverter type Floating capacitor, and if the requirement on the accuracy is higher, the circuit shown in fig. 4 may be used.
In an actual circuit working process, in order to reduce the circuit power consumption, the discrete domain amplifying circuit 20 controls the working time sequence of the module access circuit through the control switch of each module, generally, at the beginning of the circuit working, the input sampling capacitor at the input end samples the input signal and stores the input information, then the first operational amplifier performs operational amplification processing on the input signal and outputs the input signal. In the process of eliminating the gain error, the related level sampling capacitor and the first integrating capacitor are connected into the circuit according to the time sequence by controlling the switch.
The operation of the amplifier is illustrated in FIGS. 4 and 5, by first controlling switches φ 4 and φ 6 to be closed and φ 3 and φ 5 to be open, the floating capacitor C is charged RES1 And C RES2 Charging is carried out, when the amplifier amplifies the input signal, phi 4 is firstly switched off to stop the direct current supply, phi 3 is switched on, and then the floating capacitor C is used for carrying out charging RES1 The circuit is powered up by controlling the switch phi 1 to be disconnected IN And phi 2 is closed to enable the circuit to enter a gain error estimation stage, the voltage needing to be compensated is calculated through a capacitance voltage division relation, and then phi is controlled 8N Disconnect the capacitor C CLS The charge on is maintained, opening φ 7 and closing φ 8 causes the capacitance C CLS The integration loop is connected, so that the charges are transferred to the integration capacitor, and the error level is compensated.
The first operational amplifier is an inverter type differential operational amplifier powered by a high-energy-efficiency floating capacitor as shown in fig. 5, the floating capacitor is used for supplying power to charge the floating capacitor and the operational amplifier is powered by the floating capacitor through time sequence control, when the operational amplifier is powered by the floating capacitor, the voltage on the power supply capacitor is gradually reduced along with the progress of the amplification process, so that the amplifier is gradually turned off, and the requirement of the amplifier on current in the amplification process is also gradually reduced, so that the energy efficiency of the amplifier can be remarkably improved.
In one embodiment, when the compensation voltage is generated by adjusting the correlated level sampling capacitor, the correlated level sampling capacitor is an adjustable capacitor, and includes a first capacitor array, the first capacitor array is a combination of capacitors connected in series, and the first capacitor array may include C connected in a dotted line frame at the output end of the amplifier in fig. 4 CLS ,C TRIM By adjusting the capacitance C TRIM The voltage division of (a) may be such that an error level resulting from a gain error of the first operational amplifier is obtainedAnd (6) compensation. Specifically, because of the finite gain of the first operational amplifier, a certain gain error may be generated when the first operational amplifier generates an output amplified signal according to an input signal, and the gain error may affect the analog-to-digital conversion accuracy in a subsequent circuit.
In another embodiment, the gain error may also be compensated by adjusting the first integrating capacitor, fig. 6a-6b are schematic diagrams of a circuit for performing gain error compensation by adjusting the first integrating capacitor according to the embodiment of the present invention, fig. 6a is a schematic diagram of a circuit in an estimation stage, and fig. 6b is a schematic diagram of a circuit in a shift stage, as shown in fig. 6a-6b, the first integrating capacitor includes a second capacitor array, and the integrating capacitor includes the second capacitor array.
In the above embodiment, the first integrating capacitor is adjusted according to the gain error of the first operational amplifier or the related level sampling capacitor is adjusted to generate the compensation voltage having the same magnitude and the opposite direction of the error level corresponding to the gain error, so that the error level is completely compensated, the output equivalent gain of the operational amplifier circuit is improved, and the conversion accuracy of the analog-to-digital conversion circuit at the rear end is ensured.
In terms of timing, the gain boost of the first operational amplifier includes three stages: inputting sampling input voltage of a sampling capacitor; estimating the error level generated by the gain error of the first operational amplifier; and compensating for the cancellation error level phase by level slip. The three working stages can be realized through sequential switch control, the first operational amplifier can be a large-swing operational amplifier in the stage of estimating the error level generated by the gain error of the first operational amplifier, and the first operational amplifier is a high-gain operational amplifier in the stage of compensating and offsetting the error level through level sliding. In an actual circuit, the operating modes of the operational amplifier in the estimation error level stage and the level sliding stage can be switched by controlling the switch, so that the operational amplifier correspondingly operates in a large-swing mode or a high-gain mode.
According to the embodiment of the invention, the discrete domain amplifying circuit is arranged to pre-amplify the voltage difference value subjected to fine quantization input, so that the input swing amplitude of the delta-sigma modulator is improved, the quantization pressure of the delta-sigma modulator is relieved, meanwhile, the pre-amplification capability of the gain transconductance is equivalently improved due to the fact that the discrete domain amplifying circuit is used for pre-amplifying the fine quantized input signal, and the energy efficiency of the gain transconductance is improved, namely the energy efficiency of the gain transconductance stage is improved, so that the energy efficiency of the system is improved, the conversion precision of the fine quantization stage is ensured, and the fusion circuit architecture of the discrete domain and the continuous domain is realized.
On the basis of the above embodiments, in a specific application, in order to improve the overall performance of the system, an analog-to-digital converter based on a Voltage Controlled Oscillator (VCO) is adopted in the delta-sigma modulator of the second-level fine quantization, so that the nonlinearity is averaged by natural shaping, and the delta-sigma modulator not only has the advantage of multi-bit quantization, but also can significantly reduce the oversampling rate of the delta-sigma modulator, and also has the advantage of a smaller area. In order to further improve the quantization precision, the delta-sigma analog-to-digital converter is based on a double voltage-controlled oscillator and correspondingly adopts a double frequency discrimination phase discriminator to quantize, so that the quantization precision can be improved by two times. The voltage Controlled Oscillator may be implemented by a ring inverter chain, such as a CCO (Current Controlled Oscillator) shown in fig. 2 and 3.
By adopting the continuous-time analog-to-digital converter based on the VCO, the embodiment of the invention has the characteristic of traversing the DAC unit in an innate cycle, so that the nonlinearity of the DAC is naturally shaped and averaged, and the continuous-time analog-to-digital converter has more advantages when multi-bit quantization is designed; by designing the VCO-based delta-sigma analog-to-digital converter based on the inverter chain, the system can have more advantages along with the reduction of process nodes.
In practical applications, a system-level chopper (chopper) may be connected to the input end before the coarse quantization module 10 performs coarse quantization on the input signal to reduce offset.
The suspension capacitor, the input sampling capacitor, the integrating capacitor and the related level sampling capacitor can be flat capacitors, interpolation capacitors or MOS capacitors, and are particularly adopted according to the actual application.
The embodiment of the invention also provides an electronic chip which comprises the conversion circuit, and the electronic chip has low power consumption and high precision. The electronic chip can be a temperature, humidity, pressure and other sensing chip.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (10)
1. A conversion circuit, comprising: the device comprises an input end coarse quantization module, a discrete domain amplification module, a continuous domain amplification module and an output end fine quantization module which are sequentially connected, wherein the discrete domain amplification module is used for pre-amplifying a conversion result input into the coarse quantization module so as to inhibit gain noise of the continuous domain amplification module, and the conversion circuit is a capacitance digital conversion circuit or an analog digital conversion circuit.
2. The circuit of claim 1, wherein the discrete domain amplification module is an inverter type amplifier powered based on a floating capacitor.
3. The circuit of claim 1 or 2, wherein the discrete domain amplification module comprises: the first operational amplifier is connected to an input end of the operational amplifier, samples and holds an input signal of the first operational amplifier, and during work of the first operational amplifier, compensation voltages with the same error level and the opposite direction corresponding to the gain error are generated by adjusting the first integral capacitor or adjusting the correlated level sampling capacitor according to the gain error of the first operational amplifier.
4. The circuit of claim 1, wherein the output fine quantization module is a delta-sigma analog-to-digital converter based on a voltage controlled oscillator.
5. The circuit of claim 4, wherein the delta-sigma analog-to-digital converter is a dual voltage controlled oscillator based delta-sigma analog-to-digital converter.
6. The circuit of claim 4 or 5, wherein the voltage controlled oscillator is a ring inverter chain structure.
7. The circuit of claim 4, wherein the continuous-domain amplification module is a gain transconductance, and is configured to amplify and convert the signal amplified by the discrete-domain amplification module into a voltage or a current to drive an oscillator in the output-side fine quantization module.
8. The circuit of claim 1, further comprising a system level chopper of the input access to reduce offset.
9. The circuit of claim 1, wherein the input coarse quantization module is based on a successive approximation analog-to-digital conversion circuit, and is configured to perform a first stage analog-to-digital conversion on the input detection signal.
10. An electronic chip, characterized in that it comprises a conversion circuit as claimed in claims 1 to 9.
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| CN202210518973.9A CN115514372A (en) | 2022-05-15 | 2022-05-15 | Conversion circuit and electronic chip |
| PCT/CN2023/094097 WO2023221901A1 (en) | 2022-05-15 | 2023-05-14 | Conversion circuit and electronic chip |
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| CN202210518973.9A CN115514372A (en) | 2022-05-15 | 2022-05-15 | Conversion circuit and electronic chip |
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| WO2023221901A1 (en) * | 2022-05-15 | 2023-11-23 | 杭州未名信科科技有限公司 | Conversion circuit and electronic chip |
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| US7944386B2 (en) * | 2008-10-21 | 2011-05-17 | Analog Devices, Inc. | Apparatus for and method of performing an analog to digital conversion |
| US11569826B2 (en) * | 2020-02-16 | 2023-01-31 | Board Of Regents, The University Of Texas System | Time-domain incremental two-step capacitance-to-digital converter |
| CN113225084B (en) * | 2021-04-16 | 2023-08-08 | 西安交通大学 | Delta-Sigma ADC structure of self-adaptive reference voltage |
| CN113381711A (en) * | 2021-05-25 | 2021-09-10 | 杭州微纳核芯电子科技有限公司 | Power consumption-based self-sensing dynamic charge domain amplifier array capacitance sensing chip |
| CN115514372A (en) * | 2022-05-15 | 2022-12-23 | 杭州未名信科科技有限公司 | Conversion circuit and electronic chip |
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| WO2023221901A1 (en) * | 2022-05-15 | 2023-11-23 | 杭州未名信科科技有限公司 | Conversion circuit and electronic chip |
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