CN115514363B - Low-power consumption analog-to-digital conversion circuit - Google Patents
Low-power consumption analog-to-digital conversion circuit Download PDFInfo
- Publication number
- CN115514363B CN115514363B CN202211401580.6A CN202211401580A CN115514363B CN 115514363 B CN115514363 B CN 115514363B CN 202211401580 A CN202211401580 A CN 202211401580A CN 115514363 B CN115514363 B CN 115514363B
- Authority
- CN
- China
- Prior art keywords
- circuit
- gate
- analog
- digital conversion
- power
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/002—Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
- H03M1/1245—Details of sampling arrangements or methods
- H03M1/126—Multi-rate systems, i.e. adaptive to different fixed sampling rates
Abstract
The application relates to the technical field of analog-to-digital conversion, and provides a low-power-consumption analog-to-digital conversion circuit. The circuit comprises a clock selection circuit, an input signal conditioning circuit and a modulation and demodulation circuit, wherein the input end of a first OR gate in the clock selection circuit is connected with an N-bit control bit, the input end of an output NAND gate is connected with the input end of a second AND gate, the output end of a NOT gate is connected with the input end of the first AND gate, the input end of the first AND gate is connected with an internal clock signal, the output end of the first AND gate is connected with the input end of the second OR gate, the input end of a rate selection circuit is connected with the N-bit control bit and an external clock signal, the result of the rate selection circuit is input into the second AND gate, and the output end of the second AND gate is connected with the input end of the second OR gate; the input signal conditioning circuit is used for filtering and amplifying an input analog signal; the modulation and demodulation circuit converts the filtered analog signal into a digital signal according to the clock rate, thereby realizing the balance of performance and power consumption.
Description
Technical Field
The present application relates to the field of analog-to-digital conversion technologies, and in particular, to a low power consumption analog-to-digital conversion circuit.
Background
At present, an analog-to-digital conversion circuit applied to a smart power grid only provides high sampling precision and sampling rate, and power consumption is high, or only provides low sampling precision and sampling rate, and power consumption is low, so that the balance between performance and power consumption can not be realized under the requirements of different sampling performances in some specific application scenarios.
Disclosure of Invention
In view of the above, it is necessary to provide a low power consumption analog-to-digital conversion circuit capable of achieving a balance between performance and power consumption.
The application provides a low-power consumption analog-to-digital conversion circuit, the circuit includes:
the clock selection circuit comprises a first OR gate, a second OR gate, a NOT gate, a first AND gate, a second AND gate and a rate selection circuit;
the input end of the first OR gate is connected with the N-bit control bit, and the input end of the output end NAND gate is connected with the input end of the second AND gate; the output end of the NOT gate is connected with the input end of the first AND gate; the input end of the first AND gate is also connected with an internal clock signal, and the output end of the first AND gate is connected with the input end of the second OR gate;
the input end of the speed selection circuit is connected with the N-bit control bit and an external clock signal, and the speed selection circuit is used for carrying out frequency multiplication or frequency division on the external clock signal according to the N-bit control bit and inputting a frequency multiplication or frequency division result into a second AND gate; n is a natural number more than or equal to 2;
the output end of the second AND gate is connected with the input end of the second OR gate;
the input signal conditioning circuit comprises an anti-aliasing filter circuit and a bias circuit; the passing frequency band of the anti-aliasing filtering circuit and the bandwidth of an operational amplifier in the bias circuit are in positive correlation with the clock rate determined by the clock selection circuit;
the input signal conditioning circuit is used for filtering an input analog signal and amplifying the filtered analog signal;
and the modulation and demodulation circuit is used for converting the filtered analog signal into a digital signal according to the clock rate output by the clock selection circuit.
In one embodiment, the low power analog-to-digital conversion circuit further includes:
a voltage reference circuit for providing a reference voltage for analog-to-digital conversion of the modulation and demodulation circuit to cause the modulation and demodulation circuit to convert an analog signal into a digital signal based on the reference voltage.
In one embodiment, the low power consumption analog-to-digital conversion circuit further includes:
a temperature sensing circuit for temperature compensating the voltage reference circuit.
In one embodiment, the low power consumption analog-to-digital conversion circuit further includes:
a data register for storing analog-to-digital conversion data and temperature data; the temperature data is data used when the temperature sensing circuit performs temperature compensation.
In one embodiment, the low power consumption analog-to-digital conversion circuit further includes:
and the ESD circuit is connected with an external IO circuit.
In one embodiment, the low power analog-to-digital conversion circuit further includes:
and the digital filter circuit is used for performing low-pass filtering and down-sampling on the digital signal output by the modulation and demodulation circuit.
In one embodiment, the low power consumption analog-to-digital conversion circuit further includes:
and the state register is used for storing configuration information and state information in the process of carrying out analog-to-digital conversion by the modulation and demodulation circuit.
In one embodiment, the low power consumption analog-to-digital conversion circuit further includes:
and the communication interface is a data interaction interface for carrying out digital communication between the low-power-consumption analog-to-digital conversion circuit and an external chip.
In one embodiment, the low power analog-to-digital conversion circuit further includes:
and the power distribution circuit is used for performing voltage stabilization and rectification on a power supply supplied by the outside so as to supply power to other circuits in the low-power-consumption analog-to-digital conversion circuit.
In one embodiment, the low power consumption analog-to-digital conversion circuit further includes:
and the power-down control circuit is used for controlling whether each circuit in the low-power-consumption analog-to-digital conversion circuit is in a power-down state or not.
The low-power consumption analog-to-digital conversion circuit comprises a clock selection circuit, an input signal conditioning circuit and a modulation and demodulation circuit. The clock selection circuit comprises a first OR gate, a second OR gate, a NOT gate, a first AND gate, a second AND gate and a rate selection circuit, wherein the input end of the first OR gate is connected with an N-bit control bit, the input end of an output end NAND gate is connected with the input end of the second AND gate, the output end of the NOT gate is connected with the input end of the first AND gate, the input end of the first AND gate is further connected with an internal clock signal, the output end of the first AND gate is connected with the input end of the second OR gate, the input end of the rate selection circuit is connected with the N-bit control bit and an external clock signal, the rate selection circuit is used for carrying out frequency multiplication or frequency division on the external clock signal according to the N-bit control bit and inputting a frequency multiplication or frequency division result into the second AND gate, N is a natural number larger than or equal to 2, and the output end of the second AND gate is connected with the input end of the second OR gate, so that clock signals with different rates can be output through the N-bit control bit.
The input signal conditioning circuit comprises an anti-aliasing filter circuit and a bias circuit, the passing frequency band of the anti-aliasing filter circuit and the bandwidth of an operational amplifier in the bias circuit are in positive correlation with the clock rate determined by the clock selection circuit, the input signal conditioning circuit is used for filtering an input analog signal and amplifying the filtered analog signal, and the modulation and demodulation circuit is used for converting the filtered analog signal into a digital signal according to the clock rate output by the clock selection circuit. Therefore, analog-to-digital conversion with different sampling rates or sampling precision is realized according to the clock signals with different rates output by the clock selection circuit, and balance between performance and power consumption is realized.
Drawings
FIG. 1 is a schematic diagram of a low power consumption analog-to-digital conversion circuit according to an embodiment;
FIG. 2 is a schematic diagram of an embodiment of a clock selection circuit;
FIG. 3 is a schematic diagram of a temperature sensing circuit in one embodiment;
FIG. 4 is a schematic flow chart of temperature compensation in one embodiment;
FIG. 5 is a schematic diagram of an embodiment of a power distribution circuit;
FIG. 6 is a schematic diagram of a power down control circuit in one embodiment;
FIG. 7 is a flow diagram of an embodiment of a low power analog to digital conversion circuit.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more clearly understood, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
Reference in the specification to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the specification. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.
At present, common analog-to-digital conversion circuit products are either oriented to high-frequency and high-speed application scenes to provide higher sampling rate or higher sampling precision without considering the low power consumption requirement, or oriented to low-power consumption application scenes to reduce the system power consumption by various means such as dormancy or reducing the system running speed. Common low-power consumption analog-to-digital conversion circuits usually reduce sampling frequency to obtain lower power consumption, the circuits cannot meet the requirements of scenes such as harmonic analysis in smart grid application, and the analog-to-digital conversion circuits which are high in sampling rate and sampling precision cannot meet the low-power consumption requirements of energy-limited scenes such as battery power supply.
Therefore, it is necessary to provide a high-precision analog-to-digital conversion circuit applied to a smart grid, which can adjust the pass frequency band of a system clock and an anti-aliasing filter and the bandwidth of an operational amplifier according to the characteristics of a signal to be sampled, flexibly configure the enabling state of a functional module, realize the balance between power consumption and performance under different monitoring requirements, not only solve the requirement of power consumption optimization under the application scene of limited energy supply, but also meet the requirement on the performance of a digital-to-analog converter under the specific monitoring requirement.
In view of this, in one embodiment, as shown in fig. 1, there is provided a low power consumption analog-to-digital conversion circuit, the circuit comprising:
the clock selection circuit comprises a first OR gate, a second OR gate, a NOT gate, a first AND gate, a second AND gate and a rate selection circuit;
the input end of the first OR gate is connected with the N-bit control bit, and the input end of the output end NAND gate is connected with the input end of the second AND gate; the output end of the NOT gate is connected with the input end of the first AND gate; the input end of the first AND gate is also connected with an internal clock signal, and the output end of the first AND gate is connected with the input end of the second OR gate;
the input end of the speed selection circuit is connected with the N-bit control bit and an external clock signal, and the speed selection circuit is used for carrying out frequency multiplication or frequency division on the external clock signal according to the N-bit control bit and inputting a frequency multiplication or frequency division result into a second AND gate; n is a natural number more than or equal to 2;
the output end of the second AND gate is connected with the input end of the second OR gate;
the input signal conditioning circuit comprises an anti-aliasing filter circuit and a bias circuit; the passing frequency band of the anti-aliasing filtering circuit and the bandwidth of the operational amplifier in the bias circuit are positively correlated with the clock rate determined by the clock selection circuit;
the input signal conditioning circuit is used for filtering an input analog signal and amplifying the filtered analog signal;
and the modulation and demodulation circuit is used for converting the filtered analog signal into a digital signal according to the clock rate output by the clock selection circuit.
Specifically, when the N-bit control bit is 4 bits, the clock selection circuit is described with reference to fig. 2, where an internal clock refers to an internal clock signal, an external clock refers to an external clock signal, A1, A2, A3, and A4 are 4-bit control bits, a first and gate is connected to the internal clock, a rate selection circuit is connected to the external clock, and an output of the clock is output by a second or gate.
The 4 bit control bits of A1, A2, A3 and A4 are connected through a first OR gate, one of the operated results is directly subjected to AND operation with the selected external clock, and the other path of the operation is subjected to the AND operation with the internal clock after the result obtained by the first OR gate OR operation on the 4 bit control bits of A1, A2, A3 and A4 is negated. And the two paths of clocks are connected through a second OR gate and then externally output to the input signal conditioning circuit and the modulation and demodulation circuit.
When the 4 bits of control bits of A1, A2, A3 and A4 are simultaneously 0, the result of or operation performed by the first or gate is 0, at this time, the result of and operation performed by the selected external clock is 0, and after inversion, the result of and operation performed by the first and gate and the internal clock is the output of the internal clock, and then the signal is output through the second or gate. When the 4-bit control bits of A1, A2, A3 and A4 have 1 bit not 0, the result of the first or gate or operation is 1, the result after negation is 0, and the result of the and operation of the internal clock through the first and gate is 0. The 4-bit control bits A1, A2, A3 and A4 are subjected to AND operation through the first OR gate and the selected external clock through the second AND gate to output the selected external clock signal, and the result of the AND operation with the internal clock is still the selected external clock signal. Meanwhile, because the rate selection circuit is internally provided with the frequency multiplication circuit and the frequency division circuit with different multiples, the clock signal is subjected to frequency multiplication or frequency division to obtain different clock rates, a high clock rate is selected, the sampling precision and the sampling rate are high, but the power consumption is high. The low clock rate is selected, the sampling precision and the sampling rate are low, and the power consumption is reduced at the same time. The user can be according to actual need nimble selection suitable clock rate when using, can realize the balance of consumption and performance, in this embodiment, if the internal clock adopts 40kHz, and the external clock adopts 1MHz, under 4 bit control positions are configured, can realize 16 grades of consumption and the accurate selection setting of sampling rate, and the effect is as follows:
| A4A3A2A1 | selecting | Clock rate |
| 0000 | Internal RC clock | 40kHz |
| 0001 | |
1MHz |
| 0010 | |
2MHz |
| 0011 | External clock 3 | 3MHz |
| 0100 | External clock 4 | 4MHz |
| 0101 | External clock 5 | 5MHz |
| 0110 | External clock 6 | 6MHz |
| 0111 | External clock 8 | 8MHz |
| 1000 | External clock 10 | 10MHz |
| 1001 | External clock 16 | 16MHz |
| 1010 | |
20MHz |
| 1011 | External clock/2 | 500kHz |
| 1100 | External clock/4 | 250kHz |
| 1101 | External clock/8 | 125kHz |
| 1110 | External clock/10 | 100kHz |
| 1111 | External clock/16 | 62.5kHz |
TABLE 1
The input signal conditioning circuit filters the analog signal according to the clock rate output by the clock selection circuit, amplifies the filtered analog signal, and removes interference signals influencing a sampling result during filtering. The amplification is to meet the requirements of the modulation and demodulation circuit on the input signal.
The modulation and demodulation circuit is also called as an SD (sigma-delta) modulation and demodulation circuit and is responsible for the work of noise shaping, analog signal conversion and the like, and the input analog signal is converted into a digital code stream to be output. The density of the output digital code stream represents the strength of the input signal. After the input signal conditioning circuit filters and amplifies the input analog signal, because the sampling rate and the sampling precision of the modulation and demodulation circuit are in positive correlation with the clock rate, the modulation and demodulation circuit adjusts the sampling rate and the sampling precision to perform analog-to-digital conversion on the filtered and amplified analog signal according to the clock rate output by the clock selection circuit.
The low-power consumption analog-to-digital conversion circuit comprises a clock selection circuit, an input signal conditioning circuit and a modulation and demodulation circuit. The clock selection circuit comprises a first OR gate, a second OR gate, a NOT gate, a first AND gate, a second AND gate and a rate selection circuit, wherein the input end of the first OR gate is connected with an N-bit control bit, the input end of an output end NAND gate is connected with the input end of the second AND gate, the output end of the NOT gate is connected with the input end of the first AND gate, the input end of the first AND gate is further connected with an internal clock signal, the output end of the first AND gate is connected with the input end of the second OR gate, the input end of the rate selection circuit is connected with the N-bit control bit and an external clock signal, the rate selection circuit is used for carrying out frequency multiplication or frequency division on the external clock signal according to the N-bit control bit and inputting a frequency multiplication or frequency division result into the second AND gate, N is a natural number which is more than or equal to 2, and the output end of the second AND gate is connected with the input end of the second OR gate, and therefore, clock signals with different rates can be output through the N-bit control bit.
The input signal conditioning circuit comprises an anti-aliasing filter circuit and a bias circuit, the passing frequency band of the anti-aliasing filter circuit and the bandwidth of an operational amplifier in the bias circuit are in positive correlation with the clock rate determined by the clock selection circuit, the input signal conditioning circuit is used for filtering an input analog signal and amplifying the filtered analog signal, and the modulation and demodulation circuit is used for converting the filtered analog signal into a digital signal according to the clock rate output by the clock selection circuit. Therefore, analog-to-digital conversion with different sampling rates or sampling precision is realized according to the clock signals with different rates output by the clock selection circuit, and the balance between the performance and the power consumption is realized.
In one embodiment, the low power consumption analog-to-digital conversion circuit further includes: a voltage reference circuit for providing a reference voltage for analog-to-digital conversion of the modulation and demodulation circuit to cause the modulation and demodulation circuit to convert an analog signal into a digital signal based on the reference voltage.
The voltage reference circuit provides reference voltage for system data conversion, and the conversion result of the analog-to-digital conversion circuit is the operation result of the digital reading and the reference source voltage, so that the accuracy of the final data conversion result is directly influenced by the voltage accuracy of the voltage reference, and the accuracy of the analog-to-digital conversion result is ensured by arranging the voltage reference circuit.
In one embodiment, the low power consumption analog-to-digital conversion circuit further includes: a temperature sensing circuit for temperature compensating the voltage reference circuit.
Specifically, the description will be made with reference to fig. 3, in which the temperature compensation reference circuit performs temperature compensation on the voltage reference circuit, the built-in parameter refers to a built-in temperature compensation parameter, the external input parameter refers to a temperature compensation parameter inputted from the outside, and the reference source output refers to a voltage outputted from the voltage reference circuit after the temperature compensation. Because the analog-to-digital conversion circuit uses semiconductor devices which have certain temperature characteristics, the output voltages of the basic voltage reference circuit at different temperatures are slightly different, and temperature compensation is needed to obtain more accurate voltage output.
Temperature compensation of the voltage reference circuit requires the use of a temperature sensing circuit and a temperature compensation circuit. The temperature sensor is used for acquiring the temperature condition of the circuit, and the temperature result can be used for internal temperature compensation and can be output externally, so that the external circuit reads the temperature result for other purposes. The basic process of temperature compensation is to test the output of the voltage reference circuit at different temperatures, and adjust the output of different temperature points by using a compensation algorithm to correct the voltage offset caused by the temperature. Temperature compensation requires calibration tests at different temperature points, and the time required for temperature stabilization is long, so that limited data calibration can be performed only at discrete temperature points. If the user wants more precise temperature compensation or improves the compensation precision in a specific temperature interval, the calibration test can be carried out again at the interested temperature point by selecting an external compensation mode to obtain the compensation parameters so as to meet the personalized requirement.
Referring to fig. 4, in the process of temperature compensation, a temperature point list to be compensated is generated according to a temperature point to be compensated by a user, the temperature control box is controlled to set a temperature value to a first point, and after the temperature is stabilized, an output value of a reference voltage source of the voltage reference circuit is measured. Similar operations are performed at all temperature points in the temperature point list, temperature is set, the temperature is waited for to stabilize, and the output of the reference voltage source is measured. After all the temperature points complete parameter measurement, the internal program calculates the output relation between the temperature points and the pressure values of the reference points to generate a temperature compensation coefficient. And in the use process of the subsequent chip, temperature compensation is carried out on the reference voltage according to the measured temperature value of the built-in temperature sensor and the temperature compensation coefficient of the temperature value, so that the influence of temperature change on the voltage reference circuit is eliminated.
In one embodiment, the low power consumption analog-to-digital conversion circuit further includes: a data register for storing analog-to-digital conversion data and temperature data; the temperature data is data used when the temperature sensing circuit carries out temperature compensation.
Specifically, during the analog-to-digital conversion process, a large amount of data is generated, including data related to signals during the analog-to-digital conversion process and temperature data for temperature compensation, and the data is stored through a data register.
In one embodiment, the low power analog-to-digital conversion circuit further includes: and the ESD circuit is connected with an external IO circuit.
Specifically, the ESD circuit is responsible for external IO circuit connection and ESD protection of the chip, and ensures that the ESD circuit has certain antistatic capability during signal input and output and cannot be easily subjected to electrostatic breakdown.
In one embodiment, the low power consumption analog-to-digital conversion circuit further includes: and the digital filter circuit is used for performing low-pass filtering and down-sampling on the digital signal output by the modulation and demodulation circuit.
Specifically, the digital filter circuit comprises two functions of low-pass filtering and down-sampling, high-frequency components with high noise are filtered out through the low-pass filtering, signals are converted into signals with low speed through the down-sampling, and the signals are output to the outside, so that the requirement on the reading speed of an external data analysis chip is lowered.
In one embodiment, the low power consumption analog-to-digital conversion circuit further includes: and the state register is used for storing configuration information and state information in the process of carrying out analog-to-digital conversion by the modulation and demodulation circuit.
For example, the state register may store a sleep control state and a converted data output start state, and when the sleep control bit is in the sleep mode, the preceding circuits (including the voltage reference circuit, the temperature sensing circuit, the clock selection circuit, the input signal conditioning circuit, the modulation and demodulation circuit, the digital filter circuit, and the like) of the system are all in the sleep state, so that the power consumption of the system is greatly reduced. When the sleep control bit is in a non-sleep mode, all core circuits required by system conversion are powered on to enter a working state, the data conversion start output state bit is converted when the system data conversion is finished and the conversion result is started to be output, information capable of reading data is transmitted to the outside, and the outside single chip microcomputer starts to read the conversion data of the analog-digital converter after detecting the signal.
In one embodiment, the low power analog-to-digital conversion circuit further includes: and the communication interface is a data interaction interface for carrying out digital communication between the low-power-consumption analog-to-digital conversion circuit and an external chip.
Specifically, the communication interface provides a data interaction interface for digital communication with an external chip, follows an SPI protocol, and can use a single chip microcomputer with the SPI interface or an IO port analog SPI protocol to read data and states of the analog-to-digital converter and set some states and parameters of the analog-to-digital converter.
In one embodiment, the low power consumption analog-to-digital conversion circuit further includes: and the power distribution circuit is used for performing voltage stabilization and rectification on a power supply supplied by the outside so as to supply power to other circuits in the low-power-consumption analog-to-digital conversion circuit.
Specifically, as shown in fig. 5, the power distribution circuit includes a voltage stabilizing circuit and a filter circuit, and is responsible for inputting power supplied from the outside, and after voltage stabilization and filtering, distributing the power to the voltage reference circuit, the system analog circuit and the system digital circuit, where the system analog circuit includes a clock selection circuit, an input signal conditioning circuit and a modulation and demodulation circuit, and the system digital circuit includes a digital filter circuit. Because the type of the power supplied from the outside is not fixed, and the power may be a rechargeable battery, a dry battery, or a conversion energy such as solar energy and wind energy, the voltage range, the voltage stability and the like of the input power are different, so the input power is stabilized to the voltage required by the operation of the back-end circuit through the voltage stabilizing circuit.
In one embodiment, the low power consumption analog-to-digital conversion circuit further includes: and the power-down control circuit is used for controlling whether each circuit in the low-power-consumption analog-to-digital conversion circuit is in a power-down state or not.
During the analog-to-digital conversion, some functionally redundant circuits may still be powered up, causing some unnecessary power consumption. In order to further reduce the system Power consumption, a Power Down state, namely a Power Down state, is designed for each functional module, and the circuit can be flexibly set to the Power Down state when the functional circuit is not used, so that the system Power consumption is reduced to the maximum extent. Specifically, the power down control circuit may be as shown in fig. 6, where Module _ PD is a Module power control bit and can control a power down state of a Module. VDD is the positive pole of the system Power supply, VSS is the negative pole of the system Power supply (the circuit is connected with GND and the ground level when in application), P33 is a P-channel MOSFET (PMOS), N33 is an N-channel MOSFET (NMOS), and Module _ Power is the Module Power supply line, and is connected to the Module Power supply input to supply Power for the Module. Therefore, the power supply of the redundant module is not needed in the adaptability of a specific application scene, the power consumption of the analog-to-digital conversion circuit is reduced, meanwhile, if the analog-to-digital conversion is not needed for a long time, the power distribution circuit can be closed to be in a power-down state, the power of the whole chip is closed, the chip is set to be in the power-down state, and the energy consumption is reduced to the maximum extent.
In order to better understand the low power analog-to-digital conversion circuit, an application example of the low power analog-to-digital conversion circuit provided by the present application is described in detail below.
In the process of converting a traditional power grid into a smart power grid, the electric power secondary equipment is required to have stronger interface capability, control capability, protection capability, measurement capability, communication capability and data processing capability, and the analog-to-digital converter is one of key devices which need to be considered in system design as a bridge for connecting an analog signal and a digital processing circuit.
Because the smart grid monitoring sensor mostly works in the scene of limited energy such as battery power supply or optical fiber power supply, the power consumption becomes a factor which must be considered when the system is designed. The power consumption of the chip is related to various factors such as the operation rate, the circuit structure and the like, and the reduction of the system power consumption can be realized by reducing the system operation rate or optimizing the circuit structure. However, decreasing the rate often means a decrease in circuit performance such as switching speed and switching accuracy. Therefore, when the system is designed, the balance selection between the power consumption and the performance of the circuit is needed according to the difference of the monitoring parameters.
At present, a multi-channel 16-bit synchronous sampling ADC applied in a power system generally has a low power consumption mode, and a chip is set to a sleep mode when sampling is not needed so as to save power consumption. However, this method is either high power sampling or sampling is not performed in the sleep mode, and thus, flexibility in application is lacking. Besides the sleep mode, the invention supports the selection of various clock rates to adjust the sampling bandwidth, and meanwhile, the matched signal conditioning circuit is dynamically adjusted according to the sampling bandwidth configuration, so that the proper performance and power consumption can be flexibly selected according to the characteristics of the acquired signals, and the power consumption is reduced to the lowest under the premise of ensuring the basic sampling function.
In order to ensure the system performance, a low power consumption mode with a limit is not designed in the design of the general-purpose ADC, and when the system works, some functional redundant circuits are still in a power-on state, which causes some unnecessary power consumption. In order to further reduce the system Power consumption, the Power Down mode, namely the Power Down modulus, is designed for each functional module, and the module can be flexibly set to the Power Down mode when the functional module is not used, so that the system Power consumption is reduced to the maximum extent.
Based on the low-power-consumption high-precision analog-to-digital conversion circuit applied to the smart grid, the balance of power consumption and performance under different monitoring requirements is realized by selecting different sampling bandwidths and flexibly configuring the enabling states of the functional modules, the requirement of power consumption optimization under the application scene with limited energy supply can be met, and the requirement on the performance of an analog-to-digital converter under the specific monitoring requirement can be met.
The analog-to-digital conversion circuit comprises a clock selection circuit, an input signal conditioning circuit, a modulation and demodulation circuit, a voltage reference circuit, a temperature sensing circuit, a data register, a state register, an ESD circuit, a digital filter circuit, a power distribution circuit, a communication interface and a power failure control circuit.
Referring to fig. 7, firstly, after the system is powered on, the system determines the working state according to the sleep control bit, and if the sleep control bit is in the sleep state, the system shuts down the power supply of the clock selection circuit, the input signal conditioning circuit, the temperature sensing circuit, the voltage reference circuit, the modulation and demodulation circuit, the digital filter circuit and other functional modules so as to reduce the energy consumption of the system to the maximum extent. The sleep state is different from the power-down state, the power supplies of all functional modules of the power-down state system are completely powered off, no available function exists, and in the sleep mode, the system uses a clock with the lowest speed rate to maintain the most basic communication function, so that the outside can wake up a chip or read some basic register data through a data bus, and can be quickly started when being woken up from the sleep state without too long power-on waiting time.
When the system starts conversion from a sleep state, the system firstly supplies power to the modules such as the clock selection circuit, the input signal conditioning circuit, the temperature sensing circuit, the voltage reference circuit, the modulation and demodulation circuit, the digital filter circuit and the like which are closed in the sleep mode, recovers the functions of the system, selects a proper working clock rate according to the setting of the clock selection circuit, adjusts the passing frequency band of the anti-aliasing filter in the input signal conditioning circuit and the bandwidth of the operational amplifier, and starts analog-to-digital conversion. When the analog-to-digital conversion is started, the conversion completion state control bit is cleared firstly, and the conversion completion state control bit is set after the data conversion is completed. When reading chip data, the control circuit such as an external singlechip reads the state control bit at first, and valid data can be read only when the bit is in a set state.
Specifically, power supply for each module is mainly realized through a power distribution circuit, as shown in fig. 5, the power distribution circuit includes a voltage stabilizing circuit and a filter circuit, and is responsible for inputting power supplied from the outside, and after voltage stabilization and filtering, the power is distributed to a voltage reference circuit, a system analog circuit and a system digital circuit, the system analog circuit includes a clock selection circuit, an input signal conditioning circuit and a modulation and demodulation circuit, and the system digital circuit includes a digital filter circuit. Because the type of the power supplied from the outside is not fixed, and the power may be a rechargeable battery, a dry battery, or a conversion energy such as solar energy and wind energy, the voltage range, the voltage stability and the like of the input power are different, so the input power is stabilized to the voltage required by the operation of the back-end circuit through the voltage stabilizing circuit.
If the external circuit needs to sample a higher signal frequency (if a fundamental wave signal needs to be subjected to higher harmonic analysis), a system operation clock with a higher rate is selected according to needs, and the passing frequency band of the anti-aliasing filter and the bandwidth of the operational amplifier are adjusted, so that the system has high sampling capability and high power consumption. If the external circuit does not need to sample a higher signal frequency (for example, only data acquisition and analysis are performed on a fundamental wave signal), a system operation clock with a lower speed is selected according to needs, and the passing frequency band of the anti-aliasing filter and the bandwidth of the operational amplifier are adjusted, so that the system can only acquire the signal with the lower speed, and meanwhile, the power consumption is greatly reduced.
Specifically, for the above analog-to-digital conversion process, with reference to fig. 2, a description is given when the control bit is 4 bits, where the internal clock refers to an internal clock signal, the external clock refers to an external clock signal, A1, A2, A3, and A4 are 4-bit control bits, the internal clock is connected to a first and gate, the external clock is connected to a rate selection circuit, and the output of the clock is output by a second or gate.
The 4 bit control bits of A1, A2, A3 and A4 are connected through a first OR gate, one of the operated results is directly subjected to AND operation with the selected external clock, and the other path of the operation is subjected to the AND operation with the internal clock after the result obtained by the first OR gate OR operation on the 4 bit control bits of A1, A2, A3 and A4 is negated. And the two paths of clocks are connected through a second OR gate and then externally output to the input signal conditioning circuit and the modulation and demodulation circuit.
When the 4 bits of control bits of A1, A2, A3 and A4 are simultaneously 0, the result of or operation performed by the first or gate is 0, at this time, the result of and operation performed by the selected external clock is 0, and after inversion, the result of and operation performed by the first and gate and the internal clock is the output of the internal clock, and then the signal is output through the second or gate. When the 4-bit control bits of A1, A2, A3 and A4 have 1 bit not 0, the result of the first or gate or operation is 1, the result after negation is 0, and the result of the and operation of the internal clock through the first and gate is 0. The result of the OR operation of the 4-bit control bits A1, A2, A3 and A4 through the first OR gate and the selected external clock are subjected to the AND operation through the second AND gate and output as the selected external clock signal, and the result of the AND operation with the internal clock is still the selected external clock signal. Meanwhile, the rate selection circuit is internally provided with the frequency multiplication circuit and the frequency division circuit with different multiples, so that the clock signals are subjected to frequency multiplication or frequency division to obtain different clock rates, a high clock rate is selected, the sampling precision and the sampling rate are high, but the power consumption is high. The low clock rate is selected, the sampling precision and the sampling rate are low, and the power consumption is reduced at the same time. In the embodiment, the internal clock adopts a RC clock of 40kHz, the external clock adopts 1MHz, the internal RC clock has low power consumption and low precision, and the internal RC clock is generally only used for maintaining the basic operation of a system or acquiring sensing data with low speed and low signal-to-noise ratio. The external clock has high precision and is used for data acquisition with high precision, and the configuration of A1, A2, A3 and A4 is flexibly set to select a proper clock rate according to the specific requirements of the power consumption and precision of the system. Under the configuration of the 4-bit control bit, the accurate selection setting of 16-level power consumption and sampling rate can be realized, and the effect can be seen in table 1.
The input signal conditioning circuit filters the analog signal according to the clock rate output by the clock selection circuit, amplifies the filtered analog signal, and removes interference signals influencing a sampling result during filtering. The amplification is to meet the requirements of the modulation and demodulation circuit on the input signal.
The modulation and demodulation circuit is also called as an SD (sigma-delta) modulation and demodulation circuit and is responsible for the work of noise shaping, analog signal conversion and the like, and the input analog signal is converted into a digital code stream to be output. The density of the output digital code stream represents the strength of the input signal. After the input signal conditioning circuit filters and amplifies the input analog signal, because the sampling rate and the sampling precision of the modulation and demodulation circuit are in positive correlation with the clock rate, the modulation and demodulation circuit adjusts the sampling rate and the sampling precision to perform analog-to-digital conversion on the filtered and amplified analog signal according to the clock rate output by the clock selection circuit.
In the analog-to-digital conversion process, the voltage reference circuit provides reference voltage for system data conversion, and the conversion result of the analog-to-digital conversion circuit is the operation result of the digital reading and the reference source voltage, so that the voltage accuracy of the voltage reference directly influences the accuracy of the final data conversion result, and the accuracy of the analog-to-digital conversion result is ensured by arranging the voltage reference circuit.
In the analog-to-digital conversion process, the temperature sensing circuit is responsible for collecting the temperature of the chip so as to realize the temperature compensation of the voltage reference source. The temperature compensation process is realized by testing the voltage output at different temperatures to obtain an actual temperature-voltage curve, and then adjusting the output at different temperatures according to a compensation algorithm. The temperature compensation parameters are recorded in a built-in memory of the chip after temperature-voltage test before the chip leaves the factory. The user may also choose an external parameter correction if needed to correct a particular temperature point or to improve the accuracy of the overall temperature correction.
In the analog-to-digital conversion process, the ESD circuit is responsible for external IO circuit connection and ESD protection of the chip, and certain antistatic capacity is achieved when signal input and signal output are guaranteed, so that the ESD circuit cannot be easily subjected to electrostatic breakdown.
In the analog-digital conversion process, the digital filter circuit has two functions of low-pass filtering and down-sampling, high-frequency components with high noise are filtered out through the low-pass filtering, and the signals are converted into signals with lower speed through the down-sampling and are output to the outside, so that the reading speed requirement on an external data analysis chip is reduced.
During the analog-to-digital conversion process, the data register and the status register store the conversion data of the analog-to-digital converter, the temperature data of the temperature sensor, and various configuration and status information.
In the analog-to-digital conversion process, the power-down control circuit is used for controlling whether each circuit in the low-power-consumption analog-to-digital conversion circuit is in a power-down state or not. Some functionally redundant circuits may still be powered up while analog-to-digital conversion is taking place, causing some unnecessary power consumption. In order to further reduce the system Power consumption, the Power Down state is designed for each functional module, and the circuit can be flexibly set to the Power Down state when the functional circuit is not used, so that the system Power consumption is reduced to the maximum extent. Specifically, the power down control circuit may be as shown in fig. 6, where Module _ PD is a Module power control bit and can control a power down state of a Module. VDD is the positive pole of the system Power supply, VSS is the negative pole of the system Power supply (circuit application is connected with GND, ground level), P33 is P channel MOSFET (PMOS), N33 is N channel MOSFET (NMOS), module _ Power is the Module Power supply line, connect to the Module Power supply input, supply Power for the Module, when Module _ PD is high level, PMOS turns off, NMOS switches on, module _ Power and VSS switch on, the rear Module stops supplying Power, when Module _ PD is low level, PMOS switches on, NMOS turns off, module _ Power and VDD switch on, supply Power for the rear Module. Therefore, power supply for the redundant module is not needed in the adaptability of a specific application scene, power consumption of the analog-digital conversion circuit is reduced, the circuit can be set to be in a sleep mode when an external system does not need a data conversion function in a short time, if data conversion is not needed for a long time, the overall power supply of the chip can be turned off, the chip is set to be in a power-down state, and energy consumption is reduced to the maximum extent.
It should be understood that, although the steps in the flowcharts related to the embodiments as described above are sequentially displayed as indicated by arrows, the steps are not necessarily performed sequentially as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least a part of the steps in the flowcharts related to the embodiments described above may include multiple steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, and the execution order of the steps or stages is not necessarily sequential, but may be performed alternately or alternately with other steps or at least a part of the steps or stages in other steps.
All possible combinations of the technical features in the above embodiments may not be described for the sake of brevity, but should be considered as being within the scope of the present disclosure as long as there is no contradiction between the combinations of the technical features.
The above examples only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. A low power analog-to-digital conversion circuit, the circuit comprising:
the clock selection circuit comprises a first OR gate, a second OR gate, a NOT gate, a first AND gate, a second AND gate and a rate selection circuit;
the input end of the first OR gate is connected with the N-bit control bit, and the input end of the output end NAND gate is connected with the input end of the second AND gate; the output end of the NOT gate is connected with the input end of the first AND gate; the input end of the first AND gate is also connected with an internal clock signal, and the output end of the first AND gate is connected with the input end of the second OR gate;
the input end of the speed selection circuit is connected with the N-bit control bit and an external clock signal, and the speed selection circuit is used for carrying out frequency multiplication or frequency division on the external clock signal according to the N-bit control bit and inputting a frequency multiplication or frequency division result into a second AND gate; n is a natural number more than or equal to 2;
the output end of the second AND gate is connected with the input end of the second OR gate;
the input signal conditioning circuit comprises an anti-aliasing filter circuit and a bias circuit; the pass frequency band of the anti-aliasing filter circuit and the bandwidth of an operational amplifier in the bias circuit are in positive correlation with the clock rate determined by the clock selection circuit;
the input signal conditioning circuit is used for filtering an input analog signal and amplifying the filtered analog signal;
and the modulation and demodulation circuit is used for converting the filtered analog signal into a digital signal according to the clock rate output by the clock selection circuit.
2. The low power analog-to-digital conversion circuit of claim 1, further comprising:
a voltage reference circuit for providing a reference voltage for analog-to-digital conversion by the modulation and demodulation circuit to cause the modulation and demodulation circuit to convert an analog signal into a digital signal based on the reference voltage.
3. The low power analog-to-digital conversion circuit of claim 2, further comprising:
a temperature sensing circuit for temperature compensating the voltage reference circuit.
4. The low power analog-to-digital conversion circuit of claim 3, further comprising:
a data register for storing analog-to-digital conversion data and temperature data; the temperature data is data used when the temperature sensing circuit performs temperature compensation.
5. The low power analog-to-digital conversion circuit of claim 1, further comprising:
and the ESD circuit is connected with an external IO circuit.
6. The low power analog-to-digital conversion circuit of claim 1, further comprising:
and the digital filter circuit is used for low-pass filtering and down-sampling the digital signal output by the modulation and demodulation circuit.
7. The low power analog-to-digital conversion circuit of claim 1, further comprising:
and the state register is used for storing configuration information and state information in the process of carrying out analog-to-digital conversion by the modulation and demodulation circuit.
8. The low power analog-to-digital conversion circuit of claim 1, further comprising: and the communication interface is a data interaction interface for carrying out digital communication between the low-power-consumption analog-to-digital conversion circuit and an external chip.
9. The low power analog-to-digital conversion circuit according to any one of claims 1 to 8, further comprising:
and the power distribution circuit is used for performing voltage stabilization and rectification on a power supply supplied by the outside so as to supply power to other circuits in the low-power-consumption analog-to-digital conversion circuit.
10. The low power analog-to-digital conversion circuit of claim 9, further comprising:
and the power-down control circuit is used for controlling whether each circuit in the low-power-consumption analog-to-digital conversion circuit is in a power-down state or not.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211401580.6A CN115514363B (en) | 2022-11-09 | 2022-11-09 | Low-power consumption analog-to-digital conversion circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211401580.6A CN115514363B (en) | 2022-11-09 | 2022-11-09 | Low-power consumption analog-to-digital conversion circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN115514363A CN115514363A (en) | 2022-12-23 |
| CN115514363B true CN115514363B (en) | 2023-01-20 |
Family
ID=84513917
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211401580.6A Active CN115514363B (en) | 2022-11-09 | 2022-11-09 | Low-power consumption analog-to-digital conversion circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115514363B (en) |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1279844A (en) * | 1997-10-06 | 2001-01-10 | 趣点公司 | Beamformed ultrasonic imager with delta-sigma feedback control |
| US6442213B1 (en) * | 1997-04-22 | 2002-08-27 | Silicon Laboratories Inc. | Digital isolation system with hybrid circuit in ADC calibration loop |
| CN1423859A (en) * | 2000-03-04 | 2003-06-11 | 高通股份有限公司 | Digital-to-analog interface circuit having adjustable time response |
| CN101593221A (en) * | 2008-05-28 | 2009-12-02 | 北京中电华大电子设计有限责任公司 | A kind of foreign lands' clock that prevents dynamically switches the Method and circuits of burr |
| CN102201802A (en) * | 2011-03-28 | 2011-09-28 | 东南大学 | Timing sequence optimization method of anti-burr clock selector and circuit thereof |
| CN105009458A (en) * | 2013-02-21 | 2015-10-28 | 瑞典爱立信有限公司 | A frequency selective circuit configured to convert an analog input signal to a digital output signal |
| CN113014264A (en) * | 2021-03-26 | 2021-06-22 | 中山大学 | Analog-digital converter with multi-mode selection |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6686860B2 (en) * | 2000-12-12 | 2004-02-03 | Massachusetts Institute Of Technology | Reconfigurable analog-to-digital converter |
| CN109361393A (en) * | 2014-12-26 | 2019-02-19 | 华为技术有限公司 | A kind of analog-digital converter and D conversion method |
-
2022
- 2022-11-09 CN CN202211401580.6A patent/CN115514363B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6442213B1 (en) * | 1997-04-22 | 2002-08-27 | Silicon Laboratories Inc. | Digital isolation system with hybrid circuit in ADC calibration loop |
| CN1279844A (en) * | 1997-10-06 | 2001-01-10 | 趣点公司 | Beamformed ultrasonic imager with delta-sigma feedback control |
| CN1423859A (en) * | 2000-03-04 | 2003-06-11 | 高通股份有限公司 | Digital-to-analog interface circuit having adjustable time response |
| CN101593221A (en) * | 2008-05-28 | 2009-12-02 | 北京中电华大电子设计有限责任公司 | A kind of foreign lands' clock that prevents dynamically switches the Method and circuits of burr |
| CN102201802A (en) * | 2011-03-28 | 2011-09-28 | 东南大学 | Timing sequence optimization method of anti-burr clock selector and circuit thereof |
| CN105009458A (en) * | 2013-02-21 | 2015-10-28 | 瑞典爱立信有限公司 | A frequency selective circuit configured to convert an analog input signal to a digital output signal |
| CN113014264A (en) * | 2021-03-26 | 2021-06-22 | 中山大学 | Analog-digital converter with multi-mode selection |
Non-Patent Citations (1)
| Title |
|---|
| "一种全双工射频收发系统的设计与实现";谢作全等;《电脑与电信》;20170610;正文第31-33页 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN115514363A (en) | 2022-12-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9729189B2 (en) | Ultra low power sensing platform with multimodal radios | |
| CN103336667A (en) | General multi-channel data collection system | |
| Peiris et al. | A 1 V 433/868 MHz 25 kb/s-FSK 2 kb/s-OOK RF transceiver SoC in standard digital 0.18/spl mu/m CMOS | |
| CN213094182U (en) | Data acquisition equipment with self calibration function | |
| CN101123436A (en) | Analog to digital converter with interference rejection capability | |
| WO2018223100A1 (en) | System on a chip with customized data flow architecture | |
| CN205123711U (en) | Analog -to -digital conversion chip volume production test circuit | |
| CN115514363B (en) | Low-power consumption analog-to-digital conversion circuit | |
| CN110032126B (en) | Multichannel strain signal synchronous acquisition system and method | |
| CN109375092B (en) | IIC protocol-based dual-detection-mode sensor control interface circuit | |
| CN112947379A (en) | Multi-channel small signal measurement and control system hardware platform based on FPGA | |
| CN110113028A (en) | Constant calibrates circuit when the partial pressure integral form of on-chip active RC filter | |
| US9007244B2 (en) | Sampling rate based adaptive analog biasing | |
| CN107094017A (en) | A kind of Sensing interface system of multipurpose super low-power consumption | |
| CN116539212A (en) | Ultralow-power-consumption conditioning circuit and method suitable for resonant tire pressure sensor | |
| CN206504813U (en) | Pressure detecting system based on gain-programmed amplifier | |
| CN115524532A (en) | Signal acquisition circuit and signal acquisition method | |
| CN206864190U (en) | A kind of noise analyzer recording response control system | |
| Wang et al. | An RFID tag system-on-chip with wireless ECG monitoring for intelligent healthcare systems | |
| CN206450320U (en) | A kind of high-performance high-speed motion mechanism dynamic characteristic tester | |
| CN103904373A (en) | Battery current management device | |
| CN219476018U (en) | Voltage analog acquisition module | |
| Jotschke et al. | Low-power modular multi-sensor node with ZeSCIP analog frontend | |
| CN113466544A (en) | Integrated circuit chip with temperature drift correction function | |
| CN211579954U (en) | Single-power-supply synchronous data acquisition device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |