CN115513207A

CN115513207A - Semiconductor memory device with a plurality of memory cells

Info

Publication number: CN115513207A
Application number: CN202210649266.3A
Authority: CN
Inventors: 金恩靓; 金铉用; 李相昊; 安容奭; 崔宰福
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 2021-06-22
Filing date: 2022-06-09
Publication date: 2022-12-23
Also published as: KR20220170401A; US20220406791A1; TW202301636A; TWI803181B

Abstract

Provided is a semiconductor memory device including: a device isolation pattern in the substrate and defining a first active portion and a second active portion spaced apart from each other, wherein a center of the first active portion is adjacent to an end of the second active portion; a bit line crossing a center of the first active portion; a bit line contact between the bit line and the first active portion; and a first storage node pad on the end of the second active portion. The first storage node pad includes a first pad sidewall and a second pad sidewall. The first pad sidewall is adjacent to the bit line contact. The second pad sidewall is opposite the first pad sidewall. The second pad sidewall is convex in a direction away from the bit line contact when viewed in a plan view.

Description

Semiconductor memory device with a plurality of memory cells

Technical Field

The inventive concept relates to semiconductor memory devices.

Background

Semiconductor devices are beneficial in the electronics industry due to their small size, versatility, and/or low manufacturing cost. However, with the remarkable development of the electronics industry, semiconductor devices are being highly integrated. For high integration of semiconductor devices, the line width of patterns of semiconductor devices is being reduced. However, for the fineness of the pattern, a new exposure technique and/or an expensive exposure technique are required, so that it may be difficult to highly integrate the semiconductor device. Accordingly, various studies have been recently conducted on new integration technologies.

Disclosure of Invention

Some embodiments of the inventive concept provide a semiconductor memory device having improved reliability.

According to some embodiments of the inventive concept, a semiconductor memory device may include: a device isolation pattern in the substrate and defining a first active portion and a second active portion spaced apart from each other, a center of the first active portion being adjacent to an end of the second active portion; a bit line crossing the center of the first active portion; a bit line contact between the bit line and the first active portion; and a first storage node pad on the end of the second active portion. The first storage node pad may include a first pad sidewall and a second pad sidewall. The first pad sidewall may be adjacent to the bit line contact. The second pad sidewall may be opposite to the first pad sidewall. The second pad sidewall may be convex in a direction away from the bit line contact when viewed in a plan view.

According to some embodiments of the inventive concept, a semiconductor memory device may include: a device isolation pattern in the substrate and defining a first active portion and a second active portion spaced apart from each other, a center of the first active portion being adjacent to an end of the second active portion; a first word line extending in the substrate and in a first direction, the first word line crossing both the first active portion and the second active portion; a second word line in the substrate and spaced apart from the first word line, the second word line extending in the first direction and crossing the first active portion; a word line overlay pattern on each of the first word line and the second word line; a bit line crossing a center of the first active portion; a bit line contact between the bit line and the first active portion; and a storage node pad on the end of the second active portion. The storage node pad may be between the first word line and the second word line when viewed in a plan view. A first interval between the first word line and the storage node pad may be different from a second interval between the second word line and the storage node pad.

According to some embodiments of the inventive concept, a semiconductor memory device may include: a device isolation pattern in the substrate and defining a first active portion and a second active portion spaced apart from each other, a center of the first active portion being adjacent to an end of the second active portion; a first word line extending in the substrate and in a first direction, the first word line crossing both the first active portion and the second active portion; a second word line in the substrate and spaced apart from the first word line, the second word line extending in the first direction and crossing the first active portion; a first gate dielectric layer between the first word line and the substrate; a second gate dielectric layer between the second word line and the substrate; a bit line crossing a center of the first active portion; a bit line contact between the bit line and the first active portion; and a storage node pad on the end of the second active portion. The storage node pad may be between the first word line and the second word line when viewed in a plan view. The center of the width of the storage node pad may not be on an imaginary line parallel to the first direction and passing through the center of the space between the first gate dielectric layer and the second gate dielectric layer. The width of the storage node pad may be measured in a second direction orthogonal to the first direction.

Drawings

Fig. 1A illustrates a plan view of a semiconductor memory device according to some example embodiments of the inventive concepts.

FIG. 1B showsbase:Sub>A cross-sectional view taken along lines A-A 'and B-B' of FIG. 1A.

Fig. 2A to 2C illustrate enlarged views showing a portion P1 of fig. 1A.

Fig. 3A shows an enlarged view showing a portion P2 of fig. 1B.

Fig. 3B illustrates an enlarged view showing a portion P3 of fig. 1B.

Fig. 4A to 17A illustrate plan views showing an exemplary method of manufacturing the semiconductor memory device of fig. 1A.

Fig. 4B, 4C, 5B to 13B, 13C, and 14B to 17B illustrate cross-sectional views showing an example method of manufacturing the semiconductor memory device of fig. 1B.

Fig. 18 illustrates a plan view showing a semiconductor memory device according to some example embodiments of the inventive concepts.

Fig. 19 shows an enlarged view showing a portion P1 of fig. 18.

Fig. 20 is a plan view showing an exemplary method of manufacturing the semiconductor memory device having the plan view of fig. 18.

Fig. 21A illustrates a plan view showing a semiconductor memory device according to some example embodiments of the inventive concepts.

Fig. 21B illustrates an enlarged view showing a portion P1 of fig. 21A.

Fig. 22 illustrates a plan view showing an example method of manufacturing the semiconductor memory device having the plan view of fig. 21A.

Fig. 23A illustrates a plan view showing a semiconductor memory device according to some example embodiments of the inventive concepts.

Fig. 23B illustrates an enlarged view showing a portion P1 of fig. 23A.

Fig. 24 illustrates a plan view showing an exemplary method of manufacturing the semiconductor memory device having the plan view of fig. 23A.

Fig. 25A illustrates a plan view showing an example method of forming the third mask pattern of fig. 24.

Fig. 25B showsbase:Sub>A cross-sectional view taken along linesbase:Sub>A-base:Sub>A 'and B-B' of fig. 25A.

Fig. 26A illustrates a plan view showing a semiconductor memory device according to some example embodiments of the inventive concepts.

Fig. 26B illustrates an enlarged view showing a portion P1 of fig. 26A.

Fig. 27 shows a plan view showing an example method of manufacturing the semiconductor memory device having the plan view of fig. 26A.

Detailed Description

Some embodiments of the inventive concept will now be described in detail with reference to the accompanying drawings to help clarify the inventive concept. Like numbers refer to like elements throughout.

Fig. 1A illustrates a plan view showing a semiconductor memory device according to some example embodiments of the inventive concepts. FIG. 1B showsbase:Sub>A cross-sectional view taken along lines A-A 'and B-B' of FIG. 1A. Fig. 2A to 2C illustrate enlarged views showing a portion P1 of fig. 1A. Fig. 3A shows an enlarged view showing a portion P2 of fig. 1B. Fig. 3B illustrates an enlarged view showing a portion P3 of fig. 1B.

Referring to fig. 1A and 1B, a device isolation pattern 302 may be disposed on a substrate 301, defining an active portion ACT. Each active portion ACT may have an isolated shape. Each active portion ACT may have a bar shape elongated in the first direction X1 when viewed in a plan view. The active portion ACT may correspond to a portion of the substrate 301 surrounded by the device isolation pattern 302 when viewed in a plan view. The substrate 301 may include a semiconductor material. The active portions ACT may be arranged parallel to each other in the first direction X1, so that one of the active portions ACT may have an end adjacent to a central portion of an adjacent one of the active portions ACT in the second direction X2. Each of the device isolation patterns 302 may have a single-layer or multi-layer structure formed of at least one selected from, for example, silicon oxide, silicon oxynitride, and silicon nitride.

The first direction X1, the second direction X2, and the third direction X3 may be parallel to the top surface of the substrate 301. The third direction X3 and the second direction X2 may be perpendicular to each other, and the first direction X1 may be at an angle to the third direction X3 and the second direction X2. The fourth direction X4 may be perpendicular to the top surface of the substrate 301.

The device isolation pattern 302 may have a top surface 302_, which is lower than the top surface 301_, of the active portion ACT (or the substrate 301). Accordingly, the device isolation pattern 302 may expose a portion of the sidewall 301 _sof the active portion ACT (or the substrate 301). In this case, the active portion ACT may have an upper portion protruding beyond the device isolation pattern 302.

The word line WL may cross the active portion ACT. Word lines WL may be disposed in grooves GR1 formed in the device isolation pattern 302 and in the active portion ACT. The word lines WL may be parallel to the second direction X2 crossing the first direction X1. For example, the word lines WL may longitudinally extend in the second direction X2. The word lines WL may be formed of a conductive material. A gate dielectric layer 307 may be disposed between each word line WL and the inner surface of each groove GR1. Although not shown, the groove GR1 may have its bottom surface positioned relatively deep in the device isolation pattern 302 and relatively shallow in the active portion ACT. Each word line WL may have a curved bottom surface. The gate dielectric layer 307 may have a curved upper surface corresponding to the curved bottom surface of the word line WL. The gate dielectric layer 307 may include at least one selected from the group consisting of thermal oxide, silicon nitride, silicon oxynitride, and high-k dielectric. For example, gate dielectric layer 307 may comprise thermal oxide. Gate dielectric layer 307 may have a top surface 307 u lower than top surface 301 u of active portion ACT (or substrate 301). For example, the top surface 307 v of the gate dielectric layer 307 may be located at the same level as the level of the top surface 302 v of the device isolation pattern 302.

The first impurity regions 3d may be disposed in the active portion ACT between the pair of word lines WL, and the pair of second impurity regions 3b may be correspondingly disposed in opposite edge portions of each active portion ACT. The first impurity region 3d and the second impurity region 3b may be doped with, for example, N-type impurities. The first impurity region 3d may correspond to a common drain region, and the second impurity region 3b may correspond to a source region. The transistor may be constituted by each word line WL and its adjacent first impurity region 3d and second impurity region 3b. Since the word lines WL are disposed in the groove GR1, each word line WL may have a channel region thereunder, the length of which increases in a limited planar area. Therefore, short channel effects can be minimized.

The word line WL may have its top surface WL _ U lower than the top surface 301_of the active portion ACT (or substrate 301). The word line cover pattern 310 may be disposed on each word line WL. The word line cover pattern 310 may have a line shape extending along a longitudinal direction of the word line WL, and may cover the entire top surface WL _ U of the word line WL. For example, the word line cover pattern 310 may contact the top surface WL _ U of the word line WL. The groove GR1 may have an inner space not occupied by the word line WL, and the word line overlay pattern 310 may fill the unoccupied inner space of the groove GR1. The word line capping pattern 310 may be formed of, for example, a silicon nitride layer. The word line capping pattern 310 may have a top surface higher than the top surface 307\uof the gate dielectric layer 307 and/or higher than the top surface 302_of the device isolation pattern 302.

The bit line BL may be disposed on the substrate 301. The bit line BL may cross the word line capping pattern 310 and the word line WL. As disclosed in fig. 1A, the bit line BL may be parallel to a third direction X3 crossing the first and second directions X1 and X2. For example, the bit line BL may extend longitudinally in the third direction X3. The bit line BL may include a bit line diffusion barrier pattern 331 and a bit line wiring pattern 332, which are sequentially stacked. For example, the bit line wiring pattern 332 may be stacked on the bit line diffusion barrier pattern 331, contacting the bit line diffusion barrier pattern 331. The bit line diffusion barrier pattern 331 may include at least one selected from titanium, titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum nitride, and tungsten nitride. The bit line wiring pattern 332 may include a metal such as tungsten, aluminum, or copper. Although not shown, the bit line BL may further include an impurity-doped polysilicon pattern under the bit line diffusion barrier pattern 331. A bit line overlay pattern 337 may be disposed on each bit line BL. The bit line overlay pattern 337 may be formed of a dielectric material, such as a silicon nitride layer.

The bit line contact DC may be provided between the bit line BL and the active portion ACT provided with the first impurity region 3 d. The bit line contact DC may include, for example, polysilicon doped with impurities. The bit line contact DC may have a circular shape or an elliptical shape when viewed in a plan view as illustrated in fig. 2A to 2C. The bit line contact DC may have a plane area larger than that of a position where the bit line BL and the first impurity region 3d overlap each other. The plane area of the bit line contact DC may be larger than that of the first impurity region 3 d.

As shown in fig. 2A, the active portion ACT provided with the first impurity region 3d may have four substrate sidewalls 301\ us, for example, a first substrate left sidewall 301 \ (L1), a first substrate rear sidewall 301_s (B1), a first substrate right sidewall 301_s (R1), and a first substrate front sidewall 301_s (F1), the four substrate sidewalls 301 _sbeing arranged in a clockwise direction, and upper portions of the four substrate sidewalls 301 _smay be exposed without being covered by the device isolation pattern 302 or the gate dielectric layer 307. The bit line contact DC may cover the exposed first substrate left sidewall 301_s (L1), first substrate back sidewall 301_s (B1), first substrate right sidewall 301_s (R1), and first substrate front sidewall 301_s (F1). For example, the bit line contact DC may contact the exposed first substrate left sidewall 301_s (L1), first substrate back sidewall 301_s (B1), first substrate right sidewall 301_s (R1), and first substrate front sidewall 301_s (F1).

Referring to fig. 1B and 3A, the bit line contact DC may have a first width W1 at a top surface DC _ U thereof. The lower portion of the bit line contact DC may have a second width W2 greater than the first width W1. The bit line contact DC may have a width gradually increasing in a direction from an upper portion thereof toward a lower portion thereof. The bit line contact DC may have a bottom end DC _ B located at a level downwardly away from the top surface 301\ufirst height H1 of the substrate 301.

In the inventive concept, an increase in contact area between the bit line contact DC and the active portion ACT provided with the first impurity region 3d may occur, and thus contact resistance may be reduced between the bit line contact DC and the active portion ACT (or the first impurity region 3 d), with the result that the semiconductor memory device may operate at high speed and low power.

The storage node pads XP may be disposed on the active portion ACT provided with the second impurity regions 3b. The storage node pads XP may include, for example, polysilicon doped with impurities. The storage node pads XP may have a shape similar to a rectangle when viewed in plan views as shown in fig. 2A to 2C. The storage node pad XP may have first, second, third and fourth pad sidewalls XP _ S (1, XP _ S (2, XP _ S (3, XP _ S (4)) arranged in a clockwise direction. The first pad sidewall XP _ S (1) of the storage node pad XP may be recessed in a direction (e.g., the second direction X2) away from the bit line contact DC adjacent to the first pad sidewall XP _ S (1). When viewed in a plan view, the second pad sidewall XP _ S (2) and the fourth pad sidewall XP _ S (4) may not be aligned with (or overlap with) the inner sidewall of the trench GR1 or the outer sidewall 307\ S of the gate dielectric layer 307 as shown in fig. 2A and 2C, or may be aligned with (or overlap with) the inner sidewall of the trench GR1 or the outer sidewall 307 \ S of the gate dielectric layer 307 as shown in fig. 2B.

The storage node pads XP may have a third width W3 in the third direction X3. The third width W3 may be equal to or greater than the spacing DS1 between adjacent grooves GR1. The storage node pads XP may have a planar area greater than that of the single second impurity region 3b. The storage node pad XP may cover at least two sidewalls of the active portion ACT provided with the second impurity regions 3b (see, for example, 301_s (3) and 301_s (4) of fig. 3A), which are opposite to each other in the second direction X2. For example, the storage node pad XP may contact at least two sidewalls of the active portion ACT provided with the second impurity regions 3b.

Referring to fig. 2C, the active portion ACT provided with the second impurity region 3B may have a second substrate left sidewall 301_s (L2), a second substrate rear sidewall 301_s (B2), a second substrate right sidewall 301_s (R2), and a second substrate front sidewall 301 _us (F2) arranged in a clockwise direction, and upper portions of the second substrate left sidewall 301_s (L2), the second substrate rear sidewall 301_s (B2), the second substrate right sidewall 301_s (R2), and the second substrate front sidewall 301 _us (F2) may be exposed without being covered by the device isolation pattern 302 or the gate dielectric layer 307. The second substrate front sidewall 301 urs (F2) may be rounded. As shown in fig. 2C, storage node pad XP may cover all of second substrate left sidewall 301_s (L2), second substrate rear sidewall 301_s (B2), second substrate right sidewall 301_s (R2), and second substrate front sidewall 301_s (F2). For example, storage node pads XP may contact all of second substrate left sidewall 301_S (L2), second substrate back sidewall 301_S (B2), second substrate right sidewall 301_S (R2), and second substrate front sidewall 301_S (F2). In the inventive concept, an increase in contact area may be generated between the storage node pad XP and the active portion ACT provided with the second impurity regions 3b, and thus contact resistance may be reduced between the storage node pad XP and the active portion ACT (or the second impurity regions 3 b), with the result that the semiconductor memory device may operate at high speed and low power.

The storage node pads XP may have bottom ends XP _ B located at a level downwardly away from the top surface 301 xu of the substrate 301 by a first height H1. The bottom ends XP _ B of the storage node pads XP and the bottom ends DC _ B of the bit line contacts DC may be located at the same level, for example, at a position downwardly away from the top surface 301 xu of the substrate 301 by a first height H1. The storage node pads XP may have a top surface XP _ U that is lower than the top surface DC _ U of the bit line contact DC. The contact dielectric pattern 30r may be interposed between the bit line contact DC and its adjacent storage node pad XP. The contact dielectric pattern 30r may include a dielectric material, for example, silicon oxide.

The contact dielectric pattern 30r may have a ring or ring shape as shown in fig. 12A and may contact the DC around the bit line when viewed in a plan view. A portion of the contact dielectric pattern 30r may extend downward from the bit line BL as shown in the cross-sectional view of B-B' in fig. 1B. The contact dielectric pattern 30r may have a first dielectric portion 30r (1) between the bit line contact DC and its neighboring storage node pad XP, and may further include a second dielectric portion 30r (2) under the bit line BL. The first dielectric portion 30r (1) may have a second height H2. For example, the distance between the top and bottom surfaces 30r _bof the first dielectric portion 30r (1) in the fourth direction X4 may be the second height H2. The second dielectric portion 30r (2) may have a third height H3 that is greater than the second height H2. For example, the distance between the top and bottom surfaces 30r _bof the second dielectric portion 30r (2) in the fourth direction X4 may be the third height H3. The contact dielectric pattern 30r may contact the bottom surface of the bit line BL.

The contact dielectric pattern 30r may have a bottom surface 30r _blocated at the same level as or lower than the level of the top surface 302 _uof the device isolation pattern 302. The bottom surface 30r _bcontacting the dielectric pattern 30r may be located at the same level or a lower level than the top surface 307 u of the gate dielectric layer 307. The bottom surface 30r _bcontacting the dielectric pattern 30r may be located at the same level as or a lower level than the top surface of the wordline overlay pattern 310.

The bit line BL and the bit line capping pattern 337 may cover their sidewalls with bit line spacers SP. The bit line spacer SP may include a spacer liner 321, a first spacer 323, and a second spacer 325 sequentially arranged in a direction away from the bit line BL and sidewalls of the bit line capping pattern 337. For example, the spacer liner 321 may contact a side surface of the bit line BL, the first spacer 323 may contact a side surface of the spacer liner 321, and the second spacer 325 may contact a side surface of the first spacer 323. The first spacer 323 may be between the spacer liner 321 and the second spacer 325. The spacer liner 321 and the first spacer 323 may include the same material, for example, silicon oxide. Alternatively, the spacer liner 321 may include a material having an etch selectivity with respect to the first spacers 323, and in this case, the spacer liner 321 may include silicon nitride and the first spacers 323 may include silicon oxide. The second spacers 325 may include a dielectric material having an etch selectivity with respect to the first spacers 323, such as silicon nitride.

For example, the spacer liner 321 may include silicon oxide. Since silicon oxide has a dielectric constant smaller than that of silicon nitride, the insulating property of the bit line spacers SP may increase as the proportion of silicon nitride in the bit line spacers SP becomes smaller and as the proportion of silicon oxide in the bit line spacers SP becomes larger. In some embodiments of the inventive concept, since the spacer liner 321 includes silicon oxide, the insulation property of the bit line spacer SP may be improved to reduce interference between the bit line BL and the storage node contact BC, which will be discussed below. As a result, the semiconductor memory device can be improved in reliability.

The recess region R1 may be defined by sidewalls of the bit line contact DC, a top surface of the contact dielectric pattern 30R, and sidewalls of the storage node pad XP. The spacer liner 321 may extend to conformally cover the inner sidewalls and the bottom surface of the recess region R1, or sidewalls of the bit line contact DC, a top surface of the contact dielectric pattern 30R, and sidewalls of the storage node pads XP. The spacer liner 321 may be provided thereon with a buried dielectric pattern 341 filling the recess region R1. The second spacer 325 may have a lower bottom end than that of the first spacer 323. For example, a lower surface of the first spacer 323 may contact an upper surface of the buried dielectric pattern 341, and an upper surface of the buried dielectric pattern 341 may be at a higher vertical level than a lower surface of the second spacer 325.

Referring to fig. 3A, the first active portion ACT (1), the second active portion ACT (2), and the third active portion ACT (3) may be linearly arranged along the second direction X2. The first active portion ACT (1) may have a first substrate sidewall 301_s (1) and a second substrate sidewall 301_s (2) opposite to each other and exposed without being covered by the device isolation pattern 302. The first impurity region 3d may be formed in the first active portion ACT (1). The bit line contact DC may cover the top surfaces of the first substrate sidewall 301_s (1), the second substrate sidewall 301_s (2), and the first active portion ACT (1). For example, the bit line contact DC may contact the top surfaces of the first substrate sidewall 301_s (1), the second substrate sidewall 301_s (2), and the first active portion ACT (1). The second active portion ACT (2) may have a third substrate sidewall 301\ s (3) and a fourth substrate sidewall 301_s (4) opposite to each other and exposed without being covered by the device isolation pattern 302. The first storage node pads XP (1) may cover the top surfaces of the third substrate sidewall 301\ us (3), the fourth substrate sidewall 301 \\ us (4), and the second active portion ACT (2). For example, the first storage node pad XP (1) may contact the top surfaces of the third substrate sidewall 301_s (3), the fourth substrate sidewall 301_s (4), and the second active portion ACT (2). The third active portion ACT (3) may have a fifth substrate sidewall 301_s (5) and a sixth substrate sidewall 301_s (6) that are opposite to each other and exposed without being covered by the device isolation pattern 302. The second storage node pads XP (2) may cover the top surfaces of the fifth substrate sidewall 301\ us (5), the sixth substrate sidewall 301 \\ us (6), and the third active portion ACT (3). For example, the second storage node pads XP (2) may contact the top surfaces of the fifth substrate sidewall 301_s (5), the sixth substrate sidewall 301_s (6), and the third active portion ACT (3).

The pad separation patterns 38 may be interposed between adjacent storage node pads XP, for example, between the first storage node pad XP (1) and the second storage node pad XP (2) shown in fig. 3A. The pad separation pattern 38 may extend to cover the top surfaces XP _ U of the first and second storage node pads XP (1) and XP (2). For example, the pad separation pattern 38 may contact the top surfaces XP (1) and XP _ U of the first and second storage node pads XP (2). The pad separation pattern 38 may have a separation portion 38 (S) between the first storage node pad XP (1) and the second storage node pad XP (2). The separating portions 38 (S) of the pad separating pattern 38 may contact side surfaces of the first storage node pads XP (1) and side surfaces of the second storage node pads XP (2). The pad separation pattern 38 may include a dielectric material, such as silicon nitride. As shown in fig. 3B, the pad separation pattern 38 may have a bottom surface 38 v located at the same level as or a lower level than the top surface 302 u of the device isolation pattern 302. For example, a portion of the pad separation pattern 38 may protrude into the device isolation pattern 302. As shown in fig. 3A or 3B, the bottom surface 38\ B of the pad separation pattern 38 may be located at the same level as or lower than that of the bottom ends XP _ B of the storage node pads XP.

As shown in the cross-sectional view of B-B' in fig. 1B, the pad separation pattern 38 may also be disposed under the bit line BL and may contact sidewalls of the second dielectric portion 30r (2) included in the contact dielectric pattern 30r, a top surface of the word line cover pattern 310, a top surface 307 auu of the gate dielectric layer 307, and a top surface 302 auu of the device isolation pattern 302. The pad separation pattern 38 may contact a bottom surface of the bit line BL.

As shown in fig. 3A, the first bit line BL (1) may be located on the bit line contact DC covering the first impurity region 3d of the first active portion ACT (1). The second bit line BL (2) adjacent to the first bit line BL (1) may be positioned on the pad separating pattern 38 and may vertically overlap the separating portion 38 (S).

The storage node contact BC may be interposed between adjacent bit lines BL, for example, between the first bit line BL (1) and the second bit line BL (2) shown in fig. 3A. The storage node contact BC may be disposed in a storage node contact hole BCH between adjacent bit lines BL. Although not shown in fig. 1A and 1B, a plurality of node separation patterns 44 may be disposed between adjacent bit line spacers SP as shown in fig. 17A and 17B. The node separation patterns 44 may be linearly arranged between the bit line spacers SP and spaced apart from each other. The node separation pattern 44 may overlap the word line WL. Storage node contact holes BCH may be defined between the bit line spacers SP and between the node separation patterns 44. The node separation pattern 44 may include a dielectric material, for example, silicon oxide.

The storage node contact BC may include a contact metal pattern 313 and a contact diffusion barrier pattern 311 surrounding sidewalls and a bottom surface of the contact metal pattern 313. The contact diffusion barrier pattern 311 may contact the sidewall and the bottom surface of the contact metal pattern 313. The contact diffusion barrier pattern 311 may have a uniform thickness regardless of location, or may conformally cover the sidewalls and bottom surface of the storage node contact hole BCH. Both the contact metal pattern 313 and the contact diffusion barrier pattern 311 may include a metal. The contact diffusion barrier pattern 311 may include, for example, at least one selected from titanium, titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum nitride, and tungsten nitride. The contact metal pattern 313 may include, for example, tungsten, aluminum, or copper.

In the inventive concept, the storage node pad XP may make contact with the sidewall 301 s of the substrate 301, and as a result, contact resistance may be significantly reduced between the storage node contact BC and the second impurity region 3b. Therefore, the storage node contact BC may not include polysilicon. Alternatively, the storage node contact BC may additionally include a polysilicon pattern under the contact diffusion barrier pattern 311, but in this case, the polysilicon pattern may have a relatively small size. The increase in the amount of polysilicon in the storage node contact BC may increase the possibility of voids occurring in the storage node contact BC, and thus a high temperature annealing process may be required to remove the voids. The annealing process may increase the occurrence of process defects on components other than the storage node contact BC.

In contrast, according to some embodiments of the inventive concept, since the storage node contact BC does not include polysilicon and includes metal, processes (e.g., metal deposition) other than the annealing process may be performed at a low temperature. Accordingly, process defects may be reduced or prevented. In addition, such a low temperature process may form the spacer liner 321 using silicon oxide, and thus the bit line spacer SP may be improved in insulation performance.

The storage node contacts BC may have bottom ends BC _ E lower than the top surface XP _ U of the storage node pads XP. The bottom end BC _ E of the storage node contact BC may be located at a level of a fourth height H4 down away from the top surface XP _ U of the storage node pad XP. The bottom end BC _ E of the storage node contact BC may be lower than the bottom end of the second spacer 325. The contact ohmic layer 309 may be interposed between the storage node contact BC and the storage node pad XP. The contact ohmic layer 309 may include a metal silicide, such as a cobalt silicide.

Referring to fig. 1B, the contact diffusion barrier pattern 311 may have a top surface 311\ u located at the same level as that of the top surface 337 \ u of the bit line overlay pattern 337. In addition, the contact metal pattern 313 may have a top surface that is located at the same level as the top surface 311 u of the contact diffusion barrier pattern 311 and is coplanar with the top surface 311 u of the contact diffusion barrier pattern 311. The landing pads LP may be located on the corresponding storage node contacts BC. The landing pads LP may each have an isolated island shape when viewed in a plan view as shown in fig. 1A. Six landing pads LP surrounding one landing pad LP may constitute a regular hexagonal shape. The landing pads LP may be arranged to form a honeycomb shape.

The landing pad LP may simultaneously contact the top surfaces 311 u of the contact diffusion barrier pattern 311, the top surface 337 u of the bit line overlay pattern 337, and the top surface of the contact metal pattern 313. The landing pad LP may include the same material as that of the contact metal pattern 313. The landing pad separation pattern LPS may be disposed between the landing pads LP. A portion of the landing pad partition pattern LPS may be interposed between the storage node contact BC and its adjacent bitline spacer SP. Accordingly, the landing pad separation pattern LPS may have its bottom end lower than the top end of the bitline spacer SP. For example, the lower portion of the landing pad separation pattern LPS may be at a lower vertical level than the top surfaces 311 u of the contact diffusion barrier pattern 311, the top surface 337 u of the bit line overlay pattern 337, and the top surface of the contact metal pattern 313.

The data storage pattern DSP may be disposed on the corresponding landing pad LP. The data storage patterns DSP may each be a capacitor including a bottom electrode, a dielectric layer, and a top electrode. In this case, the semiconductor memory device may be a Dynamic Random Access Memory (DRAM). Alternatively, the data storage patterns DSP may each include a magnetic tunnel junction pattern. In this case, the semiconductor memory device may be a Magnetic Random Access Memory (MRAM). Differently, the data storage patterns DSP may each include a phase change material or a variable resistance material. In this case, the semiconductor memory device may be a phase change random access memory (PRAM) or a resistive random access memory (ReRAM).

In the inventive concept, the structure of the bit line contact DC and the storage node pad XP may cause a reduction in contact resistance, and thus the semiconductor memory device may operate at high speed and low power.

Fig. 4A to 17A illustrate plan views showing an exemplary method of manufacturing the semiconductor memory device of fig. 1A. Fig. 4B, 4C, 5B to 13B, 13C, and 14B to 17B illustrate cross-sectional views showing a method of manufacturing the semiconductor memory device of fig. 1B.

Referring to fig. 4A and 4B, a device isolation pattern 302 may be formed in the substrate 301, defining an active portion ACT. A device isolation trench may be formed in the substrate 301, and the device isolation pattern 302 may fill the device isolation trench. The active portion ACT and the device isolation pattern 302 may be patterned to form a groove GR1. In this step, the etching conditions of the substrate 301 and the device isolation pattern 302 may be appropriately controlled so that the device isolation pattern 302 may be more easily etched than the substrate 301. Thus, the groove GR1 may have a curved bottom surface. A gate dielectric layer 307 may be conformally formed in the groove GR1. The gate dielectric layer 307 may be formed by one or more of thermal oxidation, chemical vapor deposition, and atomic layer deposition. The gate conductive layer may be stacked to fill the groove GR1 and then may be etched back to form the word line WL. A pair of word lines WL may cross each active portion ACT. A dielectric layer such as a silicon nitride layer may be stacked on the substrate 301 to fill the groove GR1, and then the dielectric layer may be etched to form a word line capping pattern 310 on each word line WL. The word line capping pattern 310 and the device isolation pattern 302 may be used as a mask to dope impurities into the active portion ACT, which may form the first impurity region 3d and the second impurity region 3b.

Referring to fig. 4A and 4C, an upper portion of the device isolation pattern 302 may be selectively removed. In this step, the gate dielectric layer 307 may be partially removed. The selective removal of the upper portion of the device isolation pattern 302 may be, for example, a wet etching process in which silicon oxide is removed using hydrofluoric acid (HF). The above process may expose the sidewall 301 uts of the active portion ACT (or the substrate 301). In addition, sidewalls of the word line capping patterns 310 may be exposed. Since the sidewall 301 uts of the active portion ACT (or the substrate 301) is exposed as described above, a contact area between the substrate 301 and the bit line contact DC may be increased (which will be discussed below), and a contact surface between the substrate 301 and the storage node pad XP may also be increased (which will be discussed below).

Referring to fig. 5A and 5B, the conductive layer 20 may be formed on the entire surface of the substrate 301. The conductive layer 20 may be, for example, a polycrystalline silicon layer doped with impurities. The formation of the conductive layer 20 may include depositing a polysilicon layer and performing an ion implantation process to incorporate impurities into the polysilicon layer. Alternatively, the formation of the conductive layer 20 may include depositing a polysilicon layer while the polysilicon layer is doped in-situ with impurities. The conductive layer 20 may be formed to have a first thickness TH1 measured from the top surface 301 u of the substrate 301. A first mask layer (not shown) and a second mask pattern 24 may be sequentially formed on the entire surface of the conductive layer 20. The first mask layer may include a material having an etch selectivity with respect to the conductive layer 20, such as silicon oxide. The second mask pattern 24 may include a material having an etch selectivity with respect to the first mask layer, such as a spin-on hard mask (SOH) or an Amorphous Carbon Layer (ACL). As shown in fig. 5A, the second mask pattern 24 may be formed to have a plurality of first holes HL1. The first hole HL1 may overlap the first impurity region 3 d. The second mask pattern 24 may be used as an etch mask such that the first mask layer may be etched to form the first mask pattern 22 and expose the top surface of the conductive layer 20. The first mask pattern 22 may have the same planar shape as that of the second mask pattern 24. The first hole HL1 may be transferred to the first mask pattern 22. The first mask pattern 22 may be formed to have a thickness greater than that of the second mask pattern 24.

Referring to fig. 6A and 6B, the first sacrificial layer 26 may be conformally formed on the entire surface of the substrate 301. The first sacrificial layer 26 may include, for example, silicon oxide formed by Atomic Layer Deposition (ALD). The first sacrificial layer 26 may be formed to have a thickness insufficient to fill the first hole HL1. The first sacrificial layer 26 may cover top and side surfaces of the second mask pattern 24, side surfaces of the first mask pattern 22, and a top surface of the conductive layer 20 exposed in the first hole HL1. The second sacrificial pattern 28 may be formed to fill the first hole HL1. The second sacrificial pattern 28 may be formed of, for example, a spin on hard mask (SOH) having excellent filling property. The formation of the second sacrificial pattern 28 may include performing a spin-on process and a curing process to form a spin-on hard mask (SOH) layer to fill the first hole HL1, and then performing an etch-back process to expose the top surface of the first sacrificial layer 26.

Referring to fig. 6A, 6B, 7A, and 7B, an etching process may be selectively performed on the first sacrificial layer 26. In this step, the second sacrificial pattern 28 may not be etched. The etching process may expose the top surface of the second mask pattern 24. The etching process may be performed such that the first sacrificial layer 26 in the first hole HL1 may be removed to expose the conductive layer 20. The conductive layer 20 exposed within the first hole HL1 may be removed to form a second hole HL2 exposing the top surface of the device isolation pattern 302, the top surface of the gate dielectric layer 307, and the top surface of the word line capping pattern 310. The formation of the second hole HL2 may divide the conductive layer 20 into the first conductive pattern 20d and the second conductive pattern 20pb. The first and second conductive patterns 20d and 20pb may each have a first thickness TH1 of fig. 5B measured from the top surface 301 xu of the substrate 301.

The first conductive pattern 20d may have a circular shape when viewed in a plan view, and may overlap the first impurity region 3 d. The second conductive pattern 20pb may cover two adjacent second impurity regions 3b at the same time. The second conductive pattern 20pb may have a network shape when viewed in a plan view.

The second hole HL2 may be formed to have a ring or ring shape as shown in fig. 7A. In this step, the first sacrificial layer 26 positioned under the second sacrificial pattern 28 may not be etched, but may remain to form a residual sacrificial pattern 26a. The etching process may also partially remove the upper portion of the device isolation pattern 302, the upper portion of the gate dielectric layer 307, and the upper portion of the word line capping pattern 310. The residual sacrificial pattern 26a may be formed of, for example, silicon oxide.

Referring to fig. 7A, 7B, 8A, and 8B, the second mask patterns 24 and the second sacrificial patterns 28 may be all removed to expose the top surfaces of the remaining sacrificial patterns 26a and the first mask patterns 22. When both the second mask pattern 24 and the second sacrificial pattern 28 are formed of a spin on hard mask (SOH), an ashing process may be performed to remove the second mask pattern 24 and the second sacrificial pattern 28. The top surface of the residual sacrificial pattern 26a may be formed at a lower vertical level than the top surface of the first mask pattern 22. A contact dielectric layer may be formed on the entire surface of the substrate 301 to fill the second hole HL2, and then a Chemical Mechanical Polishing (CMP) process or an etch-back process may be performed to form the contact capping pattern 30 in the second hole HL2. The contact capping pattern 30 may include a dielectric material, such as silicon oxide. The contact cover pattern 30 may cover the remaining sacrificial pattern 26a and the first conductive pattern 20d.

Referring to fig. 8A, 8B, 9A, and 9B, the first mask pattern 22 may be removed to expose the second conductive pattern 20pb. An etch back process may be performed to remove an upper portion of the second conductive pattern 20pb, and thus the thickness of the second conductive pattern 20pb may be changed to a second thickness TH2 smaller than the first thickness TH1 of fig. 5B. The second thickness TH2 may be measured from the top surface 301 xu of the substrate 301. In this step, the contact cover pattern 30 may protect the first conductive pattern 20d.

Referring to fig. 10A and 10B, a third mask pattern 32 may be formed on the contact cover pattern 30 and the second conductive pattern 20pb. The third mask pattern 32 may be formed of, for example, a spin on hard mask (SOH), an Amorphous Carbon Layer (ACL), silicon nitride, silicon oxynitride, or photoresist. The third mask patterns 32 may be two-dimensionally arranged along the second direction X2 and the third direction X3. The third mask pattern 32 may be positioned on the device isolation pattern 302 and the substrate 301 between the adjacent gate dielectric layers 307. Two adjacent third mask patterns 32 may simultaneously overlap the single contact coverage pattern 30. The second conductive pattern 20pb and the contact cover pattern 30 may be exposed between the third mask patterns 32. The third mask pattern 32 may be formed by using a different patterning process, such as a Double Patterning Technique (DPT), a Quad Patterning Technique (QPT), or photo-etch-photo-etch (LELE). Spaces 34 may be provided between adjacent third mask patterns 32, and the spaces 34 may expose the top surface of the second conductive pattern 20pb.

Referring to fig. 10A, 10B, 11A and 11B, the third mask pattern 32 may be used as an etching mask to etch the second conductive patterns 20pb, which may form the storage node pads XP spaced apart from each other and also form spaces 36 between the storage node pads XP. The space 36 may expose the device isolation pattern 302. In this step, the contact capping pattern 30 and the residual sacrificial pattern 26a may protect and prevent the first conductive pattern 20d from being etched. An upper portion of the contact capping pattern 30 may be partially etched in the etching process. In addition, the upper portion of the device isolation pattern 302 may be partially etched between the storage node pads XP. The storage node pads XP may each have a second thickness TH2 of fig. 9B measured from the top surface 301 xu of the substrate 301.

Referring to fig. 11A, 11B, 12A and 12B, the third mask pattern 32 may be removed to expose the top surface of the storage node pad XP and the top surface of the contact cover pattern 30. A pad separation layer (not shown) may be formed on the entire surface of the substrate 301 to fill the spaces 36 between the storage node pads XP, and then a Chemical Mechanical Polishing (CMP) process may be performed. In this way, the contact cover pattern 30 and the residual sacrificial pattern 26a on the first conductive pattern 20d may be removed to expose the top surface of the first conductive pattern 20d and simultaneously form the contact dielectric pattern 30r covering the sidewalls of the first conductive pattern 20d. A portion of the contact coverage pattern 30 may be formed as a contact dielectric pattern 30r. The contact dielectric pattern 30r may have a ring or ring shape when viewed in a plan view. In addition, the pad separation pattern 38 may be formed to fill the spaces 36 between the storage node pads XP and cover the top surfaces of the storage node pads XP. The pad separation pattern 38 may be a part of a pad separation layer (not shown).

Referring to fig. 13A and 13B, a bit line diffusion barrier layer (not shown) and a bit line wiring layer (not shown) may be sequentially formed on the first conductive pattern 20d, the contact dielectric pattern 30r, and the pad separation pattern 38, and then a bit line overlay pattern 337 may be formed on the bit line wiring layer. The bit line cover pattern 337 may be used as an etch mask to sequentially etch the bit line wiring layer and the bit line diffusion barrier layer, thereby forming the bit line wiring pattern 332 and the bit line diffusion barrier pattern 331. Thus, the bit line BL can be formed.

Referring to fig. 13B and 13C, the bit line cover pattern 337 may be used as an etch mask to etch the first conductive pattern 20d exposed at one side of the bit line cover pattern 337, thereby forming a bit line contact DC. In addition, the contact dielectric pattern 30R exposed at one side of the bit line overlay pattern 337 may also be etched, and thus an upper portion of the contact dielectric pattern 30R may be removed and the recess region R1 may be formed at one side of the bit line contact DC. The recess regions R1 may expose sidewalls of the storage node pads XP and sidewalls of the pad separation patterns 38. In this etching process, process parameters may be appropriately adjusted to allow the bit line contact DC to have a sloped sidewall and a width increasing in a downward direction.

Referring to fig. 14A and 14B, a spacer liner 321 may be conformally formed on the entire surface of the substrate 301. A buried dielectric layer (not shown) may be formed on the spacer liner 321 to fill the recess region R1. The buried dielectric layer may be subjected to an etch-back process to form a buried dielectric pattern 341 in the recess region R1. A top surface of the pad separation pattern 38 may be exposed, and the spacer liner 321 may remain on sidewalls of the bit lines BL and sidewalls of the bit line capping patterns 337.

Referring to fig. 15A and 15B, a first spacer layer may be conformally formed on the entire surface of the substrate 301, and then the first spacer layer may be etched back to form first spacers 323 covering sidewalls of the spacer liner 321. In this step, the buried dielectric pattern 341 and the pad separation pattern 38 may be partially etched at an upper portion thereof. The second spacer layer may be conformally formed on the entire surface of the substrate 301, and then the second spacer layer may be etched back to form the second spacers 325 covering the sidewalls of the first spacers 323. Thus, the bitline spacer SP may be formed.

Referring to fig. 16A and 16B, a sacrificial buried layer may be formed on the entire surface of the substrate 301 to fill the space between the bit lines BL, and an etch-back process and a patterning process may be performed to form the sacrificial buried pattern 42 between the bit lines BL. The sacrificial buried pattern 42 may be formed of, for example, silicon oxide, tetraethylorthosilicate (TEOS), or east-fire silazane (TOSZ). The node separation hole 44H may be formed between the bit lines BL and in the sacrificial buried pattern 42. The sacrificial buried pattern 42 may overlap the storage node pad XP. A node separation layer may be formed on the entire surface of the substrate 301 to fill the node separation hole 44H, and then the node separation layer may be etched back to form the node separation pattern 44. The node separation pattern 44 may include, for example, silicon oxide.

Referring to fig. 16A, 16B, 17A, and 17B, the sacrificial buried pattern 42 may be removed to expose the buried dielectric pattern 341 and the pad separation pattern 38. An etching process may be performed to etch the buried dielectric pattern 341 and the pad separation pattern 38 exposed between the bit lines BL, thereby forming storage node contact holes BCH exposing the storage node pads XP. In this step, the upper portion of the bit line spacer SP may also be partially etched. In addition, the upper portion of the storage node pad XP may be partially etched.

Referring to fig. 17A, 17B, 1A and 1B, a contact diffusion barrier layer (not shown) may be conformally formed on the entire surface of the substrate 301, and then a contact metal layer (not shown) may be formed on the contact diffusion barrier layer to fill the storage node contact hole BCH. Both the contact diffusion barrier layer and the contact metal layer may comprise a metal and may be formed by a process (e.g., deposition) performed at a temperature (e.g., several hundred degrees celsius or from about 300 ℃ to about 400 ℃) that is lower than the temperature of the annealing process (e.g., about 1000 ℃).

A Chemical Mechanical Polishing (CMP) process may be subsequently performed to expose the top surface of the bit line cover pattern 337 and simultaneously form the contact diffusion barrier pattern 311 and the contact metal pattern 313. A portion of the contact diffusion barrier layer may be formed as a contact diffusion barrier layer pattern 311. A portion of the contact metal layer may be formed as the contact metal pattern 313. The contact diffusion barrier pattern 311 and the contact metal pattern 313 may constitute a storage node contact BC. Subsequently, a conductive layer may be formed on the storage node contact BC and the bit line overlay pattern 337, and then the conductive layer may be etched to form landing pads LP and form a trench between the landing pads LP. The trench may be filled with a dielectric layer, and then an etch-back process or a Chemical Mechanical Polishing (CMP) process may be performed to form the landing pad separation pattern LPS.

According to some embodiments of the inventive concept, a method of manufacturing a semiconductor memory device may include forming storage node pads XP, which have an area larger than that of the second impurity regions 3b, and forming storage node contact holes BCH exposing the storage node pads XP. Accordingly, when the storage node contact hole BCH is formed, the misalignment margin can be reliably obtained. Therefore, process defects can be reduced.

Fig. 18 illustrates a plan view showing a semiconductor memory device according to some example embodiments of the inventive concepts. Fig. 19 shows an enlarged view showing a portion P1 of fig. 18. The cross-sections taken along linesbase:Sub>A-base:Sub>A 'and B-B' of fig. 18 may be the same as or similar to the cross-section of fig. 1B.

Referring to fig. 18 and 19, with the semiconductor memory device according to the present embodiment, the bit line contact DC may have a shape similar to a rectangle when viewed in a plan view, and may have sidewalls DC _ S recessed inward. Further, the storage node pads XP may have first pad sidewalls XP _ S (1) protruding toward the bit line contacts DC when viewed in a plan view. Other configurations may be the same as or similar to those discussed with reference to fig. 1A-3A.

Fig. 20 is a plan view showing a method of manufacturing the semiconductor memory device having the plan view of fig. 18.

Referring to fig. 20, the second mask pattern 24 may not be formed to have a network shape as shown in fig. 5A, but may be formed to have a plurality of isolated island shapes as shown in fig. 20. The second mask pattern 24 may expose a top surface of the conductive layer 20 overlapping the first impurity region 3 d. The conductive layer 20 may constitute a network shape on its top surface exposed by the second mask pattern 24. The subsequent processes may be the same as or similar to those discussed with reference to fig. 5A-17B.

Fig. 21A illustrates a plan view showing a semiconductor memory device according to some example embodiments of the inventive concepts. Fig. 21B illustrates an enlarged view showing a portion P1 of fig. 21A. Fig. 21A omits illustration of the landing pad LP of fig. 1A. The cross-section taken along linesbase:Sub>A-base:Sub>A 'and B-B' of fig. 21A may be the same as or similar to the cross-section of fig. 1B.

Referring to fig. 1B, 21A and 21B, with the semiconductor memory device according to the present embodiment, the third pad sidewall XP _ S (3) of the storage node pad XP may be convex in the second direction X2 or in a direction away from the first pad sidewall XP _ S (1) when viewed in a plan view. The first pad sidewall XP _ S (1) of the storage node pad XP may be recessed in the second direction X2 or in a direction toward the third pad sidewall XP _ S (3). In the present embodiment, the third pad sidewall XP _ S (3) may have a curvature different from that of the first pad sidewall XP _ S (1). The second and fourth pad sidewalls XP _ S (2) and XP _ S (4) may be flat and parallel to each other, and may connect the first pad sidewall XP _ S (1) to the third pad sidewall XP _ S (3).

The substrate 301 may be provided therein with a first word line WL (1) and a second word line WL (2). The first and second word lines WL (1) and WL (2) may be provided in the substrate 301 such that a top surface of the first and second word lines WL (1) and WL (2) is lower than a top surface 301\uof the substrate 301. A first gate dielectric layer 307 (1) may be interposed between the first word line WL (1) and the substrate 301, and a second gate dielectric layer 307 (2) may be interposed between the second word line WL (2) and the substrate 301.

Storage node pads XP may have a third width W3 in a third direction X3 when viewed in a plan view. The first gate dielectric layer 307 (1) may be spaced apart from the second gate dielectric layer 307 (2) by a first spacing DS1. The center W3_ C of the third width W3 may not be located on an imaginary line SL1 passing through the center DS1_ C of the first space DS1 and parallel to the second direction X2. The center W3_ C of the third width W3 may correspond to a central position between the second pad sidewall XP _ S (2) and the fourth pad sidewall XP _ S (4) of the storage node pad XP, or to a point between and at the same distance from the second pad sidewall XP _ S (2) and the fourth pad sidewall XP _ S (4). The center DS1_ C of the first spacing DS1 may correspond to a center position between the first gate dielectric layer 307 (1) and the second gate dielectric layer 307 (2), or to a point between and at the same distance from the first gate dielectric layer 307 (1) and the second gate dielectric layer 307 (2).

When viewed in a plan view, the second interval DS2 between the first word line WL (1) and the storage node pads XP may be different from the third interval DS3 between the second word line WL (2) and the storage node pads XP.

The storage node pads XP spaced apart from each other with one bit line contact DC therebetween may have shapes that are mirror-symmetrical to each other. For example, the shapes of the storage node pads XP at opposite sides of the bit line contact DC may be mirror images of each other. Other configurations may be the same as or similar to those discussed with reference to fig. 1A-20.

Fig. 22 illustrates a plan view showing a method of manufacturing the semiconductor memory device having the plan view of fig. 21A. The cross-section taken along linesbase:Sub>A-base:Sub>A 'and B-B' of fig. 22 may be the same as or similar to the cross-section of fig. 10B.

Referring to fig. 22, as discussed with reference to fig. 10A and 10B, a third mask pattern 32 may be formed on the contact cover pattern 30 and the second conductive pattern 20pb. In this step, the third mask patterns 32 may each have a planar shape that is not rectangular as shown in fig. 10A but elliptical as shown in fig. 22. The third mask patterns 32 in one column RW1 may have their ends aligned in the third direction X3. The third mask pattern 32 may be formed by using a different patterning process, such as a Double Patterning Technique (DPT), a Quad Patterning Technique (QPT), or photo-etch-photo-etch (LELE). The subsequent processes may be the same as or similar to those discussed with reference to fig. 11A-17B.

Fig. 23A illustrates a plan view showing a semiconductor memory device according to some example embodiments of the inventive concepts. Fig. 23B illustrates an enlarged view showing a portion P1 of fig. 23A. Fig. 23A omits illustration of the landing pad LP of fig. 1A. The cross-section taken along linesbase:Sub>A-base:Sub>A 'and B-B' of fig. 23A may be the same as or similar to the cross-section of fig. 1B.

Referring to fig. 1B, 23A and 23B, the second and fourth pad sidewalls XP _ S (2) and XP _ S (4) may protrude outward, and may connect the first pad sidewall XP _ S (1) of the storage node pad XP to the third pad sidewall XP _ S (3). The storage node pads XP may have an elliptical shape with a portion thereof cut away. For example, the first pad sidewall XP _ S (1) of the storage node pad XP may have a shape recessed in the second direction X2. In the present embodiment, the overlapping area between the storage node pad XP and the active portion ACT may be relatively smaller than that in the case of fig. 21B. Storage node pads XP may not cover but expose sidewall 301 _sof substrate 301, which sidewall 301 _sis adjacent to third pad sidewall XP _ S (3) of storage node pads XP. The other configurations may be the same as or similar to the configurations discussed with reference to fig. 21A and 21B.

Fig. 24 illustrates a plan view showing an example method of manufacturing the semiconductor memory device having the plan view of fig. 23A. The cross-section taken along linesbase:Sub>A-base:Sub>A 'and B-B' of fig. 24 may be the same as or similar to the cross-section of fig. 10B.

Referring to fig. 24, as discussed with reference to fig. 10A and 10B, a third mask pattern 32 may be formed on the contact cover pattern 30 and the second conductive pattern 20pb. In this step, the third mask patterns 32 may each have a planar shape that is not rectangular as shown in fig. 10A but elliptical as shown in fig. 24. A portion of the third mask pattern 32 may overlap the contact coverage pattern 30. In the present embodiment, the third mask patterns 32 in one row RW1 may have end portions that are not aligned in the third direction X3. In the one row RW1, the odd-numbered third mask patterns 32 may be shifted in a direction opposite to the second direction X2, and the even-numbered third mask patterns 32 may be shifted in the second direction X2.

Fig. 25A illustrates a plan view showing an example method of forming the third mask pattern of fig. 24. Fig. 25B showsbase:Sub>A cross-sectional view taken along linesbase:Sub>A-base:Sub>A 'and B-B' of fig. 25A.

Referring to fig. 25A and 25B, at the step of fig. 9A and 9B, a third mask layer 32L may be formed on the contact coverage pattern 30 and the second conductive pattern 20pb. The third mask layer 32L may be formed of a single layer or a plurality of layers including at least one selected from a spin-on hard mask (SOH), an Amorphous Carbon Layer (ACL), silicon nitride, and silicon oxynitride. The fourth mask patterns PR1 and PR2 may be formed on the third mask layer 32L. The fourth mask patterns PR1 and PR2 may include first and second photoresist patterns PR1 and PR2.

The forming of the fourth mask patterns PR1 and PR2 may include: forming a photoresist layer on the third mask layer 32L; performing a first exposure process to convert a portion of the photoresist layer into a first photoresist pattern PR1; performing a second exposure process to convert other portions of the photoresist layer into a second photoresist pattern PR2; and performing a developing process to remove the remaining portion of the photoresist layer that is not converted into the first or second photoresist pattern PR1 or PR2. The first photoresist patterns PR1 may each have an island shape and may be two-dimensionally arranged to be spaced apart from each other. The same interval may be provided between the first photoresist patterns PR 1. The second photoresist patterns PR2 may be alternately arranged between the first photoresist patterns PR 1. The second photoresist pattern PR2 and the first photoresist pattern PR1 may be the same in shape and interval. The first exposure process and the second exposure process may use the same photomask, but the position of the photomask in the first exposure process may be different from the position in the second exposure process. As described above, the third mask pattern 32 of fig. 24 may be formed by forming the fourth mask patterns PR1 and PR2 and then etching the third mask layer 32L using the fourth mask patterns PR1 and PR2 as an etch mask. The subsequent processes may be the same as or similar to those discussed with reference to fig. 11A-17B.

Fig. 26A illustrates a plan view showing a semiconductor memory device according to some example embodiments of the inventive concepts. Fig. 26B illustrates an enlarged view showing a portion P1 of fig. 26A. Fig. 26A omits illustration of the landing pad LP of fig. 1A. The cross-section taken along linesbase:Sub>A-base:Sub>A 'and B-B' of fig. 26A may be the same as or similar to the cross-section of fig. 1B.

Referring to fig. 26A and 26B, with the semiconductor memory device according to the present embodiment, the bit line contacts DC and the storage node pads XP may each have a rounded (e.g., elliptical or circular) shape when viewed in a plan view. The storage node pads XP may have a diameter WD3 that is smaller than a diameter WD4 of the bit line contacts DC. The other configurations may be the same as or similar to the configurations discussed with reference to fig. 23A and 23B.

Fig. 27 illustrates a plan view showing an exemplary method of manufacturing the semiconductor memory device having the plan view of fig. 26A. The cross-section taken along linesbase:Sub>A-base:Sub>A 'and B-B' of fig. 27 may correspond to the cross-section of fig. 10B.

Referring to fig. 27, as discussed with reference to fig. 10A and 10B, a third mask pattern 32 may be formed on the contact cover pattern 30 and the second conductive pattern 20pb. In this step, the third mask patterns 32 may each have a planar shape that is not a rectangle as shown in fig. 10A but a circle as shown in fig. 27. In the present embodiment, the third mask pattern 32 may be in contact with the contact coverage pattern 30, but may not overlap with the contact coverage pattern 30. In the present embodiment, the third mask patterns 32 in one row RW1 may have their ends not aligned in the third direction X3. In one row RW1, the odd-numbered third mask patterns 32 may be shifted in a direction opposite to the second direction X2, and the even-numbered third mask patterns 32 may be shifted in the second direction X2. The formation of the third mask pattern 32 may be substantially the same as or similar to that discussed with reference to fig. 25A and 25B. However, in this case, the fourth mask patterns PR1 and PR2 may each have a circular shape. The subsequent processes may be the same as or similar to those discussed with reference to fig. 11A-17B.

In the semiconductor memory device according to the inventive concept, the substrate may protrude more than the device isolation pattern, and thus a contact area (area) between the substrate and each of the bit line pattern and the storage node pattern may be increased. Therefore, contact resistance can be reduced, and the semiconductor memory device can operate at high speed and low power. In addition, silicon oxide may be included in the spacer liner layer covering the sidewalls of the bit lines, and thus the bit line spacers may be improved in insulation performance. As a result, the semiconductor memory device can be improved in reliability.

In the method of manufacturing a semiconductor memory device according to the inventive concept, the device isolation pattern may be etched to expose a side surface of the substrate. Accordingly, a contact area between the bit line pattern and the side surface of the substrate and between the storage node pattern and the side surface of the substrate may be increased. For this reason, the storage node contact may be formed not to include polysilicon and to include metal, and thus a high temperature annealing process may not be required, which may result in preventing process defects.

Although the present inventive concept has been described in connection with some embodiments thereof shown in the accompanying drawings, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the technical ideas and essential features of the present inventive concept. It will be apparent to those skilled in the art that various substitutions, modifications and changes may be made thereto without departing from the scope and spirit of the inventive concept.

This application claims priority from korean patent application No. 10-2021-0080853, filed at the korean intellectual property office on 22/6/2021, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor memory device, comprising:

a device isolation pattern in a substrate and defining a first active portion and a second active portion spaced apart from each other, a center of the first active portion being adjacent to an end of the second active portion;

a bit line crossing the center of the first active portion;

a bit line contact between the bit line and the first active portion; and

a first storage node pad on the end of the second active portion,

wherein the first storage node pad includes a first pad sidewall adjacent the bit line contact and a second pad sidewall opposite the first pad sidewall, an

Wherein the second pad sidewall is convex in a direction away from the bit line contact when viewed in a plan view.

2. The semiconductor memory device according to claim 1, wherein the first pad sidewall is recessed in the direction away from the bit line contact when viewed in a plan view.

3. The semiconductor memory device of claim 2, wherein a curvature of the second pad sidewall is different from a curvature of the first pad sidewall.

4. The semiconductor memory device according to claim 2,

wherein the first storage node pad further includes a third pad sidewall connecting the first pad sidewall and the second pad sidewall to each other, an

Wherein the third pad sidewall is flat or convex.

5. The semiconductor memory device according to claim 1, wherein when viewed in a plan view:

the bit line contact has a circular shape with a first diameter, an

The first storage node pad has a circular shape with a second diameter smaller than the first diameter.

6. The semiconductor memory device according to claim 1, further comprising:

a first word line in the substrate and extending in a first direction, the first word line crossing over both the first active portion and the second active portion;

a second word line in the substrate and spaced apart from the first word line, the second word line extending in the first direction and crossing the first active portion;

a first gate dielectric layer between the first word line and the substrate; and

a second gate dielectric layer between the second word line and the substrate,

wherein the first storage node pad is between the first word line and the second word line when viewed in a plan view, and

wherein a center of a width of the first storage node pad is not on an imaginary line parallel to the first direction and passing through a center of a space between the first gate dielectric layer and the second gate dielectric layer, the width of the first storage node pad being measured in a second direction orthogonal to the first direction.

7. The semiconductor memory device according to claim 1, further comprising:

a first word line in the substrate and extending in a first direction, the first word line crossing over both the first active portion and the second active portion; and

a second word line in the substrate and spaced apart from the first word line, the second word line extending in the first direction and crossing the first active portion,

wherein a first spacing between the first word line and the first storage node pad is different from a second spacing between the second word line and the first storage node pad.

8. The semiconductor memory device according to claim 1,

wherein a top surface of the device isolation pattern is lower than a top surface of the substrate, an

Wherein the bitline contact covers the top surface of the substrate and a sidewall of the substrate.

9. The semiconductor memory device according to claim 1,

wherein the device isolation pattern further defines a third active portion spaced apart from the second active portion with the first active portion therebetween, an end of the third active portion being adjacent to the center of the first active portion,

wherein the semiconductor memory device further includes a second storage node pad on the end portion of the third active portion, an

Wherein the second storage node pad has a mirror-symmetrical shape to the first storage node pad.

10. A semiconductor memory device comprising:

a first word line extending in the substrate and in a first direction, the first word line crossing over both the first active portion and the second active portion;

a word line overlay pattern on each of the first and second word lines;

a bit line crossing the center of the first active portion;

a bit line contact between the bit line and the first active portion; and

a storage node pad on the end of the second active portion,

wherein the storage node pad is between the first word line and the second word line when viewed in a plan view, an

Wherein a first spacing between the first word line and the storage node pad is different from a second spacing between the second word line and the storage node pad.

11. The semiconductor memory device according to claim 10,

wherein the storage node pad includes a first pad sidewall adjacent to the bit line contact and a second pad sidewall opposite to the first pad sidewall, an

12. The semiconductor memory device according to claim 11, wherein the first pad sidewall is recessed in the direction away from the bit line contact when viewed in a plan view.

13. The semiconductor memory device according to claim 11,

wherein the storage node pad further includes a third pad sidewall connecting the first pad sidewall and the second pad sidewall to each other, an

Wherein the third pad sidewall is flat or convex.

14. The semiconductor memory device according to claim 10, wherein when viewed in a plan view:

the bit line contact has a circular shape with a first diameter, an

The storage node pad has a circular shape with a diameter smaller than the first diameter.

15. A semiconductor memory device comprising:

a first gate dielectric layer between the first word line and the substrate;

a second gate dielectric layer between the second word line and the substrate;

a bit line crossing the center of the first active portion;

a bit line contact between the bit line and the first active portion; and

a storage node pad on the end of the second active portion,

Wherein a center of a width of the storage node pad is not on an imaginary line parallel to the first direction and passing through a center of a space between the first gate dielectric layer and the second gate dielectric layer, the width of the storage node pad being measured in a second direction orthogonal to the first direction.

16. The semiconductor memory device according to claim 15,

17. The semiconductor memory device according to claim 16, wherein the first pad sidewall is recessed in the direction away from the bit line contact when viewed in a plan view.

18. The semiconductor memory device according to claim 16,

Wherein the third pad sidewall is flat or convex.

19. The semiconductor memory device according to claim 15, wherein when viewed in a plan view:

the bit line contact has a circular shape with a first diameter, an

20. The semiconductor memory device according to claim 15, wherein bottom ends of the bit line contacts and the storage node pads are lower than a top surface of the substrate.