CN115513187A - Chip of integrated on-chip inductor, integrated circuit and electronic device - Google Patents
Chip of integrated on-chip inductor, integrated circuit and electronic device Download PDFInfo
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- CN115513187A CN115513187A CN202211469983.4A CN202211469983A CN115513187A CN 115513187 A CN115513187 A CN 115513187A CN 202211469983 A CN202211469983 A CN 202211469983A CN 115513187 A CN115513187 A CN 115513187A
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/645—Inductive arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/10—Inductors
Abstract
The invention discloses a chip of an on-chip inductor, an integrated circuit and an electronic device, wherein the chip of the on-chip inductor is provided with the on-chip inductor on a bare chip, and forms an adjustable inductor connected with the on-chip inductor in parallel through a bonding wire, and then adjusts the inductance value of the on-chip inductor connected with the bonding wire in parallel through adjusting the inductance value of the bonding wire, namely, the adjustment of an equivalent inductance value connected to the circuit on the bare chip is realized, so that the on-chip inductor fluctuation caused by process errors in the chip preparation process can be eliminated under the condition of not consuming extra chip area, and the integration of the inductor required by the circuit on the bare chip is completed; the adjustable inductor connected with the on-chip inductor in parallel is formed through the bonding wire to adjust the integrated inductance value on the die, so that the inductance sensitivity is low, continuous inductance value adjustment is realized, the inductance value adjustment range is expanded, and the adjustment effect is improved. The invention can be widely applied to the technical field of integrated circuits.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a chip of an on-chip inductor, an integrated circuit and an electronic device.
Background
The development of semiconductor materials, process fabrication techniques, and chip packaging techniques has accelerated the progress of component integration. In a monolithic integrated circuit, an Inductor is integrated with other components, so the Inductor integrated in the monolithic integrated circuit is called an On-Chip Inductor (Inductor On Chip). The conventional method generally adopts a mode of gradually increasing the radius to wind a coil on a chip to realize on-chip inductance. At present, an inductor is difficult to integrate on a chip, and the reason is that the inductor occupies a large chip area, and once the chip is manufactured, the inductance of the on-chip inductor is determined, but the performance difference between the chips is large due to the existence of process errors, and particularly when the sensitivity of the inductor is too high, the performance difference is more obvious, so that the robustness of the performance of the chip is poor, and the mass production of the chip cannot be realized.
In order to assist in integration of inductors and improve robustness of chip performance, a multi-version chip screening method is adopted in the existing chip manufacturing process of integrated inductors. The multi-version chip screening method is characterized in that a plurality of bare chips with different inductance versions are manufactured on the basis of target inductance, the bare chips with the plurality of versions are tested and compared, and the bare chips which meet expected performance are screened out to be subjected to the next manufacturing process. However, the multi-version chip screening method needs to consume additional chip area to manufacture multi-version bare chips, and the larger the variable range of the inductance is, or the more the chip versions are, the larger the consumed chip area is; meanwhile, in the multi-version chip screening method, the variable range of the inductor is limited and the change is discontinuous, the sensitivity of the on-chip inductor cannot be reduced, and the screening effect on the bare chip which meets the expected performance is poor.
Disclosure of Invention
In order to solve the above technical problems, embodiments of the present invention provide a chip, an integrated circuit, and an electronic device for integrating an on-chip inductor.
The technical scheme adopted by the embodiment of the invention on the one hand is as follows:
a chip integrating an on-chip inductor, comprising:
a substrate, a bare chip and a bonding wire;
the substrate is formed by stacking a plurality of metal layers in the vertical direction, a second metal layer is arranged in the substrate and used as a ground plane, the second metal layer is any one layer of metal layer except for a first metal layer in the substrate, the second metal layer is connected with the first metal layer, and the first metal layer is the metal layer which is positioned at the topmost layer in the substrate;
the bare chip is arranged on the first metal layer, a plurality of on-chip inductors are arranged on the bare chip, a first end of each on-chip inductor is connected with a circuit on the bare chip, and a second end of each on-chip inductor is connected with the first metal layer;
the first end of the bonding wire is connected with the first end of the on-chip inductor, the second end of the bonding wire is connected with the first metal layer, and the inductance value of the bonding wire is adjustable.
As an optional implementation manner, the first metal layer is connected to the second metal layer by means of a first metal or an interlayer via, and a type of the first metal is the same as a type of a metal in the first metal layer.
As an alternative embodiment, the bare chip is attached to the first metal layer by a conductive material.
As an alternative embodiment, the conductive material is any one of a solder paste and a conductive adhesive.
As an optional implementation manner, the die is disposed on a first region of the first metal layer, an area of the first region is larger than an area of a surface of the die facing the first region, a second region of the first metal layer is covered with a protection layer, and the second region is a region of the surface of the first metal layer facing the die, except for the first region.
As an optional embodiment, a ground hole is disposed on the die, and the second end of the on-chip inductor is connected to the first metal layer through the ground hole.
As an optional implementation manner, a bonding pad is disposed at a connection between the first end of the on-chip inductor and a circuit on the bare chip, the first end of the on-chip inductor is connected to the bonding pad, and the first end of the bonding wire is connected to the bonding pad.
As an alternative embodiment, the bonding wire is any one of a bonded copper wire, a bonded aluminum wire, a bonded silver wire, and a bonded alloy wire.
The technical scheme adopted by the embodiment of the invention on the other hand is as follows:
an integrated circuit comprising at least one chip of said integrated on-chip inductor.
The technical scheme adopted by the embodiment of the invention on the other hand is as follows:
an electronic device comprising the integrated circuit.
According to the chip of the on-chip inductor, the on-chip inductor is arranged on the chip, the adjustable inductor connected with the on-chip inductor in parallel is formed through the bonding wire, and the inductance value of the on-chip inductor connected with the bonding wire in parallel is adjusted through adjusting the inductance value of the bonding wire, so that the adjustment of the equivalent inductance value connected to a circuit on the chip is realized, the fluctuation of the on-chip inductor caused by process errors in the chip preparation process can be eliminated under the condition of not consuming extra chip area, and the integration of the inductor required by the circuit on the bare chip is completed; the adjustable inductor connected with the on-chip inductor in parallel is formed through the bonding wire to adjust the integrated inductance value on the die, so that the inductance sensitivity is low, continuous inductance value adjustment is realized, the inductance value adjustment range is expanded, and the adjustment effect is improved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following description is made on the drawings of the embodiments of the present application or the related technical solutions in the prior art, and it should be understood that the drawings in the following description are only for convenience and clarity of describing some embodiments in the technical solutions of the present application, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 is a schematic diagram of a multi-version chip screening method according to the prior art;
FIG. 2 is a diagram illustrating a chip structure of an integrated on-chip inductor according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a substrate of a chip with an on-chip inductor according to an embodiment of the present invention;
FIG. 4 is a schematic diagram illustrating an inductance adjustment principle of a chip integrated with an on-chip inductor according to an embodiment of the present invention;
fig. 5 is a schematic diagram illustrating the desensitization principle and effect of the on-chip inductor of the chip integrated with the on-chip inductor according to the embodiment of the invention.
Reference numerals: 201. a substrate; 202. a bare chip; 203. a bonding wire; 204. an on-chip inductor; 301. a first metal layer; 302. a second metal layer.
Detailed Description
In order to make the technical solutions better understood by those skilled in the art, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only partial embodiments of the present application, but not all embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application without making any creative effort shall fall within the protection scope of the present application.
The terms "first," "second," "third," and "fourth," etc. in the description and claims of this application and in the accompanying drawings are used for distinguishing between different objects and not for describing a particular order. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.
The existing chip manufacturing process of the integrated inductor adopts a multi-version chip screening method to assist in integration of the inductor, so that the robustness of the performance of the chip is improved. The multi-version chip screening method comprises the steps of manufacturing a plurality of bare chips with different inductance versions on the basis of target inductance, testing and comparing the bare chips with the plurality of versions, screening the bare chips meeting expected performance, and carrying out the next processing. Fig. 1 shows a Wafer (Wafer) obtained by chip fabrication in the prior art, which includes three versions (V1, V2, V3) of bare chips (Die). Wherein, the inductance of the bare chip of the V1 version is
(target inductance), the inductance of the bare chip of V2 version is
The inductance of the bare chip of the V3 version is
. The bare chips of the three versions (V1, V2 and V3) are tested and compared, and the versions of the bare chips which accord with expected performance are screened out, so that inductance variation caused by chip process errors is counteracted.
However, the multi-version chip screening method needs to consume additional chip area to manufacture multi-version bare chips, and the larger the variable range of the inductance is, or the more the chip versions are, the larger the consumed chip area is; meanwhile, in the multi-version chip screening method, the variable range of the inductor is limited and the change is discontinuous, and the screening effect on the bare chip which meets the expected performance is poor. Therefore, the embodiment of the invention provides a chip of an on-chip inductor, an integrated circuit and an electronic device, wherein the on-chip inductor is arranged on a bare chip, an adjustable inductor connected with the on-chip inductor in parallel is formed through a bonding wire, and the inductance value of the on-chip inductor connected with the bonding wire in parallel is adjusted through adjusting the inductance value of the bonding wire, so that the adjustment of the equivalent inductance value connected to the circuit on the bare chip is realized, the fluctuation of the on-chip inductor caused by the process error in the chip preparation process can be eliminated without consuming extra chip area, and the integration of the inductor required by the circuit on the bare chip is completed; the adjustable inductor connected with the on-chip inductor in parallel is formed through the bonding wire to adjust the integrated inductance value on the die, so that the inductance sensitivity is low, continuous inductance value adjustment is realized, the inductance value adjustment range is expanded, and the adjustment effect is improved.
As shown in fig. 2 and fig. 3, an embodiment of the present invention provides a chip of an integrated on-chip inductor 204, where the chip of the integrated on-chip inductor 204 includes:
a substrate 201, a bare chip 202 and a bonding wire 203;
the substrate 201 is formed by stacking a plurality of metal layers in a vertical direction, a second metal layer 302 is arranged in the substrate 201 and serves as a ground plane, the second metal layer 302 is connected with the first metal layer 301, wherein the second metal layer 302 is any one of the metal layers in the substrate 201 except the first metal layer 301, and the first metal layer 301 is the metal layer positioned at the topmost layer in the substrate 201;
the bare chip 202 is arranged on the first metal layer 301, a plurality of on-chip inductors 204 are arranged on the bare chip 202, a first end of each on-chip inductor 204 is connected with a circuit on the bare chip 202, and a second end of each on-chip inductor 204 is connected with the first metal layer 301;
a first end of the bond wire 203 is connected to a first end of the on-chip inductor 204, a second end of the bond wire 203 is connected to the first metal layer 301, and an inductance value of the bond wire 203 is adjustable.
Wherein the bonding wires 203 realize the electrical connection between the bare chip 202 and the substrate 201.
It is understood that the substrate 201 further includes an insulating layer between the metal layers, and a protective layer (passivation layer) covering the topmost metal layer (first metal layer 301).
In some embodiments, three-dimensional routing is performed within substrate 201, and first metal layer 301 and second metal layer 302 are connected by three-dimensional routing within substrate 201. Here, the three-dimensional wiring of the substrate 201 will be described later.
Illustratively, referring to fig. 3, the first metal layer 301 is a metal layer located at the topmost layer in the substrate 201, the second metal layer 302 is a metal layer located at a layer above the metal layer located at the bottommost layer in the substrate 201, and the first metal layer 301 and the second metal layer 302 are connected by a three-dimensional routing in the substrate 201.
It can be understood that, since the first metal layer 301 is connected to the second metal layer 302, and the second metal layer 302 is a ground plane, the second end of each on-chip inductor 204 is connected to the first metal layer 301, i.e. the second end of each on-chip inductor 204 is grounded, and the second end of the bonding wire 203 is connected to the first metal layer 301, i.e. the second end of the bonding wire 203 is grounded.
It can be understood that the bond wire 203 is connected in parallel with the on-chip inductor 204, and the inductance of the bond wire 203 connected in parallel with the on-chip inductor 204 is adjustable according to a priori knowledge. Therefore, the inductance value integrated on the bare chip 202 can be adjusted by adjusting the inductance value of the bonding wire 203, so that the on-chip integrated inductance value reaches the required target inductance value, and the fluctuation of the on-chip inductor 204 caused by process errors in the chip preparation process can be eliminated without consuming extra chip area.
It can be understood that, in the embodiment of the present invention, the inductance value integrated on the bare chip 202 is adjusted by adjusting the inductance value of the bonding wire 203 connected in parallel with the on-chip inductor 204, and the inductance value is continuous in the adjustment process, so that the adjustment range of the inductance value is wider and the adjustment effect is better compared with the conventional multi-version chip screening method.
In the embodiment of the present invention, the larger the inductance value shift of the on-chip inductor 204 due to process errors, the larger the required inductance adjustment range.
According to the priori knowledge, the inductance is used as a key component of the impedance matching network, and the circuit performance can be directly changed by the change of the inductance. For a single turn inductance of the same radius, the amount of inductance is proportional to the length of the coil. Hair brushIn the embodiment, the error of the chip preparation process is considered, and the absolute error of the coil length caused by the process error is recorded as
And the deviation of inductance due to the absolute error of the coil length is recorded as
，
Is a definite value under a given process. In the embodiment of the invention, the inductance value required by the chip is called as the target inductance value (recorded as
). Under a given process, the relative error of the inductance value due to the process error is:
it will be appreciated that the greater the relative error, the greater the integrated on-chip inductance is affected by process errors. Due to the fact that
A determined value under a given process, so that the relative error delta and the target inductance
In inverse proportion, the smaller the target inductance is, the larger the relative error is, i.e., the smaller the on-chip inductance is, the larger the influence of the process error is.
Although the on-chip inductance having a small inductance value is greatly affected by process errors, it does not mean that the on-chip inductance having a small inductance value has a large influence on circuit performance. According to the embodiment of the invention, the on-chip inductor is divided into a series inductor and a parallel inductor according to the topological structure of the inductor in the circuit. The series inductor is formed by connecting an on-chip inductor with other components in series in a circuit of a bare chip; the parallel inductor is connected with other components in parallel in a circuit of the bare chip (the common form is inductor grounding, namely the on-chip inductor setting mode in the embodiment of the invention). In the series topology, the overall impedance of the circuit is determined by the components with larger impedance, so that the on-chip inductance with small inductance value does not play a role in the series topology; in contrast, in the parallel topology, the overall impedance of the circuit is determined by the components with smaller impedance, so the on-chip inductor with small inductance plays a decisive role in the parallel topology, which means that in the parallel topology, the inductance value change of the on-chip inductor with small inductance will bring about great change of the circuit performance.
As an alternative embodiment, the first metal layer 301 is connected to the second metal layer 302 by means of a first metal or an interlayer via.
Wherein the type of the first metal is the same as the type of the metal in the first metal layer 301.
In some embodiments, interlayer vias are disposed in the vertical direction of the substrate 201, penetrating through different layers of the substrate 201, enabling three-dimensional routing between metal layers stacked in the vertical direction within the substrate 201.
Optionally, in some embodiments, the inner wall of the interlayer via is provided with a conductor to conduct the metal layers stacked in the vertical direction in the substrate 201, so as to realize three-dimensional routing in the substrate 201.
Optionally, in other embodiments, a conductor (e.g., a first metal used for connection between the first metal layer 301 and the second metal layer 302) is disposed in the interlayer via to connect the metal layers stacked in the vertical direction in the substrate 201, so as to implement three-dimensional routing in the substrate 201.
In some embodiments, the interlayer via hole is obtained by performing hole making after the organic material lamination. Alternatively, holes are formed in the stacked organic layers using ultraviolet rays or laser light to obtain interlayer vias, and then metal layers are plated in the interlayer vias to achieve connection between the metal layers stacked in the vertical direction within the substrate 201.
According to the priori knowledge, the aperture and the pitch of the interlayer via holes obtained by hole making after the organic material lamination are small, and the method is suitable for the scene in which high-density wiring or high-density packaging is needed in the substrate 201.
In some embodiments, the substrate 201 on which three-dimensional wiring is obtained is prepared using a ceramic multilayer wiring board. Compared with the mode of hole making after organic material lamination, the process is high temperature resistant, metal paste can be adopted for screen printing of metal layer patterns and metal filling of interlayer via holes, electroplating is not needed, the process cost and the process complexity are low, and the method is suitable for high-temperature manufacturing or preparation scenes without electroplating conditions.
As an alternative embodiment, the bare chip 202 is attached to the first metal layer 301 by a conductive material.
It is understood that the front side (the side on which the circuit and the on-chip inductor 204 are disposed) of the bare chip 202 faces upward, and the back side of the bare chip 202 is attached to the first metal layer 301 through a conductive material.
As an alternative embodiment, the conductive material is any one of solder paste and conductive paste.
According to the priori knowledge, the solder paste is also called solder paste, and can be divided into high-temperature solder paste, medium-temperature solder paste and low-temperature solder paste according to the melting point of the solder paste. The high-temperature solder paste is lead-free solder paste, the melting point is generally higher than 217 ℃, and the welding effect is better; the melting point of the common lead-free medium-temperature solder paste is about 170 ℃, the medium-temperature solder paste has good adhesion, and the bare chip 202 or the substrate 201 can be effectively prevented from collapsing; the melting point of the low-temperature solder paste is 138 ℃, the bismuth component is added, and when the bare chip 202 of the paster can not bear the temperature of 200 ℃ or above and the paster reflow process is needed, the low-temperature solder paste can be used for carrying out the welding process. In some embodiments of the present invention, a suitable solder paste is selected based on the process temperature during the manufacturing process.
According to the prior knowledge, the conductive adhesive is an adhesive with certain conductivity after being cured or dried, and in some embodiments of the present invention, the conductive adhesive is used to connect the bare chip 202 and the substrate 201 together, so that an electrical path is formed between the bare chip 202 and the substrate 201. The variety of the conductive adhesive is various, and the conductive adhesive can be divided into a general conductive adhesive and a special conductive adhesive from the application angle. The general conductive adhesive only has requirements on the conductivity and the bonding strength of the conductive adhesive, and the special conductive adhesive has the characteristics of high temperature resistance, ultralow temperature resistance, instant curing, anisotropy, transparency and the like besides the requirements on the conductivity and the bonding strength. In some embodiments of the present invention, the selection of a suitable conductive paste is based on the process requirements during the fabrication process.
As an alternative embodiment, the bare chip 202 is disposed on a first region of the first metal layer 301, the area of the first region is larger than the area of a side of the bare chip 202 facing the first region, and a second region of the first metal layer 301 is covered with the protection layer, the second region being a region of the side of the first metal layer 301 facing the bare chip 202 except the first region.
Optionally, in some embodiments, after the substrate 201 is prepared, a first area is defined on the first metal layer 301 and etched, and the first metal layer 301 on the first area is exposed by windowing, so as to attach the bare chip 202 on the first area.
As an alternative embodiment, a ground hole is disposed on the bare chip 202, and the second terminal of the on-chip inductor 204 is connected to the first metal layer 301 through the ground hole.
It is understood that the ground terminals of the circuits on the die 202 are also connected to the first metal layer 301 through the ground holes so that the ground terminals of the circuits are connected to the common ground plane (the second metal layer 302).
As an alternative embodiment, a bonding Pad (Pad) is disposed at a connection between the first end of the on-chip inductor 204 and a circuit on the bare chip 202, the first end of the on-chip inductor 204 is connected to the bonding Pad, and the first end of the bonding wire 203 is connected to the bonding Pad.
As an alternative embodiment, the bonding wire 203 is any one of a bonded copper wire, a bonded aluminum wire, a bonded silver wire, and a bonded alloy wire.
The bonding copper wire has higher corrosion resistance and excellent secondary welding property, and becomes a mainstream integrated circuit packaging material; the bonding aluminum wire comprises a pure aluminum wire and a silicon aluminum wire, has the advantages of good bonding property and strong moisture resistance, and is mainly applied to semiconductor power devices (such as IGBT, MOSFET, UPS and power triode) and optical devices; the bonding silver wire has good bonding performance and is lower in cost compared with a bonding gold wire; the bonding alloy wire has high metal chemical stability and extremely high operation efficiency in process application. In some embodiments of the present invention, the corresponding bonding wire 203 may be selected according to an actual application scenario.
FIG. 4 shows a bonding wire 203 (with BW inductance) and an on-chip inductor 204 (with BW inductance) according to an embodiment of the present invention
) The parallel connection of the inductors is realized. As shown in FIG. 4, in some embodiments, a target inductance value required by a circuit in a chip is assumed
The inductance value of the integrated on-chip inductor 204 is shifted to due to process errors during the chip manufacturing process
. At this time, the bond wire 203 is connected in parallel with the on-chip inductor 204, and the inductance BW of the bond wire 203 is adjusted so that the inductance after the bond wire 203 is connected in parallel with the on-chip inductor 204 is equal to the target inductance
. According to the prior knowledge, the method comprises the following steps:
wherein the content of the first and second substances,
(the inductance value of the integrated on-chip inductor 204 is fixed after chip flow), the calculation can be carried out as follows:
therefore, when the inductance value of the integrated on-chip inductor 204 is shifted to due to process errors during the chip manufacturing process
While, the inductance value of the bonding wire 203 can be adjusted
So that the inductance value of the equivalent on-chip inductor on the bare chip 202
Equal to target inductance value
。
Referring to fig. 5, the inductance value of the on-chip inductor 204 is maintained
Constant value of inductance of bond wire 203BWFrom 6LBecomes 3.6LThe inductance of the equivalent on-chip inductor on the bare chip 202
From
Becomes 0.9LBy adjusting the value of the inductance on the bond wire 203BW2.4 ofLRealizes the inductance value of the equivalent on-chip inductor on the bare chip 202
0.1 ofLThe de-sense effect of the on-chip inductor 204 integrated with the bare chip 202 is achieved.
It can be appreciated that the inductance of the on-chip inductor 204
The larger the offset of (3), the required inductance value of the bonding wire 203 is adjustedBWThe larger, the less desensitizing the on-chip inductor 204.
The technical scheme adopted by the embodiment of the invention on the other hand is as follows:
an integrated circuit comprising at least one chip of said integrated on-chip inductor.
The technical scheme adopted by the embodiment of the invention on the other hand is as follows:
an electronic device comprising the integrated circuit.
Those of ordinary skill in the art will be able to implement the application as set forth in the claims without undue experimentation. It is also to be understood that the specific concepts disclosed are merely illustrative of and not intended to limit the scope of the application, which is defined by the appended claims and their full scope of equivalents.
In the foregoing description of the specification, reference to the description of "one embodiment/example," "another embodiment/example," or "certain embodiments/examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
While embodiments of the present application have been shown and described, it will be understood by those of ordinary skill in the art that: numerous changes, modifications, substitutions and alterations can be made to the embodiments without departing from the principles and spirit of the application, the scope of which is defined by the claims and their equivalents.
While the preferred embodiments of the present invention have been illustrated and described, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A chip incorporating an on-chip inductor, comprising:
a substrate, a bare chip and a bonding wire;
the substrate is formed by stacking a plurality of metal layers in the vertical direction, a second metal layer is arranged in the substrate and serves as a ground plane, the second metal layer is any one layer of metal layer except a first metal layer in the substrate, the second metal layer is connected with the first metal layer, and the first metal layer is the metal layer which is positioned at the topmost layer in the substrate;
the bare chip is arranged on the first metal layer, a plurality of on-chip inductors are arranged on the bare chip, the first end of each on-chip inductor is connected with a circuit on the bare chip, and the second end of each on-chip inductor is connected with the first metal layer;
the first end of the bonding wire is connected with the first end of the on-chip inductor, the second end of the bonding wire is connected with the first metal layer, and the inductance value of the bonding wire is adjustable.
2. The chip of the integrated on-chip inductor according to claim 1, wherein the first metal layer is connected to the second metal layer by means of a first metal or an interlayer via, and the type of the first metal is the same as that of the metal in the first metal layer.
3. The chip of claim 2, wherein the bare chip is attached to the first metal layer by a conductive material.
4. The chip of claim 3, wherein the conductive material is any one of solder paste and conductive paste.
5. The chip of claim 1, wherein the die is disposed on a first region of the first metal layer, the first region has an area larger than an area of a side of the die facing the first region, a second region of the first metal layer is covered with a protection layer, and the second region is a region of the side of the first metal layer facing the die other than the first region.
6. The chip of claim 1, wherein a ground via is disposed on the die, and the second end of the on-chip inductor is connected to the first metal layer through the ground via.
7. The chip of claim 1, wherein a bonding pad is disposed at a connection point of the first end of the on-chip inductor and a circuit on the bare chip, the first end of the on-chip inductor is connected to the bonding pad, and the first end of the bonding wire is connected to the bonding pad.
8. The chip of claim 1, wherein the bonding wire is any one of a bonding copper wire, a bonding aluminum wire, a bonding silver wire and a bonding alloy wire.
9. An integrated circuit comprising at least one chip of an integrated on-chip inductor as claimed in any one of claims 1 to 8.
10. An electronic device, characterized in that the electronic device comprises the integrated circuit of claim 9.
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|---|---|---|---|---|
| US20020011646A1 (en) * | 2000-07-28 | 2002-01-31 | Conexant Systems, Inc. | On-chip inductors |
| US6355970B1 (en) * | 1999-05-19 | 2002-03-12 | Nec Corporation | Semiconductor device having a high frequency electronic circuit |
| US6775901B1 (en) * | 1998-08-14 | 2004-08-17 | Hai Young Lee | Bonding wire inductor |
| US20050285262A1 (en) * | 2002-09-10 | 2005-12-29 | James Knapp | Semiconductor device with wire bond inductor and method |
| US20090128436A1 (en) * | 2005-04-14 | 2009-05-21 | Agency For Science, Technology And Research | On-chip inductor with trimmable inductance, a method for making the same and a method for adjusting the impedance of the inductance |
| CN103500736A (en) * | 2013-08-22 | 2014-01-08 | 上海宏力半导体制造有限公司 | Chip packaging structure and chip packaging method |
| CN114709054A (en) * | 2022-03-23 | 2022-07-05 | 上海艾为电子技术股份有限公司 | On-chip inductor and manufacturing method thereof |
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2022
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6775901B1 (en) * | 1998-08-14 | 2004-08-17 | Hai Young Lee | Bonding wire inductor |
| US6355970B1 (en) * | 1999-05-19 | 2002-03-12 | Nec Corporation | Semiconductor device having a high frequency electronic circuit |
| US20020011646A1 (en) * | 2000-07-28 | 2002-01-31 | Conexant Systems, Inc. | On-chip inductors |
| US20050285262A1 (en) * | 2002-09-10 | 2005-12-29 | James Knapp | Semiconductor device with wire bond inductor and method |
| US20090128436A1 (en) * | 2005-04-14 | 2009-05-21 | Agency For Science, Technology And Research | On-chip inductor with trimmable inductance, a method for making the same and a method for adjusting the impedance of the inductance |
| CN103500736A (en) * | 2013-08-22 | 2014-01-08 | 上海宏力半导体制造有限公司 | Chip packaging structure and chip packaging method |
| CN114709054A (en) * | 2022-03-23 | 2022-07-05 | 上海艾为电子技术股份有限公司 | On-chip inductor and manufacturing method thereof |
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