CN115509979A - FPGA bus board card suitable for multiple case slots - Google Patents

FPGA bus board card suitable for multiple case slots Download PDF

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Publication number
CN115509979A
CN115509979A CN202211276756.XA CN202211276756A CN115509979A CN 115509979 A CN115509979 A CN 115509979A CN 202211276756 A CN202211276756 A CN 202211276756A CN 115509979 A CN115509979 A CN 115509979A
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CN
China
Prior art keywords
bus
signal connection
connection area
pci
board card
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Pending
Application number
CN202211276756.XA
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Chinese (zh)
Inventor
李刚
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Chengdu Changbo Instrument Co ltd
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Chengdu Changbo Instrument Co ltd
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Priority to CN202211276756.XA priority Critical patent/CN115509979A/en
Publication of CN115509979A publication Critical patent/CN115509979A/en
Pending legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Coupling Device And Connection With Printed Circuit (AREA)

Abstract

The invention discloses an FPGA bus board card suitable for various chassis slots, which comprises a PCB board, wherein the PCB board is provided with an FPGA chip, a level conversion chip, a CPCI bus, a PXI bus, a PXIe bus and a signal connecting area; the FPGA chip comprises a processing module, and a synchronous clock control module, a trigger control logic module, a PCIe core and a PCI core which are all connected with the processing module, wherein the signal connecting area comprises a synchronous clock signal connecting area, a trigger signal connecting area, a PCIe bus signal connecting area and a PCI bus signal connecting area; the bus board card integrates the CPCI bus, the PXI bus and the PXIe bus at the same time, a connecting area suitable for various different connectors is designed, the corresponding connectors can be connected in a crimping mode according to different chassis slots so that the same bus board card can be suitable for the plugging of different slots, and therefore the technical problems of repeated design and resource waste of the existing bus board card are solved.

Description

FPGA bus board card suitable for multiple case slots
Technical Field
The invention relates to the technical field of measurement and control, in particular to an FPGA (field programmable gate array) bus board card suitable for various chassis slots.
Background
In the field of measurement and control instruments at present, four bus board cards based on an FPGA chip are mainly used, namely a CPCI bus board card, a PXI bus board card, a CPCI (CPCI Express) bus board card and a PXIe bus board card (PXI Express). The buses of the four bus boards have independent and complete specification definition and constraint. Since the PXI bus can be compatible with the CPCI bus and the PXIe bus can be compatible with the CPCIe bus, the four bus boards can be classified into two types of incompatible PXI and PXIe. In practical applications, two types of bus boards have respective markets, the use frequencies of the two types of bus boards are approximately equivalent, but due to the differences in bus throughput, bus triggering, synchronous clocks, power supply configuration and the like, a PXIe bus board with more advanced performance cannot completely replace a PXI bus board.
At present, three cases mainly exist in the market, one case is a CPCI case and supports a CPCI bus board card, the other case is a PXI case and supports a PXI bus board card, and the other case is a PXIe case and supports the PXI bus board card and the PXIe bus board card. Although a hybrid slot chassis is designed in the PXIe specification, that is, one slot can support multiple bus boards, there is no technology that can realize that one bus board supports multiple slots, and a bus board with the same function usually needs to be designed differently to face chassis with different slots, so that there are problems of repeated design and resource waste.
For this reason, it is necessary to develop a new technology to solve the above technical problems.
Disclosure of Invention
The invention provides an FPGA bus board card suitable for various chassis slots, which integrates a CPCI bus, a PXI bus and a PXIe bus at the same time and designs a connecting area suitable for various different connectors, so that the same bus board card can be connected with the corresponding connectors in a crimping mode according to different chassis slots to realize the plugging of different slots, and the technical problems of repeated design and resource waste of the conventional bus board card are solved.
In order to achieve the purpose, the technical scheme adopted by the invention is as follows:
the utility model provides a FPGA bus integrated circuit board suitable for multiple quick-witted case slot which characterized in that: the device comprises a PCB (printed circuit board), wherein the PCB is provided with an FPGA (field programmable gate array) chip, a level conversion chip, a CPCI (compact peripheral component interconnect) bus, a PXI (peripheral component interconnect) bus, a PXIe bus and a signal connection area for crimping different connectors;
the FPGA chip comprises a processing module, a synchronous clock control module, a trigger control logic module, a PCIe core and a PCI core, wherein the synchronous clock control module, the trigger control logic module, the PCIe core and the PCI core are all connected with the processing module;
the signal connection area comprises a synchronous clock signal connection area, a trigger signal connection area, a PCIe bus signal connection area and a PCI bus signal connection area; wherein the content of the first and second substances,
the PCI core is connected with a PCI bus signal connection area through a PCIe bus and a level conversion chip;
one end of the PXI bus is respectively connected with the trigger signal connection area and the PCI bus signal connection area, and the other end of the PXI bus is respectively connected with the trigger control logic module and the PCI core;
one end of the PXIe bus is respectively connected with the synchronous clock signal connection area, the trigger signal connection area and the PCIe bus signal connection area, and the other end of the PXIe bus is respectively connected with the synchronous clock control module, the trigger control logic module and the PCIe core;
when the connector is pressed on the PCI bus signal connection area, the bus board card is suitable for a CPCI chassis slot;
when the connector is in pressure joint on the synchronous clock signal connection area and the trigger signal connection area and in pressure joint on the PCI bus signal connection area, the bus board card is suitable for a PXI chassis slot;
when the connector is in pressure joint on the synchronous clock signal connection area and the trigger signal connection area and in pressure joint on the PCIe bus signal connection area, the bus board card is suitable for a PXIe case slot.
The signal connection area all sets up the homonymy at PCB board tip, and synchronous clock signal connection area, trigger signal connection area, PCIe bus signal connection area and PCI bus signal connection area set gradually from last to down.
The signal connection area is a jack matched with the connector pin.
The level conversion chip is used for converting the PCI signal of 3.3V or 5V into the PCI signal of 3.3V.
By adopting the technical scheme, the invention has the beneficial technical effects that:
the bus board card disclosed by the invention integrates the CPCI bus, the PXI bus and the PXIe bus at the same time, and the signal connection areas which are arranged on the PCB board and are respectively connected with the CPCI bus, the PXI bus and the PXIe bus and the FPGA chip are utilized, so that the bus board card disclosed by the invention can be connected with different connectors, and the corresponding connectors can be pressed and connected according to different chassis slots in actual application so as to realize that the same bus board card is suitable for the plugging of different slots. That is to say, the invention can support the plugging of different chassis slots by pressing different connectors according to actual needs, thereby solving the technical problems of repeated design and resource waste of the existing bus board card.
Drawings
FIG. 1 is a functional block diagram of the present invention;
FIG. 2 is a schematic view of the crimp J1 connector of the present invention;
FIG. 3 is a schematic view of the construction of the crimp J1 connector and the XJ4 connector of the present invention;
FIG. 4 is a schematic diagram of the construction of the crimp XJ3 connector and the XJ4 connector of the present invention.
Detailed Description
As the PCI bus specification and the PXI bus specification are relatively long, most design guides adopt the traditional design scheme, technology and devices, and can meet the performance index required by the specification. However, with the development of technology, the performance of the design, such as higher logic operation speed, higher performance of the bus transfer DMA controller, higher integration level and flexibility, can be greatly improved by the current design scheme and device model selection, and the design time cost, device cost and product power consumption are reduced, especially a part of the old device cost is increased rapidly in recent years. Therefore, the invention provides the bus board card based on the FPGA chip, and the bus board card is suitable for the plugging of various chassis slots, and can reduce the design cost for the CPCI or PXI bus board card, namely, the technology that the bus board card supports various slots can be realized, the cost can be reduced, and the performance can be improved.
As shown in fig. 1, the bus board card includes a PCB board, and the PCB board is provided with an FPGA chip, a level conversion chip, a CPCI bus, a PXI bus, a PXIe bus, and a signal connection area for crimping different connectors, and since the specification supports two PCI signal level hardware options, the level conversion chip is used to convert a PCI signal of 3.3V or 5V into a PCI signal of 3.3V. Wherein the content of the first and second substances,
the FPGA chip comprises a processing module, a synchronous clock control module, a trigger control logic module, a PCIe core and a PCI core, wherein the synchronous clock control module, the trigger control logic module, the PCIe core and the PCI core are all connected with the processing module.
The signal connection area includes synchronous clock signal connection area, trigger signal connection area, PCIe bus signal connection area and PCI bus signal connection area, and synchronous clock signal connection area, trigger signal connection area, PCIe bus signal connection area and PCI bus signal connection area all set up the homonymy at PCB board tip, and synchronous clock signal connection area, trigger signal connection area, PCIe bus signal connection area and PCI bus signal connection area set gradually from last to down.
Furthermore, the synchronous clock signal connection area, the trigger signal connection area, the PCIe bus signal connection area, and the PCI bus signal connection area are all jacks that are disposed on the PCB and are adapted to pins of the connector, and these signal connection areas are used to crimp different connectors, for example, may be used to crimp a J1 connector, an XJ3 connector, and an XJ4 connector, and by crimping different connectors, the bus board card may be suitable for plugging different chassis slots.
In the FPGA chip, a PCI core is connected with a signal connection area through a PCI bus and a level conversion chip. One end of the PXI bus is connected with the trigger signal connection area and the PCI bus signal connection area respectively, and the other end of the PXI bus is connected with the trigger control logic module and the PCI core respectively. One end of the PXIe bus is connected with the synchronous clock signal connection area, the trigger signal connection area and the PCIe bus signal connection area respectively, and the other end of the PXIe bus is connected with the synchronous clock control module, the trigger control logic module and the PCIe core respectively.
As shown in fig. 2, the bus card is adapted to fit into a CPCI chassis slot when the connector is crimped onto the PCI bus signal connection area.
As shown in fig. 3, the bus board card is adapted to a PXI chassis slot when the connector is crimped to the synchronous clock signal connection region and the trigger signal connection region, and is crimped to the PCI bus signal connection region.
As shown in fig. 4, the bus card is adapted to a PXIe chassis slot when the connector is crimped over the synchronous clock signal connection region and the trigger signal connection region, and is crimped over the PCIe bus signal connection region.
It should be noted that the FPGA chip and the level conversion chip related in the present invention are both conventional products, for example, the level conversion chip may adopt an SN74CBTD3861 chip of TI company, and the FPGA may adopt an SMQ7K325T FPGA of shenzhen china.
The two designs are used for verification, and when ICs of other manufacturers are selected, the design method is similar.
PCI core
And the PCI core part needs to instantiate the IP core of the PCI according to a conventional method and well allocates a configuration space and a user BAR space address. In particular, the signals PCI _ RST _ N and PCI _ FRAME _ N need to be pulled up in the constraint file, and the BAR space setting is exemplified by:
BAR0: the space size is 4kB, the starting address is 0x1000, and the rest of the BAR space is unused.
PCIe core
And the PCIe core is partially designed, namely the PCIe core is instantiated according to a conventional method, and a configuration space and a user BAR space address are well distributed. In particular, the signal PCIe _ RST _ N needs to be pulled up in the constraint file, the BAR space setting needs to be consistent with the lower bits of the BAR space of the PCI, the upper bits have more than one bit 1, and the BAR space setting is exemplified by:
BAR0: the space size is 4kB, the starting address is 0x3000, and the rest of the BAR space is unused.
3. Trigger control logic module
The trigger control unit is not different from the conventional design, and mainly realizes the functions of PXI trigger bus and star trigger, PXI adjacent trigger and PXIe differential synchronous trigger according to the specification.
4. Synchronous clock control module
The synchronous clock control logic needs a clock enable to gate the PCI clock and the PCIe clock, the gating signal is derived from PCIe reset signal latch, when the PCIe reset signal is low, the PCIe bus is indicated to be initialized, at the moment, the initialization of a PCIe core is completed, meanwhile, the PCI initialization is forbidden, and bus conflict is avoided.
5. Logic dedicated to board card
The board card specific logic is added when the specific board card function is designed. Specially, the board card dedicated logic address is set to be the BAR0 space address coincidence of the PCI, which is convenient for both PCI and PCIe to access, and the dedicated logic space setting is, for example: the space size is 4kB, the initial address is 0x1000, the logic internal judgment address is 13 low bits, and the high bits are not used.
Through the specific design, the invention can realize the technology that the bus board card supports various slots.
While the invention has been described with reference to specific embodiments, any feature disclosed in this specification may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise; all of the disclosed features, or all of the method or process steps, may be combined in any combination, except mutually exclusive features and/or steps.

Claims (4)

1. The utility model provides a FPGA bus integrated circuit board suitable for multiple quick-witted case slot which characterized in that: the device comprises a PCB (printed circuit board), wherein the PCB is provided with an FPGA (field programmable gate array) chip, a level conversion chip, a CPCI (compact peripheral component interconnect) bus, a PXI (peripheral component interconnect) bus, a PXIe bus and a signal connection area for crimping different connectors;
the FPGA chip comprises a processing module, a synchronous clock control module, a trigger control logic module, a PCIe core and a PCI core, wherein the synchronous clock control module, the trigger control logic module, the PCIe core and the PCI core are all connected with the processing module;
the signal connection area comprises a synchronous clock signal connection area, a trigger signal connection area, a PCIe bus signal connection area and a PCI bus signal connection area; wherein the content of the first and second substances,
the PCI core is connected with a PCI bus signal connection area through a PCIe bus and a level conversion chip;
one end of the PXI bus is connected with the trigger signal connection area and the PCI bus signal connection area respectively, and the other end of the PXI bus is connected with the trigger control logic module and the PCI core respectively;
one end of the PXIe bus is respectively connected with the synchronous clock signal connection area, the trigger signal connection area and the PCIe bus signal connection area, and the other end of the PXIe bus is respectively connected with the synchronous clock control module, the trigger control logic module and the PCIe core;
when the connector is pressed on the PCI bus signal connection area, the bus board card is suitable for a CPCI chassis slot;
when the connector is in pressure joint on the synchronous clock signal connecting area and the trigger signal connecting area and is in pressure joint on the PCI bus signal connecting area, the bus board card is suitable for a PXI case slot;
when the connector is in a pressure joint on the synchronous clock signal connection area and the trigger signal connection area and in a pressure joint on the PCIe bus signal connection area, the bus board card is suitable for PXIe case slots.
2. The FPGA bus board card suitable for various chassis slots of claim 1, characterized in that: the signal connection area all sets up the homonymy at PCB board tip, and synchronous clock signal connection area, trigger signal connection area, PCIe bus signal connection area and PCI bus signal connection area set gradually from last to down.
3. The FPGA bus board card applicable to various chassis slots of claim 1, wherein: the signal connection area is a jack matched with the connector pin.
4. The FPGA bus board card suitable for various chassis slots of claim 1, characterized in that: the level conversion chip is used for converting the PCI signal of 3.3V or 5V into the PCI signal of 3.3V.
CN202211276756.XA 2022-10-19 2022-10-19 FPGA bus board card suitable for multiple case slots Pending CN115509979A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202211276756.XA CN115509979A (en) 2022-10-19 2022-10-19 FPGA bus board card suitable for multiple case slots

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202211276756.XA CN115509979A (en) 2022-10-19 2022-10-19 FPGA bus board card suitable for multiple case slots

Publications (1)

Publication Number Publication Date
CN115509979A true CN115509979A (en) 2022-12-23

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN202211276756.XA Pending CN115509979A (en) 2022-10-19 2022-10-19 FPGA bus board card suitable for multiple case slots

Country Status (1)

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