CN115509969A

CN115509969A - Storage control circuit between multiple chips

Info

Publication number: CN115509969A
Application number: CN202211201932.3A
Authority: CN
Inventors: 蒋忠平
Original assignee: Shanghai Lianying Microelectronics Technology Co ltd
Current assignee: Shanghai Lianying Microelectronics Technology Co ltd
Priority date: 2022-09-29
Filing date: 2022-09-29
Publication date: 2022-12-23

Abstract

The utility model relates to a storage control circuit between multicore piece, through all being connected a plurality of processing chips with memory chip, mutual transmission indicator signal through the general input/output interface between a plurality of processing chips, accomplish the access authority control of a plurality of processing chips to memory chip, can guarantee a plurality of reasonable orderly sharing memory chip of processing chip, realize that a memory chip provides data for a plurality of processing chips, can only adopt a packaging substrate when carrying out chip package, and because a plurality of processing chips share a memory chip, can reduce the quantity of packaging chip on the packaging substrate, under the circumstances that guarantees to provide equivalent function, reduce the encapsulation volume.

Description

Storage control circuit between multiple chips

Technical Field

The application relates to the technical field of communication, in particular to a storage control circuit between multiple chips.

Background

With the development of wireless technology, more and more off-chip communication devices support bluetooth functionality. Increase the bluetooth chip in traditional audiphone for audiphone has bluetooth transmission function, and audio data in the smart machine can be through during bluetooth transmits to the audiphone, the accuracy of the audio data that the guarantee audiphone received. In the bluetooth hearing aid, because the digital signal processing chip and the bluetooth chip do not have memories therein, and cannot directly store algorithm programs, and both require an off-chip storage unit to place programs and applications, in the related art, the bluetooth hearing aid has 4 chip bare chips, and both the digital signal processing chip bare chip and the bluetooth chip bare chip have corresponding FLASH memories. When the hearing aid is packaged, the digital signal processing chip bare chip and the corresponding FLASH memory bare chip are packaged for one time, the Bluetooth chip bare chip and the corresponding FLASH memory bare chip are packaged for one time, and then the Bluetooth hearing aid is packaged for the third time integrally, so that the Bluetooth hearing aid is large in size and inconvenient for a patient to use.

Disclosure of Invention

In view of the above, it is desirable to provide a memory control circuit between multiple chips with small size and low package cost, which includes:

a memory chip;

the system comprises a first processing chip and a second processing chip, wherein a general input/output interface of the first processing chip is connected with a general input/output interface of the second processing chip;

the first control unit is connected between the serial peripheral output interface of the first processing chip and the serial peripheral input interface of the storage chip;

the second control unit is connected between the serial peripheral output interface of the second processing chip and the serial peripheral input interface of the storage chip;

the serial peripheral output interface of the memory chip is respectively connected with the serial peripheral input interfaces of the first processing chip and the second processing chip;

in one embodiment, the first control unit controls a path connection state between the serial peripheral output interface of the first processing chip and the serial peripheral input interface of the memory chip based on an indication signal mutually transmitted between the general input/output interface of the first processing chip and the general input/output interface of the second processing chip; the second control unit controls the path connection state between the serial peripheral output interface of the second processing chip and the serial peripheral input interface of the memory chip based on the indication signal mutually transmitted between the general input/output interface of the first processing chip and the general input/output interface of the second processing chip.

In one embodiment, the first control unit comprises a first type of tri-state buffer, and the second control unit comprises a second type of tri-state buffer;

the input end of the first type of tri-state buffer is connected with the serial peripheral output interface of the first processing chip, the enabling end of the first type of tri-state buffer is connected with the universal input/output interface of the first processing chip, and the output end of the first type of tri-state buffer is connected with the serial peripheral input interface of the memory chip;

the input end of the second type tri-state buffer is connected with the serial peripheral output interface of the second processing chip, the enabling end of the second type tri-state buffer is connected with the universal input/output interface of the second processing chip, and the output end of the second type tri-state buffer is connected with the serial peripheral input interface of the memory chip;

under the condition that the general input/output interface of the first processing chip transmits a first type of indication signal to the general input/output interface of the second processing chip, the first type of three-state buffer is in a conducting state, and the second type of three-state buffer is in a blocking state;

and under the condition that the general input/output interface of the first processing chip transmits a second type of indication signal to the general input/output interface of the second processing chip, the first type of tri-state buffer is in a blocking state, and the second type of tri-state buffer is in a conducting state.

In one embodiment, the method further comprises the following steps:

and the two NOT gates are connected between the enabling end of the first type of three-state buffer and the general input/output interface of the first processing chip in series.

the input end and the enabling end of the first type of tri-state buffer are both connected with the serial peripheral output interface of the first processing chip, and the output end of the first type of tri-state buffer is connected with the serial peripheral input interface of the storage chip;

the input end and the enabling end of the second type of tri-state buffer are both connected with the serial peripheral output interface of the second processing chip, and the output end of the second type of tri-state buffer is connected with the serial peripheral input interface of the memory chip;

when the general-purpose input/output interface of the first processing chip transmits a first type of indication signal to the general-purpose input/output interface of the second processing chip, the first type of indication signal indicates the serial peripheral output interface of the second processing chip to output a blocking signal so as to indicate that the second type of tri-state buffer is in a blocking state;

and under the condition that the general input/output interface of the second processing chip transmits a second type of indication signal to the general input/output interface of the first processing chip, the second type of indication signal indicates the serial peripheral output interface of the first processing chip to output a blocking signal so as to indicate that the first type of tri-state buffer is in a blocking state.

In one embodiment, the device further comprises a first pull-up resistor;

one end of the first pull-up resistor is connected with the output end of the first type of tri-state buffer and the output end of the second type of tri-state buffer, and the other end of the first pull-up resistor is connected with the power interface of the memory chip.

In one embodiment, the device further comprises a second pull-up resistor;

one end of the second pull-up resistor is connected with a serial peripheral output interface of the memory chip, and the second pull-up resistor is connected with a power interface of the first processing chip or the second processing chip.

In one embodiment, the method further comprises the following steps:

and the third type of tri-state buffer is connected between one end of the second pull-up resistor and the serial peripheral output interface of the memory chip.

In one embodiment, at the time of initial power-on of the first processing chip, the general purpose input/output interface of the first processing chip transmits a first type of indication signal; the first type of indication signal is used for indicating that the connection state of a path between the serial peripheral output interface of the second processing chip and the serial peripheral input interface of the storage chip is a blocking state.

The application provides hearing-aid equipment which is characterized by comprising a hearing-aid chip, wherein the hearing-aid chip is obtained by packaging based on a first processing chip, a second processing chip and a storage chip;

the first processing chip is a digital signal processing chip bare chip; or, the second processing chip is a bluetooth chip bare chip; alternatively, the memory chip is a flash memory chip bare chip.

The storage control circuit between the multiple chips is connected with the storage chips through the multiple processing chips, the indication signals are transmitted through the universal input/output interfaces between the multiple processing chips, the access authority control of the multiple processing chips on the storage chips is completed, the storage chips can be shared reasonably and orderly by the multiple processing chips, the storage chips can provide data for the multiple processing chips, only one packaging substrate can be adopted when the chips are packaged, the storage chips are shared by the multiple processing chips, the number of the packaging chips on the packaging substrate can be reduced, and the packaging volume is reduced under the condition that the same functions are guaranteed to be provided.

Drawings

FIG. 1 is a schematic diagram of a memory control circuit between multiple chips in one embodiment;

FIG. 2 is a schematic diagram of an SPI interface in one embodiment;

FIG. 3 is a diagram of a memory control circuit between multiple chips according to another embodiment;

FIG. 4 is a timing diagram illustrating the transmission of clock signals for an inter-chip memory control circuit according to another embodiment;

FIG. 5 is a diagram illustrating a memory control circuit between multiple chips according to another embodiment;

FIG. 6 is a timing diagram illustrating the transmission of clock signals in an inter-chip memory control circuit according to another embodiment.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein, but rather should be construed as broadly as the present invention is capable of modification in various respects, all without departing from the spirit and scope of the present invention.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or to implicitly indicate the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.

In the present invention, unless otherwise explicitly stated or limited, the terms "mounted," "connected," "fixed," and the like are to be construed broadly, e.g., as being permanently connected, detachably connected, or integral; the connection can be mechanical connection, electrical connection or communication; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood according to specific situations by those of ordinary skill in the art.

With the development of wireless technology, more and more off-chip communication devices support bluetooth functionality, for example, bluetooth functionality is added to hearing aids, and audio signals in a patient smart device can be directly transmitted to the hearing aids through bluetooth transmission technology, so that a patient can hear sounds. Specifically, a System In a Package SIP (System In a Package) or a Die stack may be adopted, and the digital signal processing chip and the bluetooth chip In the hearing aid may be packaged together into one chip. In the existing bluetooth hearing aid, the digital signal processing chip has a corresponding memory chip, and the bluetooth chip also has a corresponding memory chip, but because the applications in the hearing aid are more and more, the algorithm is more and more complex, and the programs to be stored are more and more, the larger off-chip storage is needed to place the data processing program of the digital signal processing chip and the data processing program of the bluetooth chip. Therefore, after the digital processing chip and the storage chip thereof, the Bluetooth chip and the storage chip thereof are packaged, the hearing aid has a larger volume, and the use feeling of a patient is further influenced.

Referring to fig. 1, an embodiment of the present application provides a multi-chip memory control circuit, which can solve the above technical problem, and the circuit includes:

a memory chip 100;

a first processing chip 200 and a second processing chip 300, wherein the general-purpose input/output interface 210 of the first processing chip is connected with the general-purpose input/output interface 310 of the second processing chip;

a first control unit 400, wherein the first control unit 400 is connected between the serial peripheral output interface 220 of the first processing chip and the serial peripheral input interface 110 of the memory chip;

and a second control unit 500, wherein the second control unit 500 is connected between the serial peripheral output interface 320 of the second processing chip and the serial peripheral input interface 110 of the memory chip;

the serial peripheral output interface 120 of the memory chip is connected with the serial

peripheral input interfaces

230 and 330 of the first processing chip and the second processing chip respectively;

the first processing chip 200 and the second processing chip 300 are both internal Read-Only memories (ROMs), and cannot directly store the application program and data in the internal processing chips. The first processing chip 200 and the second processing chip 300 both have a general input/output interface, such as an I/O pin, and further include a serial peripheral interface SPI, and the first processing chip 200 and the second processing chip 300 specifically include a clock pin CLK, a chip select pin CS, a data output pin DO, and a data input pin DI, and can communicate with other chips to obtain data. In the present application, for the first processing chip 200, the serial peripheral output interface 220 includes a clock pin CLK, a chip select pin CS, and a data output pin DO, and the serial peripheral input interface 230 includes a data input pin DI.

The memory chip 100 is a chip capable of modifying internal data of the chip by a specific program and communicating data stored in the chip with other chips, for example, a FLASH chip, and is connected to the first processing chip 200 and the second processing chip 300 through an SPI interface in the FLASH chip to provide an application program for the first processing chip 200 and the second processing chip 300. Specifically, the SPI interface in the FLASH chip includes a clock pin CLK, a chip select pin CS, a data output pin DO, and a data input pin DI, in this embodiment, the serial peripheral input interface 110 of the memory chip includes a clock pin CLK, a chip select pin CS, and a data input pin DI, and the serial peripheral output interface 120 of the memory chip includes a data output pin DO.

In one embodiment, the first control unit 400 controls a path connection state between the serial peripheral output interface 220 of the first processing chip and the serial peripheral input interface 110 of the memory chip based on an indication signal mutually transmitted between the general input/output interface 210 of the first processing chip and the general input/output interface 310 of the second processing chip; the second control unit 500 controls a path connection state between the serial peripheral output interface 320 of the second processing chip and the serial peripheral input interface 110 of the memory chip based on the indication signal mutually transmitted between the general input/output interface 210 of the first processing chip and the general input/output interface 310 of the second processing chip.

Specifically, in one embodiment, the first Processing chip 200 may be a Digital Signal Processing DSP (Digital Signal Processing) chip, and when the DSP works, the application program needs to be loaded into the DSP chip for execution through a loading operation, and the DSP chip includes an SPI interface. The memory chip 100 may be a FLASH chip. The connection relationship between the DSP chip and the FLASH chip is shown in FIG. 2. The second processing chip 300 may be a bluetooth chip, and pin connections of the bluetooth chip and the memory chip are consistent with those of the DSP chip.

The first processing chip 200 and the second processing chip 300 both have a general purpose input/output interface, such as an I/O pin, and for the first processing chip 200, the access right of the chip to the memory chip is notified to the second processing chip through the I/O pin, and the access right requirement of the second processing chip to the memory chip is obtained. That is, the I/O pin of the first processing chip is connected to the I/O pin of the second previous processing chip, and the I/O pins transmit the indication signal to each other, so as to determine the access right of the first processing chip and the second processing chip to the memory chip.

Specifically, for example, the first processing chip 200 is a DSP chip, the second processing chip 300 is a bluetooth chip, the GPIO port of the DSP chip is connected to the GPIO port of the bluetooth chip, when the DSP chip obtains the access right of the SPI interface of the memory chip, the DSP chip obtains that the GPIO port output is 0, at this time, the GPIO port input of the bluetooth chip is 0, then the bluetooth chip does not have the access right of the SPI interface of the memory chip, and the SPI interface of the bluetooth chip does not operate. It should be noted that the SPI interface of the bluetooth chip may not operate in an external casting manner, so that the output of the SPI interface of the bluetooth chip may not be input to the SPI interface of the memory chip, and the output of the SPI interface of the bluetooth chip may also be set to a fixed value, so that it may not affect data transmission between the SPI interface of the DSP chip and the SPI interface of the memory chip. And when the bluetooth chip needs to obtain the access right of the SPI interface of the memory chip, the GPIO port through the bluetooth chip transmits a request signal to the GPIO port of the DSP chip, and after the DSP chip acquires the request of the bluetooth chip, under the condition that the SPI interface of the memory chip is not accessed, the GPIO port through the DSP chip informs the bluetooth chip, namely, the output of the GPIO port of the DSP chip can be set to be 1 at the moment, and the bluetooth chip acquires the access right of the SPI interface of the memory chip at the moment.

It should be noted that the general input/output interfaces of the first processing chip 200 and the second processing chip 300 are used for determining the access rights of the two chips to the memory chip, so as to avoid access conflicts, and the memory chip cannot respond to the access requirements of the two chips at the same time. The access authority of the serial peripheral input interface 110 of the memory chip can be determined by controlling and monitoring the state of the general purpose input output interface through Firmware of the respective chips of the first processing chip 200 and the second processing chip 300.

The first control unit 400 is used for determining whether the first processing chip 200 can access the serial peripheral input interface 110 of the memory chip according to the states of the general input/output interface 210 of the first processing chip and the general input/output interface 310 of the second processing chip. Similarly, the second control unit 500 is used for determining whether the second processing chip 300 can access the serial peripheral interface 110 of the memory chip according to the states of the general input/output interface 210 of the first processing chip and the general input/output interface 310 of the second processing chip.

The indication signal mutually transmitted between the general-purpose input/output interface 210 of the first processing chip and the general-purpose input/output interface 310 of the second processing chip may directly act on the first control unit 400/the second control unit 500, so that the first processing chip 200/the second processing chip 300 cannot access the serial peripheral interface 110 of the memory chip, or may control the output of the serial peripheral output interface of the first processing chip according to the indication signal, so that the output data cannot be transmitted to the serial peripheral interface 110 of the memory chip after passing through the first control unit.

In the circuit provided by the above embodiment, the processing chips are all connected with the memory chip, the indication signals are transmitted through the general input/output interfaces among the processing chips, the access authority control of the processing chips on the memory chip is completed, a memory chip can be shared by the processing chips reasonably and orderly, data can be provided for the processing chips by the memory chip, only one packaging substrate can be adopted when the chips are packaged, and the number of the packaging chips on the packaging substrate can be reduced because the processing chips share the memory chip, the packaging volume is reduced and the packaging cost is reduced under the condition that the same function is ensured to be provided.

and under the condition that the general input/output interface of the first processing chip transmits a second type of indication signal to the general input/output interface of the second processing chip, the first type of three-state buffer is in a blocking state, and the second type of three-state buffer is in a conducting state.

It can be understood that the first control unit 400 and the second control unit 500 are used in the circuit to control the on/off of the circuit according to the indication signal transmitted between the general-purpose input/output interface of the first processing chip and the general-purpose input/output interface of the second processing chip, and therefore, a tri-state buffer can be used. The tri-state output of the tri-state buffer is controlled by the enable terminal, when the enable terminal input is valid, the device realizes normal logic state output (logic 0, logic 1), when the enable input is invalid, the output is in a high-impedance state, namely equivalent to disconnection with a connected circuit. The relationship between the input and output of the tri-state buffer from three ports can be divided into the following four types: low effective raw code output, high effective raw code output, low effective complement output, and high effective complement output. In this embodiment, as long as it can be ensured that the first processing chip and the second processing chip do not store the data in the conflict when accessing the memory chip, and the transmission logic is ensured to be correct, the first type tri-state buffer and the second type tri-state buffer may be of the same type or different types.

For example, in an embodiment, referring to fig. 3, taking the first processing chip 200 as a DSP chip and the second processing chip 300 as a bluetooth chip as an example, the first type of tri-state buffer adopts a low-activity native code output tri-state buffer, and the second type of tri-state buffer adopts a high-activity tri-state buffer. The memory chip 100 may be a FLASH chip. The enabling end of the low-effective original code output three-state buffer and the enabling end of the high-effective three-state buffer are both controlled by a universal input/output pin of the DSP chip, when the DSP accesses an SPI interface of the FLASH chip, the universal input/output pin of the DSP chip outputs a low level, at the moment, the output end of the buffer outputting the low-effective original code for three days is consistent with the level of the input end, and the high-effective three-state buffer is in a high-resistance state, namely the input of the SPI input pin of the FLASH chip is consistent with the output of the SPI output pin of the DSP chip; and when the bluetooth chip has the access right, the general purpose input/output pin of the DSP chip outputs the high level, at this moment, the output end of the buffer for three days of outputting the high effective primitive code is consistent with the input end level, the low effective tri-state buffer is in the high impedance state, i.e. the input of the SPI input pin of the FLASH chip is consistent with the output of the SPI output pin of the bluetooth chip. In detail, referring to fig. 4, taking a clock signal in the SPI interface as an example, the timing diagram provided in fig. 4 can clearly illustrate the access situation of the first processing chip and the second processing chip to the memory chip.

In the circuit provided by the above embodiment, the tri-state buffer is directly connected to the general input/output interface of the first processing chip, and the indication signal transmitted between the general input/output interface of the first processing chip and the general input/output interface of the second processing chip can indicate the access conditions of the first processing chip and the second processing chip to the memory chip, so that the working state of the tri-state buffer is directly controlled by the indication signal, the output terminal is allowed to reach the output terminal when the enable is valid, the high impedance state is realized when the enable is invalid, and the access and data reading of the SPI interface of the memory chip by the first processing chip and the second processing chip can be quickly switched.

In one embodiment, the circuit further comprises:

Referring to fig. 3, the first type of tri-state buffer and the second type of tri-state buffer have different types, and when they correspond to the same indication signal, the operating states of the first type of tri-state buffer and the second type of tri-state buffer are different. In the circuit of fig. 3, the enable terminal of the first type of tri-state buffer and the enable terminal of the second type of tri-state buffer are both directly connected to the GPIO0 pin of the first processing chip, and there is no isolation device between the first type of tri-state buffer and the second type of tri-state buffer, which may cause a short circuit risk, so that two not gates may be added between the enable terminal of the first type of tri-state buffer and the general input/output interface of the first processing chip.

Through increasing redundant NOT gate, can keep apart between a plurality of devices, avoid the interact between a plurality of devices, protection circuit that can be better.

As can be seen from the above explanation, when the enable terminal of the first type of tri-state buffer and the enable terminal of the second type of tri-state buffer are directly connected to the general input/output interface of the first processing chip, the tri-state buffer is directly controlled by the indication signal output between the general input/output interface of the first processing chip and the general input/output interface of the first processing chip, so as to implement whether the first processing chip or the second processing chip can normally access the SPI interface of the memory chip. In this embodiment, the enabling end of the first type of tri-state buffer and the enabling end of the second type of tri-state buffer are both connected to their respective input ends, and the control unit in each processing chip controls the output condition of its SPI interface by determining the indication signal in the first processing chip and the second processing chip, so as to achieve access control on the SPI interface of the memory chip.

For example, the first type of tri-state buffer and the second type of tri-state buffer are both of a low-effective original code output type, so when the indication signal indicates that the first processing chip accesses the memory chip, the second processing chip sets the output of the SPI interface thereof to a high level according to the indication signal, and at this time, the second type of tri-state buffer is in a high impedance state and cannot transmit the signal to the memory chip; similarly, when the second processing chip accesses the memory chip, the first processing chip sets the output of the SPI interface of itself to a high level based on the indication signal.

In the circuit provided by the embodiment, the enable end of the tri-state buffer is directly connected with the input end, so that the connection complexity of external pins of the chip is reduced, and the circuit assembly and the packaging among multiple chips are facilitated. And the output of the chip pin is controlled by an internal logic judgment mode, so that the influence of circuit damage on the chip can be reduced.

In one embodiment, the device further comprises a first pull-up resistor;

It should be noted that, in the circuit provided in the foregoing embodiment, there is a case where the serial peripheral output interfaces of the first processing chip and the second processing chip are output, and the first-type tri-state buffer and the second-type tri-state buffer are in a high-resistance state, at this time, the serial peripheral input interface of the memory chip is in an open circuit, that is, the SPI pin of the memory chip is in a floating state, so that a pull-up resistor needs to be provided to ensure that the serial peripheral input interface of the memory chip is at a high level.

In one embodiment, the device further comprises a second pull-up resistor;

Similarly, when the serial peripheral input interface of the first processing chip and the serial peripheral input interface of the second processing chip are in a suspended state, the serial peripheral input interface of the first processing chip and the serial peripheral input interface of the second processing chip need to be in a high level state through a pull-up resistor.

In one embodiment, the method further comprises the following steps:

It should be noted that, in an actual application scenario, when there is an inconsistency in the interface levels between the first processing chip and the memory chip, the pull-up resistor must be used to ensure that each input interface can be in a high level state.

Specifically, referring to fig. 5, in a specific embodiment, the first processing chip 200 is a DSP chip, the second processing chip 300 is a bluetooth chip, the memory chip 100 is an 8M bits FLASH chip, and an interface level of the FLASH chip is not consistent with interface levels of the DSP chip and the bluetooth chip; the first type of tri-state buffer adopts a low-effective original code output tri-state buffer, and the second type of tri-state buffer adopts a low-effective tri-state buffer.

Because the interface level of the FLASH chip is inconsistent with the interface levels of the DSP chip and the Bluetooth chip, the output of the SPI interface of the DSP chip and the Bluetooth chip needs to be adjusted to be an open-drain output structure at the moment, and the output of the SPI interface of the DSP chip or the Bluetooth chip can be received by the FLASH chip in an original state through a pull-up resistor.

It should be noted that, in the circuit in fig. 5, for example, the DSP chip has the access right of the SPI interface of the FLASH chip, the SPI interface outputs of the bluetooth chip are all high levels, and at this time, the second-class tri-state buffers are all in a high impedance state, and cannot access the SPI interface of the FLASH chip. The SPI interface output structure of the DSP chip is open-drain output, at the moment, if the output is low level, the enabling end of the first type of tri-state buffer is effective, the output is the same as the input, namely the input of the SPI interface of the FLASH chip is also low level; if the output is high level, the enabling end of the first type of tri-state buffer is invalid and is in a high resistance state, and at the moment, the level of an SPI (serial peripheral interface) pin of the FLASH chip is pulled to be high level through a pull-up resistor.

It will be appreciated that, based on the design of the open-drain output structure and the pull-up resistor operating principle, the pull-up resistor "pulls up" the input voltage signal "weakly" on the wire to which it is connected if the external component is not enabled. When external components are not connected, the external "look" is high impedance to the input. At this time, the voltage at the input port can be pulled up to a high level by the pull-up resistor. If the external component is enabled, it will remove the high level set by the pull-up resistor. That is, in this embodiment, although the pull-up resistor is connected, the output of the SPI interface of the DSP chip is at a low level, which is a determination signal, and at this time, the pull-up resistor will not affect the low level.

In addition, for the SPI interface input of the FLASH chip, the corresponding pull-up resistor needs to be connected to the power supply of the FLASH chip, so that it can meet the high level setting of the FLASH chip. For example, the pin of the FLASH chip needs to reach 3.3V to be identified as high level, and if the pull-up resistor cannot meet the requirement, the pin of the FLASH chip cannot determine that the input is high level.

For the circuit in fig. 5, which implements a storage control process between multiple chips, see fig. 6 in detail, taking a clock signal in an SPI interface as an example, the timing diagram provided in fig. 6 can clearly illustrate the access situation of the first processing chip and the second processing chip to the storage chip.

It should be noted that, in fig. 4 and fig. 6, in Stage2 and Stage4, the high-low level of GPIO0 is not consistent with the high-low level of GPIO1 at this time, which indicates that the access authority of the first processing chip is being adjusted, and at this time, the SPI interface of the memory chip has no access, that is, the memory chip does not respond.

The circuit provided in the above embodiment can solve the problem of inconsistent interface levels between the multi-chip and the memory chip by changing the output structure of the chip pin and increasing the pull-up resistance.

In one embodiment, the first processing chip and the second processing chip each include a plurality of general purpose input/output interfaces; and a data path for mutual data transmission is formed between the two through respective universal input/output interfaces.

It should be noted that, the gpio interface belongs to a full-duplex operating mode, and therefore, when the indication signal between the first processing chip and the second processing chip is transmitted, one gpio interface may be used, and a plurality of gpio interfaces may also be used to ensure the correctness of the indication signal and the correctness of the indication signal by the processing chip, but the indication signals between the plurality of gpio interfaces have a certain correlation, and the common function of the multiple gpio interfaces is to determine the access rights of the plurality of processing chips to the storage chip, thereby avoiding the situation of multi-chip access conflicts, and the correlation of the indication signal between the plurality of gpio interfaces is not specifically limited in this embodiment, and can be flexibly adjusted according to the actual application scenario.

For a bluetooth hearing aid, the first processing chip is a DSP chip, the second processing chip is a bluetooth chip, and the DSP chip is in a leading position between the two chips, so after the system is powered on, the DSP chip with the initial access right is set, that is, after the system is powered on initially, the gpio interface of the first processing chip transmits the first type of indication signal, for example, the gpio interface output of the first processing chip is 0, and for the bluetooth chip, the access right is only provided when 1 is received.

In one embodiment, the hearing aid device is characterized by comprising a hearing aid chip, wherein the hearing aid chip is packaged based on a first processing chip, a second processing chip and a memory chip;

the first processing chip is a digital signal processing chip bare chip; or the second processing chip is a Bluetooth chip bare chip; alternatively, the memory chip is a flash memory chip die.

The DIE is a small unit of a silicon wafer, and includes a single chip with a complete design and a partial scribe line region of the chip adjacent to the horizontal and vertical directions, and the DIE is cut from the wafer. In this embodiment, the digital signal processing Chip bare Chip DSP SOC DIE, the bluetooth Chip bare Chip Blue SOC DIE, and the FLASH memory Chip bare Chip FLASH DIE are bare chips that are not packaged, and the Hearing Aid Chip is obtained by packaging the three dice.

In the hearing aid chip, the connection circuit among the first processing chip, the second processing chip and the memory chip includes the above-described inter-chip memory control circuit, and the first processing chip and the second processing chip share the memory chip.

Claims

1. An inter-chip memory control circuit, comprising:

a memory chip;

and the serial peripheral output interface of the memory chip is respectively connected with the serial peripheral input interfaces of the first processing chip and the second processing chip.

2. The circuit of claim 1, wherein the first control unit is configured to control a path connection status between the spi of the first processing chip and the spi of the memory chip via an indication signal mutually transmitted between the gpio interface of the first processing chip and the gpio interface of the second processing chip; the second control unit is used for controlling the access connection state between the serial peripheral output interface of the second processing chip and the serial peripheral input interface of the memory chip through the indication signals mutually transmitted between the general input/output interface of the first processing chip and the general input/output interface of the second processing chip.

3. The circuit of claim 1, wherein the first control unit comprises a first type of tri-state buffer, and the second control unit comprises a second type of tri-state buffer;

4. The circuit of claim 3, further comprising:

5. The circuit of claim 1, wherein the first control unit comprises a first type of tri-state buffer, and the second control unit comprises a second type of tri-state buffer;

the input end and the enabling end of the second type tri-state buffer are both connected with the serial peripheral output interface of the second processing chip, and the output end of the second type tri-state buffer is connected with the serial peripheral input interface of the storage chip;

6. The circuit of claim 5, further comprising a first pull-up resistor;

7. The circuit of claim 5 or 6, further comprising a second pull-up resistor;

8. The circuit of claim 7, further comprising:

9. The circuit of claim 1, wherein at an initial power-up time of the first processing chip, the general purpose input output interface of the first processing chip transmits a first type of indication signal; the first type of indication signal is used for indicating that the connection state of a path between the serial peripheral output interface of the second processing chip and the serial peripheral input interface of the storage chip is a blocking state.

10. The hearing-aid equipment is characterized by comprising a hearing-aid chip, wherein the hearing-aid chip is packaged based on a first processing chip, a second processing chip and a storage chip;

the first processing chip is a digital signal processing chip bare chip; or, the second processing chip is a bluetooth chip bare chip; or the memory chip is a flash memory chip bare chip.