CN115495909A - Aging prediction modeling method suitable for DRAM peripheral transistor under any stress condition in on state - Google Patents

Aging prediction modeling method suitable for DRAM peripheral transistor under any stress condition in on state Download PDF

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CN115495909A
CN115495909A CN202211162708.8A CN202211162708A CN115495909A CN 115495909 A CN115495909 A CN 115495909A CN 202211162708 A CN202211162708 A CN 202211162708A CN 115495909 A CN115495909 A CN 115495909A
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纪志罡
王达
王润声
任鹏鹏
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Shanghai Jiaotong University
Beijing Superstring Academy of Memory Technology
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Abstract

The invention discloses an aging prediction modeling method suitable for a DRAM peripheral transistor under any stress condition of an on state. According to the leading stress areas of different types of defects, data are extracted from the leading stress areas of the defects to determine corresponding parameters of the defects Nit1, not-e, not-h and Nit2, all the obtained parameters are integrated and input into any stress condition, and the aging amount of the device under the condition at any time can be obtained. The invention can carry out integral calibration and parameter value fine adjustment with all experimental data, so that the consistency of the model and the experimental data is optimal. The invention can realize the prediction of the long-time aging of the device under different stress conditions of the on state (different Vg/Vd combinations). The method has the advantages of high reliability, good prediction accuracy, strong practicability and the like.

Description

Aging prediction modeling method suitable for DRAM peripheral transistor under any stress condition in on state
Technical Field
The invention relates to the technical field of DRAM peripheral devices, in particular to an aging prediction modeling method suitable for DRAM peripheral transistors under any stress condition in an on state.
Background
With the continuous decline of process nodes, the problem of device leakage becomes more serious. Under the current sub-20 nm DRAM process, various large DRAM manufacturers introduce high dielectric constant (high-k) materials onto the transistor gate oxide layer to suppress the leakage problem of the device. But with the introduction of a large number of gate oxide layer defects and the introduction of a large number of Si-H bonds during the annealing process, the Hot Carrier Degradation (HCD) phenomenon of the device is deteriorated. In addition, although the operating voltage of the DRAM is decreasing, in order to have a larger driving capability when the transistor is turned on, a high voltage such as 3V needs to be generated internally, which requires a thick oxygen device to perform the corresponding function. In recent years, serious HCD phenomenon on a thick oxygen device under a sub-20 nm process is reported in disputes of Mars, and Meiguan at abroad DRAM, and then serious HCD phenomenon is discovered on a thick oxygen PMOS by Changxin DRAM manufacturers at home. It is therefore desirable to predict the long term aging of the HCD phenomenon.
Current aging models for sub-20 nm DRAM processes include a defect-based physical model proposed by heirlich in 20 years (Seung-Geun Jung published in EDL) and a mathematical model used by samsung in 21 years (d.son published in IRPS) that only considers aging time. But the former only stays at the physical mechanism level, and does not establish a corresponding mathematical model to realize the aging prediction of the device; the latter considers the influence of aging time only under a specific stress voltage (Vg =0.5 Vd), and cannot be expanded to the whole stress voltage region for use. Although a complete aging model can be used in the logic device, the aging rules are different due to the difference of defect types in the DRAM prepared by the gate-first process and the logic device prepared by the traditional gate-last process, and the model proposed on the traditional logic device cannot be directly put into the DRAM device for use.
In summary, the prior art cannot achieve a better prediction effect on the DRAM peripheral device PMOS yet, and needs a complete HCD model to accurately predict the long-term degradation caused by HCD of the DRAM peripheral device at any turn-on voltage.
Disclosure of Invention
Aiming at the problems in the prior art, the invention provides an aging prediction modeling method suitable for a DRAM peripheral transistor under any stress condition in an on state.
The technical scheme provided by the invention is as follows:
a aging prediction modeling method suitable for DRAM peripheral transistors under any stress condition of an on state comprises the following steps:
1) Dividing all possible working voltage areas of the DRAM peripheral transistor into stress areas with different defect type dominance according to all possible defect types in a grid oxide layer of the DRAM peripheral transistor and the influence of various defects on the device when different voltages are applied to the device, and establishing a physical model of threshold voltage degradation of the device caused by different defects;
2) Selecting a plurality of groups of different V in the stress regions with different defect types as the main factors D /V G Data under high electric field stress conditions, in which the voltage | V is leaked D Or gate voltage V G If the absolute value is greater than the typical working voltage by 3V, determining model fitting parameter values representing corresponding defects in the region by realizing the coincidence of the model prediction effect and the actually measured data, and obtaining threshold voltage offset generated by different defect types under any voltage and any working time;
3) Integrating a calculation formula for representing the magnitude of the threshold voltage degradation caused by all defect types to obtain a complete aging model at a low temperatureUnder electric field stress, i.e. leakage pressure | V D Sum gate voltage | V G I is less than or equal to the typical working voltage of 3V, and the effect of the device threshold voltage degradation calculated by the verification model is matched with the actually measured experimental data;
4) Inputting V under any open-state condition by using the aging model obtained in the step 3) D /V G Stress and aging time of any duration, wherein the gate voltage | V under on-state conditions G If | is greater than the threshold voltage 0.85V, the degradation of the device under the condition can be predicted.
Further, the high electric field region of the DRAM peripheral transistor is divided into: the interface state defect Nit1 is used for leading a device aging Region1, an oxide layer electron trap Not-e is used for leading a device aging Region2, an oxide layer hole trap Not-h is used for leading a device aging Region3, and the interface state defect Nit2 is used for leading a device aging Region4;
selecting several different sets of V in region1 D /V G Substituting the data under the stress condition into a formula (1) of the defect Nit1, and determining corresponding fitting parameters A through experimental data 1 、B 1 、C 1 The value of (A) is as follows:
Figure BDA0003860800670000021
where t is the time of application of the stress, V G And V D Representing applied gate and drain stress, n 1 Is defect N it1 Time constant of (1), Δ V th_Nit1 Represents by N it1 The resulting threshold voltage offset;
determining Not-e, modeling by adopting a tensile index model, and selecting a plurality of groups of different V in region2 D /V G Substituting the data under the stress condition into corresponding formulas (2), (3) and (4) of the defect Not-E, and determining the values of corresponding fitting parameters E, p and q through experimental data; ,
ΔV th_Not-e ＝D{1-exp[-(t/τ) β ]} (2)
in the formula (2), D represents the total density of the defect Not-e, and τ represents the time constant of the defectNumber, beta, reflects the width of the distribution of the defect type, t is the time of application of the stress, Δ V th_Not-e Representing the shift in threshold voltage due to Not-e, D and τ, respectively, correspond to the following equations:
D＝E 1 exp(p 1 V G )exp(q 1 V D ) (3)
τ＝E 2 exp(p 2 V G )exp(q 2 V D ) (4)
V G and V D Representing applied gate and drain stress;
selecting several different sets of V in region3 D /V G Substituting the data under stress condition into formula (5) of the defect Not-h, and determining corresponding fitting parameter A by experimental data 2 、B 2 、C 2 The value of (A) is as follows:
Figure BDA0003860800670000031
wherein t is the time of application of the stress, V G And V D Representing applied gate and drain stress, n 2 Is the time constant, Δ V, of the defect Not-h th_Not-h Represents the threshold voltage shift due to Not-h;
selecting several different sets of V in region4 D /V G Substituting the data under the stress condition into a formula (6) of the defect Nit2, and determining a corresponding fitting parameter A through experimental data 3 、B 3 、C 3 The value of (A) is as follows:
Figure BDA0003860800670000032
where t is the time of application of the stress, V G And V D Representing applied gate and drain stress, n 3 Is the time constant, Δ V, of the defect Nit2 th_Nit2 Represents the threshold voltage offset resulting from Nit 2;
and (3) inputting any VG/VD stress voltage under the on-state condition by adopting the values of all the fitting parameters, and calculating and predicting the Vth degradation amount of the device after any aging time according to a formula (7):
ΔV th ＝ΔV th_Nit1 +ΔV th_Not-h +ΔV th_Not-e +ΔV th_Nit2 (7)
further, considering that region2 has a small amount of defect Nit1 influence, a Nit1 model can be added to region2 to determine the fitting parameters (E, p, q) of Not-E: thus fitting parameter A 1 、B 1 、C 1 The value of (2) is added to the value of (1) in the formula (2).
Further, considering that region3 has a small amount of defect Nit1 influence, a Nit1 model can be added to region3 to determine the fitting parameters (A) of Not-h 2 、B 2 、C 2 ): thus fitting parameter A 1 、B 1 、C 1 The value of (a) is substituted into the formula (1) and added to the formula (5).
Further, considering the effect of Not-h existing in region4, a Not-h model may be added to region4 to determine the corresponding parameter (A) of Nit2 3 、B 3 、C 3 ): thus fitting parameter A 2 、B 2 、C 2 The value of (b) is added to the formula (6) after being substituted into the formula (5).
The invention has the beneficial effects that: the invention can ensure that the method has the advantages of strong operability, easy implementation and utilization on the premise of good prediction precision. When a device under a new process condition is obtained, the aging condition of the long-term device under any stress condition can be predicted only by extracting parameters through multiple groups of measured data according to the established model.
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FIG. 1 is a schematic illustration of various types of defects in a device burn-in process of the present invention;
FIG. 2 is a schematic flow chart of an embodiment of the present invention;
FIG. 3 is a graph comparing the fitting effect of the model of the present invention with measured data, wherein a) is at | V G |<＝|V D Results under the condition of |; b) At | V G |>＝|V D Results under the condition of |;
FIG. 4 is a graph comparing the predicted effect of the model of the present invention with the measured data, wherein a) is at | V G |<＝|V D Results under the condition of |; b) At | V G |>＝|V D Results under the condition of |.
Detailed Description
The invention is further illustrated by the following description of specific embodiments in conjunction with the accompanying drawings.
The model of the invention is completed in a high electric field area; and then, according to the extracted model parameters, the prediction under the condition of a low electric field is realized, and the accuracy of the model can be verified by comparing with an experimental result.
As shown in fig. 1, the present invention divides stress regions where four defects are respectively dominant, and the stress regions are used for respectively determining approximate ranges of model parameters of different defects, so as to avoid the situation that the fitting effect of too many parameters is not good at the same time, and the specific regions are divided as follows:
1) Region1 (0.5 × VD | < | VG | < | VD |): interface state defect Nit1 dominates device aging;
2) Region2 (| VG | < 0.5. Multidot. VD |): oxide layer electron trap Not-e dominates device aging;
3) The Region3 (| VG | > | VD |): oxide layer hole trap Not-h leads the aging of the device;
4) Region4 (| VD | ≈ 0V) interface state defect Nit2 dominates device aging.
And then the overall correction and determination of the parameters are completed. The specific implementation flow is shown in fig. 2, and includes:
1) At least three different groups of V are selected in region1 shown in FIG. 1 D /V G Data under stress, e.g. V D /V G = 1-3.6V/-3.6v (2) -4.0V/-3.6v (3) -3.6V/-3.2V, and the data are substituted into the corresponding formula of the defect Nit1 to determine the value of the corresponding fitting parameter (a) 1 、B 1 、C 1 )：
Figure BDA0003860800670000041
Where t is the time of application of the stress, V G And V D Representing the applied gridElectrode and drain stress, n 1 Is defect N it1 Time constant of A 1 、B 1 、C 1 Are all fitting parameters, Δ V, that need to be extracted through experimental data th_Nit1 Represents by N it1 The resulting threshold voltage offset (in millivolts). The result obtained by data fitting is A 1 ＝1.16e5，B 1 ＝-0.88，C 1 ＝49。
2) At least three different groups V are also selected in region2 shown in FIG. 1 D /V G Data under stress, e.g. V D /V G = 1-3.0V/-1.2v (2) -3.6V/-1.2v (3) -3.6V/-1.8V. Since there is a small amount of defect Nit1 contribution in region2, a Nit1 model can be added to region2 to determine the fit parameters (E, p, q) for Not-E:
Figure BDA0003860800670000052
wherein D represents the total density of defect Not-e, τ represents the time constant of defect Not-e, β reflects the distribution width of defect Not-e (empirical constant, here 0.34), t is the time of applying stress, Δ V th_Not-e Representing the shift in threshold voltage (in millivolts) by Not-e, D and τ in turn correspond to the following equations:
D＝E 1 exp(p 1 V G )exp(q 1 V D )
τ＝E 2 exp(p 2 V G )exp(q 2 V D )
the parameters E, p and q are all fitting parameters needing to be extracted according to actually measured data, V G And V D Representing the applied gate and drain stress. The result obtained after data fitting is E 1 ＝-19.6，p 1 ＝3.4，q 1 ＝-1.83,E 2 ＝8.55e9，p 2 ＝15.7，q 2 ＝0.17。
3) At least three different groups V are also selected in region3 shown in FIG. 1 D /V G Data under stress, e.g. V D /V G ＝①-2.4V/-3.6V②-1.2V/-3.6V③-2.4V/-4.0V. Since region3 also has a small number of defect Nit1 effects, a Nit1 model can also be added to region3 to determine the fit parameters (A) of Not-h 2 、B 2 、C 2 )：
Figure BDA0003860800670000051
Where t is the time of application of the stress, V G And V D Representing applied gate and drain stress, n 2 Is the time constant of defect Not-h, A 2 、B 2 、C 2 Are all fitting parameters, Δ V, that need to be extracted by experimental data th_Not-h Representing the amount of threshold voltage shift (in millivolts) produced by Not-h. The result obtained by data fitting is A 2 ＝1.1，B 2 ＝-0.6，C 2 ＝2.44。
4) At least three different groups of V are also selected in region4 shown in FIG. 1 D /V G Data under stress, e.g. V D /V G 0V/-3.6V (2) = (1). Since there is Not-h effect in region4, it is necessary to add Not-h model to this region to determine the corresponding parameters of Nit2 (A) 3 、B 3 、C 3 )：
Figure BDA0003860800670000053
Wherein t is the time of application of the stress, V G And V D Representing applied gate and drain stress, n 3 Is the time constant of the defect Nit2, A 3 、B 3 、C 3 Are all fitting parameters, Δ V, that need to be extracted by experimental data th_Nit2 Representing the threshold voltage offset due to Nit 2. The result obtained by data fitting is A 3 ＝0.16，B 3 ＝-0.7，C 3 ＝2.95。
After the steps, values of all parameters are obtained, and finally, the overall global fitting parameter calibration is carried out on all the 12 groups of measured data and the mathematical model of the four types of defects to obtain a final complete model:
ΔV th ＝ΔV th_Nit1 +ΔV th_Not-h +ΔV th_Not-e +ΔV th_Nit2
ΔV th_Nit1 ＝1.16E5exp(-0.88V G )exp(49/V D )t 0.5
ΔV th_Not-h ＝1.1exp(-0.6V G )exp(2.44/V D )t 0.2
ΔV th_Not-e ＝D{1-exp[-(t/τ) 0.34 ]}
D＝-19.6exp(3.4V G )exp(-1.83V D )
τ＝8.55E9exp(15.7V G )exp(0.17V D )
ΔV th_Nit2 ＝0.16exp(-0.7V G )exp(2.95V D )t 0.2
according to the established aging model, the Vth degradation amount of the device after any aging time can be calculated and predicted only by inputting any VG/VD stress voltage under the on-state condition.
The method is based on an aging prediction model of the device under any stress, the method starts from bottom layer physics (the increase of different types of defects in the stress), the prediction effect realized by the established model has better goodness of fit with measured data (see figures 3 and 4), and the reliability of the whole scheme is strong.
As shown in FIG. 3, the parameter extraction procedure under high field conditions can see the results (V) under 3 sets of stresses (V) for region1 in graph (a) D /V G 3 sets of results (V) of region2, = (1) -3.8V/-3.0V (2) -3.6V/-3.0V (3) -3.4V/-3.0V D /V G = 1-3.8V/-1.2v (2) -3.6V/-1.2v (3) -3.4V/-1.2V, or 3 sets of results (V) for region3 in fig. (b) D /V G 2 sets of results (V) = (1) -3.6V/-3.6V (2) -3.4V/-3.6V (3) -3.0V/-3.6V), region4 D /V G 0V/-3.6V (2) -0.4V/-3.6V = 1), and the measured data (open symbols) has excellent goodness of fit with the value (solid line) calculated by parameter fitting of the model.
The parameters obtained by the fitting are establishedThe device aging model, as shown in fig. 4, realizes device aging prediction under low electric field conditions. Regardless of region1 (V) in FIG. (a) D /V G = (1) -3.2V/-3.0V (2) -3.0V/-3.0V) and region2 (V) D /V G Predicted result of = (1) -3.2V/-1.2V (2) -3.0V/-1.2V), also at region3 and region4 boundary (V) in graph (b) D /V G The prediction results (solid line) of the = 1-2.8V/-3.6V (2) -2.0V/-3.6V (3) -1.2V/-3.6V have good consistency with the experimental results (open symbols), and the reliability of the technical scheme and the accuracy of the model are proved.
The invention provides an aging model of a peripheral thick oxygen device PMOS (P-channel metal oxide semiconductor) for sub-20 nm DRAM (dynamic random access memory) process preparation, which is modeled based on different types of defects existing in the stress process of the device and can realize the prediction of long-term aging of the device under different stress conditions (Vg/Vd different combinations) of an on state. The method has the advantages of high reliability, good prediction accuracy, strong practicability and the like.
Finally, it is noted that the disclosed embodiments are intended to aid in further understanding of the invention, but those skilled in the art will appreciate that: various substitutions and modifications are possible without departing from the spirit and scope of this disclosure and the appended claims. Therefore, the invention should not be limited to the embodiments disclosed, but the scope of the invention is defined by the appended claims.

Claims (10)

1. A method for predicting and modeling aging of DRAM peripheral transistors under any stress condition in an on state comprises the following steps:
1) Dividing all possible working voltage areas of the DRAM peripheral transistor into stress areas with different defect type dominance according to all possible defect types in a grid oxide layer of the DRAM peripheral transistor and the influence of various defects on the device when different voltages are applied to the device, and establishing a physical model of threshold voltage degradation of the device caused by different defects;
2) Selecting a plurality of groups of different V in the stress regions with different defect types as the main factors D /V G Data under the condition of high electric field stress,wherein pressure drop | V D Or gate voltage | V G I is greater than the typical working voltage by 3V, model fitting parameter values representing corresponding defects in the region are determined by realizing coincidence of model prediction effect and measured data, and threshold voltage offset generated by different defect types under any voltage and any working time is obtained;
3) Integrating a calculation formula for representing the threshold voltage degradation amount caused by all defect types to obtain a complete aging model, namely, under the condition of low electric field stress, namely, under the condition of leakage voltage | V | D Sum gate voltage | V G I is less than or equal to the typical working voltage of 3V, and the effect of the device threshold voltage degradation calculated by the verification model is matched with the actually measured experimental data;
4) Using the aging model obtained in the step 3, inputting V under any open-state condition D /V G Stress and aging time of arbitrary length, wherein the gate voltage | V under on-state condition G If | is greater than the threshold voltage 0.85V, the degradation of the device under the condition can be predicted.
2. The aging prediction modeling method for DRAM peripheral transistors under any stress condition in the on state of claim 1, wherein all possible operating voltage regions of a DRAM peripheral transistor are divided into: an interface state defect Nit1 leading device aging Region1, an oxide layer electron trap Not-e leading device aging Region2 the oxide layer hole traps Not-h dominate the device aging Region3 and the interface state defect Nit2 dominate the device aging Region4.
3. The method of claim 2, wherein a plurality of different sets of V are selected in region1 for aging prediction modeling under any stress condition of DRAM peripheral transistors in an on state D /V G Substituting the data under the stress condition into a formula (1) of the defect Nit1, and determining a corresponding fitting parameter A through experimental data 1 、B 1 、C 1 Is taken to obtain a value represented by N it1 Generated threshold voltage offset amount:
Figure FDA0003860800660000011
where t is the time of application of the stress, V G And V D Representing applied gate and drain stress, n 1 Is defect N it1 Time constant of (1), Δ V th_Nit1 Represents by N it1 The resulting threshold voltage offset.
4. The method of claim 2, wherein Not-e is determined to model it using a tensile index model, and several different sets of V are selected in region2 D /V G Substituting data under a stress condition into corresponding formulas (2), (3) and (4) of the defect Not-E, and determining values of corresponding fitting parameters E, p and q through experimental data to obtain a threshold voltage offset generated by the Not-E; ,
ΔV th_Not-e ＝D{1-exp[-(t/τ) β ]} (2)
in the formula (2), D represents the total density of defects Not-e, τ represents the time constant of the defects, β reflects the distribution width of the defect type, t is the time of applying stress, Δ V th_Not-e Representing the shift in threshold voltage by Not-e, D and τ, respectively, correspond to the following equations:
D＝E 1 exp(p 1 V G )exp(q 1 V D ) (3)
τ＝E 2 exp(p 2 V G )exp(q 2 V D ) (4)
V G and V D Representing the applied gate and drain stress.
5. The method of claim 2, wherein a plurality of different sets of V are selected from region3 D /V G Data under stress conditions are substituted into the formula (5) for the defect Not-hDetermining the corresponding fitting parameters A by experimental data 2 、B 2 、C 2 To obtain the threshold voltage offset generated by Not-h:
Figure FDA0003860800660000021
wherein t is the time of application of the stress, V G And V D Representing applied gate and drain stress, n 2 Is the time constant, Δ V, of the defect Not-h th_Not-h Representing the amount of threshold voltage shift due to Not-h.
6. The method of claim 2, wherein the regions 4 are selected from different sets of V D /V G Substituting the data under the stress condition into a formula (6) of the defect Nit2, and determining a corresponding fitting parameter A through experimental data 3 、B 3 、C 3 Obtaining the threshold voltage offset generated by Nit 2:
Figure FDA0003860800660000022
where t is the time of application of the stress, V G And V D Representing applied gate and drain stress, n 3 Is the time constant, Δ V, of the defect Nit2 th_Nit2 Representing the threshold voltage offset due to Nit 2.
7. The method of claim 4, wherein the fitting parameter A is used for modeling aging prediction of DRAM peripheral transistors under any stress condition in an on state 1 、B 1 、C 1 The value of (2) is added to the value of (1) in the formula (2).
8. The on-state arbitrary stress stripe for DRAM peripheral transistors of claim 5The aging prediction modeling method under the condition is characterized in that fitting parameters A 1 、B 1 、C 1 The value of (c) is added to the formula (5) after being substituted into the formula (1).
9. The method of claim 6, wherein the fitting parameter A is used for modeling aging prediction of DRAM peripheral transistors under any stress condition in an on state 2 、B 2 、C 2 The value of (b) is added to the formula (6) after being substituted into the formula (5).
10. The aging prediction modeling method for DRAM peripheral transistors under any stress condition in the on state as claimed in claim 2, wherein V within Region1 is D /V G Stress value range is 0.5 x | V D |<|V G |<|V D L, |; region2 inner V D /V G Stress value range is | V G |<0.5*|V D L; region3 inner V D /V G Stress value range is | V G |>|V D L, |; v within Region4 data D /V G Stress value range is | V D |<0.8V。
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