CN115495407A

CN115495407A - Stacked interconnect architecture and electronic device

Info

Publication number: CN115495407A
Application number: CN202110679213.1A
Authority: CN
Inventors: 钟军威
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2021-06-18
Filing date: 2021-06-18
Publication date: 2022-12-20
Also published as: WO2022262488A1

Abstract

The application relates to the technical field of communication, and discloses a stacked interconnection architecture and an electronic device. The laminated interconnection framework comprises two or more circuit board assemblies, each circuit board assembly comprises a circuit board, a connector installed on the surface of the circuit board and electronic components such as a central processing unit, and the connectors on the two adjacent circuit boards are correspondingly inserted with each other to form a connection structure between the circuit board assemblies. The two central processing units distributed in the same circuit board assembly are electrically connected through the in-board wiring, the two central processing units distributed in different circuit board assemblies are electrically connected through the in-board wiring, and the two circuit board assemblies are electrically connected through the connecting structure. The stacked interconnection architecture simplifies the structure, reduces the link loss, improves the signal rate, improves the integration level, reduces the height of the interconnection architecture and reduces the occupied space.

Description

Stacked interconnect architecture and electronic device

Technical Field

The present invention relates to the field of communications technologies, and in particular, to a stacked interconnection architecture and an electronic device.

Background

The high-end server generally refers to a memory sharing server formed by 8 or more than 8 central processing units, and has stronger computing capacity and IO expansion capacity. Fig. 1 shows an interconnection architecture diagram of an 8P server, in which any one of the 8 cpus 310a can be individually interconnected with another cpu 310a through a trace 400 a. Currently, 8P servers are capable of achieving 32Gbps rates, and the next generation is expected to be capable of achieving 112Gbps rates.

In the existing 8P server interconnection architecture, 4 cpus are mounted on the board of a circuit board to form 2 processor circuit package structures. The 2 processor circuit packaging structures are vertically stacked and are respectively inserted into the back plate along the direction parallel to the plate surface through corresponding connectors. The circuit board is internally provided with circuit wiring for communicating the central processing unit on the board with the corresponding connectors, and the backboard is internally provided with backboard wiring for communicating each connector. Two central processing units on different processor circuit packaging structures need to be electrically connected with a backboard through circuit board wiring and a connector.

In the interconnection architecture, the interconnection between the central processing units in different processor circuit packaging structures can be realized only through the backboard, so that the cost of the interconnection architecture is increased. Secondly, the difference in the lengths of the wires between the central processing units and the connectors at different positions relative to the backplane in the same processor circuit package structure is large, which results in a large difference in the signal transmission performance between the central processing units in the interconnection architecture, and a long and complex design of the lengths of the wires between the two central processing units in different processor circuit package structures. Finally, in order to ensure the stability of the backplane to the support of the processor circuit package structure, the backplane has certain size requirements, which results in a high height of the interconnect architecture and a large space occupation by the 8P server.

Disclosure of Invention

The utility model provides a problem that in the solution interconnection framework, with high costs, the signal transmission performance between each central processing unit differs great, and the line length of walking between two central processing units in different circuit board components is longer and the design is complicated, and the height of interconnection framework is higher, this application provides a range upon range of interconnection framework and electronic equipment. In the range upon range of interconnection framework in this application, including two and more than two circuit board components, and every circuit board component includes the circuit board, installs in electronic components such as connector and central processing unit of the face of circuit board. The connectors on two adjacent circuit boards are correspondingly plugged with each other to form a connecting structure between the circuit board assemblies. And then two central processing units in the same circuit board assembly are electrically connected through the wiring in the circuit board assembly, and the two central processing units distributed between different circuit board assemblies are electrically connected through the wiring between the two central processing units in different circuit board assemblies and the connector and the connecting structure between the two circuit board assemblies. The method and the device simplify the structure of the interconnection architecture and reduce the cost of the interconnection architecture. Meanwhile, the layout position of the connector in the circuit board assembly is optimized, wiring between the connector and the electronic component is integrated in the circuit board conveniently, the integration level of the circuit board assembly is improved, and the height of an interconnection framework is reduced. Finally, the connectors are positioned among the circuit board assemblies, the circuit board assemblies can be stably supported by using a small number of connectors, an additional supporting structure is not needed, and the structure of the interconnection framework is further simplified.

The first aspect of the application provides a stacked interconnection architecture, specifically, the stacked interconnection architecture includes N stacked circuit board assemblies, where N is greater than or equal to 2; each circuit board assembly comprises a circuit board, at least one connector and at least one central processing unit arranged on the board surface of the circuit board, and the connector is arranged on the board surface; the connectors on the two adjacent circuit boards are correspondingly inserted to form at least one connecting structure in the laminated interconnection framework, and the inserting direction of the connectors is vertical to the board surface; one central processing unit in a circuit board assembly and another central processing unit in the circuit board assembly are electrically connected through the wiring in the circuit board assembly; the CPU in one circuit board assembly is electrically connected with the CPU in the other circuit board assembly through the wiring in one circuit board assembly, the wiring in the other circuit board assembly and the connecting structure.

The circuit board assembly is a combination of a circuit board, a connector and a central processing unit, and may also be referred to as a processor circuit package structure, for example, if 2 central processing units are installed on the circuit board, the circuit board assembly is a 2P processor circuit package structure, and if 4 central processing units are installed on the circuit board, the circuit board assembly is a 4P processor circuit package structure. In addition, the circuit board assembly may further include a memory bank corresponding to the central processing unit. By layerwise stacking is meant that two or more circuit board assemblies are placed in a stack and connected to each other in the stacking direction. For example, N =2, i.e., the stacked interconnect architecture includes a first circuit board assembly and a second circuit board assembly, and the first circuit board assembly and the second circuit assembly are stacked and connected along the stacking direction. For another example, N =3, that is, the stacked interconnection architecture includes a first circuit board assembly, a second circuit board assembly, and a third circuit board assembly, and the first circuit board assembly, the second circuit assembly, and the third circuit board assembly are stacked and connected along the stacking direction.

The board surface refers to a surface of a circuit board for mounting electronic components, and generally, a circuit board includes two opposite board surfaces extending in parallel directions. It will be appreciated that the cpu and connector projections on the different circuit board assemblies, respectively, coincide in plane. However, the board surfaces of the cpu and the connector on different circuit board assemblies may be different, and the present application is not particularly limited.

The connecting structure refers to a structure for connecting two adjacent circuit boards in a stacked interconnection architecture, for example, the connecting structure may be a set of connectors between the adjacent circuit boards, and the set of connectors are respectively mounted on two board surfaces of the adjacent circuit boards that are close to each other. For the connection structure between two circuit board assemblies, the connection structure may be a structure for electrically connecting two cpus disposed on two circuit board assemblies, and the connection structure does not include routing between the connectors in the two circuit board assemblies and the cpus. The electrical connections enable signal communication between any two central processors in the stacked interconnect architecture. The electrical connection refers to an interconnection relationship established between two central processing units in a stacked interconnection architecture and used for realizing data communication between the central processing units, and the electrical connection is used for realizing signal interaction and signal transmission between the two central processing units. It is understood that the electrical connection between the central processing units may be one of the central processing units electrically connected with the other central processing unit or a plurality of other central processing units. The electrical connection between the central processing units can also be that one of the central processing units is electrically connected with the other central processing unit respectively so as to realize the independent electrical connection between every two central processing units in all the central processing units.

The connector is a plug-in type connector. For example, the connector in one circuit board assembly is a plug and the connector in an adjacent circuit board assembly is a socket that mates with the plug. Wherein, the mode that the face in the circuit board was installed in the connector includes: the connector is mounted on the surface of the circuit board, or the connector is embedded in the circuit board and protrudes out of the surface of the circuit board. The connector is crimped to the circuit board by a crimping process. In other alternative embodiments, the connector is soldered to the circuit board by a soldering process.

In other words, in the embodiment of the present application, the connectors on two adjacent circuit boards are correspondingly plugged with each other to form corresponding connection structures, at least one connection structure is formed, and the plugging direction of the connector is perpendicular to the board surface. Two central processing units in the same circuit board assembly are electrically connected through the wiring in the circuit board assembly. The two different circuit board assemblies, wherein one central processing unit in one circuit board assembly is electrically connected with the central processing unit in the other circuit board assembly through the wiring in one circuit board assembly, the wiring in the other circuit board assembly and the connecting structure. It will be appreciated that the latter electrical connection may be one of the cpus in one of the circuit board assemblies electrically connected to one of the cpus in the other circuit board assembly. One central processing unit in one circuit board assembly can be electrically connected with a plurality of central processing units in another circuit board assembly. The traces may be printed traces printed in a circuit board, or the traces may be high speed cables located between the central processors, or between the central processors and the connectors.

It will be appreciated that the stacked interconnect architecture includes two or more circuit board assemblies, wherein the circuit board assemblies may be identical circuit board assemblies, and the circuit board assemblies may also be different circuit board assemblies.

In the above-mentioned stacked interconnection architecture, two cpus in the same circuit board assembly are electrically connected through the wiring in the circuit board assembly, and for two cpus respectively located in two circuit board assemblies, the electric connection is realized through the wiring in the two circuit board assemblies and the connection structure.

The circuit board assemblies in the application form a connecting structure with the circuit board assemblies through the connectors, and then the electric connection between the central processing units on different circuit board assemblies can be realized through the wiring in the circuit board assembly plates and the connecting structure, so that the structure of the interconnection framework is simplified, and the cost of the interconnection framework is reduced. Meanwhile, according to the scheme of the application, the layout position of the connector in the circuit board assembly is optimized, the distance between the connector and the on-board central processing unit is shortened and homogenized, further wiring between the connector and the central processing unit is integrated in the circuit board conveniently, wiring length is shortened, link loss is reduced, signal rate is improved, the integration level of the circuit board assembly is improved, and the height of an interconnection framework is reduced. In addition, according to the scheme of this application, the connector is located between the circuit board subassembly, uses less connector can stabilize the support circuit board subassembly promptly, need not to set up extra bearing structure, has further simplified the structure of interconnection framework, reduces the space that the server occupied. Finally, the circuit boards are not connected by using a back plate, so that the height and the cost of the circuit board assembly are reduced.

In a possible implementation of the first aspect, in the stacked interconnection architecture, every two cpus in all the cpus perform independent electrical connection. The independent electric connection means that any two central processing units among all the central processing units can be independently communicated, so that the interference of signal transmission among the central processing units can be effectively avoided, and the rate of the signal transmission among the central processing units is improved.

In order to equalize the delay performance of signal transmission between the cpus in the stacked interconnection architecture, in one possible implementation of the first aspect, the total lengths of the traces through which the electrical connections between every two cpus are made are equal to each other. It can be understood that the total length of the traces is related to the delay performance of signal transmission between the central processing units, and specifically, the longer the total length of the traces is, the more obvious the delay of signal transmission between the central processing units is; conversely, the shorter the total length of the traces, the less significant the delay in signal transmission between the cpus. The total track length is the sum of the track lengths of all the tracks electrically connected between every two central processing units, and the track length is the extension length of one end of one track extending to the other end of the track in one section of the track.

Specifically, in the same circuit board assembly, one wire can be electrically connected with two central processing units. That is, in the same circuit board assembly, the lengths of the traces for communicating the two cpus in the board are equal.

For two cpus respectively distributed on different circuit board assemblies, the routing between the two cpus includes the routing on the two circuit board assemblies. In some possible implementations, the routing between the two cpus further includes routing between the connection structures.

In order to reduce the wiring difficulty, in one possible implementation of the first aspect, the lengths of the traces between the cpus and the corresponding connectors are equal. In each circuit board assembly of the stacked interconnection architecture, the lengths of the wires between the connector and the central processing units are equal, so that the lengths of the wires between any two central processing units in the stacked interconnection architecture can be ensured to be equal by randomly matching the wires in different circuit boards, and the difficulty in planning the wire paths between the central processing units is reduced.

In a possible implementation of the first aspect, in the stacked interconnection architecture, the number of the cpus in each circuit board assembly is 4, the cpus are uniformly arrayed on the board surface in postures, and the center points of the 4 cpus are distributed in a rectangular shape; the number of the connectors on one plate surface in each circuit board assembly is 3, and the 3 connectors are distributed on a central line of a rectangle; the connector comprises a middle connector and two side connectors, the middle connector is distributed in the center of the rectangle, and the two side connectors are distributed on two sides of the middle connector; the middle connector is respectively connected with 4 central processing units, and the two side connectors are respectively connected with 2 central processing units adjacent to the middle connector; in adjacent circuit board assemblies, the intermediate connectors are plugged with each other to form an intermediate connection structure, and the side connectors are correspondingly plugged with each other to form two side connection structures.

That is, in the embodiment of the present application, each circuit board assembly includes 4 cpus, and the distribution postures of the 4 cpus are consistent, and the respective central points are distributed at four vertices of a rectangle. Still include 3 connectors on a face of every circuit board subassembly, according to the distribution position of connector on the circuit board, divide into 3 connectors and distribute in a middle connector at the rectangle center and distribute in two lateral part connectors of rectangle both sides. The middle connector is adjacent to 4 central processing units, and each side connector is adjacent to two central processing units. The middle connector is connected with 4 central processing units through wiring in the circuit board, and each side connector is connected with two adjacent central processing units.

It is understood that the traces between the cpus and the connectors are used to electrically connect the cpus in the circuit board assemblies to the cpus in the other circuit board assemblies. Therefore, when the number of the circuit board assemblies in the stacked interconnection architecture is N, that is, a cpu in a circuit board assembly needs to be electrically connected to all cpus in the other N-1 circuit board assemblies, the number of the traces between the cpu and the connector is the total number of the cpus in the other N-1 circuit board assemblies. For example, a stacked interconnect architecture includes a first circuit board assembly and a second circuit board assembly. The second circuit board assembly comprises 4 central processing units, and the number of the routing lines between one central processing unit in the first circuit board assembly and the connector in the first circuit board assembly is 4. For another example, a stacked interconnect architecture includes a first circuit board assembly, a second circuit board assembly, and a third circuit board assembly. The second circuit board assembly comprises 4 central processing units, the third circuit board assembly also comprises 4 central processing units, and the number of the routing lines between one central processing unit in the first circuit board assembly and the connector in the first circuit board assembly is 8.

Wherein, it can be understood that the consistent posture means that the arrangement angles of the central processing units are the same. For example, when two cpus have the same rectangular structure and the distribution postures of the two cpus are the same, the long sides of the two cpus are parallel to each other, and the short sides of the two cpus are parallel to each other. The central point of a central processing unit refers to a point representing the central position of the central processing unit, for example, the central point of the central processing unit may be the center of the geometric structure of the central processing unit, and the central point of the central processing unit may be a mass point of the central processing unit. The central points of the 4 central processing units are distributed in a rectangular shape, which means that the central points of the 4 central processing units are distributed on four vertexes of a rectangle. The center line of a rectangle is a straight line passing through the midpoints of a pair of parallel sides of the rectangle, and thus, a rectangle has two mutually perpendicular center lines. When the number of the connecting structures is 3 or more than 3, the connecting structure located at the middle position is a middle connecting structure, and the other connecting structures are side connecting structures.

For example, the stacked interconnection architecture includes two circuit board assemblies, and the projections of the connectors of the two circuit board assemblies and the central processor in either board plane coincide, respectively. The projection respectively overlapped means that the relative positions of the connectors of the two circuit board assemblies and the central processor on the board surface are the same, but the board surface on which the connectors and the central processor are specifically installed is not limited, that is, the connectors and the central processor in different circuit board assemblies can be installed on different board surfaces. Specifically, each circuit board assembly comprises 2 rows and 2 columns of first central processing units, second central processing units, third central processing units and fourth central processing units which are distributed in an array in turn and have consistent distribution postures, and the central points of the 4 central processing units are distributed at four vertexes of a rectangle, wherein one edge of the rectangle extends along the horizontal direction, and the other edge of the rectangle extends along the vertical direction. For convenience of the following description, a straight line passing through midpoints of two vertical sides of the rectangle is defined as a horizontal centerline, and a straight line passing through midpoints of two horizontal sides of the rectangle is defined as a vertical centerline. The first central processing unit and the second central processing unit are positioned on one side of the horizontal center line, and the third central processing unit and the fourth central processing unit are positioned on the other side of the horizontal center line. The first central processing unit and the third central processing unit are positioned on one side of the vertical central line, and the second central processing unit and the fourth central processing unit are positioned on the other side of the vertical central line.

One board side of each circuit board assembly includes one middle connector (e.g., a second connector) and 2 side connectors (e.g., a first connector on the left side of the second connector and a third connector on the right side of the second connector) distributed on the horizontal centerline. Wherein the intermediate connectors are distributed at the center point of the rectangle. Furthermore, in the circuit board assembly, the middle connector is adjacent to the 4 central processing units, the side connector on the left side is adjacent to the first central processing unit and the third central processing unit, and the side connector on the right side is adjacent to the second central processing unit and the fourth central processing unit. Therefore, in the circuit board assembly, the middle connector is connected with the 4 central processing units, the side connector on the left side is connected with the first central processing unit and the third central processing unit respectively through wires, and the side connector on the right side is connected with the second central processing unit and the fourth central processing unit respectively through wires.

In adjacent circuit board assemblies, the middle connectors are mated with one another to form a middle connection structure, the left side connectors are mated with one another to form a left side connection structure, and the right side connectors are mated with one another to form a right side connection structure.

The layout of the connector and the central processor of the circuit board assembly in the stacked interconnection structure is regular, the wiring in the circuit board assembly is uniform, and the stress of the circuit board is uniform when the connector is buckled. Meanwhile, because the connector and the central processing units are installed on the board surface of the circuit board, the distance between the connector and each central processing unit can be realized by adjusting the positions of the connector in the board surface. The connector and the central processing unit are arranged equidistantly without sacrificing the height of the interconnection architecture, and integration of the interconnection architecture is facilitated.

In a possible implementation of the first aspect, in order to improve the stability of the overall structure of the circuit board assembly, so as to improve the balance of the stress on the stacked interconnection structure, and further to prolong the service life of the stacked interconnection structure, in some embodiments of the present application, the distances between the two side connectors and the middle connector are the same. That is, the three connector groups are equally spaced. The connector group is an assembly obtained by mutually inserting two corresponding connectors.

In a possible implementation of the first aspect, in order to reduce the number of layers of wiring distribution in the circuit board, the wirings between two adjacent central processing units in the same circuit board assembly and the wirings on one of the rectangular diagonals are laid out as first-layer wirings, the wirings between the central processing units and the corresponding storage strips in the same circuit board assembly and the wirings on the other rectangular diagonal are laid out as second-layer wirings, and the wirings between the connectors and the central processing units in the same circuit board assembly are laid out as third-layer wirings. The first layer of wires, the second layer of wires and the third layer of wires are three layers of printed wires in the circuit board assembly.

In the stacked interconnection structure, the wiring in the circuit board can be effectively prevented from being crossed, the wiring is divided into a plurality of layers, all the wiring between the connector and the central processing unit is reasonably distributed in the circuit board, the use of cables is avoided, and the overall structure is simplified. Meanwhile, the areas of the first layer of wires, the second group of wires and the third layer of wires are overlapped, so that the processing difficulty and the installation difficulty of the circuits in the circuit board assembly are reduced, the cost is saved, and the economic benefit is improved. The first layer routing and the second layer routing are reasonable in layout, the board surface of the circuit board is occupied less, the routing between the central processing unit and the storage strip and the routing between partial central processing units are layered together, a layer does not need to be newly arranged for the routing between the central processing unit and the storage strip, and the number of printing layers in the circuit board is reduced. Meanwhile, the circuit board assembly comprising the first layer of wires and the second layer of wires can basically ensure that the lengths of the wires electrically connected between two central processing units in different circuit board assemblies are basically equal under the condition of meeting the electrical connection between the central processing units in the board. Therefore, the stacked interconnection architecture does not have the situation that the routing between the central processing units on different boards is too long or too short, so that the operation capacity of each central processing unit in the whole stacked interconnection architecture is balanced, and the difference of data transmission among the central processing units is reduced.

In one possible implementation of the first aspect, in the stacked interconnect structure, a communication path between a cpu in a first circuit board assembly and another cpu in another circuit board assembly includes: when one central processing unit and the other central processing unit are adjacent to the same side connecting structure, the central processing unit is electrically connected with the other central processing unit through the adjacent side connecting structure and the adjacent side connecting structure respectively; when one central processing unit and the other central processing unit are adjacent to different side connection structures, one central processing unit is electrically connected with the other central processing unit through the middle connection structure and the middle connection structure respectively and the routing between the central processing unit and the other central processing unit. The communication path refers to a routing manner selected for electrically connecting two cpus distributed on different circuit board assemblies.

In other words, in the embodiment of the present application, the connection structure through which the electrical connection between the two cpus passes is selected according to whether the connection structures adjacent to the two cpus distributed on different circuit board assemblies are the same, and then the connection structures in the stacked interconnection architecture are reasonably distributed, so as to balance the loads of the connection structures as much as possible, that is, balance the loads of the connectors as much as possible.

For example, for two cpus respectively distributed on different circuit board assemblies, after the stacked interconnection structure is assembled, the positions of the two cpus are opposite, that is, the projections of the two cpus on one board surface of one of the circuit board assemblies are overlapped, and then the two cpus are adjacent to the same side connection structure. At this time, the two cpus are respectively connected with the routing between the two cpus through the adjacent side connection structures and the adjacent side connection structures. The adjacent side connection structure may be a left side connection structure or a right side connection structure.

For another example, for two cpus respectively disposed on different circuit board assemblies, the connectors on the circuit board assemblies are disposed on the horizontal central line, and when the stacked interconnection structure is assembled, the positions of the two cpus are not opposite to each other, but the two cpus are disposed on the same side of the vertical central line, and then the two cpus are also adjacent to the same side connection structure. At this time, the two cpus are respectively connected with the routing between the two cpus through the adjacent side connection structures and the adjacent side connection structures. The adjacent side connection structure may be a left side connection structure or a right side connection structure. It can be understood that the two central processing units mentioned above are located on the same side of the center line, and the two central processing units mentioned below are located on both sides of the center line, which refers to a positional relationship of the two central processing units and a projection of the center line in one of the board surfaces of one of the circuit board assemblies, and will not be described in detail later. Similarly, the connectors on the circuit board assembly are distributed on the vertical central line, but when the two central processing units are distributed on the same side of the horizontal central line, the two central processing units are also adjacent to the same side connection structure, which is not described again.

For another example, for two cpus respectively distributed on different circuit board assemblies, the connectors on the circuit board assemblies are distributed on the horizontal central line, and when the two cpus are distributed on two sides of the vertical central line after the stacked interconnection architecture is assembled, the two cpus are adjacent to different side connection structures. At this time, the two central processing units are respectively connected with the wiring between the two central processing units through the intermediate connection structure and the intermediate connection structure. The two central processing units are distributed on two sides of the vertical central line and comprise two central processing units which are distributed on two sides of the vertical central line and distributed on the same side of the horizontal central line, and the two central processing units are distributed on two sides of the vertical central line and distributed on two sides of the horizontal central line.

In the circuit board assembly in the stacked interconnection architecture, the number of the central processing units butted by each connector is basically equal, and the lengths of the routing lines between the two central processing units in the circuit board assembly are basically the same, so that the load of the whole stacked interconnection architecture is balanced, and the stability of signal transmission between the central processing units is improved conveniently.

In a possible implementation of the first aspect, in the stacked interconnection structure, the number of central processors in each circuit board assembly is 2, and the 2 central processors are uniformly distributed in parallel in posture; the number of the connectors on one board surface in each circuit board assembly is 2, the 2 connectors are respectively arranged at two sides of the connecting line of the central points of the 2 central processing units, and the 2 connectors are distributed on the perpendicular bisector of the connecting line of the central points; in the adjacent circuit board assemblies, the connectors are correspondingly plugged with each other to form 2 connecting structures.

In a possible implementation of the first aspect, in the stacked interconnect structure, the stacked interconnect structure includes a first circuit board assembly to an nth circuit board assembly stacked in sequence; the first circuit board assembly and the nth circuit board assembly may be single connection board assemblies, which are circuit board assemblies having connectors on one side of the circuit boards. Wherein, single link plate subassembly is the circuit board subassembly that circuit board one side was equipped with the connector. In addition, a circuit board assembly having connectors on both sides of the circuit board is referred to as a dual connection board assembly. It is to be understood that the single-connection assembly or the double-connection assembly is a limitation for mounting the connector on a specific board surface of the circuit board, and does not relate to the limitation for mounting electronic components (such as a cpu and a memory bar) on the specific board surface of the circuit board. That is, electronic components in the circuit board assembly can be randomly distributed on two board surfaces of the circuit board, and generally speaking, the central processing unit and the corresponding memory strip are distributed on the same board surface of the circuit board.

That is, in an embodiment of the present application, the stacked interconnect architecture includes the first circuit board assembly to the nth circuit board assembly stacked in sequence. The projections of the connectors in the N circuit board assemblies in one of the circuit board assemblies coincide with each other, but the projections of the cpus in the N circuit board assemblies in one of the circuit board assemblies are not particularly limited. In order to improve the stability of the whole structure of the stacked interconnection architecture, the projections of the cpus in the N circuit board assemblies in one board plane in one of the circuit board assemblies are also overlapped. The outermost two circuit board assemblies in the stacked interconnect architecture may be single-board assemblies.

For example, when N =2, the stacked interconnect architecture includes a first circuit board assembly and a second circuit board assembly stacked one on top of the other. Wherein the first circuit board assembly and the second circuit board assembly may be both single connection board assemblies.

In some other implementations, the first circuit board assembly and the second circuit board assembly may both be dual connection board assemblies. Or one of the first circuit board assembly and the second circuit board assembly is a single connecting board assembly, and the other one is a double connecting board assembly.

For another example, when N =3, the stacked interconnect architecture includes a first circuit board assembly, a second circuit board assembly, and a third circuit board assembly stacked in this order. The first circuit board assembly and the third circuit board assembly can be single connection board assemblies, and the second circuit board assembly is a double connection board assembly.

The two circuit board assemblies outside the laminated interconnection framework are single connecting board assembly assemblies, so that the interconnection requirement among the circuit board assemblies can be met, the cost of the laminated interconnection framework is reduced, and the economic benefit is improved.

In a possible implementation of the first aspect, in the stacked interconnect structure, the single connection board assembly is a single connection board assembly with different directions, where the central processing unit and the connector are respectively disposed on two sides of the circuit board; or the single connecting board assembly is a same-direction single connecting board assembly with the central processing unit and the connector arranged on the same side of the circuit board.

That is, in the embodiment of the present application, when the outermost two circuit board assemblies in the stacked interconnection architecture are single-connection board assemblies, the two single-connection board assemblies may be one of a non-reciprocal single-connection board assembly and a reciprocal single-connection board assembly, respectively. That is, in the outermost two circuit board assemblies in the stacked interconnection architecture, the cpus in the circuit board assemblies are distributed on the side of the circuit board close to the other circuit board assemblies, or the cpus in the circuit board assemblies are distributed on the side of the circuit board far away from the other circuit board assemblies.

The single connecting plate assembly in the stacked interconnection architecture can be a different-direction single connecting plate assembly and a same-direction single connecting plate assembly, so that the requirements of the stacked interconnection architecture under different application scenes such as small space or poor heat dissipation are met.

In a possible implementation of the first aspect, in the stacked interconnect structure, the first circuit board assembly and the nth circuit board assembly are all anisotropic single-board assemblies; the connector in the first circuit board assembly is located on one side, close to the Nth circuit board assembly, of the circuit board, and the connector in the Nth circuit board assembly is located on one side, close to the first circuit board assembly, of the circuit board. The first circuit board component is a first circuit board component distributed along the layered superposition direction, the second circuit board component is a second circuit board component distributed along the layered superposition direction, and the like, and the Nth circuit board component is an Nth circuit board component distributed along the layered superposition direction.

That is, in the embodiment of the present application, the two outermost circuit board assemblies in the stacked interconnection architecture are all anisotropic single-connection board assemblies, and after the stacked interconnection architecture is assembled, the connectors of the two anisotropic single-connection board assemblies face each other, that is, the cpus in the two outermost circuit board assemblies in the stacked interconnection architecture face outward. When N =2, i.e., the stacked interconnect structure includes the first circuit board assembly and the second circuit board assembly, such a stacked interconnect architecture is referred to as a piggyback stacked interconnect architecture.

According to the laminated interconnection framework, the central processing units in the two circuit board assemblies on the outermost sides in the laminated interconnection framework face outwards, so that the central processing units on the outermost sides in the laminated interconnection framework can be conveniently installed and radiated, a large radiating channel and a large installing space do not need to be reserved, and the height of the whole interconnection framework is reduced. For the back-buckling type laminated interconnection structure when N =2, the central processing unit with larger size is not required to be arranged in the inner side space between the circuit boards, so that the height size of the space can be reduced, the distance between the circuit boards is further reduced, the total height of the connector group after plugging is effectively controlled, signal crosstalk is avoided, and the stability and the accuracy of signal transmission speed and signal transmission are improved. In a 2U machine frame, the first circuit board assembly and the second circuit board assembly adopt a back-buckling scheme, the overall height of the connector is about 5-15 mm, signal crosstalk of the connector is small, the integrity of signals in a high-speed serial bus is improved, and the connector is suitable for signal rates of 10-112 Gbps.

In a possible implementation of the first aspect, in the stacked interconnect structure, the first circuit board assembly is a non-reciprocal single board assembly, and the nth circuit board assembly is a unidirectional single board assembly; the connector in the first circuit board assembly is located on one side, close to the Nth circuit board assembly, of the circuit board, and the connector in the Nth circuit board assembly is located on one side, close to the first circuit board assembly, of the circuit board.

That is, in the embodiment of the present application, one of the two outermost circuit board assemblies in the stacked interconnection architecture is the anisotropic single-board assembly, and the other one is the isotropic single-board assembly, and after the stacked interconnection architecture is assembled, the connectors of the two single-board assemblies face each other, that is, the central processing unit of the outermost anisotropic single-board assembly in the stacked interconnection architecture faces outward, and the central processing unit of the outermost isotropic single-board assembly in the stacked interconnection architecture faces inward. When N =2, i.e. the stacked interconnect structure comprises a first circuit board assembly and a second circuit board assembly, such a stacked interconnect architecture is referred to as a snap-in stacked interconnect architecture.

The stacked interconnection framework avoids the connector from occupying extra height space, realizes the close arrangement of components in the interconnection framework, shortens the high-speed signal routing length communicated between the two processors, and further reduces the height size of the whole framework. For the right-hand-buckling type laminated interconnection structure when N =2, the connectors in the different-direction single-connection-board assembly, the connectors in the same-direction single-connection-board assembly and the central processing units are reasonably distributed, the connectors in the different-direction single-connection-board assembly, the connectors in the same-direction single-connection-board assembly and the central processing units can be distributed in the same height space together, the connectors are prevented from occupying extra height space, the close arrangement of components in the interconnection framework is realized, the high-speed signal wiring length communicated between the two processors is shortened, and the height size of the whole framework is further reduced. In addition, the positive-fastening type laminated interconnection structure has a connector height of about 44.45mm, and is suitable for signal rates below 56 Gbps.

In a possible implementation of the first aspect, for the N =2 positive-fit stacked interconnection structure, the heights of the connectors in the anisotropic single board assembly and the connectors in the unidirectional single board assembly are designed reasonably so that the total height of the connected connector group is slightly greater than the height of the central processing unit in the unidirectional single board assembly (when the central processing unit is provided with accessories such as a heat sink and a heat conduction pad, the total height of the connected connector group is slightly greater than the total height of the central processing unit and the accessories on the circuit board). The stacked interconnection framework can effectively reduce the overall height of the stacked interconnection framework by reasonably designing the total height of the connector set, reduce the occupied loading space and improve the loading capacity of the cabinet.

In a possible implementation of the first aspect, in the stacked interconnect structure, when N > 2, the other circuit board assemblies between the first circuit board assembly and the nth circuit board assembly are dual-connection board assemblies having connectors on both sides of the circuit board. For example, when N =3, the stacked interconnect architecture includes a first circuit board assembly, a second circuit board assembly, and a third circuit board assembly stacked in this order. Wherein, first circuit board subassembly and third circuit board subassembly can be single link plate subassembly, and the second circuit board subassembly is double link plate subassembly.

When N is greater than 2, that is, when the stacked interconnection structure includes two or more circuit board assemblies, the middle circuit board assembly is a dual-connection board assembly in which connectors are respectively disposed on two sides of the circuit board, so as to achieve interconnection between two adjacent circuit board assemblies of the two or more circuit board assemblies.

In a possible implementation of the first aspect, in the stacked interconnection structure, the stacked interconnection structure further includes a frame, and a receiving cavity for receiving the stacked circuit board assembly is formed inside the frame; the circuit board assembly further comprises a storage strip, and the machine frame is provided with a mounting hole opposite to the storage strip.

In other words, in the embodiment of the application, when the stacked interconnection architecture normally works, the mounting hole is closed, and when the memory strip needs to be plugged and unplugged, the operation can be performed only by opening the mounting hole without opening a machine frame. The stacking interconnection framework is convenient for disassembling the storage strips and is convenient for overhauling and replacing the storage strips in the stacking interconnection framework.

In a possible implementation of the first aspect, in the stacked interconnect architecture, the stacked interconnect architecture further includes: the radiator is arranged on the surface of the central processing unit; one side of the heat conducting pad is attached to the surface of the radiator, and the other side of the heat conducting pad is attached to the inner surface of the machine frame.

According to the laminated interconnection framework, the central processing unit is attached to the machine frame through the heat conducting pad, so that the heat dissipation capacity of the laminated interconnection framework is improved, and the working stability of the laminated interconnection framework is further improved.

A second aspect of the present application provides an electronic device, in particular an electronic device comprising any one of the above-mentioned first aspect of the stacked interconnect architecture.

The third aspect of the application provides a circuit board assembly, specifically includes circuit board, at least one connector and installs including at least one central processing unit on the face of circuit board, and the connector is installed in the face, and the grafting direction and the face of connector are perpendicular.

Drawings

FIG. 1 is a schematic diagram of a prior art 8P server interconnect architecture;

FIG. 2 (a) shows an interconnection architecture of an 8P server in the present application;

FIG. 2 (b) shows an interconnect architecture of 8P server in the form of "2P package +1 backplane";

FIG. 2 (c) shows an interconnect architecture of the 8P server "2P package +2 backplanes";

fig. 3 (a) is an application scenario diagram of a layer-by-layer interconnect architecture in embodiment 1 of the present application;

fig. 3 (b) is a structural diagram of the stacked interconnect structure 1 in embodiment 1 of the present application;

fig. 4 (a) is a top view of a processor circuit package structure 10a in the stacked interconnect architecture 1 according to embodiment 1 of the present application;

FIG. 4 (b) is the distribution status of the CPUs in FIG. 4 (a);

FIG. 4 (c) shows an interconnect architecture of 8P server in the form of "4P packages +1 backplane";

fig. 5 (a) is a schematic diagram of a first layer of traces 410a between electronic components 310a in a processor circuit package structure 10a according to embodiment 1 of the present application;

fig. 5 (b) is a schematic diagram of a first layer of traces 410b between electronic components 310b in a processor circuit package structure 10b according to embodiment 1 of the present application;

fig. 5 (c) is a schematic diagram of a second layer of traces 420a between electronic components 310a in another processor circuit package structure 10a according to embodiment 1 of the present application;

fig. 5 (d) is a schematic diagram of a second layer of traces 420b between electronic components 310b in another processor circuit package structure 10b according to embodiment 1 of the present application;

fig. 5 (e) is a schematic diagram of a third layer of traces 430 between the cpu 310a and the connector 200a in the processor circuit package structure 10a according to embodiment 1 of the present application;

fig. 5 (f) is a schematic diagram of a third layer of traces 430 between the cpu 310b and the connector 200b in the processor circuit package structure 10b according to embodiment 1 of the present application;

FIG. 5 (g) shows an interconnect architecture of the "2P package + cable" type for an 8P server;

FIG. 6 (a) is a schematic diagram illustrating the communication paths between the CPU 310a and the CPU 310b when the CPU 310a in the processor circuit package 10a and the CPU 310b in the processor circuit package 10b are located opposite to each other according to embodiment 1 of the present application;

fig. 6 (b) shows the communication paths between the cpu 310a in the processor circuit package 10a and the cpu 310b in the processor circuit package 10b under the condition of the same side of the other center line in embodiment 1 of the present application;

fig. 6 (c) shows the communication paths between the cpu 310a in the processor circuit package 10a and the cpu 310b in the processor circuit package 10b under the condition of being located on the same side of a center line in embodiment 1 of the present application;

fig. 6 (d) shows the communication paths between the cpu 310a in the processor circuit package 10a and the cpu 310b in the processor circuit package 10b under the condition of the diagonal line of the rectangle in embodiment 1 of the present application;

fig. 7 is a top view of another circuit package structure 10a ' of a processor in a stacked interconnection architecture 1 according to embodiment 1 of the present application, wherein a schematic diagram of routing between a connector 200a ' and a cpu 310a ' is shown;

fig. 8 is a top view of a circuit package 10a ″ of a processor in a stacked interconnection architecture 1 according to embodiment 1, wherein traces between a connector 200a ″ and a cpu 310a ″ are schematically illustrated;

FIG. 9 (a) is a cross-sectional view of a counter-rotating single connect plate assembly taken along the line M-M in FIG. 4 (a) according to example 1 of the present application;

FIG. 9 (b) shows S in FIG. 9 (a) ₁ A partial enlargement of a region;

FIG. 10 is a cross-sectional view of a uni-directional bulkhead assembly of example 1 of the present application, taken along section M-M in FIG. 4 (a);

fig. 11 is a cross-sectional view of a piggyback stacked interconnect structure 1 taken along the section M-M in fig. 4 (a) according to embodiment 1 of the present application;

fig. 12 (a) is a cross-sectional view of a snap-in stacked interconnect structure 1 taken along a section M-M in fig. 4 (a) according to embodiment 1 of the present application;

fig. 12 (b) is a cross-sectional view of another positive-fit stacked interconnect structure 1 according to embodiment 1 of the present application, taken along the section M-M in fig. 4 (a);

fig. 13 is a cross-sectional view of a stacked interconnect structure 1 taken along a section M-M in fig. 4 (a) according to embodiment 2 of the present application;

FIG. 14 (a) is a cross-sectional view of a double link plate assembly taken along the line M-M in FIG. 4 (a) according to example 2 of the present application;

FIG. 14 (b) shows S in FIG. 14 (a) ₂ A partial enlargement of the area;

FIG. 14 (c) is S in FIG. 14 (a) in another implementation ₂ Local placement of regionsAnd (4) large graphs.

Wherein, in the reference numerals,

other techniques

10 a-a first processor circuit package structure;

100 a-a circuit board;

310 a-a central processor;

400 a-line;

10a' -connector;

10 b-a second processor circuit package structure;

100 b-a circuit board;

310 b-a central processor;

400 b-line;

10b' -a connector;

10 c-a third processor circuit package structure;

100 c-a circuit board;

310 c-a central processor;

400 c-line;

10c' -connector;

10 d-a fourth processor circuit package structure;

100 d-circuit board;

310 d-a central processing unit;

400 d-line;

10d' -connector;

50-a back plate;

400' -a cable;

example 1

1-stacked interconnect architecture;

10-a processor circuit package structure;

100 a-a circuit board;

110 a-plate surface; 111 a-front side; 112 a-reverse side;

200 a-connector;

210 a-a first connector; 220 a-a second connector; 230 a-a third connector;

300 a-electronic components;

310 a-a central processor; 311 a-a first central processor; 312 a-a second central processor; 313 a-a third central processor; 314 a-a fourth central processor;

320 a-memory bank; 321 a-a first memory bank; 322 a-a second memory bank; 323 a-third memory bank; 324 a-fourth stripe;

400 a-routing;

410 a-first layer routing; 411 a-first trace; 412 a-a second trace; 413 a-a third trace; 414 a-fourth trace; 415 a-fifth trace;

420 a-second layer of traces; 421 a-sixth trace; 422 a-electronic component routing;

430 a-third layer routing; 431 a-a seventh trace; 432 a-eighth trace; 433 a-ninth trace; 434 a-tenth trace; 435 a-eleventh trace; 436 a-a twelfth trace; 437 a-thirteenth trace; 438 a-fourteenth trace; 439 a-a fifteenth trace; 440 a-a sixteenth trace; 441 a-seventeenth trace; 442 a-an eighteenth trace; 443 a-nineteenth trace; 444 a-a twentieth trace; 445 a-a twenty-first trace; 446 a-a twenty-second trace;

500 a-a heat sink;

600 a-a heat sink bar;

10 b-a processor circuit package structure;

100 b-a circuit board;

110 b-plate surface; 111 b-front side; 112 b-the reverse side;

200 b-a connector;

210 b-a first connector; 220 b-a second connector; 230 b-a third connector;

300 b-electronic components;

310 b-a central processor; 311 b-a first central processor; 312 b-a second central processor; 313 b-a third central processor; 314 b-a fourth central processor;

320 b-memory bank; 321 b-a first memory bank; 322 b-a second memory bank; 323 b-third stripe; 324 b-a fourth memory bank;

400 b-routing;

410 b-first layer routing; 411b — first trace; 412b — a second trace; 413 a-a third trace; 414 a-fourth trace; 415 b-a fifth trace;

420 b-second layer routing; 421 b-sixth trace; 422 b-electronic component routing;

430 b-third layer routing; 431 b-a seventh trace; 432 b-eighth trace; 433 b-ninth trace; 434 b-a tenth trace; 435 b-eleventh trace; 436 b-a twelfth trace; 437 b-a thirteenth trace; 438 b-a fourteenth trace; 439 b-a fifteenth trace; 440 b-a sixteenth trace; 441 b-a seventeenth trace; 442 b-an eighteenth trace; 443 b-nineteenth trace; 444 b-twentieth trace; 445 b-the twenty-first trace; 446 b-a twenty-second trace;

20-a linking structure;

30-machine frame; 31-upper cover; 32-lower cover; 33-a housing cavity; 34-mounting holes;

40-a radiator;

50-a heat conducting pad;

60-a support assembly;

r-rectangle;

l _h -a horizontal centre line;

l _v -a vertical centre line;

l _s1 -a left side edge;

l _s2 -a right side edge;

l _s3 -an upper side edge;

l _s4 -a lower side edge;

l _c -a center point line;

2, a cabinet;

3-loading space;

second implementation

100a' -a circuit board;

200a' -connectors;

210a' -a first connector; 220a' -a second connector; 230a' -a third connector;

300a' -electronic components;

310a' -a central processing unit; 311a' -a first central processor; 312a' -a second central processor; 313a' -a third central processing unit; 314a' -a fourth central processor;

320a' -memory bank; 321a' -a first memory bank;

330a' -a power supply;

430a' -a third layer trace; 431a' -seventh trace; 432a' -eighth trace; 433a' -ninth trace; 434a' -tenth trace;

500a' -management module;

600a' -an editable logic device;

third implementation

10a "-processor circuit package structure;

100a "-circuit board;

200a "-connector;

210a "-first connector; 220a "-a second connector;

300a "-electronics;

310a "-a central processor; 311a "-a first central processor; 312a "-a second central processor;

320a "-memory bank; 321a "-a first memory bank; 322a "-second memory bank;

example 2

10a' "-processor circuit package structure;

100a' -a circuit board;

200a' "-a connector; 210a' "-a first connector; 220a' "-a second connector; 230a' "-a third connector;

300a' -electronic components;

310a' "-a central processor;

320a' -memory bank;

10b' "-processor circuit package structure;

100 b' -a circuit board;

200 b' "-a connector; 210 b' "-a first connector; 220 b' "-a second connector; 230 b' "-a third connector;

300 b' -electronic components;

310 b' "-a central processor;

320 b' -memory bank;

10c' "-processor circuit package structure;

100 c' -a circuit board;

200 c' "-a connector; 210 c' "-a first connector; 220 c' "-a second connector; 230 c' "-a third connector; 240c "-fourth connector; 250 c' -a fifth connector; 260c "-a sixth connector;

300 c' -electronic components;

310 c' "-a central processor;

320 c' "-memory bank;

440' -a connecting portion.

Detailed Description

To make the objects, technical solutions and advantages of the present application more clear, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.

To solve the above problem, the present application provides a stacked interconnect architecture 1 including two or more stacked layered processor circuit package structures. As shown in fig. 2 (a), the connection relationship between the processor circuit packages in the stacked interconnection architecture 1 is described below by taking the adjacent processor circuit packages 10a and 10b as an example. The processor circuit package 10a includes a circuit board 100a, and a cpu 310a and a connector 200a mounted on a surface of the circuit board 100a, wherein the circuit board 100a is parallel to the circuit board 100b in the processor circuit package 10b. The opposite sides of the circuit board 100a and the circuit board 100b are respectively provided with a male connector seat and a female connector seat which are adaptive to each other, and the male connector seat and the female connector seat are correspondingly inserted in the direction perpendicular to the board surface. Any adjacent processor circuit package structures in the stacked interconnect architecture 1 are connected as described above to form a connection structure (not shown) that connects the individual processor circuit package structures in series. In the stacked interconnection architecture 1, two cpus in a certain processor circuit package structure are electrically connected through the traces in the processor circuit package structure, and for two cpus (e.g., the cpu 310a and the cpu 310 b) respectively located in two processor circuit package structures, the electrical connection is realized through the traces and the connection structures in the two processor circuit package structures.

The electrical connection is an interconnection relationship which is established between two central processing units in a stacked interconnection architecture and is used for realizing data communication between the central processing units, and the electrical connection is used for realizing signal interaction and signal transmission between the two central processing units. The electrical connection between the central processing units may be an electrical connection between one central processing unit and another central processing unit, or an electrical connection between one central processing unit and another plurality of central processing units. The electrical connection between the central processing units can also be that one of the central processing units is electrically connected with the other central processing unit respectively so as to realize the independent electrical connection between every two central processing units in all the central processing units.

Compared with other technical solutions for realizing circuit board connection, for example, as shown in fig. 2 (b) and fig. 2 (c), other technical solutions adopt a framework of "2 4P package structures +1 or 2 backplates 50". 4 cpus 310a are mounted on the circuit board 100a to form the processor circuit package 10a, and 4 cpus 310b are mounted on the circuit board 100b to form the processor circuit package 10b. The processor circuit package structure 10a and the first processor circuit package structure 10b are vertically stacked, and the processor circuit package structure 10a is plugged into the backplane 50 through the connector 10a 'and the processor circuit package structure 10b' in a manner that the plugging direction is parallel to the board surface of the circuit board 100a (or the circuit board 100 b). The central processors 310a/310b are connected to corresponding connectors 10a '/10b' by traces 400a and 400b, respectively, to form an 8P interconnect server. This type of interconnect structure has a height of about 4U, where U is 44.5mm, where the height of the interconnect structure refers to the dimension of the stacked interconnect structure in the direction perpendicular to the plane of the board.

In the present application, the stacked interconnection architecture 1 compares the schemes shown in fig. 2 (b) and fig. 2 (c), and at first, according to the scheme of the present application, a connection structure is formed by the connector and the processor circuit packaging structure, and then the electrical connection between the central processing units on different processor circuit packaging structures can be realized by the in-board routing of the processor circuit packaging structure and the connection structure, so that the structure of the interconnection architecture is simplified (no extra back panel is needed), and the cost of the interconnection architecture is reduced. Secondly, according to the scheme of this application, optimized the overall arrangement position of connector among the treater circuit packaging structure, shortened and homogenized the distance between connector and the inboard electronic components, and then be convenient for integrate the line of walking between connector and the electronic components in the circuit board, improve treater circuit packaging structure integrated level, reduce the height of interconnection framework. Finally, according to the scheme of the application, the connectors are located between the processor circuit packaging structures, the processor circuit packaging structures can be stably supported by using a small number of connectors, an additional supporting structure is not required to be arranged, the structure of the interconnection framework is further simplified, the height of the interconnection framework is reduced to 1U-2U, and the space occupied by the 8P server is reduced.

Example 1

Fig. 3 (a) shows a usage scenario of the layer interconnection architecture 1 in embodiment 1 of the present application. Fig. 3 (b) shows a structure diagram of the stacked interconnect architecture 1 in embodiment 1 of the present application.

As shown in fig. 3 (a), a plurality of stacked loading spaces 3 are formed in the cabinet 2, and the loading spaces 3 are used for loading servers, that is, the stacked interconnection architecture 1 in the present application, so that they form a server group. It will be appreciated that the height and number of the loading spaces 3 can be adjusted adaptively according to the desired loaded servers, for example, the height of the servers in fig. 3 (a) is 2U, 2U and 4U, and the height of the loading spaces 3 in the cabinet 2 is 2U, 2U and 4U.

As shown in fig. 3 (b), in some embodiments of the present application, the stacked interconnect architecture 1 includes 2 processor circuit package structures, specifically, a processor circuit package structure 10a, a processor circuit package structure 10b, and a subrack 30. Specifically, frame 30 includes an upper cover 31 and a lower cover 32, with an accommodating cavity 33 formed between upper cover 31 and lower cover 32 for accommodating stacked processor circuit package structures.

Specifically, the processor circuit package structure 10a includes a circuit board 100a, a connector 200a, and an electronic component 300a, and the circuit board 100a is a printed circuit board for mounting the electronic component. The connector 200a and the electronic component 300a are mounted on the board surface 110a of the circuit board 100 a. Similarly, the processor circuit package structure 10b includes a circuit board 100b, a connector 200b, and an electronic component 300b, and the circuit board 100b is a printed circuit board for mounting the electronic component. The connector 200b and the electronic component 300b are mounted on the board surface 110b of the circuit board 100b. The board surface 110a is parallel to the board surface 110b, and the plugging direction of the connector 200a and the connector 200b is perpendicular to the board surface 110a (the board surface 110 b). The plugging direction refers to a direction in which two connectors move relative to each other when one connector is plugged with the adaptive connector. The connector 300a on the processor circuit package structure 10a and the connector 300b on the processor circuit package structure 10b are correspondingly plugged to each other to form 3 connection structures 20 of the stacked interconnection architecture 1 at the connector 200a and the connector 200b. The connection structure 20 is formed by connecting a connector and a circuit board in series, and is used for stringing up the processor circuit package structures stacked in parallel to achieve the mutual communication of electronic components on different processor circuit package structures (as shown in fig. 3 (b)).

One central processing unit 310a and another central processing unit 310a in the processor circuit package structure 10a are electrically connected through the traces in the processor circuit package structure 10a. Similarly, one central processing unit 310b in the processor circuit package structure 10b is electrically connected to another central processing unit 310b through the traces in the processor circuit package structure 10b. The electrical connection between one cpu 310a in the processor circuit package structure 10a and another cpu 310b in the processor circuit package structure 10b is realized through the traces in the processor circuit package structure 10a, the traces in the processor circuit package structure 10b, and the connection structure 20.

Above-mentioned range upon range of interconnection framework 1, at first, has optimized the overall arrangement position of connector among the treater circuit packaging structure, has shortened and homogenized the distance between connector and the inboard electronic components, and then is convenient for integrate the line of walking between connector and the electronic components in the circuit board, improves treater circuit packaging structure integrated level, shortens and walks the line length, reduces the link loss, improves signal rate. Secondly, the electrical connection between the central processing units on different processor circuit packaging structures can be realized through the wiring in the processor circuit packaging structure plate and the connecting structure 20, the connector is positioned between the processor circuit packaging structures and can be used for supporting the processor circuit packaging structures, no additional supporting structure is needed to be arranged, and the structure of the interconnection framework is further simplified. Finally, the circuit boards are not connected by using a back plate, so that the height and the cost of the circuit packaging structure of the processor are reduced. Specifically, in the above stacked interconnection architecture 1, the height of the 8P interconnection servers can be controlled to be 2U, so as to improve the space utilization rate of the cabinet 2, and 16 8P servers can be distributed in the standard-height cabinet 2. Compared with other 8P servers with the height of 4U/6U/8U, the number of the computing nodes of the server group loaded with the interconnection architecture in the application can be increased by 2-4 times.

In some embodiments of the present application, the connectors 200a and 200b are plug-type connectors. For example, connector 200a is a plug and connector 200b is a socket to which the plug is adapted. The connector 200a and the connector 200b are respectively crimped to the circuit board 100a and the circuit board 100b by a crimping process. In other alternative embodiments, the connectors 200a and 200b are soldered to the circuit boards 100a and 100b, respectively, by a soldering process.

In embodiment 1 of the present application, the connection structure 20 includes a connector 200a and a connector 200b.

Before describing the connection relationship between the processor circuit package structure 10a and the processor circuit package structure 10b in the stacked interconnect architecture 1, it is necessary to first describe the structure of the single processor circuit package structure clearly. As can be seen from fig. 3, the specific structures of the processor circuit package structure 10a and the processor circuit package structure 10b are the same, and the arrangement directions of the two structures are different, and the specific structure of the processor circuit package structure 10a will be described in detail below with reference to fig. 4 (a) and 4 (b) by taking the processor circuit package structure 10a as an example. Fig. 4 (a) is a top view of a processor circuit package structure 10a in the stacked interconnect architecture 1 according to embodiment 1 of the present application. Fig. 4 (b) shows the distribution of the cpus 310a in fig. 4 (a).

As shown in fig. 4 (a), in some embodiments of the present application, in the processor circuit package structure 10a, the electronic component 300a includes a central processing unit 310a and a memory bank 320a, and the memory bank 320a is disposed on two opposite sides of the central processing unit 310a. It is understood that the positions of the connector 200a and the electronic component 300a in the board surface 110a in fig. 4 (a) merely represent the projection of the connector 200a and the electronic component 300a on the board surface 110a when the connector 200a and the electronic component 300a are mounted on the circuit board 100a, and are not a specific limitation of the board surface 110a in the circuit board 100a of the connector 200a and the electronic component 300 a. That is, in the present application, the connector 200a is mounted on the same side of the circuit board 100a as the electronic component 300a, or the connector 200a is mounted on one side of the circuit board 100a, and the electronic component 300a is mounted on the other side of the circuit board 100a, or the connector 200a is mounted on both sides of the circuit board 100a, and the position where the electronic component 300a is mounted is not particularly limited, or the electronic component 300a is mounted on both sides of the circuit board 100a, and the position where the connector 200a is mounted is not particularly limited.

In some embodiments of the present application, as shown in fig. 4 (a), the cpu 310a includes a first cpu 311a, a second cpu 312a, a third cpu 313a and a fourth cpu 314a arranged in 2 rows and 2 columns in a sequential array in a consistent posture. The connector 200a includes a first connector 210a, a second connector 220a, and a third connector 230a. The length of the wire between the first connector 210a and the first cpu 311a, the length of the wire between the first connector 210a and the third cpu 313a, the length of the wire between the second connector 220a and the first cpu 311a, the length of the wire between the second connector 220a and the second cpu 312a, the length of the wire between the second connector 220a and the third cpu 313a, the length of the wire between the second connector 220a and the fourth cpu 314a, the length of the wire between the third connector 230a and the second cpu 312a, and the length of the wire between the third connector 230a and the fourth cpu 314a are equal. In fig. 4 (a), the traces are not shown, and the length of the trace refers to the size of the trace extending trace.

In the processor circuit package structure 10a, the lengths of the wires routed between the first connector 210a, the second connector 220a, and the third connector 230a and the corresponding central processing units are all equal, so that the wires in different circuit boards can be arbitrarily collocated to ensure that the lengths of the wires routed between any two central processing units in the stacked interconnection architecture 1 are all equal, and the difficulty in planning the routing path between the central processing units is reduced.

It can be understood that, when the distribution positions of the cpus and the connectors in the circuit package structure of the processor are laid out, how to ensure that the lengths of the two cpus passing through the traces in the circuit board are equal to each other in the case of aggregation distribution as much as possible should be considered to equalize the signal transmission effect between the cpus. The two cpus can be two cpus in the same processor circuit package structure or two cpus in different processor circuit package structures. In some embodiments of the present invention, as shown in fig. 4 (b), the center point of the first cpu 311a, the center point of the second cpu 312a, the center point of the third cpu 313a, and the center point of the fourth cpu 314a are distributed at 4 vertices of the rectangle R on the board surface 110a. For convenience of description, as shown in fig. 4 (b), a straight line passing through the midpoints of both vertical sides of the rectangle R is defined as a horizontal center line l _h Meanwhile, a straight line passing through the midpoints of two horizontal sides of the rectangle R is defined as a vertical center line l _v 。

Further, depending on the position of the connector 200a on the circuit board 100a, the connector 200a may include two side connectors and one middle connector. The middle connectors are distributed in the center of the rectangle R (the center of the middle connector is coincident with the center of the rectangle R), and the side connectors are respectively arranged on two sides of the middle connectors. Specifically, as shown in fig. 4 (a), the intermediate connector is a second connector 220a located at the center of the rectangle R. The two side connectors include a first connector 210a and a third connector 230a. Wherein the first connector 210a and the third connector 230a are along the horizontal center line l _h Distributed from left to right in sequence.

It is understood that, since the second connector 220a is disposed at the center of the rectangle R (the center of the connector 220a coincides with the center of the rectangle R), the cpu 310a adjacent to the second connector 220a includes the first cpu 311a, the second cpu 312a, the third cpu 313a and the fourth cpu 314a. The first connector 210a is disposed at the left side of the second connector 220a, and therefore the cpu 310a adjacent to the first connector 210a includes a first cpu 311a and a third cpu 313a. The third connector 230a is disposed on the right side of the second connector 220a, so that the cpu 310a adjacent to the third connector 230a includes the second cpu 312a and the fourth cpu 314a.

In the scheme of the application, the central processing unit is arranged in a mode of distributing the central array of the central processing unit on four vertexes of the rectangular R, and the connector is sequentially arranged on the horizontal center line l of the rectangular R _h The distance between each connector and the adjacent central processing unit is approximately the same, and the routing length between the connector and the adjacent central processing unit is ensured to be basically consistent.

Fig. 4 (c) shows a distribution scheme of the central processing units and the connectors, different from the present application, in order to achieve approximately equal routing lengths between the connectors and the central processing units, the package structure of the scheme includes two central processing units that are distributed in parallel on the circuit board, and the connectors are disposed on one side of a central connection line of the two central processing units and have approximately equal distances from the centers of the two central processing units. As shown in fig. 4 (c), the technical solution adopts a structure of "4 2P package structures +1 backplane 50'". Specifically, 2 cpus 310a are mounted on the circuit board 100a to form a first processor circuit package structure 10a,2 cpus 310b are mounted on the circuit board 100b to form a second processor circuit package structure 10b,2 cpus 310c are mounted on the circuit board 100c to form a third processor circuit package structure 10c, and 2 cpus 310d are mounted on the circuit board 100d to form a fourth processor circuit package structure 10d. The first processor circuit package structure 10a, the second processor circuit package structure 10b, the third processor circuit package structure 10c and the fourth processor circuit package structure 10d are vertically stacked, and the first processor circuit package structure 10a is plugged into the backplane 50 through the connector 10a ', the second processor circuit package structure 10b through the connector 10b', and the third processor circuit package structure 10c through the connector 10c 'and the fourth processor circuit package structure 10d through the connector 10d' in a manner that the plugging direction is parallel to the board surface of the circuit board 100a (or 100 b/100 c/100 d). Central processors 310a/310b/310c/310d connect to connectors 10a '/10b'/10c '/10d' via traces 400a/400b/400c/400d to form an 8P interconnect server. The routing 400a/400b/400c/400d of the interconnection architecture is basically equal, but the interconnection architecture is as high as 6U due to the fact that the interconnection architecture comprises 4 vertically stacked processor circuit packaging structures, and meanwhile, due to the fact that the backboard circuit is arranged on the backboard, the routing between the two central processing units is difficult to be completely identical, and further data transmission difference between the different central processing units is large.

In the above-mentioned processor circuit package structure, compared with the scheme shown in fig. 4 (c), since the connector is provided on the board surface for mounting the central processing units, the distances between the connector and each central processing unit can be approximately equal by adjusting the position of the connector in the board surface. The connector and the central processing unit are arranged equidistantly without sacrificing the height of the interconnection architecture, and integration of the interconnection architecture is facilitated.

In order to improve the stability of the overall structure of the processor circuit package structure 10a, so as to improve the stress balance of the stacked interconnect structure 1, and further prolong the service life of the stacked interconnect structure 1, in some embodiments of the present application, the distances between the two side connectors and the middle connector are the same. That is, the first connector 210a, the second connector 220a and the third connector 230a are equally spaced.

In order to further improve the stress balance of the processor circuit package structure in the stacked interconnection architecture 1, and to reduce the layout difficulty of the routing between the connector 200a and the central processor 310a with the stability of the overall structure of the processor circuit package structure 10a, in some implementations of the present disclosure, the two side connectors and the middle connector are symmetrically distributed with respect to the side of the rectangle R therebetween.

Specifically, as shown in fig. 4 (b), the first connector 210a, the second connector 220a and the third connector 230a are distributed on the horizontal center line l of the rectangle R _h The above step (1); the first connector 210a and the second connector 220a are opposite to the left side l of the rectangle R _s1 Symmetrically distributed, the second connector 220a and the third connector 230a are opposite to the right side l of the rectangle R _s2 And are symmetrically distributed.

In other alternative implementations, the first connector 210a, the second connector 220a and the third connector 230a may be distributed on the vertical centerline l of the rectangle R _v C, removing; the first connector 210a and the second connector 220a are opposite to the upper side l of the rectangle R _s3 Symmetrically distributed, the second connector 220a and the third connector 230a are opposite to the lower side l of the rectangle R _s4 And are symmetrically distributed.

In some embodiments of the present application, as shown in fig. 4 (a), the memory bank 320a includes a first memory bank 321a corresponding to the first cpu 311a, a second memory bank 322a corresponding to the second cpu 312a, a third memory bank 323a corresponding to the third cpu 313a, and a fourth memory bank 324a corresponding to the fourth cpu 314a, and the memory bank 320a corresponding to the cpu 310a is disposed on two opposite sides of the cpu 310a. For example, the first memory bank 321a is disposed on the left and right sides of the first central processor 311 a. In other alternative embodiments, the first memory bank 321a is arranged side by side on the left side (or right side) of the first central processor 311 a. Since the memory bank 320a is in communication with the cpu 310a through the electronic component traces, and the electronic component traces are generally located in the region between the memory bank 320a and the cpu 310a, the traces between the connector 200a and the cpu 310a and the traces between the cpu 310a should be arranged to bypass the memory bank 320a and the region between the memory bank 320a and the cpu 310a as much as possible.

After describing the specific structure of the processor circuit package structure 10a, in order to clearly show the principle of the stacked interconnect architecture 1, the present application needs to further describe the traces in the processor circuit package structure 10a. The circuit layout scheme in the processor circuit package structure 10a and the circuit layout scheme in the processor circuit package structure 10b in the stacked interconnect architecture 1 according to embodiment 1 of the present application will be described in detail below with reference to fig. 5 (a) to 8.

Fig. 5 (a) is a schematic diagram of a first layer of traces 410a between electronic components 310a in a processor circuit package structure 10a according to embodiment 1 of the present application; fig. 5 (b) is a schematic diagram of a first layer of traces 410b between electronic components 310b in a processor circuit package structure 10b according to embodiment 1 of the present application; fig. 5 (c) is a schematic diagram of a second layer of traces 420a between electronic components 310a in another processor circuit package structure 10a according to embodiment 1 of the present application; fig. 5 (d) is a schematic view of second layer traces 420b between electronic components 310b in another processor circuit package structure 10b according to embodiment 1 of the present application; fig. 5 (e) is a schematic diagram of a third layer of traces 430 between the cpu 310a and the connector 200a in the processor circuit package structure 10a according to embodiment 1 of the present application; fig. 5 (f) is a schematic view of a third layer of traces 430 between the cpu 310b and the connector 200b in the processor circuit package structure 10b according to embodiment 1 of the present application.

As shown in fig. 5 (a), the number of the first memory banks 321a is 8, wherein 4 first memory banks 321a are sequentially disposed on the left side of the first central processor 311a along the direction away from the first central processor 311a, and the other 4 first memory banks 321a are sequentially disposed on the right side of the first central processor 311a along the direction away from the first central processor 311 a. Similarly, the number of the second storage bar 322a corresponding to the second central processing unit 312a, the third storage bar 323a corresponding to the third central processing unit 313a, and the fourth storage bar 324a corresponding to the fourth central processing unit 314a are the same as the number of the first storage bars 321a corresponding to the first central processing unit 311a, and the distribution positions of the first storage bars 321a relative to the corresponding central processing units 310a are the same, which is not described herein again.

Similarly, as can be seen from fig. 5 (b), in the processor circuit package structure 10b, the electronic component 300b includes a central processing unit 310b and a memory bank 320b, and the memory bank 320b is disposed on two opposite sides of the corresponding central processing unit 310b. The central processor 310b includes a first central processor 311b, a second central processor 312b, a third central processor 313b and a fourth central processor 314b. The arrangement of the central processing units 310b is the same as that of the central processing units 310a, and the distribution positions of the central processing units 310b correspond to those of the central processing units 310a, which are not described herein again.

Similarly, as shown in fig. 5 (b), the first memory bank 321b corresponding to the first cpu 311b, the second memory bank 322b corresponding to the second cpu 312b, the third memory bank 323b corresponding to the third cpu 313b, and the fourth memory bank 324b corresponding to the fourth cpu 314b. The arrangement of the memory banks 320b is the same as that of the memory banks 320a, and the distribution positions of the memory banks 320b correspond to those of the memory banks 320a, which is not described herein again.

Since any two cpus 310a in the processor circuit package structure 10a can be electrically connected independently, that is, any two cpus 310b in the processor circuit package structure 10b, and one cpu 310a on the processor circuit package structure 10a and one cpu 310b on the processor circuit package structure 10b can be electrically connected independently. In order to achieve independent electrical connection between any two cpus 310a in the processor circuit package 10a, as shown in fig. 5 (a) to 5 (f), in some embodiments of the present application, the processor circuit package 10a further includes a trace 400a, and the processor circuit package 10b further includes a trace 400b. The processor circuit package 10a realizes the electrical connection between any two cpus 310a in the processor circuit package 10a through the trace 400 a. The processor circuit package 10b realizes the electrical connection between any two cpus 310b in the processor circuit package 10b through the trace 400b. The stacked interconnect architecture 1 realizes the electrical connection between one central processing unit 310a on the processor circuit package 10a and one central processing unit 310b on the processor circuit package 10b through the connection structure 20 composed of the trace 400a, the connector 200b, the trace 400b, and the like. The trace 400a may be a printed circuit printed in the circuit board 100a, or may be a high-speed cable located between the central processors 310a or between the central processors 310a and the connector 200 a.

As shown in fig. 5 (a) to 5 (d), in some embodiments of the present application, when the traces 400a in the processor circuit package structure 10a are printed lines, the traces 400a include a first layer of traces 410a (see fig. 5 (a)) and a second layer of traces 420a (see fig. 5 (c)), and the traces 410a and the second layer of traces 420a are electrically connected between any two cpus 310a and between a cpu 310a and a memory bank 320a in the processor circuit package structure 10a. The trace 400b includes a first layer of trace 410b (see fig. 5 (b)) and a second layer of trace 420b (see fig. 5 (d)), and the electrical connection between any two cpus 310b and between a cpu 310b and a memory bar 320b in the processor circuit package 10b is achieved through the first layer of trace 410b and the second layer of trace 420 b. It is to be understood that, in the present application, the first layer of traces 410a, the second layer of traces 420a, the first layer of traces 410b, the second layer of traces 420b, and the later-mentioned third layer of traces 430a (as shown in fig. 5 (e)) and third layer of traces 430b (as shown in fig. 5 (f)) refer to traces distributed in a certain layer of the circuit board, and are not traces in the same height interval of the circuit board, where a layer may be a two-dimensional planar structure or a three-dimensional stereoscopic structure.

As shown in fig. 5 (a), the first layer of traces 410a is used for connecting any two adjacent cpus 310a mounted on the circuit board 100a, and for connecting two cpus 310a on one diagonal of the rectangle R. In the processor circuit package structure 10a, the first layer of traces 410a includes a first trace 411a, a second trace 412a, a third trace 413a, a fourth trace 414a, and a fifth trace 415a.

The first trace 411a bypasses the first storage bar 321a and the second storage bar 322a between the first cpu 311a and the second cpu 312a from a position closer to the peripheral side of the circuit board 100a (the top of the first storage bar 321a and the top of the second storage bar 322a on the drawing shown in fig. 5 (a)) to communicate the first cpu 311a and the second cpu 312a. The second trace 412a is used for connecting the first cpu 311a and the third cpu 313a. The third trace 413a passes through the second connector 220a and the third storage bar 323a and the fourth storage bar 324a to communicate the first central processor 311a and the fourth central processor 314a. In other alternative embodiments, the third trace 413a may also be disposed in a manner that the third trace 413a passes through between the second connector 220a and the first storage bar 321a and the second storage bar 322a to communicate the first cpu 311a and the fourth cpu 314a. The fourth trace 414a bypasses the third storage bar 323a and the fourth storage bar 324a between the third cpu 313a and the fourth cpu 314a from a position closer to the peripheral side of the circuit board 100a (the bottom of the third storage bar 323a and the bottom of the fourth storage bar 324a on the drawing surface shown in fig. 5 (a)) to communicate the third cpu 313a and the fourth cpu 314a. The fifth trace 415a is used to connect the second cpu 312a and the fourth cpu 314a.

For the circuit board 300b, similarly, the first layer of traces 410b is used for connecting any two adjacent cpus 310b mounted on the circuit board 100b and for connecting two cpus 310b on one diagonal of the rectangle R. As shown in fig. 5 (b), in the processor circuit package structure 10b, the first layer of trace 410b includes a first trace 411b, a second trace 412b, a third trace 413b, a fourth trace 414b and a fifth trace 415b, and the first layer of trace 410b and the first layer of trace 410a have the same structure, which is not described herein again.

As shown in fig. 5 (c), in the processor circuit package structure 10a, the second layer of traces 420a is used to implement two cpus 310a on the other diagonal of the rectangle R and connect the cpus 310a with the corresponding memory bank 320a. The second layer trace 420a includes a sixth trace 421a and an electronic component trace 422a. The sixth trace 421a passes through the second connector 220a and the third and fourth banks 323a and 324a to communicate the second central processing unit 312a and the third central processing unit 313a. In other alternative embodiments, the sixth trace 421a passes through between the second connector 220a and the first storage bar 321a and the second storage bar 322a to communicate the second cpu 312a and the third cpu 313a. The electronic component routing 422a communicates the cpu 310a with its corresponding storage bar 320a.

In order to reduce the space occupied by other traces to provide a distribution area for the wider range connector 200a, as shown in fig. 5 (c), in some embodiments of the present invention, the electronic traces 422a are distributed in the area between the cpu 310a and the memory bank 320a.

Similarly, as shown in fig. 5 (d), in the processor circuit package structure 10b, the second layer of traces 420b is used to electrically connect the two cpus 310b on the other diagonal line of the rectangle R and connect the cpus 310b and the memory bank 320b. The second layer trace 420b includes a sixth trace 421b and an electronic component trace 422b, and the second layer trace 420b and the second layer trace 420a have the same structure, which is not described herein again.

The first layer of routing and the second layer of routing are reasonable in layout, occupy fewer board surfaces of the circuit board, share the same layer of routing between the central processing unit and the storage strip and partial routing between the central processing unit, do not need to provide a layer for routing between the central processing unit and the storage strip again, and reduce the number of printing layers in the circuit board. Meanwhile, the processor circuit package structure 10a and the processor circuit package structure 10b including the first layer of traces and the second layer of traces can also basically ensure that the lengths of the traces between one central processing unit 310a in the processor circuit package structure 10a and one central processing unit 310b in the processor circuit package structure 10b are basically equal under the condition that the electrical connection between the central processing units in the board is satisfied. Therefore, the stacked interconnection architecture 1 does not have the situation that the routing between the cpus on different boards is too long or too short, so that the operation capability of each cpu in the entire stacked interconnection architecture 1 is balanced, and the difference of data transmission between the cpus is reduced.

In some embodiments of the present application, the trace 400a includes a third layer trace 430a, and the trace 400b includes a third layer trace 430b. The central processing unit 310a in the processor circuit package structure 10a and the central processing unit 310b in the processor circuit package structure 10b are electrically connected through the third layer trace 430a, the connection structure 20 and the third layer trace 430b.

As can be seen from fig. 5 (e) and fig. 5 (f), the number of the third layer traces 430a between any one of the cpus 310a on the processor circuit package 10a and the connector 200a is the same as the number of the cpus 310 on the processor circuit package 10b. For example, the processor circuit package 10a has a first cpu 311a and a connector 200a mounted thereon, and the processor circuit package 10b has 4 cpus 310b mounted thereon. In order to realize the interconnection between the first cpu 311a and the 4 cpus 310b of the processor circuit package structure 10b through the connector 200a mounted on the processor circuit package structure 10a and the connector 200b mounted on the processor circuit package structure 10b, 4 traces are disposed between the first cpu 311a and the connector 200a, and each trace corresponds to one of the cpus 310b of the processor circuit package structure 10b.

As shown in fig. 5 (e), in the processor circuit package structure 10a, the third layer trace 430a includes: a seventh trace 431a and an eighth trace 432a, one end of which is connected to the first cpu 311a, and the other end of which is led to the first connector 210a from a position (the bottom of the first bar 321a on the drawing shown in fig. 5 (e)) farther from the peripheral side of the circuit board 100a, bypassing the first bar 321 a; a ninth trace 433a and a tenth trace 434a, one end of which is connected to the first cpu 311a, and the other end of which is led to the second connector 220a from a position further away from the peripheral side of the circuit board 100a (the bottom of the first storage bar 321a on the drawing surface shown in fig. 5 (e)) bypassing the first storage bar 321 a; eleventh and twelfth traces 435a and 436a, one end of which is connected to the second cpu 312a, and the other end of which is led to the second connector 220a from a position further away from the peripheral side of the circuit board 100a (e.g., the bottom of the second storage bar 322a on the drawing surface shown in fig. 5 (e)) bypassing the second storage bar 322 a; a thirteenth routing 437a and a fourteenth routing 438a, one end of which is connected to the second cpu 312a, and the other end of which leads from a position further away from the peripheral side of the circuit board 100a (the bottom of the second storage bar 322a on the drawing surface shown in fig. 5 (e)) to the third connector 230a bypassing the second storage bar 322 a; a fifteenth trace 439a and a sixteenth trace 440a, one end of which is connected to the third cpu 313a, and the other end of which is led to the first connector 210a from a position further away from the peripheral side of the circuit board 100a (the top of the third storage bar 323a on the drawing surface shown in fig. 5 (e)) bypassing the third storage bar 323 a; seventeenth and eighteenth routing lines 441a and 442a, one end of which is connected to the third cpu 313a, and the other end of which is led from a position further away from the peripheral side of the circuit board 100a (the top of the third storage bar 323a on the drawing surface shown in fig. 5 (e)) around the third storage bar 323a toward the second connector 220 a; a nineteenth trace 443a and a twentieth trace 444a that are connected to the fourth cpu 314a at one end and lead from a position further away from the peripheral side of the circuit board 100a (the top of the fourth bar 324a on the plane of the drawing shown in fig. 5 (e)) around the fourth bar 324a to the second connector 220a at the other end; one end is connected to the fourth cpu 314a, and the other end is led to the twenty-first trace 445a and the twenty-second trace 446a of the third connector 230a from a position (the top of the fourth storage bar 324a on the drawing shown in fig. 5 (e)) farther from the peripheral side of the circuit board 100a, bypassing the fourth storage bar 324 a.

Similarly, as shown in fig. 5 (f), in the processor circuit package structure 10b, the third layer of traces 430b includes a seventh trace 431b, an eighth trace 432b, a ninth trace 433b, a tenth trace 434b, an eleventh trace 435b, a twelfth trace 436b, a thirteenth trace 437b, a fourteenth trace 438b, a fifteenth trace 439b, a sixteenth trace 440b, a seventeenth trace 441b, an eighteenth trace 442b, a nineteenth trace 443b, a twentieth trace 444b, a twenty-first trace 445b, and a twenty-second trace 446b, and the third layer of traces 430b and the third layer of traces 430a have the same structure, which is not repeated herein.

In some embodiments of the present application, the connector 200a is connected to the cpus 310a in the processor circuit package structure 10a through a trace (not shown) in the circuit board 100a, so as to avoid plugging cables and reduce the installation, debugging and maintenance difficulty.

Figure 5 (g) shows another electrical connection scheme between the central processors on the two processor circuit package structure. As shown in fig. 5 (g), it adopts an architecture of "2P 4P package structure + cable". 4 cpus 310a are mounted on the circuit board 100a to form the first processor circuit package 10a, and 4 cpus 310b are mounted on the circuit board 100b to form the second processor circuit package 10b. The first processor circuit package structure 10a and the second processor circuit package structure 10b are interconnected by a cable 400' to form an 8P interconnection server. The interconnection architecture needs 16 cables 400' to be capable of realizing interconnection of the central processing units on the two processor circuit packaging structures, so that the interconnection architecture is high in cost and high in cable plugging difficulty.

In the above processor circuit packaging structure, in order to prevent the crossing of the wires in the circuit board 100a, the wires 400a are divided into multiple layers, and all the wires between the connector and the electronic components are reasonably arranged in the circuit board, so that the use of cables is avoided, and the overall structure is simplified. Meanwhile, the areas of the first layer of wires, the second group of wires and the third layer of wires are overlapped, so that the processing difficulty and the installation difficulty of the wires in the processor circuit packaging structure 10a and the processor circuit packaging structure 10b are reduced, and the cost is saved.

After the circuit layout scheme in the processor circuit package structure 10a and the circuit layout scheme in the processor circuit package structure 10b in the stacked interconnection architecture 1 are described, it can be known that the two cpus 310a in the processor circuit package structure 10a can be electrically connected through the first layer of trace 410a and the second layer of trace 420a in the board, and the cpu 310b in the processor circuit package structure 10b can be electrically connected through the first layer of trace 410b and the second layer of trace 420b in the board.

However, since the number of the connection structures 20 formed by the processor circuit package 10a and the processor circuit package 10b is at least 3, in order to achieve load balancing of the connection structures 20, the present application needs to further describe the communication paths between the central processing units 310a and 310b between the processor circuit package 10a and the processor circuit package 10b. The communication path may be a path selection pattern stored in advance in the controller. That is, the present application also needs to reasonably arrange the specific routing paths between each cpu 310a and each cpu 310b, so as to ensure load balancing of the connector (connection structure) under the condition that the routing between the cpus is substantially equal. Hereinafter, according to the relative positions of the central processing unit 310a and the central processing unit 320a, the third layer of traces 430a in the processor circuit package structure 10a and the third layer of traces 430b in the processor circuit package structure 10b described above are reasonably selected to obtain the communication paths where the central processing unit 310a and the central processing unit 320a have substantially the same traces and the connector loads are substantially balanced. The communication path between the cpu 310a in the processor circuit package 10a and the cpu 310b in the processor circuit package 10b according to embodiment 1 of the present application will be described in detail with reference to fig. 6 (a) to 8.

FIG. 6 (a) is a drawing of this applicationIn embodiment 1, the communication paths between the cpu 310a in the processor circuit package 10a and the cpu 310b in the processor circuit package 10b are opposite; FIG. 6 (b) is a view showing the position of the center line l of the steel plate in example 1 of the present application, which is not opposite to the vertical center line l _v The communication paths between the cpu 310a in the processor circuit package 10a and the cpu 310b in the processor circuit package 10b on the same side; FIG. 6 (c) shows the position of the center line l of the steel plate in example 1 of the present application, which is not opposite to the center line l _h The communication paths between the cpu 310a in the processor circuit package 10a and the cpu 310b in the processor circuit package 10b on the same side; fig. 6 (d) shows the communication paths between the cpu 310a in the processor circuit package 10a and the cpu 310b in the processor circuit package 10b at the diagonal line R in the embodiment 1.

In some embodiments of the present application, for the opposing cpus 310a and 310b, the vertical center line l of the rectangle R on the processor circuit package 10a and the processor circuit package 10b is determined by the third layer of traces 430a on the processor circuit package 10a, the third layer of traces 430b on the processor circuit package 10b, and the vertical center lines l of the rectangles R on the processor circuit package 10a and the processor circuit package 10b _v The lateral connectors on the same side are connected. The cpu 310a and the cpu 310b in opposite positions refer to the cpu 310a and the cpu 310b projected and overlapped on the board 110a after the assembly of the processor circuit package structure 10a and the processor circuit package structure 10b is completed. For example, fig. 6 (a) shows a situation after the processor circuit package structure 10a moves along a direction perpendicular to the board surface 110a, and the first cpu 311a and the first cpu 311b are the cpu 310a and the cpu 310b which are opposite to each other.

As shown in fig. 6 (a), the communication path between the first cpu 311a and the first cpu 311b includes the seventh trace 431a communicating the first cpu 311a and the first connector 210a, then the first connector 210a and the first connector 210b communicating the circuit board 100a and the circuit board 100b, and finally the seventh trace 431b communicating the first connector 210b and the first cpu 311b.

Similarly, a communication path between the second cpu 312a and the second cpu 312b is established through the thirteenth trace 437a, the third connector 230b and the thirteenth trace 437 b.

Similarly, a communication path between the third cpu 313a and the third cpu 313b is established through the fifteenth trace 439a, the first connector 210b and the fifteenth trace 439 b.

Similarly, a communication path between the fourth cpu 314a and the fourth cpu 314b is established through the twenty-first trace 445a, the third connector 230b and the twenty-first trace 445 b.

In some embodiments of the present application, for positions other than opposite but on the vertical centerline l _v The central processing unit 310a and the central processing unit 310b on the same side pass through the third layer of traces 430a on the processor circuit package structure 10a, the third layer of traces 430b on the processor circuit package structure 10b, and the vertical center line l of the rectangle R on the processor circuit package structure 10a and the processor circuit package structure 10b _v The lateral connectors on the same side are connected. For example, fig. 6 (b) shows a situation after the processor circuit package structure 10a moves along a direction perpendicular to the board surface 110a, and the first cpu 311a and the third cpu 313b are located at the vertical center line l in the figure _v The cpu 310a and the cpu 310b on the same side.

As shown in fig. 6 (b), the communication path between the first cpu 311a and the third cpu 313b includes the eighth trace 432a communicating the first cpu 311a and the first connector 210a, the first connector 210a and the first connector 210b communicating the circuit board 100a and the circuit board 100b, and the sixteenth trace 440b communicating the first connector 210b and the third cpu 313b.

Similarly, a communication path between the third cpu 313a and the first cpu 311b is established by the sixteenth trace 440a, the first connector 210b and the eighth trace 432 b.

Similarly, a communication path between the second cpu 312a and the fourth cpu 314b is established through the fourteenth routing line 438a, the third connector 230b and the twenty-second routing line 446 b.

Similarly, a communication path between the fourth cpu 314a and the second cpu 312b is established through the twelfth trace 446a, the third connector 230b and the fourteenth trace 438 b.

In some embodiments of the present application, the location is not relative but is at the horizontal centerline l _h The cpu 310a and the cpu 310b on the same side are connected through the third layer of traces 430a on the processor circuit package structure 10a, the third layer of traces 430b on the processor circuit package structure 10b, and the middle connectors on the processor circuit package structure 10a and the processor circuit package structure 10b. For example, fig. 6 (c) shows a situation after the processor circuit package structure 10a moves along a direction perpendicular to the board surface 110a, and the first cpu 311a and the second cpu 312b are located at the horizontal center line l _h The central processing unit 310a and the central processing unit 310b on the same side.

As shown in fig. 6 (c), the communication path between the first cpu 311a and the second cpu 312b includes: the ninth trace 433a connects the first cpu 311a and the second connector 220a, the second connector 220a and the second connector 220b connect the circuit board 100a and the circuit board 100b, and the eleventh trace 435b connects the second connector 220b and the second cpu 312b.

Similarly, a communication path between the second cpu 312a and the first cpu 311b is established by the eleventh trace 435a, the second connector 220b and the ninth trace 433 b.

Similarly, a communication path between the third cpu 313a and the fourth cpu 314b is established by the seventeenth trace 441a, the second connector 220b and the nineteenth trace 443 b.

Similarly, a communication path between the fourth cpu 314a and the third cpu 313b is established by the nineteenth trace 443a, the second connector 220b and the seventeenth trace 441 b.

In some embodiments of the present application, the cpu 310a and the cpu 310b on the diagonal line of the rectangle R are connected through the third layer of traces 430a on the processor circuit package structure 10a, the third layer of traces 430b on the processor circuit package structure 10b, and the intermediate connectors on the processor circuit package structure 10a and the processor circuit package structure 10b. For example, fig. 6 (d) shows a situation after the processor circuit package structure 10a moves along a direction perpendicular to the board surface 110a, and the first cpu 311a and the fourth cpu 314b are the cpu 310a and the cpu 310b on the diagonal of the rectangle R in the figure.

As shown in fig. 6 (d), the communication path between the first cpu 311a and the fourth cpu 314b includes: the tenth trace 434a connects the first cpu 311a and the second connector 220a, the second connector 220a and the second connector 220b connect the circuit board 100a and the circuit board 100b, and the twentieth trace 444b connects the second connector 220b and the fourth cpu 314b.

Similarly, a communication path between the second cpu 312a and the third cpu 313b is established by the twelfth trace 436a, the second connector 220b and the eighteenth trace 442 b.

Similarly, a communication path between the third cpu 313a and the second cpu 312b is established by the eighteenth trace 442a, the second connector 220b and the twelfth trace 436 b.

Similarly, a communication path between the fourth cpu 314a and the first cpu 311b is established through the twentieth trace 444a, the second connector 220b and the tenth trace 434 b.

In the above stacked interconnection architecture 1, the wiring in the processor circuit packaging structure is uniform, the stress of the circuit board is uniform when the connector is buckled, the number of the central processing units butted by the connector is basically equal, and the wiring lengths between the two central processing units in the processor circuit packaging structure are basically the same, so that the load of the whole stacked interconnection architecture 1 is balanced, and the stability of signal transmission between the central processing units is improved conveniently.

It is understood that, in some embodiments of the present application, the number and the layout of the connectors 200b in the processor circuit package structure 10b are the same as the number and the layout of the connectors 200a in the processor circuit package structure 10a, and detailed description thereof is omitted here. Meanwhile, the electronic component 300b in the processor circuit package structure 10b is not particularly limited in the present application, and any distribution manner of the electronic component 300b that does not interfere with the distribution manner of the connector 200b is within the protection scope of the present application. That is, the connector 200a in the processor circuit package 10a and the connector 200b in the processor circuit package 10b are adaptively arranged to meet the assembly requirements of the processor circuit package 10a and the processor circuit package 10b.

To achieve a balanced arrangement of the stacked interconnect architecture 1, in some embodiments of the present application, the electronic components 300a in the processor circuit package structure 10a are the same number and the layout of the electronic components 300b in the processor circuit package structure 10b is the same.

Fig. 7 is a top view of another processor circuit package structure 10a ' in the stacked interconnection architecture 1 according to embodiment 1 of the present application, wherein a schematic diagram of routing between the connector 200a ' and the cpu 310a ' is shown.

As shown in fig. 7, in an alternative embodiment, the processor circuit package structure 10a 'is different from the processor circuit package structure 10a in that the first connector 210a' and the third connector 230a 'in the processor circuit package structure 10a' are arranged in a different manner from the first connector 210a and the third connector 230a in the processor circuit package structure 10a, which in turn results in a different third layer trace 430a 'in the processor circuit package structure 10a' from the third layer trace 430a in the processor circuit package structure 10a.

As shown in fig. 7, the first connector 210a ', the second connector 220a' and the third connector 230a 'of the processor circuit package structure 10a' are sequentially disposed on the vertical centerline l _v The above. Wherein the second connectors 220a 'are distributed in the center of the rectangle R, and the first connectors 210a' are disposed on the upper side of the second connectors 220aThe third connector 230a ' is provided at the lower side of the second connector 220a ' at the third connector 230a '. The traces between the cpu 310a 'and the side connectors bypass the end of the memory bank 320a' away from the middle connector. For example, the trace 431a ' and the trace 432a ' are connected to the first cpu at one end, and led to the first connector 210a ' from a position closer to the peripheral side of the circuit board 100a (the top of the first storage bar 321a ' on the drawing shown in fig. 7) by bypassing the first storage bar 321a '. The traces between the cpu 310a' and the intermediate connector bypass the end of the memory stick near the intermediate connector. For example, the trace 433a 'and the trace 434a' have one end connected to the first cpu 311a 'and the other end led to the second connector 220a' from a position further away from the peripheral side of the circuit board 100a (the bottom of the first storage bar 321a 'on the drawing surface shown in fig. 7) by bypassing the first storage bar 321 a'.

As can be seen from fig. 7, in the circuit board 100a ' of the processor circuit package structure 10a ', the power supply 330a ', the management module 500a ' and the editable logic device 600a ' are further sequentially disposed on the upper sides (see the orientation in fig. 7) of the central processor 310a ' and the memory bank 320a '. As can be seen, the longitudinal direction (l) of the circuit board 100a _v The extending direction of) is larger, the transverse dimension is smaller, and the first connector 210a ', the second connector 220a' and the third connector 230a 'are arranged along the longitudinal direction in fig. 7 (for example, the first connector 210a', the second connector 220a 'and the third connector 230a' are distributed on the longitudinal center line l _v ) The existing space of the circuit board 100a' can be fully utilized, and meanwhile, the supporting points between the processor circuit packaging structures are distributed in the direction with larger size, and the whole supporting effect can be improved.

Fig. 8 is a top view of a circuit package 10a ″ of a processor in a stacked interconnection architecture 1 according to embodiment 1 of the present application, wherein traces between a connector 200a ″ and a cpu 310a ″ are schematically shown. The present application provides a processor circuit package structure, as shown in fig. 8, a processor circuit package structure 10a "includes a circuit board 100 a", a connector 200a ", and an electronic component 300 a", and the electronic component 300a includes a central processing unit 310a "and a memory bank 310a. Treatment ofIn the circuit package 10a ", the cpu 310 a" includes a first cpu 311a "and a second cpu 312 a", and the connector 200a "includes a first connector 210 a" and a second connector 220a ". For convenience of description, a straight line passing through the center point of the first central processing unit 311a "and the center point of the second central processing unit 312 a" is defined as a center point connecting line l _c (as shown in fig. 8). The first connector 210a "and the second connector 220 a" are distributed in the area between the first CPU 311a "and the second CPU 312 a", and are symmetrically distributed on the center point connecting line l _c On both sides of the base. In addition, the bank 320a "opposite to the cpu is disposed at both sides of the cpu 310 a".

After the description of the structures, the on-board traces, and the communication paths in the plane parallel to the board surface 110a on the processor circuit package 10a and the processor circuit package 10b, since the circuit board 100 includes a pair of opposite board surfaces 110a, it is necessary to further describe the distribution of the connectors 200a and the electronic components 300a in the plane perpendicular to the board surface 110a. The positional relationship and the assembly manner of the processor circuit package structure 10a and the processor circuit package structure 10b in the stacked interconnect architecture 1 in the direction perpendicular to the board surface 110a will be described in detail below with reference to fig. 9 (a) to 12 (b).

Fig. 9 (a) is a cross-sectional view of a anisotropic single connection plate assembly according to example 1, taken along the M-M section in fig. 4 (a). FIG. 9 (b) is a view showing the state of S in FIG. 9 (a) ₁ A close up view of the area. Fig. 10 is a sectional view of a uni-directional junction plate assembly according to example 1 taken along the section M-M in fig. 4 (a). Fig. 11 is a cross-sectional view of the back-off type stacked interconnect structure 1 of embodiment 1 taken along the M-M section in fig. 4 (a). Fig. 12 (a) is a cross-sectional view of a snap-in stacked interconnect structure 1 taken along a section M-M in fig. 4 (a) in embodiment 1. Fig. 12 (b) is a cross-sectional view of a snap-in stacked interconnect structure 1 taken along a section M-M in fig. 4 (a) in embodiment 1.

As shown in fig. 3, the stacked interconnect architecture 1 includes a processor circuit package structure 10a and a processor circuit package structure 10b distributed from top to bottom. Processor circuit package 10a and processor circuit package 10b may be a single board assembly, where the single board assembly is a processor circuit package having a connector on one side of a circuit board. In other alternative embodiments, the processor circuit package structure 10a and the processor circuit package structure 10b may be a single board assembly, or may be a processor circuit package structure with connectors on both sides of the circuit board.

In some embodiments of the present application, for convenience of describing the mounting position of the connector 200a in a plane perpendicular to the board surface 110a, two board surfaces 110a of the circuit board 100a are defined first. In some embodiments of the present application, when the electronic components 300a are mounted on the same board surface 110 of the circuit board 100a, the two board surfaces 110a are distinguished by the actual mounting plane of the electronic components 300a in the processor circuit package structure 10a. For example, as shown in fig. 9a and 9b, when the electronic component 300a is mounted on the upper surface of the circuit board 100a, the board surface on which the electronic component 300a is mounted is defined as a front surface 111a (the upper surface of the circuit board 100a in fig. 9a and 10), and the other board surface 110a is defined as a back surface 112a (the lower surface of the circuit board 100a in fig. 9a and 10).

In other alternative embodiments, when the electronic component 300a is disposed on two board surfaces 110a of the circuit board 100a, one board surface 110a of the circuit board 100a is randomly defined as the front surface 111a, and the other board surface 110a is randomly defined as the back surface 112a.

As shown in fig. 9 (a), in the processor circuit package structure 10a, the first connector 210a, the second connector 220a and the third connector 230a of the connector 200a are sequentially distributed on the back surface 112a of the circuit board 100a from left to right, that is, the processor circuit package structure 10a is a single-board assembly. As shown in fig. 9 (b), the cpu 313a communicates with the bank 323a via the electronic component trace 422a. The cpu 313a communicates with the second connector 220a via the third layer trace 430 a.

As shown in fig. 10, in the processor circuit package structure 10a, the first connector 210a, the second connector 220a and the third connector 230a of the connector 200a are sequentially distributed on the front surface 111a of the circuit board 100a from left to right, that is, the processor circuit package structure 10a is a single-board assembly. The communication between the cpu 310a and the memory bank 320a and between the cpu 310a and the connector 200a are the same as those in fig. 9 (b), and are not described herein again.

Furthermore, the single-connection-board assembly comprises an anisotropic single-connection-board assembly and a homodromous single-connection-board assembly, wherein the electronic component and the connector are respectively arranged on two sides of the circuit board, and the electronic component and the connector are arranged on the same side of the circuit board.

As shown in fig. 9 (a), in the single-board assembly, in the processor circuit package structure 10a, the electronic components 300a are distributed on the front surface 111a of the circuit board 100a, and the first connector 210a, the second connector 220a and the third connector 230a of the connector 200a are distributed on the back surface 112a of the circuit board 100a from left to right in sequence. That is, in the processor circuit package structure 10a, the connector 200a and the electronic component 300a are respectively located on two sides of the circuit board 100a, and thus, the processor circuit package structure in fig. 9 (a) is an anisotropic single-board assembly.

In other embodiments of the present disclosure, the electronic component 300a is disposed on two sides of the circuit board 100a, the connector 200a is disposed on one side of the circuit board 100a, and the processor circuit package structure 10a is an anisotropic single-board assembly.

In the above processor circuit package structure, the connector 200a and the electronic component 300a are respectively disposed on two sides of the circuit board 100a, so that the distribution density of the connector 200a and the electronic component 300a on the board surface 110a is reduced, and the difficulty of assembling the processor circuit package structure into the stacked interconnection architecture 1 is reduced.

Furthermore, as shown in fig. 10, for a single-board assembly, in the processor circuit package structure 10a, the electronic components 300a are distributed on the front surface 111a of the circuit board 100a, and the first connector 210a, the second connector 220a and the third connector 230a of the connector 200a are distributed on the front surface 111a of the circuit board 100a from left to right in sequence. That is, in the processor circuit package structure 10a, the connector 200a and the electronic component 300a are respectively located on the same side of the circuit board 100a, and thus, the processor circuit package structure in fig. 10 is a unidirectional single-board assembly.

In the above processor circuit package structure, the connector 200 and the electronic component 300 are disposed at the same side of the circuit board 100, so that the height of the processor circuit package structure 10a does not exceed the larger height of the connector 200 and the electronic component 300, that is, the height of the processor circuit package structure is the sum of the larger height of the circuit board 100 and the connector 200 and the electronic component 300, the processor circuit package structure occupies a smaller space, and meanwhile, in the packaging process, the packaging difficulty of the side of the processor circuit package structure 10a where the electronic component 300 is not mounted is lower, the packaging difficulty is reduced, and the transportation cost is reduced.

In some embodiments of the present application, as shown in fig. 11, a stacked interconnect architecture 1 includes a layered stacked processor circuit package structure 10a and a processor circuit package structure 10b. Both the processor circuit package 10a and the processor circuit package 10b are anisotropic single board assemblies. The processor circuit package structure 10a and the processor circuit package structure 10b are disposed in a reverse direction, the connector 200a in the processor circuit package structure 10a is located on a side of the circuit board 100a close to the processor circuit package structure 10b, and the connector 200b in the processor circuit package structure 10b is located on a side of the circuit board 100b close to the processor circuit package structure 10a. It will be appreciated that the reverse placement characterizes the different positions of the front faces in the two processor circuit package structures. As shown in fig. 11, the front surface 111a of the circuit board 100a is the upper surface of the circuit board 100a, and the front surface 111b of the circuit board 100b is the lower surface of the circuit board 100b, and the processor circuit package structure 10a and the processor circuit package structure 10b are disposed in opposite directions.

In the above-mentioned stacked interconnection structure 1, the reverse side 112a of the circuit board 100a in the processor circuit package structure 10a faces the circuit board 100b, and the reverse side 112b of the circuit board 100b in the processor circuit package structure 10a faces the circuit board 100a, so that the stacked interconnection structure 1 is a back-buckling structure. That is, the electronic component 300a is disposed outside the circuit board 100a, and the electronic component 300b is disposed outside the circuit board 100b, so that the electronic component 300a and the electronic component 300b can be conveniently mounted and cooled, a large cooling channel and a large mounting space do not need to be reserved, and the height of the whole interconnection framework is reduced. Because electronic components with larger size do not need to be arranged in the space between the inner sides of the circuit board 100a and the circuit board 100b, the height of the space can be reduced, the distance between the circuit board 100a and the circuit board 100b is further reduced, the heights of the connector 200a and the connector 200b after plugging are effectively controlled, signal crosstalk is avoided, and the signal transmission speed and the stability and accuracy of signal transmission are improved. In a 2U machine frame, a processor circuit packaging structure 10a and a processor circuit packaging structure 10b adopt a back-buckling scheme, the connector height is about 5 mm-15 mm, the connector signal crosstalk is small, the integrity of signals in a high-speed serial bus is improved, and the high-speed serial bus is suitable for 10-112 Gbps signal rate.

In some embodiments of the present application, as shown in fig. 12 (a), a stacked interconnect architecture 1 includes a layered stacked processor circuit package structure 10a and a processor circuit package structure 10b. The processor circuit package structure 10a is a unidirectional single board assembly, and the processor circuit package structure 10b is a unidirectional single board assembly. The processor circuit package structure 10a and the processor circuit package structure 10b are disposed in the same direction, the connector 200a in the processor circuit package structure 10a is located on the side of the circuit board 100a close to the processor circuit package structure 10b, and the connector 200b in the processor circuit package structure 10b is located on the side of the circuit board 100b close to the processor circuit package structure 10a. It will be appreciated that co-directional placement characterizes the same location of the front faces in the two processor circuit package structures. For example, as shown in fig. 8, the front surface 111a of the circuit board 100a is the upper surface of the circuit board 100a, and the front surface 111b of the circuit board 100b is the upper surface of the circuit board 100b, or the front surface 111a of the circuit board 100a is the lower surface of the circuit board 100a, and the front surface 111b of the circuit board 100b is the lower surface of the circuit board 100b.

In the above embodiment, the back surface 112a of the circuit board 100a in the processor circuit package structure 10a faces the circuit board 100b, and the front surface 111b of the circuit board 100b in the processor circuit package structure 10a faces the circuit board 100a, so that the stacked interconnection structure 1 is a positive-fit structure. The electronic component 300a is disposed outside the circuit board 100a, and the electronic component 300b is disposed inside the circuit board 100b, that is, the electronic component 300b is accommodated in the space between the circuit board 100a and the circuit board 100b. Therefore, in the interconnection structure, it is also necessary to ensure that the height of the connector 200a and the connector 200b after connection is greater than the height of the electronic component 300 b.

In the above stacked interconnection architecture 1, the connectors 200a, 200b and the electronic components 300b are reasonably arranged, so that the connectors 200a, 200b and 300b can be distributed in the same height space, the connectors 200a and 200b are prevented from occupying extra height space, the components in the interconnection architecture are closely arranged, the length of high-speed signal routing communicated between two processors is shortened, and the height size of the whole architecture is further reduced. In addition, processor circuit package 10a and processor circuit package 10b use a positive-fit scheme, and the connector height is about 44.45mm, which is suitable for signal rates below 56 Gbps.

In some embodiments of the present application, as shown in fig. 12 (b), the heights of the connector 200a and the connector 200b are designed such that the heights of the connected connector 200a and the connected connector 200b are slightly larger than the height of the electronic component 300b on the circuit board 100b (when the electronic component 300b is provided with the auxiliary components such as the heat sink 40 and the thermal pad 50, the heights of the connected connector 200a and the connected connector 200b are slightly larger than the total height of the electronic component 300b and the auxiliary components on the circuit board 100 b). According to the stacked interconnection framework 1, the overall height of the stacked interconnection framework 1 can be effectively reduced by reasonably designing the heights of the connector 200a and the connector 200b, the occupied loading space is reduced, and the loading capacity of the cabinet is improved.

In some embodiments of the present application, in the stacked interconnection architecture 1, the frame 30 is provided with a mounting hole 34 opposite to the position of the storage strip 320a (the storage strip 320 b), when the stacked interconnection architecture 1 works normally, the mounting hole 34 is closed, and when the storage strips need to be plugged and unplugged, the frame 30 does not need to be opened, and only the mounting hole 34 is opened to operate. The stacked interconnection structure 1 described above facilitates detachment of the bank 320a (bank 320 b), and facilitates repair and replacement of the banks in the stacked interconnection structure 1.

Specifically, when the processor circuit package structure 10a and the processor circuit package structure 10b adopt a positive buckling type buckling scheme, the method for detaching the memory bank in the stacked interconnection architecture 1 includes: if the memory bank on the processor circuit packaging structure 10a needs to be maintained, the memory bank of the processor circuit packaging structure 10a can be plugged and unplugged by directly opening the mounting hole 34 on the machine frame 30; if a memory stick on processor circuit package 10b needs to be serviced, then subrack 30 is opened, processor circuit package 10a is removed to expose processor circuit package 10b, and the memory stick on processor circuit package 10b is then inserted and removed.

Specifically, when the processor circuit package structure 10a and the processor circuit package structure 10b adopt the back-type fastening scheme, the method for detaching the memory bank in the stacked interconnection architecture 1 includes: if the memory bank on the processor circuit package structure 10a needs to be maintained, the memory bank of the processor circuit package structure 10a can be plugged and unplugged by directly opening the mounting hole 34 on the machine frame 30, which is opposite to the processor circuit package structure 10 a; if the memory bank on processor circuit package 10b needs to be maintained, the memory bank of processor circuit package 10a can be plugged and unplugged by turning frame 30 180 degrees and opening mounting holes 34 in frame 30 opposite to processor circuit package 10b.

In some embodiments of the present application, the stacked interconnect structure 1 further includes a heat sink 40, the heat sink 40 is disposed on the surface of the cpu 310a and the surface of the cpu 310b, and the heat sink 40 is used for dissipating heat from the cpu 310a and the cpu 320a.

In some embodiments of the present application, the stacked interconnect structure 1 further includes a thermal pad 50, the thermal pad 50 is disposed on the surface of the heat sink 40, and the thermal pad 50 is used for dissipating heat absorbed by the heat sink 40. In the stacked interconnection structure 1, the cpu is attached to the frame 30 through the thermal pad 50 to improve the heat dissipation capability.

In some embodiments of the present application, one side of the thermal pad 50 is attached to the inner side of the frame 30, and the other side of the thermal pad 50 is attached to the surface of the heat sink 40, so as to transfer the heat absorbed by the heat sink 40 from the cpu 310a and the cpu 320a to the frame 30, thereby improving the heat dissipation effect of the stacked interconnect structure 1.

In order to improve the stability of the overlapped structure of the layered stacked processor circuit package structure 10a and the processor circuit package structure 10b, and thus improve the stability of the overall structure of the stacked interconnection architecture 1, in some embodiments of the present application, the stacked interconnection architecture 1 further includes a support component 60. The supporting member 60 is clamped between the upper cover 31 and the lower cover 32, and a clamping groove (not shown) for clamping the circuit board 100a and the circuit board 100b is formed on the supporting member 60.

When support assembly 60 is mounted in subrack 30, and circuit boards 100a and 100b are snapped into the snap slots in support assembly 60, processor circuit package structure 10a and processor circuit package structure 10b are fixed relatively within subrack 30.

Embodiment 1 of the present application still includes a treater circuit packaging structure, including circuit board, connector and install the electronic components including central processing unit on the face of circuit board, the connector is installed in the face, and the grafting direction of connector is perpendicular with the face.

Embodiment 1 of the present application also includes an electronic device including any one of the above-described stacked interconnect structures.

Example 2

Fig. 13 is a sectional view of a 3-plate type stacked interconnect structure 1 of embodiment 2 taken along a section M-M in fig. 4 (a), and fig. 14 (a) is a sectional view of a dual link plate assembly of embodiment 2 taken along a section M-M in fig. 4 (a). FIG. 14 (b) shows S in FIG. 14 (a) ₂ A close up view of the area. FIG. 14 (c) is S in FIG. 14 (a) in another implementation ₂ A close up view of the area.

As shown in fig. 13, the stacked interconnect architecture 1 includes a total of 3 processor circuit package structures 10a ' ", 10b '", and 10c ' ". The processor circuit package structures 10a '″ and 10b' ″ of embodiment 2 on both sides of the stacked interconnect architecture 1 are the same as the processor circuit package structures 10a and 10b of embodiment 1. Embodiment 2 differs from embodiment 1 in that a processor circuit package 10c ' "as an intermediate layer is located between the processor circuit package 10a '" and the processor circuit package 10b ' ", which is unique in embodiment 2. The processor circuit package 10c ' "is a dual-board assembly, which refers to a processor circuit package having connectors 200c '" on both sides of the circuit board 100c ' ".

The processor circuit package structure 10c '"has the connector 200 c'" and the electronic component 300c '"mounted thereon, wherein the connector 200 c'" includes the connector 210c '", the connector 220 c'" and the connector 230c '"sequentially distributed from left to right on the front side of the circuit board 100 c'" (e.g., the upper surface of the circuit board 100c '"in fig. 13), and the connector 240 c'", the connector 250c '"and the connector 260 c'" sequentially distributed from left to right on the back side of the circuit board 100c '"(e.g., the lower surface of the circuit board 100 c'" in fig. 13). The electronic component 300c ' "includes a central processor 310c '" and a memory bank 320c ' ".

As shown in fig. 13, the processor circuit package 10a '"has the connector 200 a'" and the electronic component 300a '"mounted thereon, wherein the connector 200 a'" includes the connector 210a '", the connector 220 a'" and the connector 230a '"which are arranged in sequence from left to right, and the electronic component 300 a'" includes the cpu 310a '"and the memory bar 320 a'". The processor circuit package 10b '"has the connector 200 b'" and the electronic component 300b '"mounted thereon, wherein the connector 200 b'" includes the connector 210b '", the connector 220 b'" and the connector 230b '"which are arranged in this order from left to right, and the electronic component 300 b'" includes the cpu 310b '"and the memory bar 320 b'".

As shown in fig. 14 (a), in the processor circuit package structure 10c ' "as an intermediate layer, the board face 110c '" of the circuit board 100c ' "includes a front face 111c '" and a back face 112c ' ". The first connector 210c '", the second connector 220 c'", and the third connector 230c '"of the connector 200 c'" are sequentially distributed from left to right on the front side 111c '"of the circuit board 100 c'", and the first connector 240c '", the second connector 250 c'", and the third connector 260c '"of the connector 200 c'" are sequentially distributed from left to right on the rear side 112c '"of the circuit board 100 c'". The central processor 310c ' "and the memory bank 320c '" in the electronic component 300c ' "are distributed on the front side 111c '" of the circuit board 100c ' ".

Further, it is understood that the processor circuit package structure 10a, the processor circuit package structure 10b, the processor circuit package structure 10a ', the processor circuit package structure 10b', the processor circuit package structure 10a ″ and the processor circuit package structure 10b ″ of embodiment 1, and the processor circuit package structure 10a ″ and the processor circuit package structure 10b ″ of embodiment 2 may also be a dual-connection board assembly.

In embodiment 2, the electrical connection between any two cpus 310c '"in the processor circuit package structure 10 c'" is the same as the electrical connection between any two cpus 310a (310 c) in the processor circuit package structure 10a (processor circuit package structure 10 b), and is not described herein again.

The electrical connection between the processor circuit package 10a '"and the processor circuit package 10 c'" and between the processor circuit package 10c '"and the processor circuit package 10 b'" in embodiment 2 are the same as the electrical connection between the processor circuit package 10a and the processor circuit package 10b in embodiment 1, and therefore are not described herein.

Unlike embodiment 1, referring to fig. 13 to 14 (c), the electrical connection between the cpu 310a ' "of the processor circuit package 10a '" and the cpu 310b ' "of the processor circuit package 10b '" in embodiment 2 is electrically connected through the connection structure 20 ' ", i.e., the trace 400a '" of the processor circuit package 10a ' ", the connector 200a '", the connection portion between the pair of opposing connectors 200c ' ", the connector 200b '", and the trace 400b ' ". In embodiment 1 of the present application, the connection structure 20 '"includes the connector 200 a'", the connector 200c '", the connecting portion 440 c'" between the opposing connectors 200c '", and the connector 200 b'". Wherein the connecting portion 440c '"is a structure provided between a pair of opposing connectors 200 a'", and electrical connection of at least part of the connecting ends of the opposing connectors 200a '"can be achieved by the connecting portion 440 c'".

Referring to fig. 13-14 (c), when cpu 310a ' "is placed in communication with cpu 310b '", routing internal to processor circuit package 10a is communicated to connector 210a ' "(or connector 220a '", or connector 230a ' "), connector 210c '" (or connector 220c ' ", or connector 230c '") is communicated to connector 240c ' "(or connector 250c '", or connector 260c ' "), routing connector 240c '" (or connector 250c ' ", or connector 260c '"), connector 210b ' "(or connector 220b '", or connector 230b ' "), and processor circuit package 10b '", or processor circuit package 310b ' ", is communicated to processor circuit package 310b '", and finally, routing internal to processor circuit package 310b ' ", or connector 220c '", or connector 230c ' ", and processor circuit package 10b '", is communicated to processor package 310b ' ". As shown in fig. 14 (b), central processor 310c ' "communicates with memory bank 320c '" via electrical component traces 420c ' ". The second connector 220c ' "of the processor circuit package 10c '" is positioned opposite the fifth connector 250c ' ", the central processor 310c '" is in communication with the second connector 220c ' "via the upper third layer of traces 430c '", and the central processor 310c ' "is in communication with the fifth connector 250c '" via the lower third layer of traces 430c ' ". A part of the connection end of the second connector 220c ' ″ and a part of the connection end of the fifth connector 250c ' ″ are communicated by the connection portion 440c ' ″.

As shown in fig. 14 (c), central processor 310c ' "communicates with memory bank 320c '" via electrical component traces 420c ' ". The second connector 220c ' "and the fifth connector 250c '" in the processor circuit package 10c ' "are disposed in a staggered manner, the central processing unit 310c '" is in communication with the second connector 220c ' "through the upper third layer trace 430c '", and the central processing unit 310c ' "is in communication with the fifth connector 250c '" through the lower third layer trace 430c ' ". A part of the connection end of the second connector 220c '″ and a part of the connection end of the fifth connector 250 c' ″ are communicated by a connection portion 440c '″, which may be a printed circuit in the circuit board 100 c' ″.

Embodiment 2 of the present application further includes an electronic device including the stacked interconnect structure of any one of the above.

It should be noted that in this specification, like reference numerals and letters refer to like items in the following drawings, and thus, once an item is defined in one drawing, it need not be further defined and explained in subsequent drawings. In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in this application will be understood to be a specific case for those of ordinary skill in the art. To make the objects, technical solutions and advantages of the present application more clear, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.

Reference in the specification to "some embodiments" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one example embodiment or technology in accordance with the present disclosure. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment. While the description of the present application will be presented in conjunction with certain embodiments, this is not intended to limit the features of this application to that embodiment. On the contrary, the application of the present disclosure with reference to the embodiments is intended to cover alternatives or modifications as may be extended based on the claims of the present disclosure. Numerous specific details are included in the above description in order to provide a thorough understanding of the present application. The present application may be practiced without these particulars.

Moreover, the language used in the specification has been principally selected for readability and instructional purposes, and may not have been selected to delineate or circumscribe the disclosed subject matter. Accordingly, the present disclosure is intended to be illustrative, but not limiting, of the scope of the concepts discussed herein.

Claims

1. A laminated interconnection structure is characterized by comprising N laminated circuit board components, wherein N is more than or equal to 2;

each circuit board assembly comprises a circuit board, at least one connector and at least one central processing unit arranged on the board surface of the circuit board, and the connector is arranged on the board surface;

the connectors on the two adjacent circuit boards are correspondingly inserted into each other to form at least one connecting structure in the stacked interconnection framework, and the inserting direction of the connectors is vertical to the board surface;

one central processing unit in a circuit board assembly and another central processing unit in the circuit board assembly are electrically connected through the wiring in the circuit board assembly;

the central processing unit in one circuit board assembly is electrically connected with the central processing unit in the other circuit board assembly through the wiring in the one circuit board assembly, the wiring in the other circuit board assembly and the connecting structure.

2. The stacked interconnect architecture of claim 1, wherein all of the cpus are electrically connected to each other independently.

3. The stacked interconnect architecture of claim 2,

the number of the central processing units in each circuit board assembly is 4, the 4 central processing units are arrayed on the board surface in a consistent posture, and the central points of the 4 central processing units are distributed in a rectangular shape;

the number of the connectors on one board surface in each circuit board assembly is 3, and the 3 connectors are distributed on a central line of the rectangle; the connector comprises a middle connector and two side connectors, the middle connector is distributed in the center of the rectangle, and the two side connectors are distributed on two sides of the middle connector; the middle connector is respectively connected with 4 central processing units, and the two side connectors are respectively connected with 2 adjacent central processing units;

in the adjacent circuit board assemblies, the middle connectors are mutually inserted to form a middle connecting structure, and the side connectors are mutually correspondingly inserted to form two side connecting structures.

4. The stacked interconnect architecture of claim 3, wherein a communication path between a CPU in said one circuit board assembly and another CPU in said another circuit board assembly comprises:

when the central processing unit and the other central processing unit are adjacent to the same side connecting structure, the central processing unit is electrically connected with the other central processing unit through the adjacent side connecting structure and the adjacent side connecting structure respectively and the routing between the central processing unit and the other central processing unit;

when the central processing unit and the other central processing unit are adjacent to different side connection structures, the central processing unit is electrically connected with the other central processing unit through the middle connection structure and the middle connection structure respectively and the routing between the central processing unit and the other central processing unit.

5. The stacked interconnect architecture of claim 2,

the number of the central processors in each circuit board assembly is 2, and the postures of the 2 central processors are uniformly distributed in parallel;

the number of the connectors on one board surface of each circuit board assembly is 2, the 2 connectors are respectively arranged at two sides of a connecting line of central points of the 2 central processing units, and the 2 connectors are distributed on a central vertical line of the connecting line of the central points;

in the adjacent circuit board assemblies, the connectors are correspondingly plugged with each other to form 2 connecting structures.

6. The laminated interconnect structure of any one of claims 1 to 5, wherein the laminated interconnect structure comprises a first circuit board assembly to an Nth circuit board assembly stacked in sequence;

the first circuit board assembly and the nth circuit board assembly may be a single connection board assembly, and the single connection board assembly is the circuit board assembly provided with the connector on one side of the circuit board.

7. The stacked interconnection architecture of claim 6, wherein the single board assembly is a unidirectional single board assembly in which the cpu and the connector are disposed on two sides of the circuit board;

or the single connecting board assembly is a same-direction single connecting board assembly in which the central processing unit and the connector are arranged on the same side of the circuit board.

8. The stacked interconnect architecture of claim 7, wherein the first circuit board assembly and the nth circuit board assembly are both the unidirectional single connection board assemblies;

the connector in the first circuit board assembly is positioned on one side of the circuit board close to the Nth circuit board assembly, and the connector in the Nth circuit board assembly is positioned on one side of the circuit board close to the first circuit board assembly.

9. The stacked interconnect architecture of claim 7, wherein the first circuit board assembly is the anisotropic single interconnect assembly and the nth circuit board assembly is the unidirectional single interconnect assembly;

10. The stacked interconnect architecture of any one of claims 6 to 9, wherein when N > 2,

the first circuit board assembly and the other circuit board assemblies between the Nth circuit board assembly are double-connection board assemblies, wherein the connectors are arranged on two sides of the circuit board.

11. The laminated interconnect architecture of any one of claims 1 to 10, further comprising a subrack, the subrack forming a receiving cavity therein for receiving the laminated circuit board assembly; the circuit board assembly further comprises a storage strip, and the machine frame is provided with a mounting hole opposite to the storage strip.

12. The stacked interconnect architecture of claim 11, further comprising:

the radiator is arranged on the surface of the central processing unit;

one side surface of the heat conducting pad is attached to the surface of the radiator, and the other side surface of the heat conducting pad is attached to the inner surface of the machine frame.

13. An electronic device comprising the stacked interconnect architecture of any of claims 1-12.