CN115483311A - Preparation method of solar cell - Google Patents
Preparation method of solar cell Download PDFInfo
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- CN115483311A CN115483311A CN202211068019.0A CN202211068019A CN115483311A CN 115483311 A CN115483311 A CN 115483311A CN 202211068019 A CN202211068019 A CN 202211068019A CN 115483311 A CN115483311 A CN 115483311A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/186—Particular post-treatment for the devices, e.g. annealing, impurity gettering, short-circuit elimination, recrystallisation
- H01L31/1868—Passivation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/186—Particular post-treatment for the devices, e.g. annealing, impurity gettering, short-circuit elimination, recrystallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/186—Particular post-treatment for the devices, e.g. annealing, impurity gettering, short-circuit elimination, recrystallisation
- H01L31/1864—Annealing
Abstract
The embodiment of the application relates to the technical field of solar cells, in particular to a preparation method of a solar cell, which comprises the following steps: providing a substrate, wherein the substrate is provided with a first surface; forming a doping layer and a passivation layer which are sequentially stacked along the direction departing from the first surface of the substrate on the first surface of the substrate, wherein the passivation layer is provided with a region to be subjected to laser processing; performing a laser process on a region to be subjected to laser processing on the top surface of the passivation layer to form a laser processing region, wherein the laser process converts the passivation layer with at least partial thickness corresponding to the laser processing region into a first modified film layer; and forming a first grid line electrode on the first surface of the substrate by adopting a sintering process, wherein at least part of the first grid line electrode penetrates through the first modified film layer to be in electric contact with the doping layer. The embodiment of the application is beneficial to improving the photoelectric conversion performance of the prepared solar cell.
Description
Technical Field
The embodiment of the application relates to the field of solar cells, in particular to a preparation method of a solar cell.
Background
The solar cell has good photoelectric conversion capacity, and in the solar cell, a metallization process needs to be performed on the surface of a silicon wafer to form a plurality of fine grids and main grids so as to collect current generated by the silicon wafer. Generally, the metallization process includes a sintering step to sinter a metal paste printed on the surface of the silicon wafer so that the metal paste can penetrate through the passivation layer to electrically contact the doped conductive layer or the emitter.
However, the photoelectric conversion performance of the solar cell prepared at present is not good.
Disclosure of Invention
The embodiment of the application provides a preparation method of a solar cell, which is at least beneficial to improving the photoelectric conversion performance of the solar cell.
The embodiment of the application provides a preparation method of a solar cell, which comprises the following steps: providing a substrate having a first surface; forming a doping layer and a passivation layer which are sequentially stacked along the direction departing from the first surface of the substrate on the first surface of the substrate, wherein the passivation layer is provided with a region to be subjected to laser processing; performing a laser process on a region to be subjected to laser processing on the top surface of the passivation layer to form a laser processing region, wherein the laser process converts the passivation layer with at least part of the thickness corresponding to the laser processing region into a first modified film layer; and forming a first grid line electrode on the first surface of the substrate by adopting a sintering process, wherein at least part of the first grid line electrode penetrates through the first modified film layer to be in electric contact with the doping layer.
In addition, the laser power of the laser process is 15W-45W, the laser frequency is 100 kHz-1500 kHz, the laser wavelength is 250 nm-1320 nm, the laser pulse width is 1 ps-50000 ps, and the laser linear scanning speed is 2000 mm/s-50000 mm/s.
In addition, the passivation layer has a region where a first gate line electrode is to be formed, the laser processing region and the region where the first gate line electrode is to be formed at least partially overlap, and the sintering process includes: printing metal slurry on the top surface of the passivation layer of the region where the first grid line electrode is to be formed; and carrying out heat treatment on the metal paste, wherein at least part of the metal paste penetrates through the first modified film layer to be in electrical contact with the doped layer.
In addition, the temperature of the heat treatment is 450-800 ℃.
The depth of burn-through of the metal paste is 20nm to 200nm.
In addition, the passivation layer is a first region except the laser processing region, and the density of the passivation layer of the first region is greater than that of the first modified film layer.
In addition, the region to be laser-processed includes: a plurality of spaced apart second regions, the laser processing of the regions of the passivation layer top surface to be laser processed being: and carrying out laser processing on the top surface of the passivation layer of the second region.
In addition, the passivation layer has a region where a first gate line electrode is to be formed, the second region overlaps with a part of the region where the first gate line electrode is to be formed, and the first gate line electrode includes: the first portion penetrates through the first modified film layer of the second region to be in electrical contact with the doped layer, and the second portion is in contact with a part of the passivation layer on the side facing the substrate.
In addition, the first part is flush with the top surface of the second part, and the ratio of the thickness of the first part to the thickness of the second part is 1.5-10.
In addition, a plurality of the second regions are arranged in an array, and include: the plurality of second regions are arranged at intervals along a first direction, the plurality of second regions are arranged at intervals along a second direction, the first direction is the extending direction of the first grid line electrodes, and the second direction is the arrangement direction of the plurality of first grid line electrodes.
In addition, one row of the second areas and an adjacent row of the second areas are arranged in a staggered mode in the first direction; alternatively, one row of the second regions and an adjacent row of the second regions are aligned along the second direction.
In addition, the laser process also converts at least part of the doping layer corresponding to the laser processing area into a second modified film layer, and at least part of the first grid line electrode penetrates through the first modified film layer to be electrically contacted with the second modified film layer.
In addition, the region to be subjected to laser processing is overlapped with the region of the first grid line electrode to be formed.
In addition, the doping ion type of the doping layer is the same as that of the substrate, and the material of the doping layer is at least one of doped amorphous silicon, doped polycrystalline silicon or doped microcrystalline silicon material.
In addition, still include: and forming a tunneling dielectric layer, wherein the tunneling dielectric layer is positioned between the doped layer and the first surface of the substrate.
In addition, the doping layer has a doping ion type different from that of the substrate, and the doping layer is made of the same material as that of the substrate.
In addition, the material of the passivation layer is at least one of silicon oxide, silicon nitride, aluminum oxide or silicon oxynitride.
The technical scheme provided by the embodiment of the application has at least the following advantages:
according to the technical scheme of the preparation method of the solar cell, the laser process is carried out on the region to be subjected to laser processing on the top surface of the passivation layer to form the laser processing region, and the passivation layer with at least part of the thickness in the laser processing region is converted into the first modified film layer, namely, part of the passivation layer is not removed by the laser processing, and the complete appearance of the passivation layer subjected to the laser processing is still remained. The region to be subjected to laser processing corresponds to the region of the electrode where the first grid line is to be formed; and forming a first grid line electrode on the first surface of the substrate in the area where the first grid line electrode is to be formed by adopting a sintering process, wherein at least part of the first grid line electrode penetrates through the first modified film layer to be in electric contact with the doping layer. The passivation layer after laser processing is modified, so that the first modified film layer region is easier to burn through when a sintering process is carried out, and thus, the temperature of the sintering process can be lower, and the problem that the doping layer, the emitter or the substrate is damaged due to overhigh sintering temperature is solved. In addition, the complete appearance of the passivation layer is kept after the laser processing, so that the damage of the laser processing to the substrate and the passivation layer corresponding to the non-laser processing area can be reduced.
Drawings
One or more embodiments are illustrated by corresponding figures in the drawings, which are not to be construed as limiting the embodiments, unless expressly stated otherwise, and the drawings are not to scale.
Fig. 1 is a schematic cross-sectional structure diagram illustrating a step of providing a substrate in a method for manufacturing a solar cell according to an embodiment of the present disclosure;
fig. 2 is a schematic cross-sectional structure diagram corresponding to a step of forming a tunneling layer in a method for manufacturing a solar cell according to an embodiment of the present disclosure;
fig. 3 is a schematic cross-sectional structure diagram illustrating a step of forming a doped layer in a method for manufacturing a solar cell according to an embodiment of the present disclosure;
fig. 4 is a schematic cross-sectional structure diagram corresponding to a step of forming a passivation layer in a method for manufacturing a solar cell according to an embodiment of the present disclosure;
fig. 5 is a schematic cross-sectional structure diagram corresponding to a step of forming a doping layer and a passivation layer in another method for manufacturing a solar cell according to an embodiment of the disclosure;
fig. 6 is a schematic top view illustrating a step of forming a laser processing region in a method for manufacturing a solar cell according to an embodiment of the present disclosure;
fig. 7 is a schematic top view illustrating a laser processing region formed in another method for manufacturing a solar cell according to an embodiment of the present disclosure;
FIG. 8 is a schematic cross-sectional view taken along the direction aa' in FIG. 6;
FIG. 9 is a schematic view of another cross-sectional structure along the direction aa' in FIG. 6;
FIG. 10 is a schematic view of another cross-sectional structure along the direction aa' in FIG. 6;
FIG. 11 is a schematic view of a further cross-sectional structure along the direction aa' in FIG. 6;
fig. 12 is a schematic top view illustrating a first gate line electrode in a method for manufacturing a solar cell according to an embodiment of the present disclosure;
FIG. 13 is a schematic cross-sectional view taken along aa' of FIG. 12;
FIG. 14 is a schematic cross-sectional view taken along the direction bb' of FIG. 12;
FIG. 15 is a schematic view of another cross-sectional structure in the direction of bb' in FIG. 12;
fig. 16 is a schematic structural diagram corresponding to the step of forming the anti-reflection layer and the second gate line electrode in the method for manufacturing a solar cell according to an embodiment of the present disclosure.
Detailed Description
As is clear from the background art, the current solar cells have poor photoelectric conversion performance.
Analysis finds that one of the reasons for the poor photoelectric conversion performance of the current solar cell is that, at present, in the process of forming the first grid line electrode, a sintering process is usually adopted to sinter the metal paste printed on the top surface of the passivation layer so that the metal paste can burn through the passivation layer to electrically contact with the doped layer. However, since the sintering temperature is high and the metal paste contains more highly corrosive components, the metal paste has a large damage to the passivation layer and the doping layer after penetrating through the passivation layer and being electrically connected to the doping layer at a high temperature, which results in a large metal recombination between the passivation layer and the doping layer and between the first gate line electrode and the first gate line electrode, and thus the photoelectric conversion efficiency of the solar cell is low.
The embodiment of the application provides a preparation method of a solar cell, which comprises the steps of carrying out a laser process on a region to be subjected to laser processing on the top surface of a passivation layer, and converting the passivation layer with at least part of thickness into a first modified film layer, namely, the laser processing does not remove part of the passivation layer, but still keeps the complete appearance of the passivation layer subjected to the laser processing. The passivation layer after laser processing is modified, so that the first modified film layer region is easier to burn through when a sintering process is carried out to form the first grid line electrode, and thus, the temperature of the sintering process can be lower, and the problem that the doping layer, the emitter or the substrate are damaged due to overhigh sintering temperature is solved. In addition, the complete appearance of the passivation layer is kept after the laser processing, so that the damage of the laser processing to the substrate and the passivation layer corresponding to the non-laser processing area can be reduced.
Embodiments of the present application will be described in detail below with reference to the accompanying drawings. However, it will be appreciated by those of ordinary skill in the art that in the examples of the present application, numerous technical details are set forth in order to provide a better understanding of the present application. However, the technical solution claimed in the present application can be implemented without these technical details and various changes and modifications based on the following embodiments.
Fig. 1 is a schematic structural diagram of a solar cell according to an embodiment of the present disclosure, and fig. 2 is a partial enlarged view of a dashed frame in fig. 1.
Referring to fig. 1, a substrate 100 is provided, the substrate 100 having a first surface.
The substrate 100 is used for receiving incident light and generating photo-generated carriers, and in some embodiments, the substrate 100 may be the substrate 100, and the material of the substrate 100 may include at least one of monocrystalline silicon, polycrystalline silicon, amorphous silicon, or microcrystalline silicon. The substrate 100 is an N-type semiconductor substrate 100, i.e., the substrate 100 is doped with N-type dopant ions, which may be any one of phosphorus ions, arsenic ions, or antimony ions. In other embodiments, the substrate 100 may also be a P-type semiconductor substrate 100, and the substrate 100 is doped with P-type dopant ions, which may be any one of boron ions, gallium ions, or indium ions.
The substrate 100 has a second surface disposed opposite to the first surface, and both the first surface and the second surface of the substrate 100 can be used for receiving incident light or reflected light. In some embodiments, the first surface may be a back surface of the substrate 100 and the second surface may be a front surface of the substrate 100. In other embodiments, the first surface may also be a front surface of the substrate 100, and the second surface is a back surface of the substrate 100.
In some embodiments, a texturing process may be performed on the first surface and the second surface of the substrate 100 to form a pyramid-shaped texture on the first surface and the second surface of the substrate 100, so that the absorption and utilization rate of the first surface and the second surface of the substrate 100 for incident light may be enhanced. In other embodiments, one of the first surface or the second surface of the substrate 100 is a pyramid-shaped textured surface, and the other of the first surface or the second surface may also be a non-pyramid-shaped textured surface, for example, may be a stacked step-shaped textured surface, so that a film layer formed on the stacked step-shaped textured surface has higher density and uniformity, thereby improving the quality of the formed film layer.
In some embodiments, the solar cell is a TOPCON (Tunnel Oxide Passivated Contact) cell. In other embodiments, the solar Cell may also be a PERC (Passivated Emitter and reactor Cell) Cell.
Referring to fig. 2 to 5, a doped layer 110 and a passivation layer 120 stacked in sequence along a direction away from the first surface of the substrate 100 are formed on the first surface of the substrate 100, and the passivation layer 120 has a region to be laser-processed.
Referring to fig. 2 to 3, in some embodiments, the doping ion type of the doping layer 110 is the same as that of the substrate 100, and the material of the doping layer 110 is at least one of doped amorphous silicon, doped polysilicon, or doped microcrystalline silicon material. That is, the doped layer 110 may serve as a doped conductive layer of the solar cell, the doped conductive layer being used to form the field passivation layer 120, wherein the field passivation functions as: an electrostatic field pointing to the inside of the substrate 100 is formed at the interface of the substrate 100, so that minority carriers escape from the interface, the concentration of the minority carriers is reduced, the recombination rate of the minority carriers at the interface of the substrate 100 is low, the open-circuit voltage, the short-circuit current and the fill factor of the solar cell are large, and the photoelectric conversion performance of the solar cell is improved. The formed first gate line electrode is in electrical contact with the doped conductive layer so that the first gate line electrode can collect carriers transmitted into the doped conductive layer.
In some embodiments, when the doped layer 110 is a doped conductive layer, before forming the doped layer 110, further comprising: a tunnel dielectric layer 130 is formed, and the tunnel dielectric layer 130 is located between the doped layer 110 and the first surface of the substrate 100. The tunneling dielectric layer 130 and the doped conductive layer may serve as a passivation contact structure, and the tunneling layer is in direct contact with the first surface of the substrate 100, so as to realize interface passivation of the first surface of the substrate 100, achieve a chemical passivation effect, promote the recombination of photon-generated carriers, and improve the fill factor and the conversion efficiency of the solar cell. In some embodiments, the material of tunnel dielectric layer 130 may be a dielectric material, such as silicon oxide.
In some embodiments, the method of forming tunnel dielectric layer 130 and the doped conductive layer may include:
referring to fig. 2, tunnel dielectric layer 130 is formed on the first surface of substrate 100 by a deposition process, for example, a chemical vapor deposition process. In other embodiments, when the tunneling dielectric layer 130 is made of silicon oxide, the tunneling dielectric layer 130 may also be formed by an in-situ formation process, for example, a thermal oxidation process or a nitric acid passivation process may be used to form a tunneling oxide layer on the first surface of the substrate 100.
Referring to fig. 3, after forming tunnel dielectric layer 130, an amorphous silicon layer is formed on the surface of tunnel dielectric layer 130 far from substrate 100 by using a deposition process; then, carrying out crystallization process on the amorphous silicon layer to convert the amorphous silicon layer into a polycrystalline silicon layer; after the polysilicon layer is formed, a doping process may be performed on the polysilicon layer to form a doped conductive layer, and specifically, the polysilicon layer may be doped with conductive ions, such as phosphorus ions or boron ions, by means of ion implantation or source diffusion.
Referring to fig. 5, in other embodiments, the doped layer 110 has a different dopant ion type than the substrate 100, and the doped layer 110 has the same material as the substrate 100. The doping layer 110 has a doping ion type different from that of the substrate 100 so that the doping layer 110 may serve as an emitter to form a PN junction with the substrate 100. The PN junction may receive incident light irradiated to the first surface of the substrate 100 and generate electron-hole pairs, and when the substrate 100 is an N-type substrate 100, separated electrons move into the substrate 100 and separated holes move into the emitter. Here, since the first gate line electrode is electrically contacted with the doping layer 110, the electrons moving into the emitter are collected by the first gate line electrode.
In some embodiments, a method of forming an emitter may include:
providing an initial substrate 100, performing a diffusion process on one surface of the initial substrate 100 to diffuse conductive ions into a portion of the initial substrate 100 to form an emitter, and forming the substrate 100 in a portion of the initial substrate 100 except for the emitter. In some embodiments, when the substrate 100 is an N-type substrate 100, a boron diffusion process may be performed on a surface of the initial substrate 100, and when the substrate 100 is a P-type substrate 100, a phosphorus diffusion process may be performed on a surface of the initial substrate 100.
It is noted that, referring to fig. 4, in some embodiments, when the doped layer 110 on the first surface of the substrate 100 is a doped conductive layer, the emitter 101 may be formed on the second surface of the substrate 100; referring to fig. 5, in other embodiments, when the doped layer 110 on the first surface of the substrate 100 is an emitter, the tunneling layer 130 and the doped conductive layer 102 may be formed on the second surface of the substrate 100.
The passivation layer 120 may perform a good passivation effect on the first surface of the substrate 100, for example, perform a good chemical passivation on dangling bonds on the first surface of the substrate 100, reduce the defect state density of the first surface of the substrate 100, and better inhibit carrier recombination on the first surface of the substrate 100. In some embodiments, the passivation layer 120 may have a single-layer structure, and in other embodiments, the passivation layer 120 may have a multi-layer structure. In some embodiments, the material of the passivation layer 120 may be at least one of silicon oxide, aluminum oxide, silicon nitride, or silicon oxynitride.
Referring to fig. 4 and 5, in some embodiments, a method of forming the passivation layer 120 may include: the passivation layer 120 is formed on the surface of the doped layer 110 away from the substrate 100 by using a Plasma Enhanced Chemical Vapor Deposition (PECVD) method.
Referring to fig. 6 to 10, after the passivation layer 120 is formed, a laser process is performed on a region to be laser-processed on the top surface of the passivation layer 120 to form a laser-processed region, and the laser process converts the passivation layer 120 with at least a partial thickness corresponding to the laser-processed region into the first modified film layer 10.
The laser processing region is a region where laser processing is performed, and the passivation layer 120 subjected to laser processing is modified, so that the passivation layer 120 subjected to laser processing is more easily burned through in a subsequent sintering process. That is, the sintering depth of the metal paste in the laser-processed passivation layer 120 is deeper without changing the temperature. Based on this, when the sintering depth is not changed, the sintering temperature may be lowered, so that a problem of damage to the doping layer 110, the passivation layer 120, or the substrate 100 due to an excessively high sintering temperature may be prevented. Thus, after the first gate line electrode is formed subsequently, the passivation layer 120 and the doping layer 110 are less damaged, so that the metal composition between the first gate line electrode and the passivation layer is less, the fill factor, the short-circuit current and the open-circuit voltage can be increased, and the photoelectric conversion efficiency of the solar cell can be improved.
It should be noted that in the embodiment of the present application, after the laser processing is performed on the laser processed region, the complete morphology of the passivation layer 120 still remains, i.e., the top surface of the first modified film layer 10 is still flush with the top surface of the passivation layer 120 that has not been subjected to the laser processing. Thus, the first modified film layer 10 can protect the doped layer 110 and the substrate 100, and further prevent the doped layer 110 and the substrate 100 from being damaged by the laser processing.
In addition, compared with the case that the laser-processed passivation layer 120 is completely etched away, the complete morphology of the passivation layer 120 is maintained, and the laser processing can be prevented from damaging the passivation layer 120 and the doped layer 110 corresponding to the non-laser processing region. This is because if the laser-processed passivation layer 120 is completely etched away, a groove will be formed in the passivation layer 120 and even the doped layer 110, and the sidewall of the groove will expose the passivation layer 120 and a portion of the doped layer 110 corresponding to the non-laser-processed region, so that during the process of gradually etching the passivation layer 120 and the doped layer 110 by the laser process, the depth of the formed groove will become deeper and deeper, and the portion of the passivation layer 120 exposed to the outside first in the non-laser-processed region will also be irradiated by the laser, thereby causing damage, which may irreversibly affect the passivation performance of the passivation layer 120 and the doped layer 110, resulting in an increase of metal recombination with the subsequently formed first gate line electrode, thereby reducing the photoelectric conversion performance of the solar cell. Based on this, in the embodiment of the present application, the laser processing region only modifies a portion of the passivation layer 120, and the complete morphology of the passivation layer 120 is maintained, so that the sintering temperature can be reduced, and the complete morphology of the passivation layer 120 and the doped layer 110 can be protected.
In some embodiments, the region of the passivation layer 120 other than the laser processing region is a first region, and the density of the passivation layer 120 of the first region is greater than that of the first modified film layer 10. The regions other than the laser-treated region are regions that are not subjected to laser treatment, that is, the passivation layer 120 after being subjected to laser treatment has low density, so that the first modified film layer 10 can be more easily burned through by a subsequent sintering process, thereby reducing the temperature of the sintering process.
In some embodiments, the parameters of the laser process can be adjusted so that the first modified film layer 10 formed by the laser treatment still retains the complete morphology. In addition, the depth of the laser reaching the passivation layer 120 can be controlled by controlling the laser process, so as to control the profile of the formed first modified film layer 10. Specifically, in some embodiments, the laser power of the laser process may be 15W to 45W, for example, may be 15W to 20W, 20W to 25W, 25W to 30W, 30W to 35W, 35W to 40W, or 40W to 45W. The laser frequency may be 100kHz to 1500kHz, for example, 100kHz to 300kHz, 300kHz to 600kHz, 600kHz to 1000kHz, 1000kHz to 1200kHz, or 1200kHz to 1500kHz. The laser wavelength may be 250nm to 1320nm, for example 250nm to 420nm, 420nm to 580nm, 580nm to 700nm, 700nm to 850nm, 850nm to 1000nm or 1000nm to 1320nm. The laser pulse width is 1 ps-50000 ps, such as 1 ps-1000 ps, 1000 ps-5000 ps, 5000 ps-10000 ps, 10000 ps-18000 ps, 18000 ps-30000 ps, 30000 ps-45000 ps or 45000 ps-50000 ps, the laser linear scanning speed is 2000 mm/s-50000 mm/s, such as 2000 mm/s-4000 mm/s, 4000 mm/s-4500 mm/s, 4500 mm/s-6000 mm/s, 6000 mm/s-9000 mm/s, 10000 mm/s-15000 mm/s, 15000 mm/s-20000 mm/s, 20000 mm/s-30000 mm/s, 30000 mm/s-40000 mm/s, 40000 mm/s-50000 mm/s. Within this range, the first modified film layer 10 formed by laser processing can be allowed to retain the complete morphology. In addition, in this range, the energy of the laser process is not too large, and the problem that the laser reaches the substrate 100 to damage the substrate 100 due to the excessive energy of the laser process is prevented.
In some embodiments, the laser used in the laser process may be any one of infrared laser, green laser, and ultraviolet laser, and the laser used in the laser process may be CO 2 Any one of a laser, an excimer laser, a titanium sapphire laser, and a semiconductor laser, and the embodiment of the present application does not specifically limit the type of the laser.
Referring to fig. 6, in some embodiments, the passivation layer 120 has a first gate line electrode region to be formed, and the laser processing region coincides with the first gate line electrode region to be formed. And forming a first grid line electrode area to be formed, and setting the laser processing area to be superposed with the first grid line electrode area to be formed. That is to say, in the subsequent process of performing the sintering process to form the first gate line electrode, the passivation layers 120 to be sintered are all subjected to laser processing, that is, the passivation layers 120 to be sintered are all modified, so that the whole formed first gate line electrode is easily sintered at different positions, and thus the whole sintering process of the region where the first gate line electrode is to be formed can be easily performed, and the sintering temperature of the sintering process can be integrally reduced.
Referring to fig. 7, in other embodiments, the laser treatment region includes: a plurality of spaced apart second regions 20 laser-treating the laser-treated areas of the top surface of the passivation layer 120 to: the top surface of the passivation layer 120 of the second region 20 is laser-processed. The laser process can precisely position the target portion of the passivation layer 120, so that only the second region 20 can be processed, and the region outside the second region 20 is not processed by the laser, so that the formed first modified film layer 10 corresponds to the second region 20 in the arrangement manner, that is, the first modified film layers 10 are also arranged at intervals. In this way, after the first gate line electrode is formed, the formed first gate line electrode penetrates through the corresponding first modified film layer 10 to be electrically connected with the doped layer 110, that is, the first gate line electrode is not continuously in electrical contact with the doped layer 110, but is in electrical contact with the doped layer 110 at intervals. Thus, damage to the doped layer 110 due to the first gate line electrode penetrating the doped layer 110 may be reduced.
In some embodiments, the plurality of second regions 20 are arranged in an array, including: the plurality of columns of second regions 20 are arranged at intervals along a first direction X, the plurality of columns of second regions 20 are arranged at intervals along a second direction Y, the first direction X is an extending direction of the first gate line electrodes, and the second direction Y is an arrangement direction of the plurality of first gate line electrodes. The second regions 20 are arranged in the same direction, so that the structure of the screen printing plate can be simplified and the printing process can be simplified when the metal paste is printed on the surface of the passivation layer 120 in the subsequent process of forming the first gate line electrode. In some embodiments, a plurality of second regions 20 arranged at intervals in the first direction X may correspond to the same first gate line electrode, so that in the process of forming the first gate line electrode by using the sintering process, since more passivation layers 120 or even doping layers 110 corresponding to the second regions 20 are modified, the difficulty of the sintering process is reduced, and the sintering temperature is further reduced.
In some embodiments, one column of second regions 20 is offset from an adjacent column of second regions 20 in the first direction X; alternatively, one column of the second regions 20 is aligned with an adjacent column of the second regions 20 along the second direction Y. The offset arrangement means that each second region 20 in one column of second regions 20 is not opposite to each second region 20 in the adjacent column of second regions 20 in the second direction Y. The aligned arrangement means that one second zone 20 in one row of second zones 20 is directly opposite to the second zone 20 in the adjacent row of second zones 20 in the second direction Y. Arranging one type of second regions 20 aligned with an adjacent column of second regions 20 in the second direction Y facilitates simplifying the laser process. Specifically, in the laser process, parameters of the laser beam need to be set in advance to determine the action position of the laser beam. When two adjacent columns of the second regions 20 are aligned, the columns of the second regions 20 may be formed using the same parameters of the laser beam, so that the process may be simplified.
It is understood that the arrangement of the second region 20 is not specifically limited in the embodiments of the present application, and the laser process may be adjusted based on the process requirement to form the arrangement of the second region 20 meeting the requirement.
Referring to fig. 8, fig. 8 is a schematic diagram illustrating that when the doped layer 110 is used as an emitter, a part of the passivation layer on the top surface of the emitter is converted into a modified film layer, and in some embodiments, the laser process is controlled to be small so that the laser process only acts on a part of the passivation layer 120, thereby converting only a part of the passivation layer 120 into the first modified film layer 10.
Referring to fig. 9, fig. 9 is a schematic view illustrating that when the doped layer 110 is used as a doped conductive layer, a portion of the passivation layer on the top surface of the doped conductive layer is converted into a modified film layer.
Referring to fig. 10, in other embodiments, the laser process may also be performed on the passivation layer 120 with the entire thickness in the laser processing region by adjusting parameters of the laser process, so that the passivation layer 120 with the entire thickness corresponding to the laser processing region is converted into the first modified film layer 10. Thus, the thickness of the first modified film layer 10 is relatively large, and in the subsequent process of performing a sintering process to make the formed first gate line electrode penetrate through the passivation layer 120 and contact the doped layer 110, the entire passivation layer 120 to be subjected to the sintering process can be easily burned through, so that the temperature of the sintering process can be further reduced, and the damage to the passivation layer 120, the doped layer 110 and the substrate 100 can be further reduced.
Referring to fig. 11, in some embodiments, the laser process also converts at least a portion of the doped layer 110 corresponding to the laser processed region into a second modified film layer 11. Specifically, in some embodiments, the first gate line electrode may penetrate a portion of the doped layer 110 such that a side surface of the first gate line electrode makes electrical contact with the doped layer 110. Based on this, the laser process can convert the part of the doped layer 110 that needs to be penetrated by the first gate line electrode into the second modified film layer 11, so that the sintering process can more easily burn through the second modified film layer 11.
Referring to fig. 12 to 15, after the laser processing is performed, further including: a first gate line electrode 140 is formed on the first surface of the substrate 100 by a sintering process, and at least a portion of the first gate line electrode 140 penetrates through the first modified film layer 10 and electrically contacts the doped layer 110. Since the laser process converts a portion of the passivation layer 120 into the first modified film layer 10 that is easier to burn through, the sintering process can be performed at a lower temperature, so as to prevent the doped layer 110, the emitter, or the substrate 100 from being damaged due to an excessively high sintering temperature.
Referring to fig. 11 and 13, in some embodiments, the laser process further converts at least a portion of the doped layer 110 corresponding to the laser processing region into the second modified film layer 11, and at least a portion of the first gate line electrode 140 penetrates through the first modified film layer 10 and electrically contacts the second modified film layer 11. In this way, during the sintering process, all the layers through which the first gate line electrode 140 needs to penetrate are modified, so that the temperature required by the sintering process can be further reduced compared to merely converting the passivation layer 120 into the first modified layer 10. Thereby further improving damage to the passivation layer 120, the doped layer 110, and the substrate 100 due to an excessively high sintering temperature. In addition, the doped layer 110 subjected to laser treatment still has a complete morphology, so that the doped layer 110 and the substrate 100 which are not subjected to laser treatment can be protected by the second modified film layer 11.
In some embodiments, the passivation layer 120 has a region where the first gate line electrode 140 is to be formed, the laser processing region at least partially overlaps the region where the first gate line electrode 140 is to be formed, and the sintering process includes:
and printing a metal paste on the top surface of the passivation layer 120 in the region where the first gate line electrode 140 is to be formed. In some embodiments, the metal paste is a material having a high corrosive component such as glass, so that during the sintering process, the corrosive component will corrode the passivation layer 120 and the partially doped layer 110, so that the metal paste penetrates through the passivation layer 120 and the partially doped layer 110. Since the first modified film layer 10 is more easily burned through, in the subsequent sintering process, a metal paste with low burning through property can be used, and corrosive components in the metal paste with low burning through property are less, so that excessive damage of the sintering process to the passivation layer 120 due to excessive corrosive components in the metal paste can be prevented, and the better passivation performance of the passivation layer 120 can be maintained. In some embodiments, a screen printing process may be used to print a metal paste on the top surface of the passivation layer 120.
The metal paste is thermally treated, and at least a portion of the metal paste penetrates through the first modified film layer 10 to electrically contact the doped layer 110. Because the first modified film layer 10 is the passivation layer 120 processed by the laser, the metal paste is more easily sintered in the first modified film layer 10, and therefore, under the condition that the sintering depth is not changed, the temperature used for the heat treatment can be lower, so that the passivation layer 120 and the doped layer 110 can be prevented from being damaged due to overhigh sintering temperature, and the passivation layer 120 and the doped layer 110 in the region to be formed with the first gate line electrode 140 can be prevented from being damaged, and further, the metal recombination among the formed first gate line electrode 140, the passivation layer 120 and the doped layer 110 can be smaller, so that the filling factor, the short-circuit current and the open-circuit voltage can be improved, and the photoelectric conversion performance of the solar cell can be improved.
Specifically, in some embodiments, the temperature of the heat treatment is 450 ℃ to 800 ℃, and may be, for example, 450 ℃ to 550 ℃, 550 ℃ to 600 ℃, 600 ℃ to 680 ℃, 680 ℃ to 750 ℃, or 750 ℃ to 800 ℃. In this temperature range, the temperature of the thermal treatment is not too high, so that the passivation layer 120 and the doped layer 110 are prevented from being damaged by the sintering process. In addition, the temperature of the heat treatment is not too low in this temperature range, so that the metal paste can be burned through to a predetermined depth at this heat treatment temperature.
In some embodiments, the metal paste has a depth of burn-through of 20nm to 200nm, for example, 20nm to 50nm, 50nm to 80nm, 80nm to 100nm, 100nm to 130nm, 130nm to 160nm, or 160nm to 200nm. In this range, the depth of the metal paste fired through is not too deep, so that it is possible to prevent the doped layer 110 and even the substrate 100 from being damaged due to the too deep sintering depth of the metal paste in the doped layer 110. And the depth of the burn-through is set not to be too deep, and the temperature of heat treatment in the sintering process can be correspondingly reduced. In addition, in this range, the depth of the metal paste burned through is not too shallow, so that the contact area between the formed first gate line electrode 140 and the doped layer 110 is large, the contact resistance between the first gate line electrode 140 and the doped layer 110 is reduced, the metal contact recombination is improved, and the transmission rate of carriers into the first gate line electrode 140 is increased.
Referring to fig. 7, in some embodiments, when the laser processing region includes: in the plurality of spaced apart second regions 20, the laser-treated areas of the top surface of the passivation layer 120 are laser-treated by: the top surface of the passivation layer 120 of the second region 20 is laser-processed. Based on this process, referring to fig. 15, in some embodiments, the passivation layer 120 has a region where the first gate line electrode 140 is to be formed, the second region 20 coincides with a portion of the region where the first gate line electrode 140 is to be formed, and the first gate line electrode 140 includes: a first portion 141 and a second portion 142, wherein the first portion 141 penetrates the first modified film layer 10 of the second region 20 to electrically contact the doped layer 110, and a side of the second portion 142 facing the substrate 100 contacts a portion of the passivation layer 120. That is, in the first gate line electrode 140, a portion of the first gate line electrode 140 corresponding to the second region 20 has a deeper sintering depth, so that the first portion 141 forms an electrical contact with the doped layer 110 for collecting carriers in the doped layer 110. A portion of the first gate line electrode 140 corresponding to an area where the first gate line electrode 140 is to be formed except for the second region 20 is less deeply sintered so that the second portion 142 penetrates a portion of the passivation layer 120 to be in contact with a portion of the passivation layer 120. Since only a part of the first gate line electrode 140 penetrates through the passivation layer 120, damage of the first gate line electrode 140 to the passivation layer 120 can be reduced, and a complete appearance of the passivation layer 120 is maintained, so that adverse effects on passivation performance of the passivation layer 120 due to the fact that the first gate line electrode 140 penetrates through the passivation layer 120 can be weakened. In other embodiments, the first gate line electrode 140 may further include a third portion, where the third portion is located on the top surface of the passivation layer 120, that is, in the process of sintering the metal paste, since a part of the passivation layer 120 in the region where the gate line is to be formed is not subjected to the laser treatment, when the metal paste is sintered at a lower sintering temperature, there is a case where the metal paste corresponding to the region where the gate line is to be formed, which is not subjected to the laser treatment, does not penetrate into the passivation layer 120, so that the first gate line electrode 140 formed in the region is not in electrical contact with the passivation layer 120, and the complete morphology of the passivation layer 120 in the part is maintained, thereby maintaining the better passivation performance of the passivation layer 120.
The first portion 141 is in electrical contact with the doped layer 110 and plays a role of collecting carriers in the doped layer 110, and therefore, the sintering depth of the first portion 141 needs to be set to be deeper, that is, the thickness of the first portion 141 is set to be larger, so that the contact area between the first portion 141 and the doped layer 110 is larger, the contact resistance between the first portion 141 and the doped layer 110 is smaller, and thus the metal contact recombination between the first portion 141 and the doped layer 110 can be reduced, and the carrier collection efficiency of the first gate line electrode 140 is improved. On the other hand, it is required to set the sintering depth of the first portion 141 not too deep, so as to prevent the first gate line electrode 140 of the first portion 141 from penetrating the doped layer 110 and damaging the doped layer 110 and the substrate 100. In view of the above, in some embodiments, the first portion 141 is disposed flush with the top surface of the second portion 142, and the ratio of the thickness of the first portion 141 to the thickness of the second portion 142 is 1.5 to 10, and may be, for example, 1.5 to 2, 2 to 3, 3 to 3.5, 3.5 to 4.5, 4.5 to 6, 6 to 7, 7 to 8.5, or 8.5 to 10. Within this range, the thickness of the first portion 141 is made larger than that of the second portion 142, so that the first portion 141 forms a good ohmic contact with the doped layer 110. On the other hand, in this range, the thickness of the first portion 141 is not too thick compared to the thickness of the second portion 142, so that the problem of the first portion 141 penetrating the doped layer 110 can be prevented.
Referring to fig. 16, in some embodiments, further comprising: the antireflection layer 150 is formed on the second surface. Specifically, in some embodiments, when the doped layer 110 on the first surface is a doped conductive layer, the second surface of the substrate 100 has the emitter 101, and the anti-reflection layer 150 is located on the surface of the emitter away from the substrate 100. In other embodiments, when the doped layer 110 on the first surface is an emitter, the second surface of the substrate 100 has a tunneling layer and a doped conductive layer, and the anti-reflection layer 150 is located on the doped conductive layer away from the surface of the substrate 100. The anti-reflection layer 150 is used to reduce the reflection of the incident light from the second surface of the substrate 100, thereby increasing the absorption efficiency of the substrate 100 for the incident light. In some embodiments, the anti-reflective layer 150 may be a single layer or a multi-layer structure, and the material of the anti-reflective layer 150 may be at least one of aluminum oxide, silicon nitride, or silicon oxynitride. In some embodiments, the antireflective layer 150 may be formed using a PECVD process.
In some embodiments, further comprising: a second gate line electrode 160 is formed, and the second gate line electrode 160 is located on the second surface of the substrate 100. In some embodiments, when the second surface of the substrate 100 has an emitter, the second gate line electrode 160 penetrates the anti-reflection layer 150 to be in electrical contact with the emitter; in other embodiments, when the second surface of the substrate 100 has the doped conductive layer, the second gate line electrode 160 penetrates through the anti-reflection layer 150 to electrically contact the doped conductive layer. It should be noted that the method for forming the second gate line electrode 160 may be the same as the method for forming the first gate line electrode 140, that is, the second surface of the substrate 100 may be subjected to a laser process to modify at least a portion of the anti-reflection layer 150, and then a sintering process is performed to sinter the metal paste to form the second gate line electrode 160, and the specific method may refer to the description of forming the first gate line electrode 140.
In the method for manufacturing a solar cell provided in the above embodiment, the laser processing is performed on the laser processing region on the top surface of the passivation layer 120, so that the passivation layer 120 with at least a part of the thickness is converted into the first modified film layer 10, that is, the laser processing does not remove a part of the passivation layer 120, but the complete morphology of the laser processed passivation layer 120 still remains. The passivation layer 120 after the laser processing is modified, so that when a sintering process is performed to form the first gate line electrode 140, the first modified film layer 10 is more easily burned through, and thus, the temperature of the sintering process can be low, thereby preventing the doped layer 110, the emitter, or the substrate 100 from being damaged due to an excessively high sintering temperature. In addition, since the complete morphology of the passivation layer 120 is maintained after the laser processing, damage to the substrate 100 and the passivation layer 120 corresponding to the non-laser processing region caused by the laser processing can be reduced.
Although the present application has been described with reference to the preferred embodiments, it is not intended to limit the scope of the claims, and many possible variations and modifications may be made by one skilled in the art without departing from the spirit of the present application.
It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples for carrying out the present application, and that various changes in form and details may be made therein without departing from the spirit and scope of the present application in practice. Various changes and modifications may be effected therein by one of ordinary skill in the pertinent art without departing from the scope or spirit of the present disclosure, and the scope of the present disclosure should be defined only by the appended claims.
Claims (17)
1. A method for manufacturing a solar cell, comprising:
providing a substrate having a first surface;
forming a doping layer and a passivation layer which are sequentially stacked along the direction departing from the first surface of the substrate on the first surface of the substrate, wherein the passivation layer is provided with a region to be subjected to laser processing;
performing a laser process on a region to be subjected to laser processing on the top surface of the passivation layer to form a laser processing region, wherein the laser process converts the passivation layer with at least part of the thickness corresponding to the laser processing region into a first modified film layer;
and forming a first grid line electrode on the first surface of the substrate by adopting a sintering process, wherein at least part of the first grid line electrode penetrates through the first modified film layer to be electrically contacted with the doped layer.
2. The method for preparing the solar cell according to claim 1, wherein the laser power of the laser process is 15W-45W, the laser frequency is 100 kHz-1500 kHz, the laser wavelength is 250 nm-1320 nm, the laser pulse width is 1 ps-50000 ps, and the laser linear scanning speed is 2000 mm/s-50000 mm/s.
3. The method according to claim 1 or 2, wherein the passivation layer has a region where a first gate line electrode is to be formed, the laser processing region at least partially coincides with the region where the first gate line electrode is to be formed, and the sintering process comprises:
printing metal slurry on the top surface of the passivation layer of the region where the first grid line electrode is to be formed;
and carrying out heat treatment on the metal paste, wherein at least part of the metal paste penetrates through the first modified film layer to be in electrical contact with the doped layer.
4. The method according to claim 3, wherein the temperature of the heat treatment is 450 to 800 ℃.
5. The method of claim 4, wherein the metal paste has a depth of fire-through of 20nm to 200nm.
6. The method according to claim 1 or 2, wherein the passivation layer is a first region except the laser-processed region, and the density of the passivation layer of the first region is greater than that of the first modified film layer.
7. The method for manufacturing a solar cell according to claim 1, wherein the region to be laser-processed comprises: a plurality of spaced apart second regions, the laser processing of the region of the top surface of the passivation layer to be laser processed being: and carrying out laser processing on the top surface of the passivation layer of the second region.
8. The method of claim 7, wherein the passivation layer has a region where a first gate line electrode is to be formed, and the second region coincides with a portion of the region where the first gate line electrode is to be formed, and the first gate line electrode comprises: the first portion penetrates through the first modified film layer of the second region to be in electrical contact with the doped layer, and the second portion is in contact with a part of the passivation layer on the side facing the substrate.
9. The method of claim 8, wherein the first portion is flush with the top surface of the second portion, and a ratio of a thickness of the first portion to a thickness of the second portion is 1.5 to 10.
10. The method of claim 7, wherein the plurality of second regions are arranged in an array comprising: the plurality of columns of the second regions are arranged at intervals along a first direction, the plurality of columns of the second regions are arranged at intervals along a second direction, the first direction is the extending direction of the first grid line electrodes, and the second direction is the arrangement direction of the plurality of first grid line electrodes.
11. The method of claim 10, wherein one row of the second regions is offset from an adjacent row of the second regions in the first direction; alternatively, one row of the second regions and an adjacent row of the second regions are aligned along the second direction.
12. The method according to claim 1 or 6, wherein the laser process further converts at least a portion of the doped layer corresponding to the laser processing region into a second modified film layer, and at least a portion of the first gate line electrode penetrates through the first modified film layer and is electrically contacted with the second modified film layer.
13. The method according to claim 3, wherein the region to be laser-processed is overlapped with the region where the first grid line electrode is to be formed.
14. The method as claimed in claim 1, wherein the doping layer has a doping ion type same as that of the substrate, and the material of the doping layer is at least one of doped amorphous silicon, doped polysilicon, or doped microcrystalline silicon.
15. The method for manufacturing a solar cell according to claim 14, further comprising: and forming a tunneling dielectric layer, wherein the tunneling dielectric layer is positioned between the doped layer and the first surface of the substrate.
16. The method according to claim 1, wherein the doping layer has a doping ion type different from that of the substrate, and the doping layer has a material identical to that of the substrate.
17. The method of claim 1, wherein the passivation layer is made of at least one of silicon oxide, silicon nitride, aluminum oxide, or silicon oxynitride.
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