CN115483106A - P-type GaN-based high electron mobility transistor and manufacturing method thereof - Google Patents

P-type GaN-based high electron mobility transistor and manufacturing method thereof Download PDF

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CN115483106A
CN115483106A CN202110601948.2A CN202110601948A CN115483106A CN 115483106 A CN115483106 A CN 115483106A CN 202110601948 A CN202110601948 A CN 202110601948A CN 115483106 A CN115483106 A CN 115483106A
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barrier layer
layer
epitaxial
groove
primary
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张晓荣
孙国臻
杨凯
林晓霞
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Wuxi China Resources Microelectronics Co Ltd
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Wuxi China Resources Microelectronics Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT

Abstract

The invention relates to a P-type GaN-based high electron mobility transistor and a manufacturing method thereof, wherein the method comprises the following steps: obtaining a substrate; the substrate comprises a channel layer, a primary epitaxial barrier layer on the channel layer and a gate structure on the primary epitaxial barrier layer, wherein the gate structure is made of P-type doped GaN; forming a source electrode groove and a drain electrode groove on two sides of the grid electrode structure, wherein the source electrode groove and the drain electrode groove extend downwards to the channel layer from the upper surface of the primary epitaxial barrier layer; forming a secondary epitaxial barrier layer on the substrate by secondary epitaxy, wherein the material of the secondary epitaxial barrier layer is the same as that of the primary epitaxial barrier layer; forming a source electrode, a drain electrode and a gate electrode; the source electrode forms ohmic contact with the epitaxial layer in the source groove, and the drain electrode forms ohmic contact with the epitaxial layer in the drain groove. The invention can simultaneously meet the requirements of high threshold voltage of the device and low square resistance of the active region.

Description

P-type GaN-based high electron mobility transistor and manufacturing method thereof
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a P-type GaN-based high electron mobility transistor and a manufacturing method thereof.
Background
The power electronic system safety requires that the threshold voltage of the power device is generally more than 2V, and for a P-GaN HEMT (High Electron Mobility Transistor) device, a sufficiently High threshold voltage is desired.
Disclosure of Invention
In view of the above, it is necessary to provide a P-type GaN-based high electron mobility transistor having a sufficiently high threshold voltage and a method for manufacturing the same.
A manufacturing method of a P-type GaN-based high electron mobility transistor comprises the following steps: obtaining a substrate; the substrate comprises a GaN channel layer, a primary epitaxial AlGaN barrier layer on the GaN channel layer and a gate structure on the primary epitaxial barrier layer, and the gate structure is made of P-type doped GaN; forming a source groove and a drain groove on two sides of the gate structure, wherein the source groove and the drain groove extend downwards from the upper surface of the primary epitaxial AlGaN barrier layer to the GaN channel layer; forming a secondary epitaxial AlGaN barrier layer on the substrate by secondary epitaxy, wherein the material of the secondary epitaxial AlGaN barrier layer is the same as that of the primary epitaxial AlGaN barrier layer; forming a source electrode, a drain electrode and a gate electrode; the source electrode forms ohmic contact with the secondary epitaxial AlGaN barrier layer in the source groove, and the drain electrode forms ohmic contact with the secondary epitaxial AlGaN barrier layer in the drain groove.
According to the manufacturing method of the P-type GaN-based high electron mobility transistor, after the gate structure is formed, the secondary epitaxial AlGaN barrier layer which is made of the same material as the primary epitaxial AlGaN barrier layer is formed on the primary epitaxial AlGaN barrier layer, so that the primary epitaxial AlGaN barrier layer below the gate structure can be made thinner, two-dimensional electron gas under the gate structure is easier to be exhausted, and the threshold voltage of the device is higher; meanwhile, the square resistance of the active region is influenced by the thickness of the AlGaN barrier layer, and the secondary epitaxy of the active region thickens the AlGaN barrier layer to a certain thickness, so that the square resistance of the active region can be reduced by the secondary epitaxy of the AlGaN barrier layer. That is to say, the thickness of the primary epitaxial AlGaN barrier layer under the gate structure and the thickness of the secondary epitaxial AlGaN barrier layer in the active region can be adjusted independently from each other, and the active region barrier layer can be made thick enough under the condition that the barrier layer under the gate structure is thin, so that the requirements of high threshold voltage of the device and low sheet resistance of the active region can be met at the same time.
In one embodiment, the substrate further comprises an insertion layer formed between the channel layer and barrier layer, the material of the insertion layer comprising AlN; and etching the barrier layer, the insertion layer and the channel layer on two sides of the gate structure by adopting an etching process to form the source electrode groove and the drain electrode groove.
In one embodiment, the thickness of the insertion layer is 1nm.
In one embodiment, in the step of etching the barrier layer, the insertion layer and the channel layer to form the source recess and the drain recess, the thickness of the channel layer removed by etching is less than 20 nanometers.
In one embodiment, the thickness of the channel layer removed by etching is 0 to 20 nm.
In one embodiment, the materials of the barrier layer and the epitaxial layer comprise AlGaN.
In one embodiment, in the step of epitaxially forming an epitaxial layer on the substrate, the thickness of the grown epitaxial layer is 1 to 10 nm.
In one embodiment, the substrate further comprises a buffer layer, the channel layer and the primary epitaxial barrier layer being formed on the buffer layer.
In one embodiment, the material of the buffer layer includes GaN.
In one embodiment, the material of the channel layer comprises GaN.
In one embodiment, the step of epitaxially forming an epitaxial layer on the substrate is forming an epitaxial layer by a metal organic chemical vapor deposition technique.
In one embodiment, the method further comprises the step of forming a dielectric layer on the epitaxial layer.
A P-type GaN-based high electron mobility transistor, comprising: a GaN channel layer; the primary epitaxial AlGaN barrier layer is arranged on the GaN channel layer; the grid structure is arranged on the primary epitaxial AlGaN barrier layer, and the material of the grid structure comprises P-type doped GaN; an active electrode groove and a drain electrode groove are formed on two sides of the grid structure, and the source electrode groove and the drain electrode groove downwards penetrate through the primary epitaxial AlGaN barrier layer to extend to the GaN channel layer; the secondary epitaxial AlGaN barrier layer is arranged on the primary epitaxial AlGaN barrier layer and is also arranged at the bottom and the side wall of the source electrode groove and the drain electrode groove; the source electrode is filled in the source electrode groove and forms ohmic contact with the secondary epitaxial AlGaN barrier layer; the drain electrode is filled in the drain electrode groove and forms ohmic contact with the secondary epitaxial AlGaN barrier layer; and the gate electrode is arranged on the gate structure.
In the P-type GaN-based high electron mobility transistor, the secondary epitaxial AlGaN barrier layer which is the same as the primary epitaxial AlGaN barrier layer in material is arranged on the primary epitaxial AlGaN barrier layer, so that the primary epitaxial AlGaN barrier layer below the gate structure can be made thinner, two-dimensional electron gas under the gate structure is easier to be exhausted, and the threshold voltage of the device is higher; meanwhile, the square resistance of the active region is influenced by the thickness of the AlGaN barrier layer, and the secondary epitaxy of the active region thickens the AlGaN barrier layer to a certain thickness, so that the square resistance of the active region can be reduced by the secondary epitaxy of the AlGaN barrier layer. That is to say, the thickness of the primary epitaxial AlGaN barrier layer under the gate structure and the thickness of the secondary epitaxial AlGaN barrier layer in the active region can be adjusted independently from each other, and the active region barrier layer can be made thick enough under the condition that the barrier layer under the gate structure is thin, so that the requirements of high threshold voltage of the device and low sheet resistance of the active region can be met at the same time.
In one embodiment, the GaN device further comprises an insertion layer arranged between the GaN channel layer and the primary epitaxial AlGaN barrier layer, wherein the source groove and the drain groove penetrate through the insertion layer, and the material of the insertion layer comprises AlN.
In one embodiment, the thickness of the insertion layer is 1nm.
In one embodiment, the secondary epitaxial AlGaN barrier layer has a thickness of 1 to 10 nm.
In one embodiment, the source recess and the drain recess are less than 20 nanometers deep in the channel layer.
In one embodiment, the depth is 5 to 15 nanometers.
In one embodiment, the P-type GaN-based hemt further comprises a buffer layer; the channel layer is formed on the buffer layer.
In one embodiment, the material of the buffer layer includes GaN.
In one embodiment, the P-type GaN-based HEMT further comprises a dielectric layer disposed on the epitaxial layer.
In one embodiment, the P-doped GaN is in direct contact with the barrier layer.
In one embodiment, the material of the source electrode comprises a metal and/or an alloy.
In one embodiment, the material of the drain electrode comprises a metal and/or an alloy.
In one embodiment, the material of the gate electrode includes a metal and/or an alloy.
Drawings
For a better understanding of the description and/or illustration of embodiments and/or examples of those inventions disclosed herein, reference may be made to one or more of the drawings. The additional details or examples used to describe the figures should not be considered as limiting the scope of any of the disclosed inventions, the presently described embodiments and/or examples, and the presently understood best modes of these inventions.
FIGS. 1a-1d are schematic cross-sectional views of devices in an embodiment of a process for fabricating a P-GaN HEMT using the method of FIG. 3;
FIG. 2 is a schematic cross-sectional view of an embodiment of a P-type GaN-based HEMT;
FIG. 3 is a flow chart of a method for fabricating a P-type GaN-based HEMT in an embodiment.
Detailed Description
To facilitate an understanding of the invention, the invention will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatially relative terms, such as "under," "below," "beneath," "under," "above," "over," and the like, may be used herein for convenience in describing the relationship of one element or feature to another element or feature illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the invention should not be limited to the particular shapes of regions illustrated herein, but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle will typically have rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted region. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present invention.
As used herein, the term semiconductor is used in the art to distinguish between P-type and N-type impurities, and for example, P + type represents P-type with heavy doping concentration, P-type represents P-type with medium doping concentration, P-type represents P-type with light doping concentration, N + type represents N-type with heavy doping concentration, N-type represents N-type with medium doping concentration, and N-type represents N-type with light doping concentration.
The AlGaN barrier layer thickness of the illustrative P-GaN HEMT device is about 15nm, and the hole in the P-GaN grid can be normally closed only by depleting the two-dimensional electron gas under the grid. The threshold voltage of a power device is generally required to be more than 2V by the safety of a power electronic system, the thin AlGaN barrier layer enables two-dimensional electron gas under a gate to be exhausted more easily, the threshold voltage of a P-GaN device is higher, but the square resistance of a thinner AlGaN active region is correspondingly increased, so that the on-resistance of the device is increased.
Accordingly, the present application provides a P-type GaN-based high electron mobility transistor having a sufficiently high threshold voltage and a small sheet resistance in an active region, and a method for fabricating the same. FIG. 3 is a flow chart of a method for fabricating a P-type GaN-based HEMT according to an embodiment, including the steps of:
s310, obtaining a substrate.
The substrate includes a channel layer 120, a primary epitaxial barrier layer 140 on the channel layer 120, and a gate structure 150 on the primary epitaxial barrier layer 140. The material of the gate structure 150 is P-type doped GaN.
In one embodiment of the present application, the primary epitaxial barrier layer 140 is 5-15nm thick.
In one embodiment of the present application, the gate structure 150 may be formed by photolithography and etching of the P-GaN layer 152 on the primary epitaxial barrier layer 140, see fig. 1a and fig. 1b, with the P-doped GaN (i.e., the gate structure 150) in direct contact with the primary epitaxial barrier layer 140.
In one embodiment of the present application, the substrate further includes an intervening layer 130 formed between the channel layer 120 and the primary epitaxial barrier layer 140. In one embodiment of the present application, the insertion layer 130 is AlN Spacer. The arrangement of the AlN insert layer 130 can improve the confinement of the two-dimensional electron gas, thereby improving the current collapse effect of the device and improving the reliability of the device. The groove process of the source electrode and the drain electrode can enable the ohmic contact process of the AlN Spacer to be better realized. In one embodiment of the present application, the thickness of the insertion layer 130 is 0.2 to 1.5nm; further, it may be 1nm.
In one embodiment of the present application, the substrate further includes a buffer layer 110. The channel layer 120 and the primary epitaxial barrier layer 140 are formed on the buffer layer 110. It is understood that other structures of the HEMT device known in the art, such as a substrate, may be disposed under the buffer layer 110.
In one embodiment of the present application, the Buffer layer 110 is a GaN Buffer.
In one embodiment of the present application, the channel layer 120 is a GaN layer.
In one embodiment of the present application, the primary epitaxial barrier layer 140 is an AlGaN layer.
And S320, forming a source electrode groove and a drain electrode groove on two sides of the grid electrode structure.
A source recess 141 and a drain recess 143 extend from the upper surface of the primary epitaxial barrier layer 140 down to the channel layer 120, see fig. 1c. In one embodiment of the present application, the source recess 141 and the drain recess 143 are formed by etching down from the upper surface of the primary epitaxial barrier layer 140 to the channel layer 120 by a photolithography and etching process. The epitaxial barrier layer 140 is all processed once and etched through the insertion layer 130 followed by zero to twenty nanometers of etching of the channel layer 120, i.e., the thickness of the channel layer 120 etched away at the source Recess 141 and the drain Recess 143 may be zero to twenty nanometers. Further, the channel layer 120 is etched to a thickness of 0 to 20 nm.
And S330, epitaxially forming a secondary epitaxial barrier layer on the substrate.
The material of the secondary epitaxial barrier layer 142 is the same as the material of the primary epitaxial barrier layer 140. In the embodiment shown in fig. 1d, the secondary epitaxial barrier layer 142 is a secondary epitaxially formed AlGaN layer. In one embodiment of the present application, the secondary epitaxially grown secondary epitaxial barrier layer 142 has a thickness of 1 to 10 nanometers.
In an embodiment of the present application, after step S320 and before step S330, a step of cleaning the structure obtained in step S320 (i.e., the structure corresponding to fig. 1 c) is further included.
In one embodiment of the present application, the secondary epitaxial barrier layer 142 is formed using an MOCVD (metal organic chemical vapor deposition) apparatus.
S340, a source electrode, a drain electrode, and a gate electrode are formed.
And opening an electrode window to manufacture an electrode. Gate electrode 172 is formed on gate structure 150. The source electrode 171 forms an ohmic contact with the secondary epitaxial barrier layer 142 in the source recess, and the drain electrode 173 forms an ohmic contact with the secondary epitaxial barrier layer 142 in the drain recess. The processes after step S330 may employ conventional processes known in the art. Fig. 2 is a cross-sectional view of the device after step S340 is completed in an embodiment in which a dielectric layer 160 is further formed on the secondary epitaxial barrier layer 142. The gate electrode 172, the source electrode 171, and the drain electrode 173 may be formed by a contact hole photolithography and etching process after the dielectric layer 160 is formed, and a metal sputtering process.
According to the manufacturing method of the P-type GaN-based high electron mobility transistor, after the gate structure 150 is formed, the secondary epitaxial barrier layer 142 which is made of the same material as the primary epitaxial barrier layer 140 is epitaxially formed on the primary epitaxial barrier layer 140, so that the primary epitaxial barrier layer 140 below the gate structure 150 can be made thinner, two-dimensional electron gas below the gate structure 150 is more easily exhausted, and the threshold voltage of the device is higher; meanwhile, the square resistance of the active region is influenced by the thickness of the AlGaN barrier layer, and the secondary epitaxy of the active region thickens the AlGaN barrier layer to a certain thickness, so that the square resistance of the active region can be reduced by the secondary epitaxy of the AlGaN barrier layer. That is, the thickness of the primary epitaxial barrier layer 140 under the gate structure 150 and the thickness of the active region secondary epitaxial barrier layer 142 can be adjusted independently, so that the AlGaN barrier layer in the active region can be made thick enough under the condition that the primary epitaxial barrier layer 140 under the gate structure 150 is thin, thereby simultaneously satisfying the requirements of high threshold voltage of the device and low sheet resistance of the active region.
According to the P-GaN HEMT device with the AlN Spacer layer, a source-drain extremely-low ohmic contact structure needs to adopt a process technology, and the uniformity of in-chip etching of a process technology of a six-inch wire device is poor at present. For a P-GaN HEMT device with an AlN Spacer layer, the high-aluminum component of the AlN Spacer layer makes ohmic contact of the structure difficult to manufacture, the process uniformity is poor, and the requirement on process equipment is high. Specifically, etching to form the source recess and the drain recess requires etching through the AlN Spacer layer and then continuously etching the channel layer down to a shallow depth (illustratively, 5nm, depending on the design of the channel layer), so that it is difficult for a general etching apparatus to meet the requirements of etching endpoint control and etching uniformity. In the manufacturing method of the P-type GaN-based high electron mobility transistor, the secondary epitaxial barrier layer 142 is formed by epitaxy on the inner surfaces of the source groove 141 and the drain groove 143, so that even if the etching depths of the source groove 141 and the drain groove 143 are not well controlled (deeply etched), an AlGaN layer with good thickness uniformity and repeatability can be obtained through the secondary epitaxial barrier layer 142, the thickness of the secondary epitaxial barrier layer 142 can be precisely controlled, that is, the thickness of AlGaN in ohmic contact can be precisely controlled, and therefore, the uniformity and stability when ohmic contact between the source electrode and the drain electrode is formed can be guaranteed. Therefore, the secondary epitaxial barrier layer 142 can reduce the requirement of the stress etching uniformity and accurately control the thickness of AlGaN in ohmic contact, thereby improving the uniformity of ohmic contact with the AlN Spacer structure and solving the problems of repeatability among batches and uniformity in chips of ohmic contact of the P-GaN HEMT with the AlN Spacer structure.
The present application correspondingly provides a P-type GaN-based high electron mobility transistor, referring to fig. 2, including a channel layer 120, a primary epitaxial barrier layer 140, a gate structure 150, a secondary epitaxial barrier layer 142, a source electrode 171, a drain electrode 173, and a gate electrode 172. The primary epitaxial barrier layer 140 is disposed on the channel layer 120. A gate structure 150 is disposed on the primary epitaxial barrier layer 140. The gate structure 150 is P-doped GaN, which is in direct contact with the primary epitaxial barrier layer 140. An active electrode groove and a drain groove are formed at both sides of the gate structure, and extend downward to the channel layer 120 through the primary epitaxial barrier layer 140. The secondary epitaxial barrier layer 142 is disposed on the primary epitaxial barrier layer 140 and also on the bottom and sidewalls of the source and drain recesses. The material of the secondary epitaxial barrier layer 142 is the same as the material of the primary epitaxial barrier layer 140. The source electrode 171 fills the source recess and forms an ohmic contact with the secondary epitaxial barrier layer 142. The drain electrode 173 fills the drain recess and forms an ohmic contact with the secondary epitaxial barrier layer 142. Gate electrode 172 is disposed on gate structure 150.
In the P-type GaN-based high electron mobility transistor, the primary epitaxial barrier layer 140 is provided with the secondary epitaxial barrier layer 142 which is made of the same material as the primary epitaxial barrier layer 140, so that the primary epitaxial barrier layer 140 under the gate structure 150 can be made thinner, the two-dimensional electron gas under the gate structure 150 is more easily exhausted, and the threshold voltage of the device is also higher; meanwhile, the square resistance of the active region is influenced by the thickness of the AlGaN barrier layer, and the AlGaN barrier layer is thickened to a certain thickness by secondary epitaxy of the active region, so that the square resistance of the active region can be reduced by the secondary epitaxy barrier layer 142. That is, the thickness of the primary epitaxial barrier layer 140 under the gate structure 150 and the thickness of the active region secondary epitaxial barrier layer 142 can be adjusted independently, so that the AlGaN barrier layer in the active region can be made thick enough under the condition that the primary epitaxial barrier layer 140 under the gate structure 150 is thin, thereby simultaneously satisfying the requirements of high threshold voltage of the device and low sheet resistance of the active region.
In the embodiment shown in fig. 2, the P-type GaN-based hemt further includes an insertion layer 130 disposed between the channel layer 120 and the primary epitaxial barrier layer 140, and the source and drain recesses are formed through the insertion layer 130 downward. In one embodiment of the present application, the insertion layer 130 is AlN Spacer. The arrangement of the AlN insert layer 130 can improve the confinement of the two-dimensional electron gas, thereby improving the current collapse effect of the device and improving the reliability of the device. In one embodiment of the present application, the thickness of the insertion layer 130 is 0.2 to 1.5nm; further, it may be 1nm.
In one embodiment of the present application, the P-type GaN-based hemt further includes a buffer layer 110. The channel layer 120 and the primary epitaxial barrier layer 140 are formed on the buffer layer 110. It is understood that other structures of the HEMT device known in the art, such as a substrate, may be disposed under the buffer layer 110.
In one embodiment of the present application, the Buffer layer 110 is a GaN Buffer.
In one embodiment of the present application, the channel layer 120 is a GaN layer.
In one embodiment of the present application, the primary epitaxial barrier layer 140 is an AlGaN layer.
In one embodiment of the present application, the secondary epitaxial barrier layer is 1 to 10 nanometers thick.
In one embodiment of the present application, the depth of the source recess and the drain recess in the channel layer 120 is 0 to 20 nm.
In the embodiment shown in fig. 2, the P-type GaN-based hemt further comprises a dielectric layer 160 disposed on the secondary epitaxial barrier layer 142.
It should be understood that, although the steps in the flowcharts of the present application are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least a part of the steps in the flowchart of the present application may include a plurality of steps or a plurality of stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of performing the steps or the stages is not necessarily sequential, but may be performed alternately or alternately with other steps or at least a part of the steps or the stages in other steps.
In the description herein, references to the description of "some embodiments," "other embodiments," "desired embodiments," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, a schematic description of the above terminology may not necessarily refer to the same embodiment or example.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is specific and detailed, but not to be understood as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims (10)

1. A manufacturing method of a P-type GaN-based high electron mobility transistor comprises the following steps:
obtaining a substrate; the substrate comprises a channel layer, a primary epitaxial barrier layer on the channel layer and a gate structure on the primary epitaxial barrier layer, the channel layer is made of GaN, the primary epitaxial barrier layer is made of AlGaN, and the gate structure is made of P-type doped GaN;
forming a source groove and a drain groove on two sides of the gate structure, wherein the source groove and the drain groove extend downwards from the upper surface of the primary epitaxial barrier layer to the channel layer;
forming a secondary epitaxial barrier layer on the substrate by secondary epitaxy, wherein the material of the secondary epitaxial barrier layer is the same as that of the primary epitaxial barrier layer;
forming a source electrode, a drain electrode and a gate electrode; the source electrode forms ohmic contact with the epitaxial layer in the source groove, and the drain electrode forms ohmic contact with the epitaxial layer in the drain groove.
2. The method of claim 1, wherein the substrate further comprises an insertion layer formed between the channel layer and the primary epitaxial barrier layer, the material of the insertion layer comprising AlN; and etching the primary epitaxial barrier layer, the insertion layer and the channel layer on two sides of the gate structure by adopting an etching process to form the source electrode groove and the drain electrode groove.
3. The method of claim 2, wherein in the step of etching the primary epitaxial barrier layer, the insertion layer, and the channel layer to form the source recess and the drain recess, the thickness of the etched-away channel layer is no greater than 20 nm.
4. The method according to claim 2, wherein in the step of forming the secondary epitaxial barrier layer on the substrate by secondary epitaxy, the thickness of the secondary epitaxial barrier layer is 1 to 10 nm.
5. The method of claim 1, wherein the substrate further comprises a buffer layer, and the channel layer is formed on the buffer layer.
6. The method of claim 1, wherein the step of forming the secondary epitaxial barrier layer on the substrate by secondary epitaxy is performed by a Metal Organic Chemical Vapor Deposition (MOCVD) technique.
7. A P-type GaN-based high electron mobility transistor, comprising:
a GaN channel layer;
the primary epitaxial AlGaN barrier layer is arranged on the GaN channel layer;
the grid structure is arranged on the primary epitaxial AlGaN barrier layer, and the material of the grid structure comprises P-type doped GaN; an active electrode groove and a drain electrode groove are formed on two sides of the grid structure, and the source electrode groove and the drain electrode groove downwards penetrate through the primary epitaxial AlGaN barrier layer to extend to the GaN channel layer;
the secondary epitaxial AlGaN barrier layer is arranged on the primary epitaxial AlGaN barrier layer and is also arranged at the bottom and the side wall of the source electrode groove and the drain electrode groove;
the source electrode is filled in the source electrode groove and forms ohmic contact with the secondary epitaxial AlGaN barrier layer;
the drain electrode is filled in the drain electrode groove and forms ohmic contact with the secondary epitaxial AlGaN barrier layer;
and the gate electrode is arranged on the gate structure.
8. The P-type GaN-based hemt of claim 7, further comprising an insertion layer disposed between said GaN channel layer and primary epitaxial AlGaN barrier layer, said source and drain recesses passing through said insertion layer, the material of said insertion layer comprising AlN.
9. The P-type GaN-based hemt of claim 7, wherein said secondary epitaxial AlGaN barrier layer has a thickness of 1 to 10 nm.
10. The P-type GaN-based hemt of claim 7, wherein said source and drain recesses have a depth in said channel layer of no more than 20 nm.
CN202110601948.2A 2021-05-31 2021-05-31 P-type GaN-based high electron mobility transistor and manufacturing method thereof Pending CN115483106A (en)

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