CN115483033A - Capacitor, circuit board and circuit board embedding process - Google Patents
Capacitor, circuit board and circuit board embedding process Download PDFInfo
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- CN115483033A CN115483033A CN202211069806.7A CN202211069806A CN115483033A CN 115483033 A CN115483033 A CN 115483033A CN 202211069806 A CN202211069806 A CN 202211069806A CN 115483033 A CN115483033 A CN 115483033A
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- copper foil
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- 239000003990 capacitor Substances 0.000 title claims abstract description 102
- 238000000034 method Methods 0.000 title claims abstract description 21
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 154
- 239000011889 copper foil Substances 0.000 claims abstract description 154
- 239000004020 conductor Substances 0.000 claims abstract description 16
- 238000009713 electroplating Methods 0.000 claims description 10
- 238000005553 drilling Methods 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 9
- 238000010030 laminating Methods 0.000 claims description 6
- 239000002245 particle Substances 0.000 claims description 4
- 239000002952 polymeric resin Substances 0.000 claims description 4
- 229920003002 synthetic resin Polymers 0.000 claims description 4
- 230000000149 penetrating effect Effects 0.000 claims description 2
- 239000003822 epoxy resin Substances 0.000 description 5
- 229920000647 polyepoxide Polymers 0.000 description 5
- JRPBQTZRNDNNOP-UHFFFAOYSA-N barium titanate Chemical compound [Ba+2].[Ba+2].[O-][Ti]([O-])([O-])[O-] JRPBQTZRNDNNOP-UHFFFAOYSA-N 0.000 description 4
- 229910002113 barium titanate Inorganic materials 0.000 description 4
- 238000009413 insulation Methods 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000009434 installation Methods 0.000 description 3
- 238000000576 coating method Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000011259 mixed solution Substances 0.000 description 2
- 239000002904 solvent Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 230000001502 supplementing effect Effects 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/30—Stacked capacitors
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/423—Plated through-holes or plated via connections characterised by electroplating method
- H05K3/424—Plated through-holes or plated via connections characterised by electroplating method by direct electroplating
Abstract
The invention discloses a capacitor, a circuit board and a circuit board capacitance embedding process, wherein the capacitor comprises a plurality of first copper foil layers which are arranged in a stacked mode, and hollow parts are arranged on the plurality of first copper foil layers; the capacitor-embedded dielectric layer is arranged between two adjacent first copper foil layers; and in any three first copper foil layers, an electric conductor is connected between the other two first copper foil layers with one first copper foil layer at intervals, and the electric conductor penetrates through the hollow part of the middle first copper foil layer. The capacitor of the invention has small volume and high capacitance value.
Description
Technical Field
The invention relates to the technical field of circuit boards, in particular to a capacitor, a circuit board and a circuit board capacitance embedding process.
Background
Along with the more and more abundant functions of intelligent electronic products, the performance of electronic components applied to the intelligent electronic products is also continuously improved. Among them, a circuit board is one of its important components, and intelligent electronic products put higher demands on the circuit board. In the correlation technique, the capacitance value of the condenser in the current circuit board is low, can't satisfy the requirement of realizing diversified function, if the great capacitance value of demand, then needs the circuit board structure of great volume, is unfavorable for the miniaturization of installation and circuit board.
Disclosure of Invention
The present invention is directed to solving at least one of the problems of the prior art. Therefore, the invention provides a capacitor with small volume and high capacitance value.
The invention also provides a circuit board with the capacitor and a circuit board capacitance embedding process.
A capacitor according to an embodiment of the first aspect of the invention, comprises: the copper foil comprises a plurality of first copper foil layers which are arranged in a stacked mode, wherein hollow parts are arranged on the first copper foil layers; the capacitor-embedded dielectric layer is arranged between two adjacent first copper foil layers; and in any three first copper foil layers, an electric conductor is connected between the other two first copper foil layers with one first copper foil layer at intervals, and the electric conductor penetrates through the hollow part of the first copper foil layer in the middle.
The technical scheme at least has the following beneficial effects: the capacitor is characterized in that a plurality of stacked first copper foil layers are arranged, the capacitor burying dielectric layers are arranged between every two adjacent first copper foil layers, and the other two first copper foil layers which are spaced by one first copper foil layer are conducted through the electric conductors penetrating through the hollow parts in any three first copper foil layers, so that the two adjacent first copper foil layers and the capacitor burying dielectric layers form a capacitor unit, the number of the capacitor units is the same as that of the capacitor burying dielectric layers, and therefore, a capacitor with the capacitance value being multiplied is formed to meet the functional requirements of a circuit board, and the whole volume of the capacitor is effectively reduced due to the stacked arrangement, and the miniaturization requirement of the circuit board is met.
According to some embodiments of the invention, the buried dielectric layer is made of a mixture of dielectric particles and a polymer resin.
According to some embodiments of the invention, the dielectric constant of the buried dielectric layer is D, which satisfies: d is more than or equal to 15 and less than or equal to 30.
According to some embodiments of the invention, the first copper foil layer has a thickness T1, satisfying: t1 is more than or equal to 1 and less than or equal to 200 mu m.
According to some embodiments of the invention, the thickness of the capacitor-embedded dielectric layer is T2, and satisfies: t2 is more than or equal to 0.1 and less than or equal to 50 mu m.
A capacitor according to an embodiment of the second aspect of the invention, comprises: the capacitor of the embodiment of the first aspect described above; the two insulating layers are respectively arranged on the outer sides of the two first copper foil layers on the outermost side of the capacitor; and the two second copper foil layers are respectively arranged at the outer sides of the two insulating layers, and are communicated with the first copper foil layer at the outermost side, or are communicated with the other first copper foil layer which is separated by one first copper foil layer.
The technical scheme at least has the following beneficial effects: the circuit board adopts the capacitor, the insulating layer and the second copper foil layer are sequentially pressed on two sides of the capacitor, and the second copper foil layer is communicated with the first copper foil layer on the outermost side or is communicated with the other first copper foil layer which is separated by one first copper foil layer. Therefore, the circuit board has all the technical effects of the capacitor, and meets the functional requirements and the miniaturization requirements.
According to the third aspect of the invention, the circuit board embedding process comprises the following steps: the method comprises the following steps: forming a core board by a capacitor-embedded dielectric layer and first copper foil layers arranged on two sides of the capacitor-embedded dielectric layer, and etching the two first copper foil layers of the core board; forming a capacitor-embedded plate by a capacitor-embedded dielectric layer and a first copper foil layer arranged on one side of the capacitor-embedded dielectric layer, etching the first copper foil layer of the capacitor-embedded plate, and laminating the sides of the capacitor-embedded plates, which are provided with the capacitor-embedded dielectric layers, on two sides of the core plate in a laminating manner respectively; drilling and electroplating the embedded capacitor plate and the core plate to ensure that the other two first copper foil layers with one first copper foil layer at intervals among any three first copper foil layers are conducted; the circuit board is composed of an insulating layer and a second copper foil layer arranged on one side of the insulating layer, the second copper foil layer is etched, and one side of each of the two circuit boards provided with the insulating layer is respectively pressed on the two capacitor embedding plates on the outermost side; and drilling and electroplating the circuit board to ensure that the two second copper foil layers are respectively conducted with the first copper foil layers of the two adjacent capacitor embedding plates.
The technical scheme at least has the following beneficial effects: the circuit board is characterized in that the hollow-out portions are obtained by etching the core board and the first copper foil layers of the embedded capacitor boards, the embedded capacitor boards are laminated with two sides of the core board in a stacking mode respectively, the other two first copper foil layers with one first copper foil layer are separated in the middle of any three first copper foil layers in a drilling and electroplating mode to be conducted, the circuit board is laminated on the two embedded capacitor boards on the outermost side, the two second copper foil layers are conducted with the adjacent two first copper foil layers of the embedded capacitor boards through the same hole and the electroplating mode, and therefore the circuit board with the high capacitance value and the small size is obtained, and the functional requirements and the miniaturization requirements are met.
According to some embodiments of the invention, the capacitor burying medium layer of the capacitor burying plate is coated on the first copper foil layer of the capacitor burying plate.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
The above and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
FIG. 1 is a cross-sectional view of a capacitor according to a first embodiment of the present invention;
FIG. 2 is a cross-sectional view of a capacitor according to a second embodiment of the present invention;
FIG. 3 is a cross-sectional view of a circuit board in a second embodiment of the present invention;
FIG. 4 is a flow chart of a circuit board burying process according to an embodiment of the present invention.
Reference numerals:
a first copper foil layer 100; a hollowed-out portion 110; an electrically conductive body 120;
a buried capacitor dielectric layer 200;
a second copper foil layer 300;
an insulating layer 400;
a core board 500;
a buried capacitor plate 600;
a wiring board 700.
Detailed Description
Reference will now be made in detail to the present embodiments of the present invention, preferred embodiments of which are illustrated in the accompanying drawings, wherein the drawings are provided for the purpose of visually supplementing the description in the specification and so forth, and which are not intended to limit the scope of the invention.
In the description of the present invention, it should be understood that the orientation or positional relationship referred to in the description of the orientation, such as the upper, lower, front, rear, left, right, etc., is based on the orientation or positional relationship shown in the drawings, and is only for convenience of description and simplification of description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention.
In the description of the present invention, the meaning of a plurality of means is one or more, the meaning of a plurality of means is two or more, and larger, smaller, larger, etc. are understood as excluding the number, and larger, smaller, inner, etc. are understood as including the number. If the first and second are described for the purpose of distinguishing technical features, they are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated or implicitly indicating the precedence of the technical features indicated.
In the description of the present invention, unless otherwise specifically limited, terms such as set, installation, connection and the like should be understood in a broad sense, and those skilled in the art can reasonably determine the specific meanings of the above terms in the present invention by combining the specific contents of the technical solutions.
Referring to fig. 1 and 2, it can be understood that the first aspect embodiment of the present invention provides a capacitor, which includes a plurality of first copper foil layers 100 and a plurality of buried dielectric layers 200, and generally speaking, the number of the first copper foil layers 100 is one more than the number of the buried dielectric layers 200. The plurality of first copper foil layers 100 are sequentially stacked from bottom to top, each first copper foil layer 100 obtains a desired circuit through an etching process, and the etched portion forms a hollow portion 110. The capacitor-embedded dielectric layer 200 is disposed between two adjacent first copper foil layers 100 for insulation, and the capacitor-embedded dielectric layer 200 has a higher dielectric constant.
Referring to fig. 1 and 2, it can be understood that, in any three first copper foil layers 100, an electrical conductor 120 is connected between two other copper foil layers spaced by one first copper foil layer 100, and the electrical conductor 120 is inserted into the hollow portion 110 of the middle first copper foil layer 100. So that two first copper foil layers 100 having one first copper foil layer 100 at any interval are conducted and two adjacent first copper foil layers 100 are not conducted. Two adjacent first copper foil layers 100 and the capacitor-embedded dielectric layers 200 therebetween form one capacitor unit, and it is understood that the number of the capacitor units is equal to the number of the capacitor-embedded dielectric layers 200. Therefore, the capacitor consisting of a plurality of capacitor units is obtained, the capacitance value of the capacitor is expanded by multiple times, and the expansion times are the same as the number of the capacitor units, so that the functional requirements are met. Meanwhile, due to the adoption of the laminated arrangement mode, the thickness is only increased, the width and the length are not changed, and the whole volume of the capacitor can be effectively reduced.
The structure of the capacitor will be described in detail below by taking a capacitor having three first copper foil layers 100 as an example.
Referring to fig. 1, it can be understood that, in the three first copper foil layers 100, a capacitor-burying dielectric layer 200 is disposed between the adjacent two first copper foil layers 100, that is, two capacitor-burying dielectric layers 200 are provided. The three first copper foil layers 100 are defined as a first layer, a second layer, and a third layer from top to bottom, respectively. The first layer is conducted with the third layer, and the first layer is not conducted with the second layer and the second layer is not conducted with the third layer. The first layer, the second layer and the embedded capacitance medium layer 200 therebetween, and the second layer, the third layer and the embedded capacitance medium layer 200 therebetween all form capacitor units, that is, a capacitor formed by two capacitor units is formed, and the capacitance value of the capacitor is twice of that of a common plate capacitor.
The structure of the capacitor will be further described by taking the capacitor with four first copper foil layers 100 as an example.
Referring to fig. 2, it can be understood that, in the four first copper foil layers 100, a capacitor-embedded dielectric layer 200 is disposed between the adjacent two first copper foil layers 100, i.e., three capacitor-embedded dielectric layers 200 are disposed. The four first copper foil layers 100 are defined as a first layer, a second layer, a third layer and a fourth layer from top to bottom, respectively. The first layer is conducted with the third layer, the second layer is conducted with the fourth layer, and the first layer is not conducted with the second layer, the second layer is not conducted with the third layer, and the third layer is not conducted with the fourth layer. The first layer, the second layer and the embedded capacitance medium layer 200 therebetween, the second layer, the third layer and the embedded capacitance medium layer 200 therebetween, and the third layer, the fourth layer and the embedded capacitance medium layer 200 therebetween all form capacitor units, that is, a capacitor formed by three capacitor units is formed, and the capacitance value of the capacitor is three times of that of a common plate capacitor.
It is understood that the burying dielectric layer 200 is made of dielectric particles mixed with polymer resin. Specifically, barium titanate is selected as the dielectric particles, epoxy resin is adopted as the polymer resin, and the barium titanate and the epoxy resin are mixed according to a certain proportion to obtain the material of the high-dielectric-constant embedding dielectric layer 200, so that the embedding dielectric layer 200 with the adhesion and the high dielectric constant is obtained, on one hand, the first copper foil layers 100 on two adjacent sides can be adhered for stacking, and on the other hand, the capacitor with the high capacitance value can be manufactured.
It is understood that the dielectric constant of the buried dielectric layer 200 is D, satisfying: d is more than or equal to 15 and less than or equal to 30. The dielectric constant of a general capacitor dielectric layer is only 10, and in this embodiment, the dielectric constant of the embedded capacitor dielectric layer 200 reaches 15 to 30 according to different proportions of barium titanate and epoxy resin, so that a capacitor with a high dielectric constant is obtained, and the functional requirements are met.
Referring to fig. 2, it can be understood that the first copper foil layer 100 has a thickness T1 and the buried dielectric layer 200 has a thickness T2. Generally, the thickness of the first copper foil layer 100 is small, satisfying: t1 is more than or equal to 1 and less than or equal to 200 mu m, and the thickness of the capacitor-embedding dielectric layer 200 is not more than the thickness of the first copper foil layer 100, i.e. the thickness of the capacitor-embedding dielectric layer 200 is thinner. Since the thinner the capacitor dielectric layer is, the higher the capacitance value of the capacitor is, the thinner the capacitor-embedded dielectric layer 200 can further increase the capacitance value of the capacitor, and meet the functional requirements. Specifically, T2 is more than or equal to 0.1 and less than or equal to 50 mu m.
Referring to fig. 3, it can be understood that the second aspect embodiment of the present invention provides a circuit board, which includes the capacitor of the first aspect embodiment, two insulating layers 400 and two second copper foil layers 300.
The specific structure of the circuit board will be described in detail below by taking as an example a circuit board embedded with a capacitor having four first copper foil layers 100.
Referring to fig. 3, it can be understood that the insulation layer 400 is an epoxy resin plate, two insulation layers 400 are laminated on the outer sides of the first copper foil layer 100 and the fourth copper foil layer 100, respectively, and two second copper foil layers 300 are laminated on the outer sides of the two insulation layers 400, respectively. The second copper foil layer 300 on the upper side is conducted to the first copper foil layer 100 through the conductor 120, and the second copper foil layer 300 on the lower side is conducted to the fourth copper foil layer 100 through the conductor 120, thereby embedding the capacitor in the circuit board. Because the capacitance value of condenser has enlarged four times, then the circuit board possesses the condenser of four times capacitance value to satisfy the functional requirement, and the volume of condenser is less, can obtain miniaturized circuit board, in order to satisfy the installation requirement.
In other embodiments, it is understood that for a circuit board embedded with a capacitor having three first copper foil layers 100, the upper second copper foil layer 300 is in electrical communication with the first copper foil layer 100 through the electrical conductor 120, and the lower second copper foil layer 300 is in electrical communication with the third copper foil layer 100 through the electrical conductor 120.
Of course, the capacitor may be embedded in a capacitor having more layers of the first copper foil layer 100 as needed.
Referring to fig. 4, it can be understood that the embodiment of the third aspect of the present invention provides a circuit board embedding process, which is applied to process the circuit board of the embodiment of the second aspect, so as to obtain a circuit board with a high capacitance value and a small volume.
The circuit board embedding process comprises the following steps:
s100: the capacitor-embedded dielectric layer and the first copper foil layers arranged on two sides of the capacitor-embedded dielectric layer form a core plate, and two first copper foil layers of the core plate are etched.
The capacitor-embedded dielectric layer 200 is disposed on one side of one first copper foil layer 100, and the other first copper foil layer 100 is laminated on the capacitor-embedded dielectric layer 200, so that the capacitor-embedded dielectric layer 200 is sandwiched between the two first copper foil layers 100, thereby forming the core board 500. According to the set circuit diagram, the first copper foil layers 100 on both sides of the core board 500 are etched by an etching process, the etched portions form hollow portions 110, and the remaining portions are the circuits of the core board 500.
S200: the capacitor-embedded plates are formed by capacitor-embedded dielectric layers and first copper foil layers arranged on one sides of the capacitor-embedded dielectric layers, the first copper foil layers of the capacitor-embedded plates are etched, and one sides of the capacitor-embedded plates, which are provided with the capacitor-embedded dielectric layers, are respectively pressed on two sides of the core plate in a laminating mode.
The capacitor-embedded dielectric layer 200 is disposed on one side of the first copper foil layer 100 to form the capacitor-embedded board 600, the first copper foil layer 100 of the capacitor-embedded board 600 is etched by an etching process according to a set circuit diagram, a hollow portion 110 is formed in the etched portion, and the remaining portion is a circuit of the capacitor-embedded board 600.
The plurality of capacitor embedding plates 600 are respectively laminated on two sides of the core plate 500 in a laminating manner, and the capacitor embedding dielectric layers 200 of the capacitor embedding plates 600 face the core plate 500, so that the first copper foil layers 100 are laminated.
S300: and drilling and electroplating the embedded capacitor plate and the core plate to ensure that the other two first copper foil layers with one first copper foil layer at intervals among any three first copper foil layers are conducted.
The capacitor-embedded board 600 and the core board 500 are drilled, generally speaking, the drilling position corresponds to the hollow portion 110 in the vertical direction, and then electroplating is performed at the through hole, so that the electric conductor 120 is formed between the other two first copper foil layers 100 spaced by one first copper foil layer 100, thereby conducting the other two first copper foil layers 100 spaced by one first copper foil layer 100 in any three first copper foil layers 100, and thus forming the capacitor with the multiple first copper foil layers 100, which has high capacitance and small volume.
S400: and the circuit board consists of an insulating layer and a second copper foil layer arranged on one side of the insulating layer, the second copper foil layer is etched, and one side of each of the two circuit boards provided with the insulating layer is respectively pressed on the two capacitor embedding plates on the outermost side.
The insulating layer 400 is disposed on one side of the second copper foil layer 300 to form a circuit board 700, the second copper foil layer 300 is etched by an etching process according to a set circuit diagram, the etched portion forms a hollow portion 110, and the remaining portion is a circuit of the capacitor embedding board 600.
The two circuit boards 700 are respectively pressed against the outer sides of the two outermost buried capacitor plates 600 with the insulating layer 400 facing the buried capacitor plates 600, thereby burying the capacitor in the circuit board.
S500: and drilling and electroplating the circuit board to ensure that the two second copper foil layers are respectively conducted with the first copper foil layers of the two adjacent capacitor embedding plates.
The circuit board 700 is drilled, generally speaking, the drilling position corresponds to the hollow portion 110 in the vertical direction, and then electroplating is performed at the through hole, so that the electrical conductor 120 is formed between the second copper foil layer 300 and the adjacent first copper foil layer 100, or the electrical conductor 120 is formed between the second copper foil layer 300 and another first copper foil layer 100 spaced by one first copper foil layer 100, thereby enabling the two second copper foil layers 300 to be respectively conducted with the first copper foil layers 100 of the two adjacent capacitor embedding plates 600, while the two second copper foil layers 300 are not conducted, so that the capacitor is conducted with the two circuit boards 700.
The circuit board produced and processed by the process steps has the characteristics of high capacitance value and small volume, and meets the functional requirements and miniaturization requirements.
It is understood that the material of the embedding medium layer 200 is a mixed solution of barium titanate and epoxy resin mixed in a solvent according to a certain ratio. The mixed solution is coated on one side of the first copper foil layer 100 by a coating process, and the capacitor-embedded dielectric layer 200 is formed after the solvent is dried. The capacitor burying dielectric layer 200 is disposed at one side of the first copper foil layer 100 through a coating process, so that the thickness of the capacitor burying dielectric layer 200 is easily controlled to produce the capacitor burying dielectric layer 200 with a desired thickness as required. Particularly, it is easy to produce a thinner embedded capacitor dielectric layer 200 so as to obtain a higher dielectric constant embedded capacitor dielectric layer 200, and further obtain a higher capacitance capacitor and a circuit board, thereby satisfying the functional requirements.
The embodiments of the present invention have been described in detail with reference to the accompanying drawings, but the present invention is not limited to the above embodiments, and various changes can be made within the knowledge of those skilled in the art without departing from the gist of the present invention.
Claims (8)
1. A capacitor, comprising:
the copper foil comprises a plurality of first copper foil layers which are arranged in a stacked mode, wherein hollow parts are arranged on the first copper foil layers;
the capacitor-embedded dielectric layer is arranged between two adjacent first copper foil layers;
and in any three first copper foil layers, an electric conductor is connected between the other two first copper foil layers with one first copper foil layer at intervals, and the electric conductor is arranged in the hollow part of the first copper foil layer in the middle in a penetrating manner.
2. A capacitor according to claim 1, wherein: the capacitor-embedded dielectric layer is made by mixing dielectric particles and polymer resin.
3. A capacitor according to claim 1, wherein: the dielectric constant of the embedded capacitor dielectric layer is D, and the following requirements are met: d is more than or equal to 15 and less than or equal to 30.
4. A capacitor according to any one of claims 1 to 3, wherein: the thickness of first copper foil layer is T1, satisfies: t1 is more than or equal to 1 and less than or equal to 200 mu m.
5. A capacitor according to any one of claims 1 to 3, wherein: the thickness of the capacitor-embedded dielectric layer is T2, and the following requirements are met: t2 is more than or equal to 0.1 and less than or equal to 50 mu m.
6. Circuit board, its characterized in that: the method comprises the following steps:
the capacitor of any one of claims 1 to 5;
the two insulating layers are respectively arranged on the outer sides of the two first copper foil layers on the outermost side of the capacitor;
and the two second copper foil layers are respectively arranged at the outer sides of the two insulating layers, and are communicated with the first copper foil layer at the outermost side, or are communicated with the other first copper foil layer which is separated by one first copper foil layer.
7. The burying process of the circuit board, which is applied to process the circuit board of claim 6, characterized by comprising the following steps:
forming a core board by a capacitor-embedded dielectric layer and first copper foil layers arranged on two sides of the capacitor-embedded dielectric layer, and etching the two first copper foil layers of the core board;
forming a capacitor-embedded plate by a capacitor-embedded dielectric layer and a first copper foil layer arranged on one side of the capacitor-embedded dielectric layer, etching the first copper foil layer of the capacitor-embedded plate, and laminating the sides of the capacitor-embedded plates, which are provided with the capacitor-embedded dielectric layers, on two sides of the core plate in a laminating manner respectively;
drilling and electroplating the embedded capacitor plate and the core plate to ensure that the other two first copper foil layers with one first copper foil layer at intervals among any three first copper foil layers are conducted;
the circuit board is composed of an insulating layer and a second copper foil layer arranged on one side of the insulating layer, the second copper foil layer is etched, and one side of each of the two circuit boards provided with the insulating layer is respectively pressed on the two capacitor embedding plates on the outermost side;
and drilling and electroplating the circuit board to ensure that the two second copper foil layers are respectively conducted with the first copper foil layers of the two adjacent capacitor embedding plates.
8. The circuit board burying process of claim 7, wherein: and the capacitor-embedding dielectric layer of the capacitor-embedding plate is coated on the first copper foil layer of the capacitor-embedding plate.
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| CN202211069806.7A CN115483033A (en) | 2022-09-02 | 2022-09-02 | Capacitor, circuit board and circuit board embedding process |
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| CN202211069806.7A CN115483033A (en) | 2022-09-02 | 2022-09-02 | Capacitor, circuit board and circuit board embedding process |
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| CN107683032A (en) * | 2017-08-31 | 2018-02-09 | 江苏普诺威电子股份有限公司 | Two-sided etching burying capacitance circuit board manufacture craft |
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