CN115474313A - Control method and circuit - Google Patents

Abstract

The circuit is applied to a silicon controlled LED driver and comprises a voltage conversion module, a zero-crossing detection module, an abnormal state detection module, a timing module, a leakage current threshold value regulation module and a constant current module; the invention also provides a corresponding control method, which can realize real-time automatic adjustment of the discharge current according to the detected abnormal state of the dimmer and is compatible with dimmers of various models.

Description

Control method and circuit

Technical Field

The invention relates to the field of LED dimming power supplies, in particular to a self-adaptive control circuit and a control method thereof.

Background

The invention discloses a silicon controlled dimmer, which is used for realizing illumination by heating a resistance wire to generate light, and adjusting the brightness of an incandescent lamp by adjusting the conduction angle of a silicon controlled to adjust the effective value of input voltage in order to meet the adjustment of the illumination brightness in different application occasions.

As the times have progressed, a Light Emitting Diode (LED) is widely used as a new light source because it has advantages of color adjustability, high light emitting efficiency, low power consumption, high reliability, and long life. The dimming mode of the LED light source has various modes, such as silicon controlled rectifier dimming, analog dimming, PWM dimming, switch dimming and the like, but the market share of the silicon controlled rectifier dimming LED lamp is very large because silicon controlled rectifier dimmers are installed in a plurality of early buildings, and the linear driving silicon controlled rectifier dimming mode has the advantages of simple circuit structure, no need of magnetic devices, low cost, good EMI (electro-magnetic interference), small volume and wide application.

The existing linear driving silicon controlled rectifier dimming LED driving circuit is shown in figure 1, the scheme is provided with two current limiting units, the current limiting unit 1 is used for setting a leakage current with a fixed size and maintaining the normal work of the silicon controlled rectifier, the current limiting unit 2 is used for setting a fixed LED current maximum value, as the specifications of the maintenance current of the silicon controlled rectifier are various, the silicon controlled rectifier is in a dimmer box and is fixed on the wall surface early, a linear driver with larger leakage current is needed to be compatible with dimmers with different models, the traditional scheme often causes the phenomenon that the leakage current is much larger than the actually required maintenance current, the excessive leakage current does not have any effect, the power consumption is wasted, the power consumption is large, the heating is severe, and the like.

Disclosure of Invention

In view of the above, the technical problem to be solved by the present invention is to provide a controller and a control method for a dimming power supply, which enable the linear thyristor LED driver of the present invention to detect an abnormal state of a dimmer, and automatically adjust a bleed current in real time according to the abnormal state, so as to achieve self-use bleed current adjustment and be compatible with dimmers of various models.

The technical scheme for solving the problems is as follows:

a control circuit is applied to an LED driver and comprises a voltage conversion module, a zero-crossing detection module, an abnormal state detection module, a timing module, a leakage current threshold value adjusting module and a constant current module; the voltage conversion module, the zero-crossing detection module and the abnormal state detection module are used for inputting bus voltage partial pressure rectified by the LED driver, the voltage conversion module is connected with the abnormal state detection module and outputs differential voltage V1 and integral voltage V2 to the abnormal state detection module, the zero-crossing detection module is connected with the abnormal state detection module and the timing module and outputs zero-crossing signals Vz to the abnormal state detection module, the timing module is connected with the abnormal state detection module and outputs timing signals Vm to the abnormal state detection module, the abnormal state detection module is connected with the leakage current threshold value adjustment module and outputs leakage current adjustment signals Vt to the leakage current threshold value adjustment module, the leakage current threshold value adjustment module outputs reference voltage Vref1 to the constant current module, one end of the constant current module is connected with one end of a resistor Rb of the LED driver, the other end of the resistor Rb of the LED driver is connected with the bus voltage rectified by the LED driver, and the other end of the constant current module is connected with a reference ground GND.

One end of the upper voltage-dividing resistor RH is connected to the rectified bus voltage VBUS, the other end of the upper voltage-dividing resistor RH is connected to one end of the lower voltage-dividing resistor RL, the voltage conversion module, the zero-cross detection module and the abnormal state detection module, and the other end of the lower voltage-dividing resistor RL is connected to the ground GND.

As a specific embodiment of the voltage conversion module, the voltage conversion module includes a resistor R2, a resistor R3, a resistor R4, a resistor R5, a capacitor C2, and a capacitor C3; one end of the resistor R5 is connected with one end of the capacitor C2, the connection point is used for connecting bus voltage division after rectification of the LED driver, the other end of the capacitor C2 is connected with one end of the resistor R2, one end of the resistor R3 and one end of the resistor R4, the connection point is used for outputting differential voltage V1, the other end of the resistor R2 is used for connecting reference voltage Vref, the other end of the resistor R5 is connected with one end of the capacitor C3 and used for outputting integral voltage V2, and the other end of the resistor R3, the other end of the resistor R4 and the other end of the capacitor C3 are connected with reference ground GND.

The zero-crossing detection module comprises a comparator 1, a comparator 2, a capacitor C4, a resistor R6, a diode D2 and a diode D3; the negative input end of the comparator 1 is used for being connected with the rectified bus voltage division of the LED driver, the positive input end of the comparator 1 is used for being connected with a reference voltage Vref0, the output end of the comparator 1 is connected with one end of the capacitor C4, the other end of the capacitor C4 is connected with the cathode of the diode D2 and the anode of the diode D3, the cathode of the diode D3 is connected with one end of the resistor R6 and the negative input end of the comparator 2, the positive input end of the comparator 2 is used for being connected with the reference voltage Vref2, the output end of the comparator 2 is connected with one end of the timing module and used for outputting a zero-crossing signal Vz, the other end of the timing module is connected with the abnormal state detection module and used for outputting a timing signal Vm, and the anode of the diode D2 and the other end of the resistor R6 are connected with a reference ground GND.

As a specific embodiment of the abnormal state detection module, the abnormal state detection module includes a comparator 3, a comparator 4, a comparator 5, a comparator 6, a D flip-flop 1, a D flip-flop 2, a counter 1, and an or gate 1; the positive input end of the comparator 3 is used for inputting an integral voltage V2, the negative input end of the comparator 3 is used for connecting a reference voltage Vref3, the output end of the comparator 3 is connected with a data input end D of the D flip-flop 1, the output end Q of the D flip-flop 1 is connected with a first input end of the OR gate 1, the reset end R of the D flip-flop 1 is used for inputting a zero-crossing signal Vz, the positive input end of the comparator 4 is used for connecting a reference voltage Vref4, the negative input end of the comparator 4 is used for inputting a differential voltage V1, the output end of the comparator 4 is connected with a second input end of the OR gate 1, the positive input end of the comparator 5 is used for inputting the differential voltage V1, the negative input end of the comparator 5 is used for connecting a reference voltage Vref5, the output of the comparator 5 is connected with an edge signal input end CP of the D flip-flop 1 and is simultaneously connected with a clock signal input end CLK of the counter 1, the reset end of the counter 1 is used for inputting the zero-crossing signal Vz, the output end Q1 of the OR gate 1 is connected with a third input end of the OR gate 1, the positive input end of the comparator 6 is connected with a positive input end of the reference voltage Vref6, the negative input end of the thyristor driver RST driver, the comparator 6 is used for inputting a rectified current regulator D gate 2, and the output end Vt is connected with a fourth input end of the output end of the rectified signal Vr gate 2, and the output end of the rectified output end of the rectifier gate 1, the rectifier gate 2, the comparator 3 is used for outputting a rectified current regulator, and the output end Vr.

As a specific implementation manner of the bleeding current threshold adjusting module, the bleeding current threshold adjusting module includes a counter 2, a resistor R7, a voltage-controlled current source 1, a voltage-controlled current source 2, a voltage-controlled current source 3, and a voltage-controlled current source 4; the clock signal input end CLK of the counter 2 is used for inputting the bleeder current adjustment signal Vt, the output end Q0 of the counter 2 is connected with the voltage control end of the voltage-controlled current source 1, the output end Q1 of the counter 2 is connected with the voltage control end of the voltage-controlled current source 2, the output end Q2 of the counter 2 is connected with the voltage control end of the voltage-controlled current source 3, the output end Q3 of the counter 2 is connected with the voltage control end of the voltage-controlled current source 4, the power supply ends of the four voltage-controlled current sources are all connected with the VCC, the reference ends of the four voltage-controlled current sources are all connected with the GND (ground), the current output ends of the four voltage-controlled current sources are all connected with one end of the resistor R7, the reference voltage Vref1 is output, and the other end of the resistor R7 is connected with the GND.

The specific implementation mode of the constant current module comprises an operational amplifier 1, an MOS (metal oxide semiconductor) transistor S1 and a resistor R8; the positive input end of the operational amplifier 1 is used for inputting a reference voltage Vref1, the negative input end of the operational amplifier 1 is connected with one end of a resistor R8 and is connected to the source electrode of a switch tube S1, the grid electrode of the MOS tube S1 is connected with the output end of the operational amplifier 1, the drain electrode of the MOS tube S1 is used for being connected with one end of a resistor Rb of a silicon controlled LED driver, and the other end of the resistor R8 is connected with a reference ground GND.

Preferably, the control circuit further comprises a controlled silicon access identification module, and the controlled silicon access identification module is connected with the abnormal state detection module and the constant current module.

The specific implementation mode of the thyristor access identification module comprises a D trigger 3 and a diode D4; an edge signal input end CP of the D trigger 3 is connected with the abnormal state detection module, a data input end D of the D trigger 3 is used for being connected with a voltage VCC, an output end Q of the D trigger 3 is connected with a cathode of a diode D4, and an anode of the diode D4 is connected with the constant current module.

The invention also provides a control method applied to the LED driver, which is characterized by comprising the following steps:

a voltage conversion step, namely dividing and converting the input bus voltage into a differential voltage V1 and an integral voltage V2 and then outputting the differential voltage V1 and the integral voltage V2;

a zero-crossing detection step, namely detecting the voltage division of the bus and outputting a zero-crossing signal Vz after detecting that the voltage division of the bus is reduced from a high voltage to a low voltage;

a timing step, namely taking the input zero-crossing signal Vz as a periodic reset signal for abnormal state identification, starting timing after receiving the zero-crossing signal Vz, wherein the timing time is first timing time, and outputting a timing signal Vm after the first timing time is up;

an abnormal state detection step, namely identifying whether the working state of the dimmer is normal or not according to the differential voltage V1 or the integral voltage V2 or the zero-crossing signal Vz or according to the timing signal Vm and the bus voltage division, and outputting a discharge current regulation signal Vt when the abnormal state occurs, wherein the discharge current regulation signal Vt is a pulse signal;

a step of adjusting a leakage current threshold, namely increasing a reference voltage Vref1 according to a leakage current adjusting signal Vt until the leakage current influenced by the reference voltage Vref1 is just larger than the maintaining current of a dimmer in the LED driver, wherein the increasing amplitude of the reference voltage Vref1 is smaller each time, so that the leakage current is better matched with the maintaining current of the dimmer in the LED driver;

and a constant current step of adjusting the magnitude of the bleed current according to the change of the reference voltage Vref1.

The specific step of "identifying whether the working state of the dimmer is normal according to the differential voltage V1, the integral voltage V2, the zero-crossing signal Vz, or the timing signal Vm and the bus voltage division" is:

the differential voltage V1 is compared with a first set threshold value in the abnormal state detection module, a first counting signal is output when the differential voltage V1 is higher than the first set threshold value, and the working state of the dimmer is judged to be abnormal when the first counting signal exceeds 1 time;

the differential voltage V1 is also compared with a second set threshold value in the abnormal state detection module, and the working state of the dimmer is judged to be abnormal when the differential voltage V1 is lower than the second set threshold value;

the integral voltage V2 is compared with a third threshold value inside the abnormal state detection module at the moment when the first counting signal is generated for the first time, and if the integral voltage V2 is higher than the third threshold value, the working state of the dimmer is judged to be abnormal;

when the abnormal state detection module receives the timing signal Vm, the bus voltage division voltage VB is compared with a fourth threshold value inside the abnormal state detection module, and if the bus voltage division voltage VB is lower than the fourth threshold value, the working state of the dimmer is judged to be abnormal.

The invention has the beneficial effects that:

1. the self-adaptive adjustment of the discharge current is realized through the detection of the abnormal state of the controlled silicon;

2. the dimmer compatibility of the driving circuit scheme is improved through self-adaptive bleeder current regulation;

3. the leakage current and the holding current are optimally matched through self-adaptive leakage current regulation, so that the power consumption is reduced, and the efficiency is improved.

Drawings

Fig. 1 is a circuit diagram of a conventional linear driving thyristor dimming LED driving circuit;

FIG. 2 is a schematic block diagram of the circuit of the present invention;

FIG. 3 is a schematic diagram of a first portion of modules according to one embodiment of the present invention;

FIG. 4 is a schematic diagram of a second portion of modules in accordance with one embodiment of the present invention;

fig. 5 is a waveform diagram of an abnormal state of a first type of scr dimmer recognized according to a first embodiment of the present invention;

fig. 6 is a waveform diagram of abnormal states of a second type of scr dimmer recognized according to a first embodiment of the present invention;

fig. 7 is a waveform diagram of an abnormal state of a third type of scr dimmer recognized according to the first embodiment of the present invention;

fig. 8 is a waveform diagram of an abnormal state of a fourth type of scr dimmer recognized according to the first embodiment of the present invention;

FIG. 9 is a schematic diagram of a second first portion of the modules of the embodiment of the present invention;

fig. 10 is a schematic diagram of a second module according to the second embodiment of the present invention.

Detailed Description

The present invention will be described in detail with reference to the following embodiments and the accompanying drawings to help those skilled in the art to better understand the inventive concept of the present invention, but the scope of the claims of the present invention is not limited to the following embodiments, and all other embodiments obtained without inventive efforts by those skilled in the art will fall within the scope of the present invention without departing from the inventive concept of the present invention.

The technical scheme of the invention is as shown in fig. 2, and in combination with fig. 1, a linear LED driver comprises a thyristor dimmer, a rectifier bridge, an upper voltage-dividing resistor RH, a lower voltage-dividing resistor RL, a control circuit, a resistor Rb, a diode D1, a load LED, a current-limiting unit and a capacitor C1, wherein the control circuit comprises a voltage conversion module, a zero-crossing detection module, an abnormal state detection module, a timing module, a leakage current threshold value adjustment module and a constant current module. The rectified bus voltage VBUS is connected with one end of an upper voltage-dividing resistor RH, the other end of the upper voltage-dividing resistor RH is connected with one end of a lower voltage-dividing resistor RL, the other end of the upper voltage-dividing resistor RH is connected with a voltage conversion module, a zero-crossing detection module and an abnormal state detection module, the other end of the lower voltage-dividing resistor RL is connected with a ground reference GND, the voltage conversion module outputs a differential voltage V1 and an integral voltage V2 which are all connected into the abnormal state detection module, the zero-crossing detection module outputs a zero-crossing signal Vz to the abnormal state detection module and the timing module, the timing module outputs a timing signal Vm to the abnormal state detection module, the abnormal state detection module outputs a leakage current adjusting signal Vt to the leakage current threshold adjusting module, the leakage current threshold adjusting module outputs a reference voltage Vref1 to a constant current module, one end of the constant current module is connected with one end of a resistor Rb, the other end of the resistor Rb is connected with the bus voltage VBUS, the bus voltage VBUS is also connected with the anode of a diode D1, the cathode of the diode D1 is connected with the anode of a load LED and the anode of a capacitor C1, the cathode of the load LED is connected with the cathode of the capacitor C1 and the other end of the current limiting unit, and the ground reference GND.

The working principle of the circuit of the invention is as follows:

when the silicon controlled dimmer is connected to a power grid, a capacitor in the silicon controlled dimmer is charged, the bus voltage VBUS begins to rise, the capacitor in the silicon controlled dimmer is charged enough to break through the bidirectional voltage stabilizing diode and then trigger the silicon controlled dimmer to be conducted, the leakage current is the minimum value in the initial state, the bus voltage VBUS is divided by the upper voltage dividing resistor RH and the lower voltage dividing resistor RL to obtain a bus voltage dividing voltage VB, the bus voltage dividing voltage VB is input to the voltage conversion module, the abnormal state detection module and the zero-crossing detection module, and the voltage conversion module can convert the bus voltage dividing voltage VB into differential voltage V1 and integral voltage V2;

when the zero-crossing detection module detects that the bus voltage divided voltage VB is reduced from a high voltage to a low voltage, the zero-crossing signal Vz is output to the abnormal state detection module and serves as a periodic reset signal for abnormal state identification, the timing module starts timing after receiving the zero-crossing signal Vz, the timing time is first timing time, and when the first timing time is up, the timing module outputs a timing signal Vm;

the differential voltage V1 is compared with a first set threshold value in the abnormal state detection module, a first counting signal is output when the differential voltage V1 is higher than the first threshold value, and the abnormal condition 1 is judged to be achieved when the first counting signal exceeds 1 time; the differential voltage V1 is also compared with a second set threshold value in the abnormal state detection module, and when the differential voltage V1 is lower than the second threshold value, the abnormal condition 2 is judged to be achieved; comparing the integrated voltage V2 with a third threshold value inside the abnormal state detection module at the moment when the first counting signal is generated for the first time, and judging that an abnormal condition 3 is achieved if the integrated voltage V2 is higher than the third threshold value; when the abnormal state detection module receives the timing signal Vm, comparing the bus voltage division voltage VB with a fourth threshold value inside the abnormal state detection module, and if the bus voltage division voltage VB is lower than the fourth threshold value, judging that an abnormal condition 4 is achieved;

when any one of the abnormal conditions is achieved, the abnormal state detection module outputs a leakage current adjusting signal Vt, the leakage current threshold adjusting module receives the leakage current adjusting signal Vt, adjusts the constant current reference voltage Vref1 of the constant current module to rise by one gear, the leakage current is raised by one gear from the minimum value, if no abnormal condition is achieved, the silicon controlled dimmer normally works, the same operation is performed in the next period, the state identification of the silicon controlled dimmer is performed, if the leakage current is smaller than the maintenance current of the silicon controlled dimmer, the abnormal state is identified, the reference voltage Vref1 of the constant current module is raised by one gear again, the detection is performed in the same mode in the next period until the leakage current is just larger than the maintenance current, and the amplitude of the increase of one gear is small, so that the leakage current can be better matched with the maintenance current of the silicon controlled dimmer.

Only the key blocks of the invention, i.e. the principle of the control circuit, will be described in detail when introducing the embodiments, the rest being conventional known technical blocks, which will not be described.

Example one

Fig. 3 is a schematic diagram of a first part of module circuits in this embodiment, and fig. 4 is a schematic diagram of a second part of module circuits in this embodiment, where this embodiment includes a voltage conversion module, a zero-crossing detection module, a timing module, an abnormal state detection module, a bleeding current threshold adjustment module, and a constant current module.

The voltage conversion module comprises a resistor R2, a resistor R3, a resistor R4, a resistor R5, a capacitor C2 and a capacitor C3, a zero-crossing detection module comprises a comparator 1, a comparator 2, a capacitor C4, a resistor R6, a diode D2 and a D3, an abnormal state detection module comprises a comparator 3, a comparator 4, a comparator 5, a comparator 6, a D trigger 1, a D trigger 2, a counter 1 and an OR gate 1, a leakage current threshold value regulation module comprises a counter 2, a resistor R7 and a voltage-controlled current source 1, 2, 3 and 4, a constant current module comprises an operational amplifier 1, an MOS (metal oxide semiconductor) tube S1 and a resistor R8, and the specific connection relation is as follows:

one end of the resistor R5 and one end of the capacitor C2 are connected with a bus voltage dividing point, the other end of the capacitor C2 is connected with one end of the resistor R2, one end of the resistor R3 and one end of the resistor R4, the connecting point is a differential signal output end, the other end of the resistor R3 and the other end of the resistor R4 are connected with a reference ground GND, the other end of the resistor R2 is connected with a reference voltage Vref, the other end of the resistor R5 is an integral voltage output end, the one end is connected with one end of the capacitor C3, and the other end of the capacitor C3 is connected with the reference ground GND;

the negative input end of a comparator 1 of a zero-crossing detection module is connected with a bus voltage dividing point, the positive input end of the comparator 1 is connected with a reference voltage Vref0, the output end of the comparator 1 is connected with one end of a capacitor C4, the other end of the capacitor C4 is connected with the cathode of a diode D2 and the anode of the diode D3, the anode of the diode D2 is connected with a reference ground GND, the cathode of the diode D3 is connected with one end of a resistor R6 and the negative input end of the comparator 2, the other end of the resistor R6 is connected with the reference ground GND, the positive input end of the comparator 2 is connected with the reference voltage Vref2, the output end of the comparator 2 is a zero-crossing signal output point, the zero-crossing signal output point is connected with one end of a timing module, and the other end of the timing module is a timing signal output end;

in the abnormal state detection module, a positive input end of a comparator 3 is connected with an integrated voltage output end, a negative input end of the comparator 3 is connected with a reference voltage Vref3, an output end of the comparator 3 is connected with a data input end D of a D trigger 1, an output end Q of the D trigger 1 is connected with a first input end of an OR gate 1, a reset end R of the D trigger 1 is connected with a zero-crossing signal output end, a positive input end of a comparator 4 is connected with a reference voltage Vref4, a negative input end of the comparator 4 is connected with a differential signal output end, an output end of the comparator 4 is connected with a second input end of the OR gate 1, a positive input end of the comparator 5 is connected with a differential signal output end, a negative input end of the comparator 5 is connected with a reference voltage Vref5, an output end of the comparator 5 is connected with an edge signal input end CP of the D trigger 1 and is simultaneously connected with a clock signal input end CLK of the counter 1, a reset end RST of the counter 1 is connected with a zero-crossing signal output end, an output end Q1 is connected with a third input end of the OR gate 1, a positive input end of the comparator 6 is connected with a reference voltage Vref6, a negative input end of the D trigger signal output end of the D trigger module, a fourth input end of the D trigger module is connected with a timing signal output end of the timing signal module, and a timing signal output end of the timing module, four timing module, and a timing signal output end of the timing signal module;

a clock signal input end CLK of a counter 2 in the bleeder current threshold adjusting module is connected with an output end of an OR gate 1, an output end Q0 of the counter 2 is connected with a voltage control end of a voltage-controlled current source 1, an output end Q1 of the counter 2 is connected with a voltage control end of the voltage-controlled current source 2, an output end Q2 of the counter 2 is connected with a voltage control end of the voltage-controlled current source 3, an output end Q3 of the counter 2 is connected with a voltage control end of a voltage-controlled current source 4, power supply ends of the four voltage-controlled current sources are all connected with VCC, reference ends of the four voltage-controlled current sources are all connected with GND, current output ends of the four voltage-controlled current sources are all connected with one end of a resistor R7, the one end is a reference output end of the threshold adjusting module, and the other end of the resistor R7 is connected with GND;

the positive input end of an operational amplifier 1 in the constant current module is connected with a reference output end, the negative input end of the operational amplifier 1 is connected with one end of a resistor R8 and is simultaneously connected to the source electrode of an MOS (metal oxide semiconductor) tube S1, the other end of the resistor R8 is connected with a reference ground GND (ground), the grid electrode of the MOS tube S1 is connected with the output end of the operational amplifier 1, and the drain electrode of the MOS tube S1 is connected with one end of a bleeder current branch circuit resistor Rb;

the bus voltage division point outputs a bus voltage division voltage VB, the integral voltage output end outputs an integral voltage V2, the differential signal output end outputs a differential voltage V1, the zero-crossing signal output end outputs a zero-crossing signal Vz, the timing signal output end outputs a timing signal Vm, the regulating signal output end outputs a leakage current regulating signal Vt, and the reference output end outputs a reference voltage Vref1.

The working process is as follows:

in case 1, when the leakage current is slightly smaller than the holding current and the triac dimmer is located near the brightest (RC minimum), such an abnormal state as shown in fig. 5 occurs, and the triac dimmer is turned on and off many times, and the specific principle of the abnormal recognition is that the bus voltage VBUS is in a state close to zero before the first phase cut, the differential voltage V1 maintains the voltage of the reference voltage Vref divided by the resistors R2 and R4, the comparator 5 does not turn over, when the bus voltage VBUS is subjected to the first phase cut, the differential voltage V1 generates a higher voltage spike, the spike voltage is higher than the reference voltage Vref5, the comparator 5 turns over, the output terminal Q0 is set to 1 after the counter 1 receives a rising edge signal, and the triac dimmer is turned off after a period of time due to insufficient leakage current after the phase cut, and the bus voltage VBUS decreases, then the capacitor in the silicon controlled dimmer is recharged again, when the voltage of the capacitor in the silicon controlled dimmer is recharged to the voltage which can trigger the silicon controlled dimmer to be switched on again, the bus voltage VBUS is subjected to phase cutting again, the voltage rises rapidly, the differential voltage V1 generates a higher voltage peak again, the voltage peak is higher than the reference voltage Vref5, the comparator 5 is overturned, the counter 1 receives a rising edge signal again, the output end Q0 is set to 0, the output end Q1 is set to 1, or the third input end of the gate 1 is at high level, so that the bleeder current adjusting signal Vt becomes high level, a rising edge is generated, the signal is input to the clock signal input end CLK of the counter 2, the output end Q0 of the counter 2 is set to 1, the voltage-controlled current source 1 outputs 1 unit of current, the counter 2 counts according to the number of times of the actually received bleeder current adjusting signal Vt, finally, the four voltage-controlled current sources output unit currents with the same unit quantity of times of occurrence of the adjusting signals, the currents generate a leakage current reference on a resistor R7, the output current of the voltage-controlled current source 1 is generally set to be 1 time of the unit current, the output current of the voltage-controlled current source 2 is 2 times of the unit current, the output current of the voltage-controlled current source 3 is 4 times of the unit current, the output current of the voltage-controlled current source 4 is 8 times of the unit current, and the operational amplifier 1 adjusts the gate voltage of the MOS transistor S1 according to the size of the reference voltage Vref1 and the voltage on the resistor R8, so that the leakage current is constant at a desired value;

in case 2, when the leakage current is slightly smaller than the holding current and the triac dimmer is located near the middle (RC is medium), such an abnormal state as shown in fig. 6 occurs, and the triac dimmer has a phenomenon of turning off in advance, and the specific principle of the abnormal state is that the bus voltage VBUS is in a state close to zero before the first phase cut, the differential voltage V1 keeps the voltage of the reference voltage Vref divided by the resistors R2 and R4, the comparator 5 does not flip, when the bus voltage VBUS has the first phase cut, the differential voltage V1 generates a higher voltage spike, the spike voltage is higher than the reference voltage Vref5, the comparator 5 flips, the counter 1 receives a rising edge signal and then the output Q0 is set to 1, and when the phase cut occurs, the grid voltage is higher than the voltage drop of the load LED or the like, so the bus voltage VBUS provides the load LED with current, therefore, although the drain current is not large, the normal operation of the silicon controlled rectifier can be maintained by adding the current of the load LED, when the grid voltage is lower than the positive voltage drop of the load LED, the drain current is insufficient, the silicon controlled rectifier is turned off, the bus voltage VBUS drops quickly, the differential voltage V1 generates a negative voltage spike, the spike voltage is lower than the reference voltage Vref4, the comparator 4 is turned over, the second input end of the OR gate 1 is at a high level, the drain current adjusting signal Vt is changed into a high level, a rising edge is generated, the signal is input to the clock signal input end CLK of the counter 2, the output end Q0 of the counter 2 is set to be 1, the voltage controlled current source 1 outputs 1 unit current, the counter 2 counts according to the number of times of actually received drain current adjusting signals Vt, and finally the four voltage controlled current sources output unit currents with the same number of times as the number of times of occurrence of adjusting signals, the current generates a leakage current reference on a resistor R7, the output current of a voltage-controlled current source 1 is generally set to be 1 time of unit current, the output current of a voltage-controlled current source 2 is 2 times of unit current, the output current of a voltage-controlled current source 3 is 4 times of unit current, the output current of a voltage-controlled current source 4 is 8 times of unit current, and an operational amplifier 1 adjusts the grid voltage of an MOS transistor S1 according to the size of a reference voltage Vref1 and the voltage on the resistor R8 so that the leakage current is constant at a desired value;

in case 3, when the bleed current is very small and the triac dimmer is located near the brightest (RC minimum), such an abnormal state as shown in fig. 7 occurs, and the triac dimmer has a voltage plateau, and the specific principle of the abnormality recognition is that the bus voltage VBUS will slowly increase with the grid voltage, but the triac dimmer cannot be turned on, when the bus voltage VBUS increases to the voltage of the load LED parallel capacitor, the bus voltage VBUS will not continuously increase, and the voltage will be maintained unchanged, because there is no voltage jump in this process, the comparators will not turn over, and when the plateau voltage is maintained for a certain period of time, the capacitor inside the triac dimmer charges to the voltage that can turn on the triac dimmer, the triac dimmer turns on, and the bus voltage VBUS has the first phase cut within the period, the differential voltage V1 generates a higher voltage spike, the spike voltage is higher than the reference voltage Vref5, the comparator 5 is turned over to provide a rising edge to the edge signal input CP of the D flip-flop 1, at this time, the integral voltage V2 is the divided voltage value of the platform voltage before the bus voltage abrupt change, the value is higher than the reference voltage Vref3, the comparator 3 is turned over, the output Q of the D flip-flop 1 is high level, the high level enters the first input end of the OR gate 1 to change the bleed current adjusting signal Vt into high level, a rising edge is generated, the signal is input to the clock signal input CLK of the counter 2, the output Q0 of the counter 2 is set to be 1, the voltage-controlled current source 1 outputs 1 unit current, the counter 2 counts according to the times of the actually received bleed current adjusting signal Vt, and finally the four voltage-controlled current sources output unit currents with the same unit number of times as the adjusting signals, the current generates a leakage current reference on a resistor R7, the output current of a voltage-controlled current source 1 is generally set to be 1 time of unit current, the output current of a voltage-controlled current source 2 is 2 times of unit current, the output current of a voltage-controlled current source 3 is 4 times of unit current, the output current of a voltage-controlled current source 4 is 8 times of unit current, and an operational amplifier 1 adjusts the grid voltage of an MOS transistor S1 according to the size of a reference voltage Vref1 and the voltage on the resistor R8 so that the leakage current is constant at a desired value;

in case 4, when the drain current is very small and the dimmer is located near the darkest (RC maximum), the abnormal state shown in fig. 8 occurs, and the triac dimmer fails to turn on at all, the specific principle of the abnormal recognition is that the bus voltage VBUS increases slowly with the grid voltage, because the drain current is small, the internal capacitor of the dimmer charges very slowly and cannot reach the turn-on point of the triac dimmer, the triac dimmer fails to turn on, when the bus voltage VBUS increases to the voltage of the load LED parallel capacitor, the bus voltage VBUS does not increase continuously and maintains the voltage unchanged, because there is no abrupt voltage change during this process, the comparators do not turn over, because the drain current is very small, the capacitor voltage in the dimmer cannot charge to the voltage for turning on the triac dimmer, therefore, the bus voltage VBUS keeps the voltage value of the capacitor connected in parallel with the load LED, when the timing module times out, the timing module outputs a timing signal Vm, which is input to the edge signal input end CP of the D flip-flop 2, the output result of the comparator 6 is output to the output end Q of the D flip-flop 2, the negative input of the comparator 6 is the bus voltage division VB which is normally substantially identical to the grid voltage, but the voltage is clamped by the load LED parallel capacitor voltage in the current abnormal state, so that the value of the bus voltage division VB is smaller than the value of the reference voltage Vref6, the voltage output by the comparator 6 is high, the level of the output end Q of the D flip-flop 2 is high, and the output end Q is input to the fourth input end of the or gate 1, so that the bleed current adjusting signal Vt becomes high, a rising edge is generated, and the signal is input to the clock signal input end CLK of the counter 2, the output end Q0 of the counter 2 is set to be 1, the voltage-controlled current source 1 outputs current of 1 unit, the counter 2 can count according to the number of times of actually received bleeder current adjusting signals Vt, finally, four voltage-controlled current sources output unit current with the same unit number of times of occurrence of the adjusting signals, the current generates a bleeder current reference on a resistor R7, the output current of the voltage-controlled current source 1 is generally set to be 1 time of the unit current, the output current of the voltage-controlled current source 2 is 2 times of the unit current, the output current of the voltage-controlled current source 3 is 4 times of the unit current, the output current of the voltage-controlled current source 4 is 8 times of the unit current, and the operational amplifier 1 adjusts the grid voltage of the MOS tube S1 according to the size of the reference voltage Vref1 and the voltage on the resistor R8, so that the bleeder current is constant at a desired value.

Fig. 3 and 4 illustrate only one embodiment of fig. 2, but the scope of the claims of the present invention is not limited to the embodiment described above.

Example two

The second embodiment of the present invention is shown in fig. 9 and 10, in which a thyristor access identification module is added on the basis of the first embodiment, the thyristor access identification module is connected with an abnormal state detection module and a constant current module, the thyristor access identification module is composed of a D trigger 3 and a diode D4, and the connection relationship is as follows: an edge signal input end CP of the D trigger 3 is connected with an output end Q0 of the counter 1, a data input end D of the D trigger 3 is connected with a voltage VCC, an output end Q of the D trigger 3 is connected with a cathode of a diode D4, and an anode of the diode D4 is connected with a grid VG of an MOS tube S1 in the constant current module.

The method comprises the following steps that in the state that the silicon controlled dimmer is connected, when the system is started to work, although no leakage current is provided, the voltage of a load LED parallel capacitor is zero, so that the capacitor charging current can charge a capacitor in the silicon controlled dimmer, the silicon controlled dimmer is switched on for at least 1 time in the state that the silicon controlled dimmer is connected, the bus voltage VBUS is suddenly changed after the silicon controlled dimmer is switched on, the differential voltage V1 generates a voltage spike, the spike voltage is higher than the reference voltage Vref5, the comparator 5 is turned over, the counter 1 receives a rising edge signal, the output end Q0 is arranged at the edge signal input end CP of the D trigger 3 to generate a rising edge, the VCC high-level signal at the input end D of the D trigger 3 is output to the output end Q of the D trigger 3, the diode D4 is cut off reversely, normal discharge of a constant current module is not influenced, and the voltage value is smaller than the gate source voltage of the MOS tube S1, so that the current is discharged to control the gate source voltage threshold; when the silicon controlled dimmer is not connected and is just started to work, the bus voltage VBUS is directly equal to the voltage of a power grid, therefore, the voltage division VB of the bus voltage cannot generate voltage mutation and only can slowly change, therefore, all comparators cannot overturn, the output end Q0 of the counter 1 can keep a low level, the D trigger 3 cannot transmit data of the input end D to the output end Q, the output end Q of the D trigger 3 keeps the low level, the anode of the diode D4 is clamped near 0.7V, the voltage is smaller than the gate-source opening threshold of the MOS tube S1, therefore, the MOS tube S1 cannot be opened all the time, the constant current module does not generate leakage current, and the power consumption is not wasted. The specific principle of the rest of the working states is similar to that of the first embodiment, and is not described again.

The above is only a preferred embodiment of the present invention, it should be noted that the above preferred embodiment should not be considered as limiting the present invention, and it will be apparent to those skilled in the art that several modifications and decorations can be made without departing from the spirit and scope of the present invention, and the modifications and decorations of the triangle wave generation module, the duty ratio generation module and the logic processing module should also be considered as the protection scope of the present invention, which is not repeated herein by examples, and the protection scope of the present invention should be subject to the scope defined by the claims.

Claims (11)

1. A control circuit is applied to an LED driver and is characterized in that: the device comprises a voltage conversion module, a zero-crossing detection module, an abnormal state detection module, a timing module, a leakage current threshold value regulation module and a constant current module;

the voltage conversion module, the zero-crossing detection module and the abnormal state detection module are used for inputting bus voltage partial pressure rectified by the LED driver, the voltage conversion module is connected with the abnormal state detection module and outputs differential voltage V1 and integral voltage V2 to the abnormal state detection module, the zero-crossing detection module is connected with the abnormal state detection module and the timing module and outputs zero-crossing signals Vz to the abnormal state detection module, the timing module is connected with the abnormal state detection module and outputs timing signals Vm to the abnormal state detection module, the abnormal state detection module is connected with the leakage current threshold value adjustment module and outputs leakage current adjustment signals Vt to the leakage current threshold value adjustment module, the leakage current threshold value adjustment module outputs reference voltage Vref1 to the constant current module, one end of the constant current module is connected with one end of a resistor Rb of the LED driver, the other end of the resistor Rb of the LED driver is connected with the bus voltage rectified by the LED driver, and the other end of the constant current module is connected with a reference ground GND.

2. The control circuit of claim 1, wherein: the bus voltage division mode is that one end of an upper voltage division resistor RH is connected with the rectified bus voltage VBUS, the other end of the upper voltage division resistor RH is connected with one end of a lower voltage division resistor RL, a voltage conversion module, a zero-crossing detection module and an abnormal state detection module, and the other end of the lower voltage division resistor RL is connected with a reference ground GND.

3. The control circuit of claim 1, wherein: the voltage conversion module comprises a resistor R2, a resistor R3, a resistor R4, a resistor R5, a capacitor C2 and a capacitor C3; one end of the resistor R5 is connected with one end of the capacitor C2, the connection point is used for connecting bus voltage division after rectification of the LED driver, the other end of the capacitor C2 is connected with one end of the resistor R2, one end of the resistor R3 and one end of the resistor R4, the connection point is used for outputting differential voltage V1, the other end of the resistor R2 is used for connecting reference voltage Vref, the other end of the resistor R5 is connected with one end of the capacitor C3 and used for outputting integral voltage V2, and the other end of the resistor R3, the other end of the resistor R4 and the other end of the capacitor C3 are connected with reference ground GND.

4. The control circuit of claim 1, wherein: the zero-crossing detection module comprises a comparator 1, a comparator 2, a capacitor C4, a resistor R6, a diode D2 and a diode D3; the negative input end of the comparator 1 is used for being connected with the rectified bus voltage division of the LED driver, the positive input end of the comparator 1 is used for being connected with a reference voltage Vref0, the output end of the comparator 1 is connected with one end of the capacitor C4, the other end of the capacitor C4 is connected with the cathode of the diode D2 and the anode of the diode D3, the cathode of the diode D3 is connected with one end of the resistor R6 and the negative input end of the comparator 2, the positive input end of the comparator 2 is used for being connected with the reference voltage Vref2, the output end of the comparator 2 is connected with one end of the timing module and used for outputting a zero-crossing signal Vz, the other end of the timing module is connected with the abnormal state detection module and used for outputting a timing signal Vm, and the anode of the diode D2 and the other end of the resistor R6 are connected with a reference ground GND.

5. The control circuit of claim 1, wherein: the abnormal state detection module comprises a comparator 3, a comparator 4, a comparator 5, a comparator 6, a D trigger 1, a D trigger 2, a counter 1 and an OR gate 1; the positive input end of the comparator 3 is used for inputting an integral voltage V2, the negative input end of the comparator 3 is used for connecting a reference voltage Vref3, the output end of the comparator 3 is connected with a data input end D of the D flip-flop 1, the output end Q of the D flip-flop 1 is connected with a first input end of the OR gate 1, the reset end R of the D flip-flop 1 is used for inputting a zero-crossing signal Vz, the positive input end of the comparator 4 is used for connecting a reference voltage Vref4, the negative input end of the comparator 4 is used for inputting a differential voltage V1, the output end of the comparator 4 is connected with a second input end of the OR gate 1, the positive input end of the comparator 5 is used for inputting the differential voltage V1, the negative input end of the comparator 5 is used for connecting a reference voltage Vref5, the output of the comparator 5 is connected with an edge signal input end CP of the D flip-flop 1 and is simultaneously connected with a clock signal input end CLK of the counter 1, the reset end of the counter 1 is used for inputting the zero-crossing signal Vz, the output end Q1 of the OR gate 1 is connected with a third input end of the OR gate 1, the positive input end of the comparator 6 is connected with a positive input end of the reference voltage Vref6, the negative input end of the thyristor driver RST driver, the comparator 6 is used for inputting a rectified current regulator D gate 2, and the output end Vt is connected with a fourth input end of the output end of the rectified signal Vr gate 2, and the output end of the rectified output end of the rectifier gate 1, the rectifier gate 2, the comparator 3 is used for outputting a rectified current regulator, and the output end Vr.

6. The control circuit of claim 1, wherein: the bleeder current threshold value adjusting module comprises a counter 2, a resistor R7, a voltage-controlled current source 1, a voltage-controlled current source 2, a voltage-controlled current source 3 and a voltage-controlled current source 4; the clock signal input end CLK of the counter 2 is used for inputting a bleeder current adjusting signal Vt, the output end Q0 of the counter 2 is connected with the voltage control end of the voltage-controlled current source 1, the output end Q1 of the counter 2 is connected with the voltage control end of the voltage-controlled current source 2, the output end Q2 of the counter 2 is connected with the voltage control end of the voltage-controlled current source 3, the output end Q3 of the counter 2 is connected with the voltage control end of the voltage-controlled current source 4, the power supply ends of the four voltage-controlled current sources are connected with the VCC, the reference ends of the four voltage-controlled current sources are connected with the GND (ground), the current output ends of the four voltage-controlled current sources are connected with one end of the resistor R7, the reference voltage Vref1 is output, and the other end of the resistor R7 is connected with the GND.

7. The control circuit of claim 1, wherein: the constant current module comprises an operational amplifier 1, an MOS (metal oxide semiconductor) tube S1 and a resistor R8; the positive input end of the operational amplifier 1 is used for inputting a reference voltage Vref1, the negative input end of the operational amplifier 1 is connected with one end of a resistor R8 and is connected to the source electrode of a switch tube S1, the grid electrode of the MOS tube S1 is connected with the output end of the operational amplifier 1, the drain electrode of the MOS tube S1 is used for being connected with one end of a resistor Rb of a silicon controlled LED driver, and the other end of the resistor R8 is connected with a reference ground GND.

8. The control circuit of claim 1, wherein: the system also comprises a silicon controlled rectifier access identification module, and the silicon controlled rectifier access identification module is connected with the abnormal state detection module and the constant current module.

9. The control circuit of claim 8, wherein: the silicon controlled access identification module comprises a D trigger 3 and a diode D4; an edge signal input end CP of the D trigger 3 is connected with the abnormal state detection module, a data input end D of the D trigger 3 is used for being connected with a voltage VCC, an output end Q of the D trigger 3 is connected with a cathode of a diode D4, and an anode of the diode D4 is connected with the constant current module.

10. A control method is applied to an LED driver and is characterized by comprising the following steps:

a voltage conversion step, namely dividing and converting the input bus voltage into a differential voltage V1 and an integral voltage V2 and then outputting the differential voltage V1 and the integral voltage V2;

a zero-crossing detection step, namely detecting the voltage division of the bus and outputting a zero-crossing signal Vz after detecting that the voltage division of the bus is reduced from a high voltage to a low voltage;

a timing step, namely taking the input zero-crossing signal Vz as a periodic reset signal for abnormal state identification, starting timing after receiving the zero-crossing signal Vz, wherein the timing time is first timing time, and outputting a timing signal Vm after the first timing time is up;

an abnormal state detection step, namely identifying whether the working state of the dimmer is normal or not according to the differential voltage V1 or the integral voltage V2 or the zero-crossing signal Vz or according to the timing signal Vm and the bus voltage division, and outputting a discharge current regulation signal Vt when the abnormal state occurs, wherein the discharge current regulation signal Vt is a pulse signal;

a step of adjusting a leakage current threshold, namely increasing a reference voltage Vref1 according to a leakage current adjusting signal Vt until the leakage current influenced by the reference voltage Vref1 is just larger than the maintaining current of a dimmer in the LED driver, wherein the increasing amplitude of the reference voltage Vref1 is smaller each time, so that the leakage current is better matched with the maintaining current of the dimmer in the LED driver;

and a constant current step of adjusting the magnitude of the bleed current according to the change of the reference voltage Vref1.

11. The control method according to claim 10, characterized in that: the identifying whether the working state of the dimmer is normal or not according to the differential voltage V1 or the integral voltage V2 or the zero-crossing signal Vz or according to the timing signal Vm and the bus voltage division is specifically as follows:

the differential voltage V1 is compared with a first set threshold value in the abnormal state detection module, a first counting signal is output when the differential voltage V1 is higher than the first set threshold value, and the working state of the dimmer is judged to be abnormal when the first counting signal exceeds 1 time;

the differential voltage V1 is also compared with a second set threshold value in the abnormal state detection module, and the working state of the dimmer is judged to be abnormal when the differential voltage V1 is lower than the second set threshold value;

the integral voltage V2 is compared with a third threshold value inside the abnormal state detection module at the moment when the first counting signal is generated for the first time, and if the integral voltage V2 is higher than the third threshold value, the working state of the dimmer is judged to be abnormal;

when the abnormal state detection module receives the timing signal Vm, the bus voltage division voltage VB is compared with a fourth threshold value inside the abnormal state detection module, and if the bus voltage division voltage VB is lower than the fourth threshold value, the working state of the dimmer is judged to be abnormal.

Images