CN115473426A - Circuit for preventing output crosstalk for rectifier bridge multiplexing - Google Patents

Abstract

The invention discloses a rectifier bridge multiplexing output crosstalk prevention circuit.A crosstalk prevention circuit is arranged on the basis of a rectifier bridge multiplexing circuit, and the conduction of a body diode of a first PMOS (P-channel metal oxide semiconductor) tube is inhibited when the body diode of a transistor of a second output branch is conducted through a self-adaptive body biasing module, so that the output crosstalk problem caused by the conduction and leakage of the body diode of the first PMOS tube when the body diode of the transistor of the second output branch is conducted is solved, and the output voltage is stabilized; the voltage is stored when the second end of the alternating current source outputs low level through the charging and discharging module, when the second end of the alternating current source outputs high level, the first driving input voltage is higher than the voltage output by the second end of the alternating current source through discharging, the phenomenon of mistaken opening of the first PMOS tube does not occur when the body diode of the transistor of the second output branch circuit is conducted, output crosstalk caused by the problem of electric leakage of mistaken opening of the first PMOS tube is solved, and output voltage is further stabilized.

Description

A rectifier bridge multiplex output crosstalk prevention circuit

technical field

The invention relates to the field of integrated circuits, in particular to a rectifier bridge multiplexing output crosstalk prevention circuit.

Background technique

Compared with wired energy transmission, wireless energy transmission system has the characteristics of usage boundaries and one-to-many power supply, and is more and more frequently used in biomedical and other fields. In recent years, the resonant wireless energy transfer system has higher flexibility and practicability than the traditional inductive wireless energy transfer system. The working principle of the resonant wireless energy transfer system is as follows: first step, the wireless energy transmitting circuit drives the transmitting resonant circuit through a power amplifier to generate an AC resonant voltage; second step, the AC voltage on the transmitting resonant circuit is coupled to the receiving resonant circuit; third In the first step, the energy receiving circuit (receiving end circuit) converts the AC voltage on the receiving resonant circuit into a DC output voltage to provide stable energy supply for subsequent circuit modules.

Due to the rapid development of electronic products, the types and quantities of power sources required by electronic products are increasing. In the receiving end circuit of the series-series resonant wireless energy transfer system, by using a rectifier bridge multiplexing circuit, a single rectifier bridge is used to realize the conversion from a single AC input to multiple DC outputs to meet the needs of current electronic products, and The complexity, power consumption and area of the circuit are greatly reduced. However, the multiplexing of rectifier bridges leads to output crosstalk between output voltages, and in extreme cases, even lower output voltages cannot be stabilized, resulting in the failure of the entire system to work properly.

Contents of the invention

In order to solve the above technical problem, an embodiment of the present invention provides a rectifier bridge multiplexing output crosstalk prevention circuit.

The technical scheme that the embodiment of the present invention takes is:

A rectifier bridge multiplexing anti-output crosstalk circuit, which is applied to a receiving end circuit of a series-series resonant wireless energy transmission system, including:

The rectifier bridge multiplexing circuit includes an AC current source, a first output branch and a second output branch, the input ends of the first output branch and the second output branch are connected to the second of the AC current source terminal connection, the output terminal of the first output branch is used to output the first power supply, the output terminal of the second output branch is used to output the second power supply, and the first power supply is smaller than the second A power supply, the first output branch includes a first PMOS transistor and a first driver, the output end of the first driver is connected to the gate of the first PMOS transistor, and the drain of the first PMOS transistor is connected to the gate of the first PMOS transistor. The second end of the AC current source is connected, the source of the first PMOS transistor is the output end of the first output branch, and the AC current source is the receiving end circuit of the series-series resonant wireless energy transmission system Input the equivalent input source of the multiplexing circuit of the rectifier bridge;

The anti-output crosstalk circuit includes an adaptive body bias module and a charging and discharging module, the adaptive body bias module is used to suppress the first PMOS transistor when the body diode of the transistor of the second output branch is turned on The body diode of the AC current source is turned on, the charging and discharging module is used to store voltage when the second terminal of the AC current source outputs a low level, and the charging and discharging module is used to output a high voltage at the second terminal of the AC current source The input voltage of the first driver is usually higher than the output voltage of the second terminal of the AC current source by discharging.

As an optional implementation manner, the first output branch further includes a first comparator, a first selector, a first capacitor, and a first resistor;

The drain of the first PMOS transistor is connected to the inverting input terminal of the first comparator, the output terminal of the first comparator is connected to the input terminal of the first selector, and the first selector The output end of the first drive is connected to the first input end of the first driver, the source of the first PMOS transistor is connected to the non-inverting input end of the first comparator, and the non-inverting input end of the first comparator connected to the first end of the first capacitor, the first end of the first capacitor is connected to the first end of the first resistor, the second end of the first capacitor and the first end of the first resistor The two ends are grounded respectively.

As an optional implementation manner, the second output branch includes a second PMOS transistor, a second driver, a second selector, a second comparator, a second capacitor, and a second resistor;

The second end of the AC current source is connected to the drain of the second PMOS transistor, the drain of the second PMOS transistor is connected to the inverting input end of the second comparator, and the second comparator The output terminal of the second selector is connected to the input terminal of the second selector, the output terminal of the second selector is connected to the input terminal of the second driver, and the output terminal of the second driver is connected to the second PMOS transistor The gate of the second PMOS transistor is connected to the non-inverting input terminal of the second comparator, and the non-inverting input terminal of the second comparator is connected to the first terminal of the second capacitor , the first end of the second capacitor is connected to the first end of the second resistor, the second end of the second capacitor and the second end of the second resistor are respectively grounded, and the second PMOS transistor source of the output of the second output branch.

As an optional implementation manner, the rectifier bridge multiplexing circuit further includes a third PMOS transistor, a third driver, a third selector, a third comparator, a first NMOS transistor, a fourth driver, and a fourth selector , the fourth comparator, the second NMOS transistor, the fifth driver, the fifth selector, the fifth comparator, the sixth comparator and the seventh comparator;

The first end of the AC current source is connected to the drain of the third PMOS transistor, the drain of the third PMOS transistor is connected to the inverting input end of the third comparator, and the third comparator The output terminal of the third selector is connected to the input terminal of the third selector, the output terminal of the third selector is connected to the input terminal of the third driver, and the output terminal of the third driver is connected to the third PMOS transistor The gate of the third PMOS transistor is connected, the source of the third PMOS transistor is connected to the non-inverting input of the third comparator, and the non-inverting input of the third comparator is connected to the source of the second PMOS transistor ;

The first terminal of the AC current source is connected to the drain of the first NMOS transistor, the drain of the first NMOS transistor is connected to the inverting input terminal of the fourth comparator, and the fourth comparator The output terminal of the fourth selector is connected to the input terminal of the fourth selector, the output terminal of the fourth selector is connected to the input terminal of the fourth driver, and the output terminal of the fourth driver is connected to the first NMOS transistor The gate of the first NMOS transistor is connected, the source of the first NMOS transistor is connected to the non-inverting input of the fourth comparator, and the non-inverting input of the fourth comparator is connected to the source of the second NMOS transistor , the source of the second NMOS transistor is connected to the non-inverting input terminal of the fifth comparator, the non-inverting input terminal of the fifth comparator is grounded, and the output terminal of the fifth comparator is connected to the non-inverting input terminal of the fifth comparator. The input terminal of the fifth selector is connected, the output terminal of the fifth selector is connected to the input terminal of the fifth driver, the output terminal of the fifth driver is connected to the gate of the second NMOS transistor, and the The drain of the second NMOS transistor is connected to the inverting input terminal of the fifth comparator, and the inverting input terminal of the fifth comparator is connected to the drain of the first PMOS transistor;

The non-inverting input terminal of the sixth comparator inputs the first reference voltage, the inverting input terminal of the sixth comparator is connected to the source of the first PMOS transistor, and the output terminal of the sixth comparator is connected to the source of the first PMOS transistor. The input terminal of the first selector is connected, and the output terminal of the sixth comparator is connected with the input terminal of the fifth selector;

The non-inverting input terminal of the seventh comparator inputs the second reference voltage, the inverting input terminal of the seventh comparator is connected to the source of the second PMOS transistor, and the output terminal of the seventh comparator is connected to the source of the second PMOS transistor. The input terminal of the second selector is connected, the output terminal of the sixth comparator is connected with the input terminal of the third selector, the output terminal of the sixth comparator is connected with the input terminal of the fourth selector end connection.

As an optional implementation manner, the adaptive body bias module includes a fourth PMOS transistor and a fifth PMOS transistor;

The source of the fourth PMOS transistor is connected to the source of the first PMOS transistor, the source of the first PMOS transistor is connected to the gate of the fifth PMOS transistor, and the source of the fifth PMOS transistor The pole is connected to the gate of the fourth PMOS transistor, the gate of the fourth PMOS transistor is connected to the drain of the first PMOS transistor, and the substrate of the first PMOS transistor is connected to the fourth PMOS transistor. The drain of the fourth PMOS transistor is connected to the drain of the fifth PMOS transistor.

As an optional implementation manner, the charging and discharging module includes a third capacitor;

The first end of the third capacitor is connected to the second input end of the first driver, and the second end of the third capacitor is connected to the drain of the first PMOS transistor;

The third capacitor stores a voltage when the second terminal of the AC current source outputs a low level, and discharges to make the input voltage of the first driver higher than the specified voltage when the second terminal of the AC current source outputs a high level. The voltage output by the second terminal of the AC current source.

As an optional implementation manner, the charging and discharging module further includes a unidirectional conduction component;

The source of the second PMOS transistor is connected to the first end of the third capacitor through the unidirectional conduction component.

As an optional implementation manner, the unidirectional conduction component includes a diode;

The anode of the diode is connected to the source of the second PMOS transistor, and the cathode of the diode is connected to the first terminal of the third capacitor.

In the rectifier bridge multiplexing anti-output crosstalk circuit of the embodiment of the present invention, the output crosstalk prevention circuit is set on the basis of the rectifier bridge multiplexing circuit, and the transistor of the second output branch is connected by the adaptive body bias module of the output crosstalk prevention circuit. When the body diode is turned on, the body diode of the first PMOS transistor is suppressed from being turned on, thereby solving the problem of output crosstalk caused by the body diode conduction leakage of the first PMOS transistor when the body diode of the transistor of the second output branch is turned on, so that the output Voltage stabilization; through the charge and discharge module of the anti-output crosstalk circuit, the voltage is stored when the second terminal of the AC current source outputs a low level, and the input voltage of the first driver is made high by discharging when the second terminal of the AC current source outputs a high level Based on the voltage output by the second terminal of the AC current source, the first PMOS transistor does not appear to be falsely turned on when the body diode of the transistor of the second output branch is turned on, thereby solving the leakage problem caused by the false turn-on of the first PMOS transistor The output crosstalk further stabilizes the output voltage.

Description of drawings

Fig. 1 is the circuit connection schematic diagram of the rectifier bridge multiplexing anti-output crosstalk circuit of the embodiment of the present invention;

2 is a schematic diagram of the output crosstalk principle of the rectifier bridge multiplexing circuit according to an embodiment of the present invention;

FIG. 3 is a functional simulation waveform diagram of the rectifier bridge multiplexing output crosstalk prevention circuit according to the embodiment of the present invention.

Reference signs: I _AC , alternating current source; CMP ₁ , first comparator; CMP ₂ , second comparator; CMP ₃ , third comparator; CMP ₄ , fourth comparator; CMP ₅ , fifth comparator ; CMP ₆ , the sixth comparator; CMP ₇ , the seventh comparator; B ₁ , the first drive; B ₂ , the second drive; B ₃ , the third drive; B ₄ , the fourth drive; B ₅ , the fifth Drive; Mux ₁ , the first selector; Mux ₂ , the second selector; Mux ₃ , the third selector; Mux ₄ , the fourth selector; Mux ₅ , the fifth selector; M _P1 , the first PMOS tube; M _P2 , the second PMOS transistor; M _P3 , the third PMOS transistor; M _PA , the fourth PMOS transistor; M _PB , the fifth PMOS transistor; M _N1 , the first NMOS transistor; M _N2 , the second NMOS transistor; C ₁ , the first capacitor; C ₂ , the second capacitor; C ₃ , the third capacitor; R ₁ , the first resistor; R ₂ , the second resistor; D ₁ , the diode; V _REFL , the first reference voltage; V _REFH , the first 2. Reference voltage; 101. Adaptive body bias module; 102. Charging and discharging module.

detailed description

In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiment of the application will be clearly and completely described below in conjunction with the accompanying drawings in the embodiment of the application. Obviously, the described embodiment is only It is an embodiment of a part of the application, but not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without creative efforts shall fall within the scope of protection of this application.

The terms "first", "second", "third" and "fourth" in the specification and claims of the present application and the drawings are used to distinguish different objects, rather than to describe a specific order . Furthermore, the terms "include" and "have", as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units is not limited to the listed steps or units, but optionally also includes unlisted steps or units, or optionally further includes For other steps or units inherent in these processes, methods, products or apparatuses.

Reference herein to an "embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the present application. The occurrences of this phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is understood explicitly and implicitly by those skilled in the art that the embodiments described herein can be combined with other embodiments.

In the receiving end circuit of the series-series resonant wireless energy transfer system, by using a rectifier bridge multiplexing circuit, a single rectifier bridge is used to realize the conversion from a single AC input to multiple DC outputs to meet the needs of current electronic products, and The complexity, power consumption and area of the circuit are greatly reduced. However, the multiplexing of rectifier bridges leads to output crosstalk between output voltages, and in extreme cases, even lower output voltages cannot be stabilized, resulting in the failure of the entire system to work properly. For this reason, the embodiment of the present invention proposes a rectifier bridge multiplexing anti-output crosstalk circuit, an output crosstalk prevention circuit is set on the basis of the rectifier bridge multiplexing circuit, and the adaptive body bias module of the output crosstalk prevention circuit is used in the second When the body diode of the transistor of the output branch is turned on, the body diode of the first PMOS transistor is suppressed, thereby solving the problem caused by the body diode conduction leakage of the first PMOS transistor when the body diode of the transistor of the second output branch is turned on The problem of output crosstalk makes the output voltage stable; the charge and discharge module of the anti-output crosstalk circuit stores the voltage when the second end of the AC current source outputs a low level, and discharges the second end of the AC current source when the second end outputs a high level. The input voltage of a drive is higher than the voltage output by the second terminal of the AC current source, so that when the body diode of the transistor in the second output branch is turned on, the first PMOS transistor does not turn on by mistake, thereby solving the problem of the first PMOS transistor being turned on by mistake. The output crosstalk caused by the open leakage problem further makes the output voltage regulation.

As shown in Figure 1, the embodiment of the present invention proposes a rectifier bridge multiplexing output crosstalk prevention circuit, which is applied to the receiving end circuit of the series-series resonant wireless energy transmission system, including:

Rectifier bridge multiplexing circuit, including alternating current source I _AC , a first output branch and a second output branch, the input terminals of the first output branch and the second output branch are connected to the alternating current source I The second end of the _AC is connected, the output end of the first output branch is used to output the first power supply, the output end of the second output branch is used to output the second power supply, and the first power supply is less than The second power supply, the first output branch includes a first PMOS transistor M _P1 and a first driver B ₁ , the output terminal of the first driver B ₁ is connected to the gate of the first PMOS transistor M _P1 connected, the drain of the first _PMOS transistor MP1 is connected to the second end of the alternating current source I _AC , and the source of the first _PMOS transistor MP1 is the output end of the first output branch, so The AC current source I _AC is an equivalent input source for the receiving end circuit of the series-series resonant wireless energy transfer system to input the rectifier bridge multiplexing circuit;

The anti-output crosstalk circuit includes an adaptive body bias module 101 and a charging and discharging module 102, and the adaptive body bias module 101 is used to suppress the first The body diode of a PMOS transistor M _P1 is turned on, and the charging and discharging module 102 is used for storing voltage when the second end of the alternating current source I _AC outputs a low level, and the charging and discharging module 102 is used for When the second terminal of the current source I _AC outputs a high level, the input voltage V _BOOST of the first driver B ₁ is higher than the voltage V _IN2 output by the second terminal of the AC current source I _AC by discharging.

Wherein, the first power source represents the output voltage V _OL of the first output branch, and the second power source represents the output voltage V _OH of the second output branch.

Referring to Figure 2, it can be seen that the reasons for the output crosstalk of the rectifier bridge multiplexing circuit include:

1) Due to the existence of the body diode _DP1 of the first PMOS transistor MP1 and the body diode _DP2 of the second _PMOS transistor _MP2 , and the delay of the gate control signal of the second _PMOS transistor MP2, when the second PMOS transistor M When the body diode D _P2 of _P2 is turned on, the forward voltage across the body diode D _P1 of the first PMOS transistor _MP1 is V _OH +0.7-V _OL , so the body diode D _P1 of the first PMOS transistor _MP1 is also turned on . Since the voltage difference across the body diode D _P1 of the first PMOS transistor _{MP1 is greater than the voltage difference across the body diode D P2 of} the second PMOS transistor _MP2 , the current output by the alternating current source I _AC flows to the output of the first output branch terminal, so that the voltage V _OL output by the output terminal of the first output branch fails to be stabilized;

2) When the body diode D _P2 of the second PMOS transistor _MP2 is turned on, the source-drain exchange of the first PMOS transistor _MP1 will occur, and at this time the source-gate voltage of the first _PMOS transistor MP1 is V _OH +0.7-V _OH , the first PMOS transistor M _P1 is on the edge of conduction. At this time, the source-drain voltage of the first _PMOS transistor MP1 is V _OH -V _OL , which is much higher than the source-drain voltage of the second _PMOS transistor MP2, so the current output by the alternating current source I _AC flows to the output of the first output branch. terminal, so that the voltage V _OL output from the output terminal of the first output branch fails to be regulated.

Based on the above reasons for the output crosstalk of the rectifier bridge multiplexing circuit, the embodiment of the present invention sets an anti-output crosstalk circuit on the basis of the rectifier bridge multiplexing circuit, and the adaptive body bias module 101 of the anti-output crosstalk circuit is used in the second output branch When the body diode of the transistor is turned on, the body diode of the first PMOS transistor M _P1 is suppressed from being turned on, thereby solving the problem of leakage caused by the body diode of the first PMOS transistor _MP1 when the body diode of the transistor of the second output branch is turned on output crosstalk problem, so that the output voltage is stabilized; the charge and discharge module 102 of the anti-output crosstalk circuit stores the voltage when the second end of the alternating current source I _AC outputs a low level, and outputs a high level at the second end of the alternating current source I _AC level, the input voltage V _BOOST of the first driver B ₁ is higher than the voltage V _IN2 output by the second terminal of the AC current source I _AC by discharging, so that the body diode of the transistor of the second output branch is turned on when the first PMOS transistor M _P1 does not appear to be turned on by mistake, thereby solving the output crosstalk caused by the leakage problem of the first PMOS transistor M _P1 being turned on by mistake, and further stabilizing the output voltage.

Referring to FIG. 1(a), in one embodiment of the present invention, the first output branch further includes a first comparator CMP ₁ , a first selector Mux ₁ , a first capacitor C ₁ and a first resistor R ₁ ;

The drain of the first PMOS transistor MP ₁ is connected to the inverting input terminal of the first comparator CMP ₁ , and the output terminal of the first comparator CMP ₁ is connected to the input terminal of the first selector Mux ₁ connected, the output terminal of the first selector Mux ₁ is connected to the first input terminal of the first driver B ₁ , the source of the first PMOS transistor MP ₁ is connected to the positive terminal of the first comparator CMP ₁ The phase input terminal is connected, the non-inverting input terminal of the first comparator CMP ₁ is connected to the first terminal of the first capacitor C ₁ , and the first terminal of the first capacitor C ₁ is connected to the first resistor R1 The first terminal of the first capacitor _C1 and the second terminal of the _first resistor R1 are respectively grounded.

Referring to FIG. 1(a), as an optional implementation, the second output branch includes a second _PMOS transistor MP2, a second driver B ₂ , a second selector Mux ₂ , and a second comparator CMP ₂ , the second capacitor C ₂ and the second resistor R ₂ ;

The second terminal of the alternating current source I _AC is connected to the drain of the second _PMOS transistor _MP2 , and the drain of the second PMOS transistor MP2 is connected to the inverting input terminal of the _second comparator CMP2 connected, the output of the second comparator CMP ₂ is connected to the input of the second selector Mux ₂ , and the output of the second selector Mux ₂ is connected to the input of the second driver B ₂ , the output terminal of the _second driver B2 is connected to the gate of the second _PMOS transistor _MP2 , and the source of the second PMOS transistor MP2 is connected to the non-inverting input terminal of the _second comparator CMP2 connected, the non-inverting input terminal of the second comparator CMP ₂ is connected to the first terminal of the second capacitor C ₂ , and the first terminal of the second capacitor C ₂ is connected to the first terminal of the second resistor R ₂ One end is connected, the second end of the second capacitor C2 and the _second end of the _second resistor R2 are respectively grounded, the source of the second _PMOS transistor MP2 is the output of the second output branch end.

Wherein, the _first resistor R1 and the _second resistor R2 are load resistors. When the _second resistor R2 is the heaviest load and the _first resistor R1 is the lightest load, the rectifier bridge multiplexing circuit is in the most extreme situation.

It can be understood that the function of the output crosstalk prevention circuit in this embodiment of the present invention is not limited by the load conditions of the _first resistor R1 and the load condition of the _second resistor R2.

Continuing to refer to FIG. 1(a), as an optional implementation, the rectifier bridge multiplexing circuit further includes a third PMOS transistor _MP3 , a third driver B ₃ , a third selector Mux ₃ , and a third comparator CMP ₃ , first NMOS transistor M _N1 , fourth driver B ₄ , fourth selector Mux ₄ , fourth comparator CMP ₄ , second NMOS transistor M _N2 , fifth driver B ₅ , fifth selector Mux ₅ , fifth comparator CMP ₅ , sixth comparator CMP ₆ and seventh comparator CMP ₇ ;

The first terminal of the alternating current source I _AC is connected to the drain of the third PMOS transistor _MP3 , and the drain of the third PMOS transistor MP3 is connected to the inverting input terminal of the _third comparator _CMP3 connected, the output of the third comparator CMP ₃ is connected to the input of the third selector Mux ₃ , and the output of the third selector Mux ₃ is connected to the input of the third driver B ₃ , the output terminal of the third driver _B3 is connected to the gate of the third PMOS transistor _MP3 , the source of the third PMOS transistor MP3 is connected to the non-inverting input terminal of the _third comparator _CMP3 connected, the non-inverting input terminal of the third comparator CMP ₃ is connected to the source of the second _PMOS transistor MP2;

The first terminal of the alternating current source I _AC is connected to the drain of the first NMOS transistor M _N1 , and the drain of the first NMOS transistor M _N1 is connected to the inverting input terminal of the fourth comparator CMP ₄ connected, the output of the fourth comparator CMP ₄ is connected to the input of the fourth selector Mux ₄ , and the output of the fourth selector Mux ₄ is connected to the input of the fourth driver B ₄ , the output terminal of the _fourth driver B4 is connected to the gate of the first NMOS transistor _MN1 , and the source of the first NMOS transistor MN1 is connected to the non-inverting input terminal of the _fourth comparator _CMP4 connected, the non-inverting input terminal of the fourth comparator CMP ₄ is connected to the source of the second NMOS transistor M _N2 , and the source of the second NMOS transistor M _N2 is connected to the source of the fifth comparator CMP ₅ The non-inverting input end of the fifth comparator CMP ₅ is connected to the ground, the output end of the fifth comparator CMP ₅ is connected to the input end of the fifth selector Mux ₅ , and the fifth comparator CMP 5 is connected to the input end of the fifth selector Mux 5. The output end of the selector Mux ₅ is connected to the input end of the _fifth driver B5, the output end of the _fifth driver B5 is connected to the gate of the second NMOS transistor _MN2 , and the second NMOS transistor The drain of M _N2 is connected to the inverting input terminal of the fifth comparator CMP ₅ , and the inverting input terminal of the fifth comparator CMP ₅ is connected to the drain of the first _PMOS transistor MP1;

The non-inverting input terminal of the sixth comparator CMP ₆ inputs the first reference voltage V _REFL , the inverting input terminal of the sixth comparator CMP ₆ is connected to the source of the first _PMOS transistor MP1, and the The output end of the sixth comparator CMP ₆ is connected to the input end of the first selector Mux ₁ , and the output end of the sixth comparator CMP ₆ is connected to the input end of the fifth selector Mux ₅ ;

The non-inverting input terminal of the seventh comparator CMP ₇ inputs the second reference voltage V _REFH , the inverting input terminal of the seventh comparator CMP ₇ is connected to the source of the second _PMOS transistor MP2, and the The output end of the seventh comparator CMP ₇ is connected to the input end of the second selector Mux ₂ , the output end of the sixth comparator CMP ₆ is connected to the input end of the third selector Mux ₃ , and the The output terminal of the sixth comparator CMP ₆ is connected with the input terminal of the fourth selector Mux ₄ .

Referring to FIG. 1(b), as an optional implementation manner, the adaptive body bias module 101 includes a fourth PMOS transistor _MPA and a fifth PMOS transistor _MPB ;

The source of the fourth PMOS transistor _MPA is connected to the source of the first _PMOS transistor MP1, the source of the first _PMOS transistor MP1 is connected to the gate of the fifth PMOS transistor _MPB , The source of the fifth PMOS transistor _MPB is connected to the gate of the fourth PMOS transistor _MPA , and the gate of the fourth PMOS transistor _MPA is connected to the drain of the first _PMOS transistor MP1, The substrate of the first PMOS transistor MP1 is connected to the drain of the fourth _PMOS transistor M _PA , and the drain of the fourth PMOS transistor M _PA is connected to the drain of the fifth PMOS transistor _MPB .

Continuing to refer to FIG. 1(b), as an optional implementation manner, the charging and discharging module 102 includes a third capacitor C ₃ ;

The first end of the _third capacitor C3 is connected to the second input end of the _first driver B1, and the second end of the _third capacitor C3 is connected to the drain of the first _PMOS transistor MP1 ;

The _third capacitor C3 stores a voltage when the second end of the alternating current source I _AC outputs a low level, and discharges the first drive when the second end of the alternating current source I _AC outputs a high level. The input voltage V _BOOST of B ₁ is higher than the voltage V _IN2 output by the second terminal of the AC current source I _AC .

Specifically, when the second terminal of the AC current source I _AC outputs a high level, the _third capacitor C3 raises the input voltage V _BOOST of the _first driver B1 to be higher than the voltage output by the second terminal of the AC current source I _AC V _IN2 , so that the source-gate voltage of the first _PMOS transistor MP1 is less than zero, so that the first _PMOS transistor MP1 will not be turned on by mistake, thereby solving the problem of output crosstalk caused by the wrong turn-on of the first _PMOS transistor MP1.

It can be understood that, in the embodiment of the present invention, when the first _PMOS transistor MP1 works normally, the gate voltage is zero, so the boost of the input voltage V _BOOST of the _first driver B1 will not cause the first PMOS transistor The on-resistance of M _P1 is increased to maintain a small on-voltage drop of the first PMOS transistor M _P1 without affecting the conversion efficiency of the series-series resonant wireless energy transmission system.

As an optional implementation manner, the charging and discharging module 102 also includes a unidirectional conduction component;

The source of the second _PMOS transistor MP2 is connected to the first end of the _third capacitor C3 through the unidirectional conduction component.

Wherein, in the embodiment of the present invention, the unidirectional conduction component includes a diode D ₁ ;

_The anode of the diode D1 is connected to the source of the second _PMOS transistor MP2, and the cathode of the diode D1 is connected to the _first end of the _third capacitor C3.

Fig. 3 shows the functional simulation waveform diagram of the rectifier bridge multiplexing anti-output crosstalk circuit of the embodiment of the present invention, the simulation condition is that the _first resistor R1 is the lightest load, and the _second resistor R2 is the heaviest load, i.e. series- The receiver circuit of the series resonant wireless energy transfer system is the most extreme case. It can be seen from FIG. 3 that the rectifier bridge multiplexing anti-output crosstalk circuit of the embodiment of the present invention not only solves the output crosstalk caused by the conduction leakage of the body diode of the first PMOS transistor M _P1 through the adaptive body bias module 101, but also solves the output crosstalk caused by the first _The input voltage V _BOOST for driving B1 solves the output crosstalk caused by the wrong turn-on of the first PMOS transistor M _P1 . As shown in Figure 3, the simulation results show that the source-leakage current of the first PMOS transistor M _P1 is significantly reduced to a level that does not affect the output voltage regulation. After one charging cycle of the _third capacitor C3, the output voltage V of the first output branch _OL showed a downward trend and successfully achieved a regulated output.

The above is a specific description of the preferred implementation of the present invention, but the present invention is not limited to the described embodiments, and those skilled in the art can also make various equivalent deformations or replacements without violating the spirit of the present invention. These equivalent modifications or replacements are all within the scope defined by the claims of the present application.

Claims (8)

1. A kind of bridge rectifier multiplexes and defends the circuit of the output crosstalk, characterized by, apply to the receiving end circuit of the wireless energy transmission system of series-series resonance type, including:

the rectifier bridge multiplexing circuit comprises an alternating current source, a first output branch and a second output branch, wherein the input ends of the first output branch and the second output branch are connected with the second end of the alternating current source, the output end of the first output branch is used for outputting a first power supply, the output end of the second output branch is used for outputting a second power supply, the first power supply is smaller than the second power supply, the first output branch comprises a first PMOS (P-channel metal oxide semiconductor) tube and a first driver, the output end of the first driver is connected with the grid electrode of the first PMOS tube, the drain electrode of the first PMOS tube is connected with the second end of the alternating current source, the source electrode of the first PMOS tube is the output end of the first output branch, and the alternating current source is an equivalent input source of a receiving end circuit of a series-series resonant wireless energy transmission system which inputs the rectifier bridge multiplexing circuit;

the output crosstalk prevention circuit comprises an adaptive body biasing module and a charge and discharge module, wherein the adaptive body biasing module is used for inhibiting the conduction of a body diode of a first PMOS (P-channel metal oxide semiconductor) tube when the body diode of a transistor of the second output branch is conducted, the charge and discharge module is used for storing voltage when a second end of the alternating current source outputs low level, and the charge and discharge module is used for enabling the input voltage of the first driver to be higher than the voltage output by the second end of the alternating current source through discharging when the second end of the alternating current source outputs high level.

2. The circuit of claim 1, wherein the first output branch further comprises a first comparator, a first selector, a first capacitor, and a first resistor;

the drain electrode of the first PMOS tube is connected with the inverting input end of the first comparator, the output end of the first comparator is connected with the input end of the first selector, the output end of the first selector is connected with the first input end of the first drive, the source electrode of the first PMOS tube is connected with the positive input end of the first comparator, the positive input end of the first comparator is connected with the first end of the first capacitor, the first end of the first capacitor is connected with the first end of the first resistor, and the second end of the first capacitor and the second end of the first resistor are respectively grounded.

3. The circuit of claim 2, wherein the second output branch comprises a second PMOS transistor, a second driver, a second selector, a second comparator, a second capacitor, and a second resistor;

the second end of the alternating current source is connected with the drain electrode of the second PMOS tube, the drain electrode of the second PMOS tube is connected with the inverting input end of the second comparator, the output end of the second comparator is connected with the input end of the second selector, the output end of the second selector is connected with the second driving input end, the second driving output end is connected with the grid electrode of the second PMOS tube, the source electrode of the second PMOS tube is connected with the positive phase input end of the second comparator, the positive phase input end of the second comparator is connected with the first end of the second capacitor, the first end of the second capacitor is connected with the first end of the second resistor, the second end of the second capacitor and the second end of the second resistor are respectively grounded, and the source electrode of the second PMOS tube is connected with the output end of the second output branch circuit.

4. The circuit of claim 3, wherein the circuit further comprises a third PMOS transistor, a third driver, a third selector, a third comparator, a first NMOS transistor, a fourth driver, a fourth selector, a fourth comparator, a second NMOS transistor, a fifth driver, a fifth selector, a fifth comparator, a sixth comparator, and a seventh comparator;

a first end of the alternating current source is connected with a drain electrode of the third PMOS transistor, a drain electrode of the third PMOS transistor is connected with an inverting input end of the third comparator, an output end of the third comparator is connected with an input end of the third selector, an output end of the third selector is connected with an input end of the third driver, an output end of the third driver is connected with a gate electrode of the third PMOS transistor, a source electrode of the third PMOS transistor is connected with a positive-phase input end of the third comparator, and a positive-phase input end of the third comparator is connected with a source electrode of the second PMOS transistor;

a first end of the alternating current source is connected with a drain electrode of the first NMOS transistor, a drain electrode of the first NMOS transistor is connected with an inverting input terminal of the fourth comparator, an output terminal of the fourth comparator is connected with an input terminal of the fourth selector, an output terminal of the fourth selector is connected with an input terminal of the fourth driver, an output terminal of the fourth driver is connected with a gate electrode of the first NMOS transistor, a source electrode of the first NMOS transistor is connected with a positive-phase input terminal of the fourth comparator, a positive-phase input terminal of the fourth comparator is connected with a source electrode of the second NMOS transistor, a source electrode of the second NMOS transistor is connected with a positive-phase input terminal of the fifth comparator, a positive-phase input terminal of the fifth comparator is grounded, an output terminal of the fifth comparator is connected with an input terminal of the fifth selector, an output terminal of the fifth selector is connected with an input terminal of the fifth driver, an output terminal of the fifth driver is connected with a gate electrode of the second NMOS transistor, a drain electrode of the second NMOS transistor is connected with an inverting input terminal of the fifth comparator, and an inverting input terminal of the fifth comparator is connected with a drain electrode of the PMOS transistor;

a positive phase input end of the sixth comparator inputs a first reference voltage, an inverted phase input end of the sixth comparator is connected with a source electrode of the first PMOS tube, an output end of the sixth comparator is connected with an input end of the first selector, and an output end of the sixth comparator is connected with an input end of the fifth selector;

a second reference voltage is input to a positive phase input end of the seventh comparator, an inverted input end of the seventh comparator is connected to a source electrode of the second PMOS transistor, an output end of the seventh comparator is connected to an input end of the second selector, an output end of the sixth comparator is connected to an input end of the third selector, and an output end of the sixth comparator is connected to an input end of the fourth selector.

5. The circuit of claim 4, wherein the adaptive body bias module comprises a fourth PMOS transistor and a fifth PMOS transistor;

the source electrode of the fourth PMOS tube is connected with the source electrode of the first PMOS tube, the source electrode of the first PMOS tube is connected with the grid electrode of the fifth PMOS tube, the source electrode of the fifth PMOS tube is connected with the grid electrode of the fourth PMOS tube, the grid electrode of the fourth PMOS tube is connected with the drain electrode of the first PMOS tube, the substrate of the first PMOS tube is connected with the drain electrode of the fourth PMOS tube, and the drain electrode of the fourth PMOS tube is connected with the drain electrode of the fifth PMOS tube.

6. The circuit of claim 5, wherein the charge/discharge module comprises a third capacitor;

the first end of the third capacitor is connected with the second input end of the first driver, and the second end of the third capacitor is connected with the drain electrode of the first PMOS tube;

the third capacitor stores voltage when the second end of the alternating current source outputs low level, and enables the input voltage of the first driver to be higher than the voltage output by the second end of the alternating current source through discharging when the second end of the alternating current source outputs high level.

7. The circuit of claim 6, wherein the charge-discharge module further comprises a unidirectional conducting element;

and the source electrode of the second PMOS tube is connected with the first end of the third capacitor through the one-way conduction assembly.

8. The circuit of claim 7, wherein the unidirectional conducting component comprises a diode;

the anode of the diode is connected with the source electrode of the second PMOS tube, and the cathode of the diode is connected with the first end of the third capacitor.

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