CN115473426A - Circuit for preventing output crosstalk for rectifier bridge multiplexing - Google Patents

Circuit for preventing output crosstalk for rectifier bridge multiplexing Download PDF

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CN115473426A
CN115473426A CN202210997839.1A CN202210997839A CN115473426A CN 115473426 A CN115473426 A CN 115473426A CN 202210997839 A CN202210997839 A CN 202210997839A CN 115473426 A CN115473426 A CN 115473426A
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output
comparator
selector
pmos tube
circuit
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CN115473426B (en
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郭建平
陈宇棠
罗宇萱
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Sun Yat Sen University
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Sun Yat Sen University
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    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00Details of apparatus for conversion
    • H02M1/44Circuits or arrangements for compensating for electromagnetic interference in converters or inverters
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02JCIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J50/00Circuit arrangements or systems for wireless supply or distribution of electric power
    • H02J50/10Circuit arrangements or systems for wireless supply or distribution of electric power using inductive coupling
    • H02J50/12Circuit arrangements or systems for wireless supply or distribution of electric power using inductive coupling of the resonant type
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00Details of apparatus for conversion
    • H02M1/0083Converters characterised by their input or output configuration
    • H02M1/009Converters characterised by their input or output configuration having two or more independently controlled outputs
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00Conversion of AC power input into DC power output; Conversion of DC power input into AC power output
    • H02M7/02Conversion of AC power input into DC power output without possibility of reversal
    • H02M7/04Conversion of AC power input into DC power output without possibility of reversal by static converters
    • H02M7/12Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/21Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/217Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M7/219Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only in a bridge configuration

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Rectifiers (AREA)

Abstract

The invention discloses a rectifier bridge multiplexing output crosstalk prevention circuit.A crosstalk prevention circuit is arranged on the basis of a rectifier bridge multiplexing circuit, and the conduction of a body diode of a first PMOS (P-channel metal oxide semiconductor) tube is inhibited when the body diode of a transistor of a second output branch is conducted through a self-adaptive body biasing module, so that the output crosstalk problem caused by the conduction and leakage of the body diode of the first PMOS tube when the body diode of the transistor of the second output branch is conducted is solved, and the output voltage is stabilized; the voltage is stored when the second end of the alternating current source outputs low level through the charging and discharging module, when the second end of the alternating current source outputs high level, the first driving input voltage is higher than the voltage output by the second end of the alternating current source through discharging, the phenomenon of mistaken opening of the first PMOS tube does not occur when the body diode of the transistor of the second output branch circuit is conducted, output crosstalk caused by the problem of electric leakage of mistaken opening of the first PMOS tube is solved, and output voltage is further stabilized.

Description

一种整流桥复用防输出串扰电路A rectifier bridge multiplex output crosstalk prevention circuit

技术领域technical field

本发明涉及集成电路领域,尤其是一种整流桥复用防输出串扰电路。The invention relates to the field of integrated circuits, in particular to a rectifier bridge multiplexing output crosstalk prevention circuit.

背景技术Background technique

相较于有线能量传输,无线能量传输系统具有使用边界、一对多供电等特点,越来越频繁地用于生物医疗等领域中。近年来,谐振式无线传能系统相较于传统的电感式无线传能系统,具有更高的灵活度和实用性。谐振式无线传能系统的工作原理为:第一步,无线能量发射电路通过功率放大器驱动发射谐振电路产生交流谐振电压;第二步,发射谐振电路上交流电压耦合到接收谐振电路上;第三步,能量接收电路(接收端电路)将接收谐振电路上的交流电压转化为直流输出电压,为后续的电路模块提供稳定供能。Compared with wired energy transmission, wireless energy transmission system has the characteristics of usage boundaries and one-to-many power supply, and is more and more frequently used in biomedical and other fields. In recent years, the resonant wireless energy transfer system has higher flexibility and practicability than the traditional inductive wireless energy transfer system. The working principle of the resonant wireless energy transfer system is as follows: first step, the wireless energy transmitting circuit drives the transmitting resonant circuit through a power amplifier to generate an AC resonant voltage; second step, the AC voltage on the transmitting resonant circuit is coupled to the receiving resonant circuit; third In the first step, the energy receiving circuit (receiving end circuit) converts the AC voltage on the receiving resonant circuit into a DC output voltage to provide stable energy supply for subsequent circuit modules.

由于电子产品的快速发展,电子产品所需的电源种类与数目越来越多。在串联-串联谐振式无线能量传输系统的接收端电路中,通过采用整流桥复用电路,利用单个整流桥来实现单个交流输入到多个直流输出的转换,以满足当前电子产品的需求,并大大降低了电路的复杂度、功耗与面积。然而,整流桥的复用使得输出电压之间存在输出串扰问题,在极端情况下甚至导致较低的输出电压无法稳压,从而导致整个系统无法正常工作。Due to the rapid development of electronic products, the types and quantities of power sources required by electronic products are increasing. In the receiving end circuit of the series-series resonant wireless energy transfer system, by using a rectifier bridge multiplexing circuit, a single rectifier bridge is used to realize the conversion from a single AC input to multiple DC outputs to meet the needs of current electronic products, and The complexity, power consumption and area of the circuit are greatly reduced. However, the multiplexing of rectifier bridges leads to output crosstalk between output voltages, and in extreme cases, even lower output voltages cannot be stabilized, resulting in the failure of the entire system to work properly.

发明内容Contents of the invention

为解决上述技术问题,本发明实施例提供了一种整流桥复用防输出串扰电路。In order to solve the above technical problem, an embodiment of the present invention provides a rectifier bridge multiplexing output crosstalk prevention circuit.

本发明实施例所采取的技术方案是:The technical scheme that the embodiment of the present invention takes is:

一种整流桥复用防输出串扰电路,应用于串联-串联谐振式无线能量传输系统的接收端电路,包括:A rectifier bridge multiplexing anti-output crosstalk circuit, which is applied to a receiving end circuit of a series-series resonant wireless energy transmission system, including:

整流桥复用电路,包括交流电流源、第一输出支路和第二输出支路,所述第一输出支路和所述第二输出支路的输入端与所述交流电流源的第二端连接,所述第一输出支路的输出端用于输出第一功率电源,所述第二输出支路的输出端用于输出第二功率电源,所述第一功率电源小于所述第二功率电源,所述第一输出支路包括第一PMOS管和第一驱动,所述第一驱动的输出端与所述第一PMOS管的栅极连接,所述第一PMOS管的漏极与所述交流电流源的第二端连接,所述第一PMOS管的源极为所述第一输出支路的输出端,所述交流电流源为串联-串联谐振式无线能量传输系统的接收端电路输入所述整流桥复用电路的等效输入源;The rectifier bridge multiplexing circuit includes an AC current source, a first output branch and a second output branch, the input ends of the first output branch and the second output branch are connected to the second of the AC current source terminal connection, the output terminal of the first output branch is used to output the first power supply, the output terminal of the second output branch is used to output the second power supply, and the first power supply is smaller than the second A power supply, the first output branch includes a first PMOS transistor and a first driver, the output end of the first driver is connected to the gate of the first PMOS transistor, and the drain of the first PMOS transistor is connected to the gate of the first PMOS transistor. The second end of the AC current source is connected, the source of the first PMOS transistor is the output end of the first output branch, and the AC current source is the receiving end circuit of the series-series resonant wireless energy transmission system Input the equivalent input source of the multiplexing circuit of the rectifier bridge;

防输出串扰电路,包括自适应体偏置模块和充放电模块,所述自适应体偏置模块用于在所述第二输出支路的晶体管的体二极管导通时抑制所述第一PMOS管的体二极管导通,所述充放电模块用于在所述交流电流源的第二端输出低电平时存储电压,所述充放电模块用于在所述交流电流源的第二端输出高电平时通过放电使所述第一驱动的输入电压高于所述交流电流源的第二端输出的电压。The anti-output crosstalk circuit includes an adaptive body bias module and a charging and discharging module, the adaptive body bias module is used to suppress the first PMOS transistor when the body diode of the transistor of the second output branch is turned on The body diode of the AC current source is turned on, the charging and discharging module is used to store voltage when the second terminal of the AC current source outputs a low level, and the charging and discharging module is used to output a high voltage at the second terminal of the AC current source The input voltage of the first driver is usually higher than the output voltage of the second terminal of the AC current source by discharging.

作为一种可选的实施方式,所述第一输出支路还包括第一比较器、第一选择器、第一电容和第一电阻;As an optional implementation manner, the first output branch further includes a first comparator, a first selector, a first capacitor, and a first resistor;

所述第一PMOS管的漏极与所述第一比较器的反相输入端连接,所述第一比较器的输出端与所述第一选择器的输入端连接,所述第一选择器的输出端与所述第一驱动的第一输入端连接,所述第一PMOS管的源极与所述第一比较器的正相输入端连接,所述第一比较器的正相输入端与所述第一电容的第一端连接,所述第一电容的第一端与所述第一电阻的第一端连接,所述第一电容的第二端以及所述第一电阻的第二端分别接地。The drain of the first PMOS transistor is connected to the inverting input terminal of the first comparator, the output terminal of the first comparator is connected to the input terminal of the first selector, and the first selector The output end of the first drive is connected to the first input end of the first driver, the source of the first PMOS transistor is connected to the non-inverting input end of the first comparator, and the non-inverting input end of the first comparator connected to the first end of the first capacitor, the first end of the first capacitor is connected to the first end of the first resistor, the second end of the first capacitor and the first end of the first resistor The two ends are grounded respectively.

作为一种可选的实施方式,所述第二输出支路包括第二PMOS管、第二驱动、第二选择器、第二比较器、第二电容和第二电阻;As an optional implementation manner, the second output branch includes a second PMOS transistor, a second driver, a second selector, a second comparator, a second capacitor, and a second resistor;

所述交流电流源的第二端与所述第二PMOS管的漏极连接,所述第二PMOS管的漏极与所述第二比较器的反相输入端连接,所述第二比较器的输出端与所述第二选择器的输入端连接,所述第二选择器的输出端与所述第二驱动的输入端连接,所述第二驱动的输出端与所述第二PMOS管的栅极连接,所述第二PMOS管的源极与所述第二比较器的正相输入端连接,所述第二比较器的正相输入端与所述第二电容的第一端连接,所述第二电容的第一端与所述第二电阻的第一端连接,所述第二电容的第二端以及所述第二电阻的第二端分别接地,所述第二PMOS管的源极所述第二输出支路的输出端。The second end of the AC current source is connected to the drain of the second PMOS transistor, the drain of the second PMOS transistor is connected to the inverting input end of the second comparator, and the second comparator The output terminal of the second selector is connected to the input terminal of the second selector, the output terminal of the second selector is connected to the input terminal of the second driver, and the output terminal of the second driver is connected to the second PMOS transistor The gate of the second PMOS transistor is connected to the non-inverting input terminal of the second comparator, and the non-inverting input terminal of the second comparator is connected to the first terminal of the second capacitor , the first end of the second capacitor is connected to the first end of the second resistor, the second end of the second capacitor and the second end of the second resistor are respectively grounded, and the second PMOS transistor source of the output of the second output branch.

作为一种可选的实施方式,所述整流桥复用电路还包括第三PMOS管、第三驱动、第三选择器、第三比较器、第一NMOS管、第四驱动、第四选择器、第四比较器、第二NMOS管、第五驱动、第五选择器、第五比较器、第六比较器和第七比较器;As an optional implementation manner, the rectifier bridge multiplexing circuit further includes a third PMOS transistor, a third driver, a third selector, a third comparator, a first NMOS transistor, a fourth driver, and a fourth selector , the fourth comparator, the second NMOS transistor, the fifth driver, the fifth selector, the fifth comparator, the sixth comparator and the seventh comparator;

所述交流电流源的第一端与所述第三PMOS管的漏极连接,所述第三PMOS管的漏极与所述第三比较器的反相输入端连接,所述第三比较器的输出端与所述第三选择器的输入端连接,所述第三选择器的输出端与所述第三驱动的输入端连接,所述第三驱动的输出端与所述第三PMOS管的栅极连接,所述第三PMOS管的源极与所述第三比较器的正相输入端连接,所述第三比较器的正相输入端与所述第二PMOS管的源极连接;The first end of the AC current source is connected to the drain of the third PMOS transistor, the drain of the third PMOS transistor is connected to the inverting input end of the third comparator, and the third comparator The output terminal of the third selector is connected to the input terminal of the third selector, the output terminal of the third selector is connected to the input terminal of the third driver, and the output terminal of the third driver is connected to the third PMOS transistor The gate of the third PMOS transistor is connected, the source of the third PMOS transistor is connected to the non-inverting input of the third comparator, and the non-inverting input of the third comparator is connected to the source of the second PMOS transistor ;

所述交流电流源的第一端与所述第一NMOS管的漏极连接,所述第一NMOS管的漏极与所述第四比较器的反相输入端连接,所述第四比较器的输出端与所述第四选择器的输入端连接,所述第四选择器的输出端与所述第四驱动的输入端连接,所述第四驱动的输出端与所述第一NMOS管的栅极连接,所述第一NMOS管的源极与所述第四比较器的正相输入端连接,所述第四比较器的正相输入端与所述第二NMOS管的源极连接,所述第二NMOS管的源极与所述第五比较器的正相输入端连接,所述第五比较器的正相输入端接地,所述第五比较器的输出端与所述第五选择器的输入端连接,所述第五选择器的输出端与所述第五驱动的输入端连接,所述第五驱动的输出端与所述第二NMOS管的栅极连接,所述第二NMOS管的漏极与所述第五比较器的反相输入端连接,所述第五比较器的反相输入端与所述第一PMOS管的漏极连接;The first terminal of the AC current source is connected to the drain of the first NMOS transistor, the drain of the first NMOS transistor is connected to the inverting input terminal of the fourth comparator, and the fourth comparator The output terminal of the fourth selector is connected to the input terminal of the fourth selector, the output terminal of the fourth selector is connected to the input terminal of the fourth driver, and the output terminal of the fourth driver is connected to the first NMOS transistor The gate of the first NMOS transistor is connected, the source of the first NMOS transistor is connected to the non-inverting input of the fourth comparator, and the non-inverting input of the fourth comparator is connected to the source of the second NMOS transistor , the source of the second NMOS transistor is connected to the non-inverting input terminal of the fifth comparator, the non-inverting input terminal of the fifth comparator is grounded, and the output terminal of the fifth comparator is connected to the non-inverting input terminal of the fifth comparator. The input terminal of the fifth selector is connected, the output terminal of the fifth selector is connected to the input terminal of the fifth driver, the output terminal of the fifth driver is connected to the gate of the second NMOS transistor, and the The drain of the second NMOS transistor is connected to the inverting input terminal of the fifth comparator, and the inverting input terminal of the fifth comparator is connected to the drain of the first PMOS transistor;

所述第六比较器的正相输入端输入第一参考电压,所述第六比较器的反相输入端与所述第一PMOS管的源极连接,所述第六比较器的输出端与所述第一选择器的输入端连接,所述第六比较器的输出端与所述第五选择器的输入端连接;The non-inverting input terminal of the sixth comparator inputs the first reference voltage, the inverting input terminal of the sixth comparator is connected to the source of the first PMOS transistor, and the output terminal of the sixth comparator is connected to the source of the first PMOS transistor. The input terminal of the first selector is connected, and the output terminal of the sixth comparator is connected with the input terminal of the fifth selector;

所述第七比较器的正相输入端输入第二参考电压,所述第七比较器的反相输入端与所述第二PMOS管的源极连接,所述第七比较器的输出端与所述第二选择器的输入端连接,所述第六比较器的输出端与所述第三选择器的输入端连接,所述第六比较器的输出端与所述第四选择器的输入端连接。The non-inverting input terminal of the seventh comparator inputs the second reference voltage, the inverting input terminal of the seventh comparator is connected to the source of the second PMOS transistor, and the output terminal of the seventh comparator is connected to the source of the second PMOS transistor. The input terminal of the second selector is connected, the output terminal of the sixth comparator is connected with the input terminal of the third selector, the output terminal of the sixth comparator is connected with the input terminal of the fourth selector end connection.

作为一种可选的实施方式,所述自适应体偏置模块包括第四PMOS管和第五PMOS管;As an optional implementation manner, the adaptive body bias module includes a fourth PMOS transistor and a fifth PMOS transistor;

所述第四PMOS管的源极与所述第一PMOS管的源极连接,所述第一PMOS管的源极与所述第五PMOS管的栅极连接,所述第五PMOS管的源极与所述第四PMOS管的栅极连接,所述第四PMOS管的栅极与所述第一PMOS管的漏极连接,所述第一PMOS管的衬底与所述第四PMOS管的漏极连接,所述第四PMOS管的漏极与所述第五PMOS管的漏极连接。The source of the fourth PMOS transistor is connected to the source of the first PMOS transistor, the source of the first PMOS transistor is connected to the gate of the fifth PMOS transistor, and the source of the fifth PMOS transistor The pole is connected to the gate of the fourth PMOS transistor, the gate of the fourth PMOS transistor is connected to the drain of the first PMOS transistor, and the substrate of the first PMOS transistor is connected to the fourth PMOS transistor. The drain of the fourth PMOS transistor is connected to the drain of the fifth PMOS transistor.

作为一种可选的实施方式,所述充放电模块包括第三电容;As an optional implementation manner, the charging and discharging module includes a third capacitor;

所述第三电容的第一端与所述第一驱动的第二输入端连接,所述第三电容的第二端与所述第一PMOS管的漏极连接;The first end of the third capacitor is connected to the second input end of the first driver, and the second end of the third capacitor is connected to the drain of the first PMOS transistor;

所述第三电容在所述交流电流源的第二端输出低电平时存储电压,在所述交流电流源的第二端输出高电平时通过放电使所述第一驱动的输入电压高于所述交流电流源的第二端输出的电压。The third capacitor stores a voltage when the second terminal of the AC current source outputs a low level, and discharges to make the input voltage of the first driver higher than the specified voltage when the second terminal of the AC current source outputs a high level. The voltage output by the second terminal of the AC current source.

作为一种可选的实施方式,所述充放电模块还包括单向导通组件;As an optional implementation manner, the charging and discharging module further includes a unidirectional conduction component;

所述第二PMOS管的源极通过所述单向导通组件与所述第三电容的第一端连接。The source of the second PMOS transistor is connected to the first end of the third capacitor through the unidirectional conduction component.

作为一种可选的实施方式,所述单向导通组件包括二极管;As an optional implementation manner, the unidirectional conduction component includes a diode;

所述二极管的正极与所述第二PMOS管的源极连接,所述二极管的负极与所述第三电容的第一端连接。The anode of the diode is connected to the source of the second PMOS transistor, and the cathode of the diode is connected to the first terminal of the third capacitor.

本发明实施例的整流桥复用防输出串扰电路,在整流桥复用电路的基础上设置防输出串扰电路,通过防输出串扰电路的自适应体偏置模块在第二输出支路的晶体管的体二极管导通时抑制第一PMOS管的体二极管导通,从而解决了第二输出支路的晶体管的体二极管导通时第一PMOS管的体二极管导通漏电引起的输出串扰问题,使得输出电压稳压;通过防输出串扰电路的充放电模块在交流电流源的第二端输出低电平时存储电压,在交流电流源的第二端输出高电平时通过放电使第一驱动的输入电压高于交流电流源的第二端输出的电压,使得第二输出支路的晶体管的体二极管导通时第一PMOS管不出现误开启现象,从而解决了第一PMOS管误开启的漏电问题引起的输出串扰,进一步使得输出电压稳压。In the rectifier bridge multiplexing anti-output crosstalk circuit of the embodiment of the present invention, the output crosstalk prevention circuit is set on the basis of the rectifier bridge multiplexing circuit, and the transistor of the second output branch is connected by the adaptive body bias module of the output crosstalk prevention circuit. When the body diode is turned on, the body diode of the first PMOS transistor is suppressed from being turned on, thereby solving the problem of output crosstalk caused by the body diode conduction leakage of the first PMOS transistor when the body diode of the transistor of the second output branch is turned on, so that the output Voltage stabilization; through the charge and discharge module of the anti-output crosstalk circuit, the voltage is stored when the second terminal of the AC current source outputs a low level, and the input voltage of the first driver is made high by discharging when the second terminal of the AC current source outputs a high level Based on the voltage output by the second terminal of the AC current source, the first PMOS transistor does not appear to be falsely turned on when the body diode of the transistor of the second output branch is turned on, thereby solving the leakage problem caused by the false turn-on of the first PMOS transistor The output crosstalk further stabilizes the output voltage.

附图说明Description of drawings

图1为本发明实施例整流桥复用防输出串扰电路的电路连接示意图;Fig. 1 is the circuit connection schematic diagram of the rectifier bridge multiplexing anti-output crosstalk circuit of the embodiment of the present invention;

图2为本发明实施例整流桥复用电路的输出串扰原理示意图;2 is a schematic diagram of the output crosstalk principle of the rectifier bridge multiplexing circuit according to an embodiment of the present invention;

图3为本发明实施例整流桥复用防输出串扰电路的功能仿真波形图。FIG. 3 is a functional simulation waveform diagram of the rectifier bridge multiplexing output crosstalk prevention circuit according to the embodiment of the present invention.

附图标记:IAC、交流电流源;CMP1、第一比较器;CMP2、第二比较器;CMP3、第三比较器;CMP4、第四比较器;CMP5、第五比较器;CMP6、第六比较器;CMP7、第七比较器;B1、第一驱动;B2、第二驱动;B3、第三驱动;B4、第四驱动;B5、第五驱动;Mux1、第一选择器;Mux2、第二选择器;Mux3、第三选择器;Mux4、第四选择器;Mux5、第五选择器;MP1、第一PMOS管;MP2、第二PMOS管;MP3、第三PMOS管;MPA、第四PMOS管;MPB、第五PMOS管;MN1、第一NMOS管;MN2、第二NMOS管;C1、第一电容;C2、第二电容;C3、第三电容;R1、第一电阻;R2、第二电阻;D1、二极管;VREFL、第一参考电压;VREFH、第二参考电压;101、自适应体偏置模块;102、充放电模块。Reference signs: I AC , alternating current source; CMP 1 , first comparator; CMP 2 , second comparator; CMP 3 , third comparator; CMP 4 , fourth comparator; CMP 5 , fifth comparator ; CMP 6 , the sixth comparator; CMP 7 , the seventh comparator; B 1 , the first drive; B 2 , the second drive; B 3 , the third drive; B 4 , the fourth drive; B 5 , the fifth Drive; Mux 1 , the first selector; Mux 2 , the second selector; Mux 3 , the third selector; Mux 4 , the fourth selector; Mux 5 , the fifth selector; M P1 , the first PMOS tube; M P2 , the second PMOS transistor; M P3 , the third PMOS transistor; M PA , the fourth PMOS transistor; M PB , the fifth PMOS transistor; M N1 , the first NMOS transistor; M N2 , the second NMOS transistor; C 1 , the first capacitor; C 2 , the second capacitor; C 3 , the third capacitor; R 1 , the first resistor; R 2 , the second resistor; D 1 , the diode; V REFL , the first reference voltage; V REFH , the first 2. Reference voltage; 101. Adaptive body bias module; 102. Charging and discharging module.

具体实施方式detailed description

为了使本技术领域的人员更好地理解本申请方案,下面将结合本申请实施例中的附图,对本申请实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅仅是本申请一部分的实施例,而不是全部的实施例。基于本申请中的实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例,都应当属于本申请保护的范围。In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiment of the application will be clearly and completely described below in conjunction with the accompanying drawings in the embodiment of the application. Obviously, the described embodiment is only It is an embodiment of a part of the application, but not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without creative efforts shall fall within the scope of protection of this application.

本申请的说明书和权利要求书及所述附图中的术语“第一”、“第二”、“第三”和“第四”等是用于区别不同对象,而不是用于描述特定顺序。此外,术语“包括”和“具有”以及它们任何变形,意图在于覆盖不排他的包含。例如包含了一系列步骤或单元的过程、方法、系统、产品或设备没有限定于已列出的步骤或单元,而是可选地还包括没有列出的步骤或单元,或可选地还包括对于这些过程、方法、产品或设备固有的其它步骤或单元。The terms "first", "second", "third" and "fourth" in the specification and claims of the present application and the drawings are used to distinguish different objects, rather than to describe a specific order . Furthermore, the terms "include" and "have", as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units is not limited to the listed steps or units, but optionally also includes unlisted steps or units, or optionally further includes For other steps or units inherent in these processes, methods, products or apparatuses.

在本文中提及“实施例”意味着,结合实施例描述的特定特征、结构或特性可以包含在本申请的至少一个实施例中。在说明书中的各个位置出现该短语并不一定均是指相同的实施例,也不是与其它实施例互斥的独立的或备选的实施例。本领域技术人员显式地和隐式地理解的是,本文所描述的实施例可以与其它实施例相结合。Reference herein to an "embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the present application. The occurrences of this phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is understood explicitly and implicitly by those skilled in the art that the embodiments described herein can be combined with other embodiments.

在串联-串联谐振式无线能量传输系统的接收端电路中,通过采用整流桥复用电路,利用单个整流桥来实现单个交流输入到多个直流输出的转换,以满足当前电子产品的需求,并大大降低了电路的复杂度、功耗与面积。然而,整流桥的复用使得输出电压之间存在输出串扰问题,在极端情况下甚至导致较低的输出电压无法稳压,从而导致整个系统无法正常工作。为此,本发明实施例提出了一种整流桥复用防输出串扰电路,在整流桥复用电路的基础上设置防输出串扰电路,通过防输出串扰电路的自适应体偏置模块在第二输出支路的晶体管的体二极管导通时抑制第一PMOS管的体二极管导通,从而解决了第二输出支路的晶体管的体二极管导通时第一PMOS管的体二极管导通漏电引起的输出串扰问题,使得输出电压稳压;通过防输出串扰电路的充放电模块在交流电流源的第二端输出低电平时存储电压,在交流电流源的第二端输出高电平时通过放电使第一驱动的输入电压高于交流电流源的第二端输出的电压,使得第二输出支路的晶体管的体二极管导通时第一PMOS管不出现误开启现象,从而解决了第一PMOS管误开启的漏电问题引起的输出串扰,进一步使得输出电压稳压。In the receiving end circuit of the series-series resonant wireless energy transfer system, by using a rectifier bridge multiplexing circuit, a single rectifier bridge is used to realize the conversion from a single AC input to multiple DC outputs to meet the needs of current electronic products, and The complexity, power consumption and area of the circuit are greatly reduced. However, the multiplexing of rectifier bridges leads to output crosstalk between output voltages, and in extreme cases, even lower output voltages cannot be stabilized, resulting in the failure of the entire system to work properly. For this reason, the embodiment of the present invention proposes a rectifier bridge multiplexing anti-output crosstalk circuit, an output crosstalk prevention circuit is set on the basis of the rectifier bridge multiplexing circuit, and the adaptive body bias module of the output crosstalk prevention circuit is used in the second When the body diode of the transistor of the output branch is turned on, the body diode of the first PMOS transistor is suppressed, thereby solving the problem caused by the body diode conduction leakage of the first PMOS transistor when the body diode of the transistor of the second output branch is turned on The problem of output crosstalk makes the output voltage stable; the charge and discharge module of the anti-output crosstalk circuit stores the voltage when the second end of the AC current source outputs a low level, and discharges the second end of the AC current source when the second end outputs a high level. The input voltage of a drive is higher than the voltage output by the second terminal of the AC current source, so that when the body diode of the transistor in the second output branch is turned on, the first PMOS transistor does not turn on by mistake, thereby solving the problem of the first PMOS transistor being turned on by mistake. The output crosstalk caused by the open leakage problem further makes the output voltage regulation.

如图1所示,本发明实施例提出了一种整流桥复用防输出串扰电路,应用于串联-串联谐振式无线能量传输系统的接收端电路,包括:As shown in Figure 1, the embodiment of the present invention proposes a rectifier bridge multiplexing output crosstalk prevention circuit, which is applied to the receiving end circuit of the series-series resonant wireless energy transmission system, including:

整流桥复用电路,包括交流电流源IAC、第一输出支路和第二输出支路,所述第一输出支路和所述第二输出支路的输入端与所述交流电流源IAC的第二端连接,所述第一输出支路的输出端用于输出第一功率电源,所述第二输出支路的输出端用于输出第二功率电源,所述第一功率电源小于所述第二功率电源,所述第一输出支路包括第一PMOS管MP1和第一驱动B1,所述第一驱动B1的输出端与所述第一PMOS管MP1的栅极连接,所述第一PMOS管MP1的漏极与所述交流电流源IAC的第二端连接,所述第一PMOS管MP1的源极为所述第一输出支路的输出端,所述交流电流源IAC为串联-串联谐振式无线能量传输系统的接收端电路输入所述整流桥复用电路的等效输入源;Rectifier bridge multiplexing circuit, including alternating current source I AC , a first output branch and a second output branch, the input terminals of the first output branch and the second output branch are connected to the alternating current source I The second end of the AC is connected, the output end of the first output branch is used to output the first power supply, the output end of the second output branch is used to output the second power supply, and the first power supply is less than The second power supply, the first output branch includes a first PMOS transistor M P1 and a first driver B 1 , the output terminal of the first driver B 1 is connected to the gate of the first PMOS transistor M P1 connected, the drain of the first PMOS transistor MP1 is connected to the second end of the alternating current source I AC , and the source of the first PMOS transistor MP1 is the output end of the first output branch, so The AC current source I AC is an equivalent input source for the receiving end circuit of the series-series resonant wireless energy transfer system to input the rectifier bridge multiplexing circuit;

防输出串扰电路,包括自适应体偏置模块101和充放电模块102,所述自适应体偏置模块101用于在所述第二输出支路的晶体管的体二极管导通时抑制所述第一PMOS管MP1的体二极管导通,所述充放电模块102用于在所述交流电流源IAC的第二端输出低电平时存储电压,所述充放电模块102用于在所述交流电流源IAC的第二端输出高电平时通过放电使所述第一驱动B1的输入电压VBOOST高于所述交流电流源IAC的第二端输出的电压VIN2The anti-output crosstalk circuit includes an adaptive body bias module 101 and a charging and discharging module 102, and the adaptive body bias module 101 is used to suppress the first The body diode of a PMOS transistor M P1 is turned on, and the charging and discharging module 102 is used for storing voltage when the second end of the alternating current source I AC outputs a low level, and the charging and discharging module 102 is used for When the second terminal of the current source I AC outputs a high level, the input voltage V BOOST of the first driver B 1 is higher than the voltage V IN2 output by the second terminal of the AC current source I AC by discharging.

其中,第一功率电源表示第一输出支路的输出电压VOL,第二功率电源表示第二输出支路的输出电压VOHWherein, the first power source represents the output voltage V OL of the first output branch, and the second power source represents the output voltage V OH of the second output branch.

参照图2可知,整流桥复用电路的输出串扰原因包括:Referring to Figure 2, it can be seen that the reasons for the output crosstalk of the rectifier bridge multiplexing circuit include:

1)由于第一PMOS管MP1的体二极管DP1以及第二PMOS管MP2的体二极管DP2的存在,以及第二PMOS管MP2的栅极控制信号的延迟,当第二PMOS管MP2的体二极管DP2导通时,第一PMOS管MP1的体二极管DP1两端的正向电压为VOH+0.7-VOL,故第一PMOS管MP1的体二极管DP1也导通。由于第一PMOS管MP1的体二极管DP1两端的压差比第二PMOS管MP2的体二极管DP2两端的压差大,交流电流源IAC输出的电流流向第一输出支路的输出端,使得第一输出支路的输出端输出的电压VOL稳压失败;1) Due to the existence of the body diode DP1 of the first PMOS transistor MP1 and the body diode DP2 of the second PMOS transistor MP2 , and the delay of the gate control signal of the second PMOS transistor MP2, when the second PMOS transistor M When the body diode D P2 of P2 is turned on, the forward voltage across the body diode D P1 of the first PMOS transistor MP1 is V OH +0.7-V OL , so the body diode D P1 of the first PMOS transistor MP1 is also turned on . Since the voltage difference across the body diode D P1 of the first PMOS transistor MP1 is greater than the voltage difference across the body diode D P2 of the second PMOS transistor MP2 , the current output by the alternating current source I AC flows to the output of the first output branch terminal, so that the voltage V OL output by the output terminal of the first output branch fails to be stabilized;

2)当第二PMOS管MP2的体二极管DP2导通时,第一PMOS管MP1会发生源漏互换,此时第一PMOS管MP1的源栅电压为VOH+0.7-VOH,第一PMOS管MP1处于导通边缘。此时第一PMOS管MP1的源漏电压为VOH-VOL,远大于第二PMOS管MP2的源漏电压,故此时交流电流源IAC输出的电流流向第一输出支路的输出端,使得第一输出支路的输出端输出的电压VOL稳压失败。2) When the body diode D P2 of the second PMOS transistor MP2 is turned on, the source-drain exchange of the first PMOS transistor MP1 will occur, and at this time the source-gate voltage of the first PMOS transistor MP1 is V OH +0.7-V OH , the first PMOS transistor M P1 is on the edge of conduction. At this time, the source-drain voltage of the first PMOS transistor MP1 is V OH -V OL , which is much higher than the source-drain voltage of the second PMOS transistor MP2, so the current output by the alternating current source I AC flows to the output of the first output branch. terminal, so that the voltage V OL output from the output terminal of the first output branch fails to be regulated.

基于上述的整流桥复用电路输出串扰原因,本发明实施例在整流桥复用电路的基础上设置防输出串扰电路,通过防输出串扰电路的自适应体偏置模块101在第二输出支路的晶体管的体二极管导通时抑制第一PMOS管MP1的体二极管导通,从而解决了第二输出支路的晶体管的体二极管导通时第一PMOS管MP1的体二极管导通漏电引起的输出串扰问题,使得输出电压稳压;通过防输出串扰电路的充放电模块102在交流电流源IAC的第二端输出低电平时存储电压,在交流电流源IAC的第二端输出高电平时通过放电使第一驱动B1的输入电压VBOOST高于交流电流源IAC的第二端输出的电压VIN2,使得第二输出支路的晶体管的体二极管导通时第一PMOS管MP1不出现误开启现象,从而解决了第一PMOS管MP1误开启的漏电问题引起的输出串扰,进一步使得输出电压稳压。Based on the above reasons for the output crosstalk of the rectifier bridge multiplexing circuit, the embodiment of the present invention sets an anti-output crosstalk circuit on the basis of the rectifier bridge multiplexing circuit, and the adaptive body bias module 101 of the anti-output crosstalk circuit is used in the second output branch When the body diode of the transistor is turned on, the body diode of the first PMOS transistor M P1 is suppressed from being turned on, thereby solving the problem of leakage caused by the body diode of the first PMOS transistor MP1 when the body diode of the transistor of the second output branch is turned on output crosstalk problem, so that the output voltage is stabilized; the charge and discharge module 102 of the anti-output crosstalk circuit stores the voltage when the second end of the alternating current source I AC outputs a low level, and outputs a high level at the second end of the alternating current source I AC level, the input voltage V BOOST of the first driver B 1 is higher than the voltage V IN2 output by the second terminal of the AC current source I AC by discharging, so that the body diode of the transistor of the second output branch is turned on when the first PMOS transistor M P1 does not appear to be turned on by mistake, thereby solving the output crosstalk caused by the leakage problem of the first PMOS transistor M P1 being turned on by mistake, and further stabilizing the output voltage.

参照图1(a),在本发明的一个实施例中,所述第一输出支路还包括第一比较器CMP1、第一选择器Mux1、第一电容C1和第一电阻R1Referring to FIG. 1(a), in one embodiment of the present invention, the first output branch further includes a first comparator CMP 1 , a first selector Mux 1 , a first capacitor C 1 and a first resistor R 1 ;

所述第一PMOS管MP1的漏极与所述第一比较器CMP1的反相输入端连接,所述第一比较器CMP1的输出端与所述第一选择器Mux1的输入端连接,所述第一选择器Mux1的输出端与所述第一驱动B1的第一输入端连接,所述第一PMOS管MP1的源极与所述第一比较器CMP1的正相输入端连接,所述第一比较器CMP1的正相输入端与所述第一电容C1的第一端连接,所述第一电容C1的第一端与所述第一电阻R1的第一端连接,所述第一电容C1的第二端以及所述第一电阻R1的第二端分别接地。The drain of the first PMOS transistor MP 1 is connected to the inverting input terminal of the first comparator CMP 1 , and the output terminal of the first comparator CMP 1 is connected to the input terminal of the first selector Mux 1 connected, the output terminal of the first selector Mux 1 is connected to the first input terminal of the first driver B 1 , the source of the first PMOS transistor MP 1 is connected to the positive terminal of the first comparator CMP 1 The phase input terminal is connected, the non-inverting input terminal of the first comparator CMP 1 is connected to the first terminal of the first capacitor C 1 , and the first terminal of the first capacitor C 1 is connected to the first resistor R1 The first terminal of the first capacitor C1 and the second terminal of the first resistor R1 are respectively grounded.

参照图1(a),作为一种可选的实施方式,所述第二输出支路包括第二PMOS管MP2、第二驱动B2、第二选择器Mux2、第二比较器CMP2、第二电容C2和第二电阻R2Referring to FIG. 1(a), as an optional implementation, the second output branch includes a second PMOS transistor MP2, a second driver B 2 , a second selector Mux 2 , and a second comparator CMP 2 , the second capacitor C 2 and the second resistor R 2 ;

所述交流电流源IAC的第二端与所述第二PMOS管MP2的漏极连接,所述第二PMOS管MP2的漏极与所述第二比较器CMP2的反相输入端连接,所述第二比较器CMP2的输出端与所述第二选择器Mux2的输入端连接,所述第二选择器Mux2的输出端与所述第二驱动B2的输入端连接,所述第二驱动B2的输出端与所述第二PMOS管MP2的栅极连接,所述第二PMOS管MP2的源极与所述第二比较器CMP2的正相输入端连接,所述第二比较器CMP2的正相输入端与所述第二电容C2的第一端连接,所述第二电容C2的第一端与所述第二电阻R2的第一端连接,所述第二电容C2的第二端以及所述第二电阻R2的第二端分别接地,所述第二PMOS管MP2的源极所述第二输出支路的输出端。The second terminal of the alternating current source I AC is connected to the drain of the second PMOS transistor MP2 , and the drain of the second PMOS transistor MP2 is connected to the inverting input terminal of the second comparator CMP2 connected, the output of the second comparator CMP 2 is connected to the input of the second selector Mux 2 , and the output of the second selector Mux 2 is connected to the input of the second driver B 2 , the output terminal of the second driver B2 is connected to the gate of the second PMOS transistor MP2 , and the source of the second PMOS transistor MP2 is connected to the non-inverting input terminal of the second comparator CMP2 connected, the non-inverting input terminal of the second comparator CMP 2 is connected to the first terminal of the second capacitor C 2 , and the first terminal of the second capacitor C 2 is connected to the first terminal of the second resistor R 2 One end is connected, the second end of the second capacitor C2 and the second end of the second resistor R2 are respectively grounded, the source of the second PMOS transistor MP2 is the output of the second output branch end.

其中,第一电阻R1和第二电阻R2为负载电阻。当第二电阻R2为最重载,第一电阻R1为最轻载时,整流桥复用电路处于最极端情况。Wherein, the first resistor R1 and the second resistor R2 are load resistors. When the second resistor R2 is the heaviest load and the first resistor R1 is the lightest load, the rectifier bridge multiplexing circuit is in the most extreme situation.

可以理解的是,本发明实施例的防输出串扰电路的功能不受第一电阻R1负载状况和第二电阻R2负载状况的限制。It can be understood that the function of the output crosstalk prevention circuit in this embodiment of the present invention is not limited by the load conditions of the first resistor R1 and the load condition of the second resistor R2.

继续参照图1(a),作为一种可选的实施方式,所述整流桥复用电路还包括第三PMOS管MP3、第三驱动B3、第三选择器Mux3、第三比较器CMP3、第一NMOS管MN1、第四驱动B4、第四选择器Mux4、第四比较器CMP4、第二NMOS管MN2、第五驱动B5、第五选择器Mux5、第五比较器CMP5、第六比较器CMP6和第七比较器CMP7Continuing to refer to FIG. 1(a), as an optional implementation, the rectifier bridge multiplexing circuit further includes a third PMOS transistor MP3 , a third driver B 3 , a third selector Mux 3 , and a third comparator CMP 3 , first NMOS transistor M N1 , fourth driver B 4 , fourth selector Mux 4 , fourth comparator CMP 4 , second NMOS transistor M N2 , fifth driver B 5 , fifth selector Mux 5 , fifth comparator CMP 5 , sixth comparator CMP 6 and seventh comparator CMP 7 ;

所述交流电流源IAC的第一端与所述第三PMOS管MP3的漏极连接,所述第三PMOS管MP3的漏极与所述第三比较器CMP3的反相输入端连接,所述第三比较器CMP3的输出端与所述第三选择器Mux3的输入端连接,所述第三选择器Mux3的输出端与所述第三驱动B3的输入端连接,所述第三驱动B3的输出端与所述第三PMOS管MP3的栅极连接,所述第三PMOS管MP3的源极与所述第三比较器CMP3的正相输入端连接,所述第三比较器CMP3的正相输入端与所述第二PMOS管MP2的源极连接;The first terminal of the alternating current source I AC is connected to the drain of the third PMOS transistor MP3 , and the drain of the third PMOS transistor MP3 is connected to the inverting input terminal of the third comparator CMP3 connected, the output of the third comparator CMP 3 is connected to the input of the third selector Mux 3 , and the output of the third selector Mux 3 is connected to the input of the third driver B 3 , the output terminal of the third driver B3 is connected to the gate of the third PMOS transistor MP3 , the source of the third PMOS transistor MP3 is connected to the non-inverting input terminal of the third comparator CMP3 connected, the non-inverting input terminal of the third comparator CMP 3 is connected to the source of the second PMOS transistor MP2;

所述交流电流源IAC的第一端与所述第一NMOS管MN1的漏极连接,所述第一NMOS管MN1的漏极与所述第四比较器CMP4的反相输入端连接,所述第四比较器CMP4的输出端与所述第四选择器Mux4的输入端连接,所述第四选择器Mux4的输出端与所述第四驱动B4的输入端连接,所述第四驱动B4的输出端与所述第一NMOS管MN1的栅极连接,所述第一NMOS管MN1的源极与所述第四比较器CMP4的正相输入端连接,所述第四比较器CMP4的正相输入端与所述第二NMOS管MN2的源极连接,所述第二NMOS管MN2的源极与所述第五比较器CMP5的正相输入端连接,所述第五比较器CMP5的正相输入端接地,所述第五比较器CMP5的输出端与所述第五选择器Mux5的输入端连接,所述第五选择器Mux5的输出端与所述第五驱动B5的输入端连接,所述第五驱动B5的输出端与所述第二NMOS管MN2的栅极连接,所述第二NMOS管MN2的漏极与所述第五比较器CMP5的反相输入端连接,所述第五比较器CMP5的反相输入端与所述第一PMOS管MP1的漏极连接;The first terminal of the alternating current source I AC is connected to the drain of the first NMOS transistor M N1 , and the drain of the first NMOS transistor M N1 is connected to the inverting input terminal of the fourth comparator CMP 4 connected, the output of the fourth comparator CMP 4 is connected to the input of the fourth selector Mux 4 , and the output of the fourth selector Mux 4 is connected to the input of the fourth driver B 4 , the output terminal of the fourth driver B4 is connected to the gate of the first NMOS transistor MN1 , and the source of the first NMOS transistor MN1 is connected to the non-inverting input terminal of the fourth comparator CMP4 connected, the non-inverting input terminal of the fourth comparator CMP 4 is connected to the source of the second NMOS transistor M N2 , and the source of the second NMOS transistor M N2 is connected to the source of the fifth comparator CMP 5 The non-inverting input end of the fifth comparator CMP 5 is connected to the ground, the output end of the fifth comparator CMP 5 is connected to the input end of the fifth selector Mux 5 , and the fifth comparator CMP 5 is connected to the input end of the fifth selector Mux 5. The output end of the selector Mux 5 is connected to the input end of the fifth driver B5, the output end of the fifth driver B5 is connected to the gate of the second NMOS transistor MN2 , and the second NMOS transistor The drain of M N2 is connected to the inverting input terminal of the fifth comparator CMP 5 , and the inverting input terminal of the fifth comparator CMP 5 is connected to the drain of the first PMOS transistor MP1;

所述第六比较器CMP6的正相输入端输入第一参考电压VREFL,所述第六比较器CMP6的反相输入端与所述第一PMOS管MP1的源极连接,所述第六比较器CMP6的输出端与所述第一选择器Mux1的输入端连接,所述第六比较器CMP6的输出端与所述第五选择器Mux5的输入端连接;The non-inverting input terminal of the sixth comparator CMP 6 inputs the first reference voltage V REFL , the inverting input terminal of the sixth comparator CMP 6 is connected to the source of the first PMOS transistor MP1, and the The output end of the sixth comparator CMP 6 is connected to the input end of the first selector Mux 1 , and the output end of the sixth comparator CMP 6 is connected to the input end of the fifth selector Mux 5 ;

所述第七比较器CMP7的正相输入端输入第二参考电压VREFH,所述第七比较器CMP7的反相输入端与所述第二PMOS管MP2的源极连接,所述第七比较器CMP7的输出端与所述第二选择器Mux2的输入端连接,所述第六比较器CMP6的输出端与所述第三选择器Mux3的输入端连接,所述第六比较器CMP6的输出端与所述第四选择器Mux4的输入端连接。The non-inverting input terminal of the seventh comparator CMP 7 inputs the second reference voltage V REFH , the inverting input terminal of the seventh comparator CMP 7 is connected to the source of the second PMOS transistor MP2, and the The output end of the seventh comparator CMP 7 is connected to the input end of the second selector Mux 2 , the output end of the sixth comparator CMP 6 is connected to the input end of the third selector Mux 3 , and the The output terminal of the sixth comparator CMP 6 is connected with the input terminal of the fourth selector Mux 4 .

参照图1(b),作为一种可选的实施方式,所述自适应体偏置模块101包括第四PMOS管MPA和第五PMOS管MPBReferring to FIG. 1(b), as an optional implementation manner, the adaptive body bias module 101 includes a fourth PMOS transistor MPA and a fifth PMOS transistor MPB ;

所述第四PMOS管MPA的源极与所述第一PMOS管MP1的源极连接,所述第一PMOS管MP1的源极与所述第五PMOS管MPB的栅极连接,所述第五PMOS管MPB的源极与所述第四PMOS管MPA的栅极连接,所述第四PMOS管MPA的栅极与所述第一PMOS管MP1的漏极连接,所述第一PMOS管MP1的衬底与所述第四PMOS管MPA的漏极连接,所述第四PMOS管MPA的漏极与所述第五PMOS管MPB的漏极连接。The source of the fourth PMOS transistor MPA is connected to the source of the first PMOS transistor MP1, the source of the first PMOS transistor MP1 is connected to the gate of the fifth PMOS transistor MPB , The source of the fifth PMOS transistor MPB is connected to the gate of the fourth PMOS transistor MPA , and the gate of the fourth PMOS transistor MPA is connected to the drain of the first PMOS transistor MP1, The substrate of the first PMOS transistor MP1 is connected to the drain of the fourth PMOS transistor M PA , and the drain of the fourth PMOS transistor M PA is connected to the drain of the fifth PMOS transistor MPB .

继续参照参照图1(b),作为一种可选的实施方式,所述充放电模块102包括第三电容C3Continuing to refer to FIG. 1(b), as an optional implementation manner, the charging and discharging module 102 includes a third capacitor C 3 ;

所述第三电容C3的第一端与所述第一驱动B1的第二输入端连接,所述第三电容C3的第二端与所述第一PMOS管MP1的漏极连接;The first end of the third capacitor C3 is connected to the second input end of the first driver B1, and the second end of the third capacitor C3 is connected to the drain of the first PMOS transistor MP1 ;

所述第三电容C3在所述交流电流源IAC的第二端输出低电平时存储电压,在所述交流电流源IAC的第二端输出高电平时通过放电使所述第一驱动B1的输入电压VBOOST高于所述交流电流源IAC的第二端输出的电压VIN2The third capacitor C3 stores a voltage when the second end of the alternating current source I AC outputs a low level, and discharges the first drive when the second end of the alternating current source I AC outputs a high level. The input voltage V BOOST of B 1 is higher than the voltage V IN2 output by the second terminal of the AC current source I AC .

具体地,当交流电流源IAC的第二端输出高电平时,第三电容C3将第一驱动B1的输入电压VBOOST抬高到大于交流电流源IAC的第二端输出的电压VIN2,使得第一PMOS管MP1的源栅电压小于零,使得第一PMOS管MP1不会出现误开启现象,进而解决了第一PMOS管MP1误开启导致的输出串扰问题。Specifically, when the second terminal of the AC current source I AC outputs a high level, the third capacitor C3 raises the input voltage V BOOST of the first driver B1 to be higher than the voltage output by the second terminal of the AC current source I AC V IN2 , so that the source-gate voltage of the first PMOS transistor MP1 is less than zero, so that the first PMOS transistor MP1 will not be turned on by mistake, thereby solving the problem of output crosstalk caused by the wrong turn-on of the first PMOS transistor MP1.

可以理解的是,在本发明的实施例中,当第一PMOS管MP1正常工作时,栅极电压为零,故第一驱动B1的输入电压VBOOST的提升不会造成第一PMOS管MP1的导通阻抗增大,维持第一PMOS管MP1小的导通压降,不影响串联-串联谐振式无线能量传输系统的转换效率。It can be understood that, in the embodiment of the present invention, when the first PMOS transistor MP1 works normally, the gate voltage is zero, so the boost of the input voltage V BOOST of the first driver B1 will not cause the first PMOS transistor The on-resistance of M P1 is increased to maintain a small on-voltage drop of the first PMOS transistor M P1 without affecting the conversion efficiency of the series-series resonant wireless energy transmission system.

作为一种可选的实施方式,所述充放电模块102还包括单向导通组件;As an optional implementation manner, the charging and discharging module 102 also includes a unidirectional conduction component;

所述第二PMOS管MP2的源极通过所述单向导通组件与所述第三电容C3的第一端连接。The source of the second PMOS transistor MP2 is connected to the first end of the third capacitor C3 through the unidirectional conduction component.

其中,在本发明的实施例中,所述单向导通组件包括二极管D1Wherein, in the embodiment of the present invention, the unidirectional conduction component includes a diode D 1 ;

所述二极管D1的正极与所述第二PMOS管MP2的源极连接,所述二极管D1的负极与所述第三电容C3的第一端连接。 The anode of the diode D1 is connected to the source of the second PMOS transistor MP2, and the cathode of the diode D1 is connected to the first end of the third capacitor C3.

图3示出了本发明实施例的整流桥复用防输出串扰电路的功能仿真波形图,仿真条件为第一电阻R1为最轻载,第二电阻R2为最重载,即串联-串联谐振式无线能量传输系统的接收端电路处于最极端情况下。根据图3可知,本发明实施例的整流桥复用防输出串扰电路不仅通过自适应体偏置模块101解决了第一PMOS管MP1体二极管导通漏电引起的输出串扰,还通过抬升第一驱动B1的输入电压VBOOST解决了第一PMOS管MP1误开启带来的输出串扰。如图3所示,仿真结果显示第一PMOS管MP1的源漏电流明显降低至不影响输出稳压的水平,在第三电容C3一个充电周期后,第一输出支路的输出电压VOL呈下降趋势,成功实现稳压输出。Fig. 3 shows the functional simulation waveform diagram of the rectifier bridge multiplexing anti-output crosstalk circuit of the embodiment of the present invention, the simulation condition is that the first resistor R1 is the lightest load, and the second resistor R2 is the heaviest load, i.e. series- The receiver circuit of the series resonant wireless energy transfer system is the most extreme case. It can be seen from FIG. 3 that the rectifier bridge multiplexing anti-output crosstalk circuit of the embodiment of the present invention not only solves the output crosstalk caused by the conduction leakage of the body diode of the first PMOS transistor M P1 through the adaptive body bias module 101, but also solves the output crosstalk caused by the first The input voltage V BOOST for driving B1 solves the output crosstalk caused by the wrong turn-on of the first PMOS transistor M P1 . As shown in Figure 3, the simulation results show that the source-leakage current of the first PMOS transistor M P1 is significantly reduced to a level that does not affect the output voltage regulation. After one charging cycle of the third capacitor C3, the output voltage V of the first output branch OL showed a downward trend and successfully achieved a regulated output.

以上是对本发明的较佳实施进行了具体说明,但本发明并不限于所述实施例,熟悉本领域的技术人员在不违背本发明精神的前提下还可做作出种种的等同变形或替换,这些等同的变形或替换均包含在本申请权利要求所限定的范围内。The above is a specific description of the preferred implementation of the present invention, but the present invention is not limited to the described embodiments, and those skilled in the art can also make various equivalent deformations or replacements without violating the spirit of the present invention. These equivalent modifications or replacements are all within the scope defined by the claims of the present application.

Claims (8)

1. A kind of bridge rectifier multiplexes and defends the circuit of the output crosstalk, characterized by, apply to the receiving end circuit of the wireless energy transmission system of series-series resonance type, including:
the rectifier bridge multiplexing circuit comprises an alternating current source, a first output branch and a second output branch, wherein the input ends of the first output branch and the second output branch are connected with the second end of the alternating current source, the output end of the first output branch is used for outputting a first power supply, the output end of the second output branch is used for outputting a second power supply, the first power supply is smaller than the second power supply, the first output branch comprises a first PMOS (P-channel metal oxide semiconductor) tube and a first driver, the output end of the first driver is connected with the grid electrode of the first PMOS tube, the drain electrode of the first PMOS tube is connected with the second end of the alternating current source, the source electrode of the first PMOS tube is the output end of the first output branch, and the alternating current source is an equivalent input source of a receiving end circuit of a series-series resonant wireless energy transmission system which inputs the rectifier bridge multiplexing circuit;
the output crosstalk prevention circuit comprises an adaptive body biasing module and a charge and discharge module, wherein the adaptive body biasing module is used for inhibiting the conduction of a body diode of a first PMOS (P-channel metal oxide semiconductor) tube when the body diode of a transistor of the second output branch is conducted, the charge and discharge module is used for storing voltage when a second end of the alternating current source outputs low level, and the charge and discharge module is used for enabling the input voltage of the first driver to be higher than the voltage output by the second end of the alternating current source through discharging when the second end of the alternating current source outputs high level.
2. The circuit of claim 1, wherein the first output branch further comprises a first comparator, a first selector, a first capacitor, and a first resistor;
the drain electrode of the first PMOS tube is connected with the inverting input end of the first comparator, the output end of the first comparator is connected with the input end of the first selector, the output end of the first selector is connected with the first input end of the first drive, the source electrode of the first PMOS tube is connected with the positive input end of the first comparator, the positive input end of the first comparator is connected with the first end of the first capacitor, the first end of the first capacitor is connected with the first end of the first resistor, and the second end of the first capacitor and the second end of the first resistor are respectively grounded.
3. The circuit of claim 2, wherein the second output branch comprises a second PMOS transistor, a second driver, a second selector, a second comparator, a second capacitor, and a second resistor;
the second end of the alternating current source is connected with the drain electrode of the second PMOS tube, the drain electrode of the second PMOS tube is connected with the inverting input end of the second comparator, the output end of the second comparator is connected with the input end of the second selector, the output end of the second selector is connected with the second driving input end, the second driving output end is connected with the grid electrode of the second PMOS tube, the source electrode of the second PMOS tube is connected with the positive phase input end of the second comparator, the positive phase input end of the second comparator is connected with the first end of the second capacitor, the first end of the second capacitor is connected with the first end of the second resistor, the second end of the second capacitor and the second end of the second resistor are respectively grounded, and the source electrode of the second PMOS tube is connected with the output end of the second output branch circuit.
4. The circuit of claim 3, wherein the circuit further comprises a third PMOS transistor, a third driver, a third selector, a third comparator, a first NMOS transistor, a fourth driver, a fourth selector, a fourth comparator, a second NMOS transistor, a fifth driver, a fifth selector, a fifth comparator, a sixth comparator, and a seventh comparator;
a first end of the alternating current source is connected with a drain electrode of the third PMOS transistor, a drain electrode of the third PMOS transistor is connected with an inverting input end of the third comparator, an output end of the third comparator is connected with an input end of the third selector, an output end of the third selector is connected with an input end of the third driver, an output end of the third driver is connected with a gate electrode of the third PMOS transistor, a source electrode of the third PMOS transistor is connected with a positive-phase input end of the third comparator, and a positive-phase input end of the third comparator is connected with a source electrode of the second PMOS transistor;
a first end of the alternating current source is connected with a drain electrode of the first NMOS transistor, a drain electrode of the first NMOS transistor is connected with an inverting input terminal of the fourth comparator, an output terminal of the fourth comparator is connected with an input terminal of the fourth selector, an output terminal of the fourth selector is connected with an input terminal of the fourth driver, an output terminal of the fourth driver is connected with a gate electrode of the first NMOS transistor, a source electrode of the first NMOS transistor is connected with a positive-phase input terminal of the fourth comparator, a positive-phase input terminal of the fourth comparator is connected with a source electrode of the second NMOS transistor, a source electrode of the second NMOS transistor is connected with a positive-phase input terminal of the fifth comparator, a positive-phase input terminal of the fifth comparator is grounded, an output terminal of the fifth comparator is connected with an input terminal of the fifth selector, an output terminal of the fifth selector is connected with an input terminal of the fifth driver, an output terminal of the fifth driver is connected with a gate electrode of the second NMOS transistor, a drain electrode of the second NMOS transistor is connected with an inverting input terminal of the fifth comparator, and an inverting input terminal of the fifth comparator is connected with a drain electrode of the PMOS transistor;
a positive phase input end of the sixth comparator inputs a first reference voltage, an inverted phase input end of the sixth comparator is connected with a source electrode of the first PMOS tube, an output end of the sixth comparator is connected with an input end of the first selector, and an output end of the sixth comparator is connected with an input end of the fifth selector;
a second reference voltage is input to a positive phase input end of the seventh comparator, an inverted input end of the seventh comparator is connected to a source electrode of the second PMOS transistor, an output end of the seventh comparator is connected to an input end of the second selector, an output end of the sixth comparator is connected to an input end of the third selector, and an output end of the sixth comparator is connected to an input end of the fourth selector.
5. The circuit of claim 4, wherein the adaptive body bias module comprises a fourth PMOS transistor and a fifth PMOS transistor;
the source electrode of the fourth PMOS tube is connected with the source electrode of the first PMOS tube, the source electrode of the first PMOS tube is connected with the grid electrode of the fifth PMOS tube, the source electrode of the fifth PMOS tube is connected with the grid electrode of the fourth PMOS tube, the grid electrode of the fourth PMOS tube is connected with the drain electrode of the first PMOS tube, the substrate of the first PMOS tube is connected with the drain electrode of the fourth PMOS tube, and the drain electrode of the fourth PMOS tube is connected with the drain electrode of the fifth PMOS tube.
6. The circuit of claim 5, wherein the charge/discharge module comprises a third capacitor;
the first end of the third capacitor is connected with the second input end of the first driver, and the second end of the third capacitor is connected with the drain electrode of the first PMOS tube;
the third capacitor stores voltage when the second end of the alternating current source outputs low level, and enables the input voltage of the first driver to be higher than the voltage output by the second end of the alternating current source through discharging when the second end of the alternating current source outputs high level.
7. The circuit of claim 6, wherein the charge-discharge module further comprises a unidirectional conducting element;
and the source electrode of the second PMOS tube is connected with the first end of the third capacitor through the one-way conduction assembly.
8. The circuit of claim 7, wherein the unidirectional conducting component comprises a diode;
the anode of the diode is connected with the source electrode of the second PMOS tube, and the cathode of the diode is connected with the first end of the third capacitor.
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